mlx4.h revision c82e9aa0a8bcf7a1643ccb71678bab57f3cb4bc6
1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37#ifndef MLX4_H 38#define MLX4_H 39 40#include <linux/mutex.h> 41#include <linux/radix-tree.h> 42#include <linux/timer.h> 43#include <linux/semaphore.h> 44#include <linux/workqueue.h> 45 46#include <linux/mlx4/device.h> 47#include <linux/mlx4/driver.h> 48#include <linux/mlx4/doorbell.h> 49#include <linux/mlx4/cmd.h> 50 51#define DRV_NAME "mlx4_core" 52#define DRV_VERSION "1.0" 53#define DRV_RELDATE "July 14, 2011" 54 55enum { 56 MLX4_HCR_BASE = 0x80680, 57 MLX4_HCR_SIZE = 0x0001c, 58 MLX4_CLR_INT_SIZE = 0x00008, 59 MLX4_SLAVE_COMM_BASE = 0x0, 60 MLX4_COMM_PAGESIZE = 0x1000 61}; 62 63enum { 64 MLX4_MGM_ENTRY_SIZE = 0x100, 65 MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2), 66 MLX4_MTT_ENTRY_PER_SEG = 8 67}; 68 69enum { 70 MLX4_NUM_PDS = 1 << 15 71}; 72 73enum { 74 MLX4_CMPT_TYPE_QP = 0, 75 MLX4_CMPT_TYPE_SRQ = 1, 76 MLX4_CMPT_TYPE_CQ = 2, 77 MLX4_CMPT_TYPE_EQ = 3, 78 MLX4_CMPT_NUM_TYPE 79}; 80 81enum { 82 MLX4_CMPT_SHIFT = 24, 83 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 84}; 85 86enum mlx4_mr_state { 87 MLX4_MR_DISABLED = 0, 88 MLX4_MR_EN_HW, 89 MLX4_MR_EN_SW 90}; 91 92#define MLX4_COMM_TIME 10000 93enum { 94 MLX4_COMM_CMD_RESET, 95 MLX4_COMM_CMD_VHCR0, 96 MLX4_COMM_CMD_VHCR1, 97 MLX4_COMM_CMD_VHCR2, 98 MLX4_COMM_CMD_VHCR_EN, 99 MLX4_COMM_CMD_VHCR_POST, 100 MLX4_COMM_CMD_FLR = 254 101}; 102 103/*The flag indicates that the slave should delay the RESET cmd*/ 104#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 105/*indicates how many retries will be done if we are in the middle of FLR*/ 106#define NUM_OF_RESET_RETRIES 10 107#define SLEEP_TIME_IN_RESET (2 * 1000) 108enum mlx4_resource { 109 RES_QP, 110 RES_CQ, 111 RES_SRQ, 112 RES_XRCD, 113 RES_MPT, 114 RES_MTT, 115 RES_MAC, 116 RES_VLAN, 117 RES_EQ, 118 RES_COUNTER, 119 MLX4_NUM_OF_RESOURCE_TYPE 120}; 121 122enum mlx4_alloc_mode { 123 RES_OP_RESERVE, 124 RES_OP_RESERVE_AND_MAP, 125 RES_OP_MAP_ICM, 126}; 127 128 129/* 130 *Virtual HCR structures. 131 * mlx4_vhcr is the sw representation, in machine endianess 132 * 133 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 134 * to FW to go through communication channel. 135 * It is big endian, and has the same structure as the physical HCR 136 * used by command interface 137 */ 138struct mlx4_vhcr { 139 u64 in_param; 140 u64 out_param; 141 u32 in_modifier; 142 u32 errno; 143 u16 op; 144 u16 token; 145 u8 op_modifier; 146 u8 e_bit; 147}; 148 149struct mlx4_vhcr_cmd { 150 __be64 in_param; 151 __be32 in_modifier; 152 __be64 out_param; 153 __be16 token; 154 u16 reserved; 155 u8 status; 156 u8 flags; 157 __be16 opcode; 158}; 159 160struct mlx4_cmd_info { 161 u16 opcode; 162 bool has_inbox; 163 bool has_outbox; 164 bool out_is_imm; 165 bool encode_slave_id; 166 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 167 struct mlx4_cmd_mailbox *inbox); 168 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 169 struct mlx4_cmd_mailbox *inbox, 170 struct mlx4_cmd_mailbox *outbox, 171 struct mlx4_cmd_info *cmd); 172}; 173 174#ifdef CONFIG_MLX4_DEBUG 175extern int mlx4_debug_level; 176#else /* CONFIG_MLX4_DEBUG */ 177#define mlx4_debug_level (0) 178#endif /* CONFIG_MLX4_DEBUG */ 179 180#define mlx4_dbg(mdev, format, arg...) \ 181do { \ 182 if (mlx4_debug_level) \ 183 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 184} while (0) 185 186#define mlx4_err(mdev, format, arg...) \ 187 dev_err(&mdev->pdev->dev, format, ##arg) 188#define mlx4_info(mdev, format, arg...) \ 189 dev_info(&mdev->pdev->dev, format, ##arg) 190#define mlx4_warn(mdev, format, arg...) \ 191 dev_warn(&mdev->pdev->dev, format, ##arg) 192 193#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 194#define ALL_SLAVES 0xff 195 196struct mlx4_bitmap { 197 u32 last; 198 u32 top; 199 u32 max; 200 u32 reserved_top; 201 u32 mask; 202 u32 avail; 203 spinlock_t lock; 204 unsigned long *table; 205}; 206 207struct mlx4_buddy { 208 unsigned long **bits; 209 unsigned int *num_free; 210 int max_order; 211 spinlock_t lock; 212}; 213 214struct mlx4_icm; 215 216struct mlx4_icm_table { 217 u64 virt; 218 int num_icm; 219 int num_obj; 220 int obj_size; 221 int lowmem; 222 int coherent; 223 struct mutex mutex; 224 struct mlx4_icm **icm; 225}; 226 227/* 228 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 229 */ 230struct mlx4_mpt_entry { 231 __be32 flags; 232 __be32 qpn; 233 __be32 key; 234 __be32 pd_flags; 235 __be64 start; 236 __be64 length; 237 __be32 lkey; 238 __be32 win_cnt; 239 u8 reserved1[3]; 240 u8 mtt_rep; 241 __be64 mtt_seg; 242 __be32 mtt_sz; 243 __be32 entity_size; 244 __be32 first_byte_offset; 245} __packed; 246 247/* 248 * Must be packed because start is 64 bits but only aligned to 32 bits. 249 */ 250struct mlx4_eq_context { 251 __be32 flags; 252 u16 reserved1[3]; 253 __be16 page_offset; 254 u8 log_eq_size; 255 u8 reserved2[4]; 256 u8 eq_period; 257 u8 reserved3; 258 u8 eq_max_count; 259 u8 reserved4[3]; 260 u8 intr; 261 u8 log_page_size; 262 u8 reserved5[2]; 263 u8 mtt_base_addr_h; 264 __be32 mtt_base_addr_l; 265 u32 reserved6[2]; 266 __be32 consumer_index; 267 __be32 producer_index; 268 u32 reserved7[4]; 269}; 270 271struct mlx4_cq_context { 272 __be32 flags; 273 u16 reserved1[3]; 274 __be16 page_offset; 275 __be32 logsize_usrpage; 276 __be16 cq_period; 277 __be16 cq_max_count; 278 u8 reserved2[3]; 279 u8 comp_eqn; 280 u8 log_page_size; 281 u8 reserved3[2]; 282 u8 mtt_base_addr_h; 283 __be32 mtt_base_addr_l; 284 __be32 last_notified_index; 285 __be32 solicit_producer_index; 286 __be32 consumer_index; 287 __be32 producer_index; 288 u32 reserved4[2]; 289 __be64 db_rec_addr; 290}; 291 292struct mlx4_srq_context { 293 __be32 state_logsize_srqn; 294 u8 logstride; 295 u8 reserved1; 296 __be16 xrcd; 297 __be32 pg_offset_cqn; 298 u32 reserved2; 299 u8 log_page_size; 300 u8 reserved3[2]; 301 u8 mtt_base_addr_h; 302 __be32 mtt_base_addr_l; 303 __be32 pd; 304 __be16 limit_watermark; 305 __be16 wqe_cnt; 306 u16 reserved4; 307 __be16 wqe_counter; 308 u32 reserved5; 309 __be64 db_rec_addr; 310}; 311 312struct mlx4_eqe { 313 u8 reserved1; 314 u8 type; 315 u8 reserved2; 316 u8 subtype; 317 union { 318 u32 raw[6]; 319 struct { 320 __be32 cqn; 321 } __packed comp; 322 struct { 323 u16 reserved1; 324 __be16 token; 325 u32 reserved2; 326 u8 reserved3[3]; 327 u8 status; 328 __be64 out_param; 329 } __packed cmd; 330 struct { 331 __be32 qpn; 332 } __packed qp; 333 struct { 334 __be32 srqn; 335 } __packed srq; 336 struct { 337 __be32 cqn; 338 u32 reserved1; 339 u8 reserved2[3]; 340 u8 syndrome; 341 } __packed cq_err; 342 struct { 343 u32 reserved1[2]; 344 __be32 port; 345 } __packed port_change; 346 struct { 347 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 348 u32 reserved; 349 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 350 } __packed comm_channel_arm; 351 struct { 352 u8 port; 353 u8 reserved[3]; 354 __be64 mac; 355 } __packed mac_update; 356 struct { 357 u8 port; 358 } __packed sw_event; 359 struct { 360 __be32 slave_id; 361 } __packed flr_event; 362 } event; 363 u8 slave_id; 364 u8 reserved3[2]; 365 u8 owner; 366} __packed; 367 368struct mlx4_eq { 369 struct mlx4_dev *dev; 370 void __iomem *doorbell; 371 int eqn; 372 u32 cons_index; 373 u16 irq; 374 u16 have_irq; 375 int nent; 376 struct mlx4_buf_list *page_list; 377 struct mlx4_mtt mtt; 378}; 379 380struct mlx4_slave_eqe { 381 u8 type; 382 u8 port; 383 u32 param; 384}; 385 386struct mlx4_slave_event_eq_info { 387 u32 eqn; 388 u16 token; 389 u64 event_type; 390}; 391 392struct mlx4_profile { 393 int num_qp; 394 int rdmarc_per_qp; 395 int num_srq; 396 int num_cq; 397 int num_mcg; 398 int num_mpt; 399 int num_mtt; 400}; 401 402struct mlx4_fw { 403 u64 clr_int_base; 404 u64 catas_offset; 405 u64 comm_base; 406 struct mlx4_icm *fw_icm; 407 struct mlx4_icm *aux_icm; 408 u32 catas_size; 409 u16 fw_pages; 410 u8 clr_int_bar; 411 u8 catas_bar; 412 u8 comm_bar; 413}; 414 415struct mlx4_comm { 416 u32 slave_write; 417 u32 slave_read; 418}; 419 420#define MGM_QPN_MASK 0x00FFFFFF 421#define MGM_BLCK_LB_BIT 30 422 423#define VLAN_FLTR_SIZE 128 424 425struct mlx4_vlan_fltr { 426 __be32 entry[VLAN_FLTR_SIZE]; 427}; 428 429struct mlx4_promisc_qp { 430 struct list_head list; 431 u32 qpn; 432}; 433 434struct mlx4_steer_index { 435 struct list_head list; 436 unsigned int index; 437 struct list_head duplicates; 438}; 439 440struct mlx4_mgm { 441 __be32 next_gid_index; 442 __be32 members_count; 443 u32 reserved[2]; 444 u8 gid[16]; 445 __be32 qp[MLX4_QP_PER_MGM]; 446}; 447 448struct mlx4_slave_state { 449 u8 comm_toggle; 450 u8 last_cmd; 451 u8 init_port_mask; 452 bool active; 453 u8 function; 454 dma_addr_t vhcr_dma; 455 u16 mtu[MLX4_MAX_PORTS + 1]; 456 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 457 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 458 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 459 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 460 struct mlx4_slave_event_eq_info event_eq; 461 u16 eq_pi; 462 u16 eq_ci; 463 spinlock_t lock; 464 /*initialized via the kzalloc*/ 465 u8 is_slave_going_down; 466 u32 cookie; 467}; 468 469struct slave_list { 470 struct mutex mutex; 471 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 472}; 473 474struct mlx4_resource_tracker { 475 spinlock_t lock; 476 /* tree for each resources */ 477 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 478 /* num_of_slave's lists, one per slave */ 479 struct slave_list *slave_list; 480}; 481 482#define SLAVE_EVENT_EQ_SIZE 128 483struct mlx4_slave_event_eq { 484 u32 eqn; 485 u32 cons; 486 u32 prod; 487 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 488}; 489 490struct mlx4_master_qp0_state { 491 int proxy_qp0_active; 492 int qp0_active; 493 int port_active; 494}; 495 496struct mlx4_mfunc_master_ctx { 497 struct mlx4_slave_state *slave_state; 498 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 499 int init_port_ref[MLX4_MAX_PORTS + 1]; 500 u16 max_mtu[MLX4_MAX_PORTS + 1]; 501 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 502 struct mlx4_resource_tracker res_tracker; 503 struct workqueue_struct *comm_wq; 504 struct work_struct comm_work; 505 struct work_struct slave_event_work; 506 struct work_struct slave_flr_event_work; 507 spinlock_t slave_state_lock; 508 __be32 comm_arm_bit_vector[4]; 509 struct mlx4_eqe cmd_eqe; 510 struct mlx4_slave_event_eq slave_eq; 511 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 512}; 513 514struct mlx4_mfunc { 515 struct mlx4_comm __iomem *comm; 516 struct mlx4_vhcr_cmd *vhcr; 517 dma_addr_t vhcr_dma; 518 519 struct mlx4_mfunc_master_ctx master; 520}; 521 522struct mlx4_cmd { 523 struct pci_pool *pool; 524 void __iomem *hcr; 525 struct mutex hcr_mutex; 526 struct semaphore poll_sem; 527 struct semaphore event_sem; 528 struct semaphore slave_sem; 529 int max_cmds; 530 spinlock_t context_lock; 531 int free_head; 532 struct mlx4_cmd_context *context; 533 u16 token_mask; 534 u8 use_events; 535 u8 toggle; 536 u8 comm_toggle; 537}; 538 539struct mlx4_uar_table { 540 struct mlx4_bitmap bitmap; 541}; 542 543struct mlx4_mr_table { 544 struct mlx4_bitmap mpt_bitmap; 545 struct mlx4_buddy mtt_buddy; 546 u64 mtt_base; 547 u64 mpt_base; 548 struct mlx4_icm_table mtt_table; 549 struct mlx4_icm_table dmpt_table; 550}; 551 552struct mlx4_cq_table { 553 struct mlx4_bitmap bitmap; 554 spinlock_t lock; 555 struct radix_tree_root tree; 556 struct mlx4_icm_table table; 557 struct mlx4_icm_table cmpt_table; 558}; 559 560struct mlx4_eq_table { 561 struct mlx4_bitmap bitmap; 562 char *irq_names; 563 void __iomem *clr_int; 564 void __iomem **uar_map; 565 u32 clr_mask; 566 struct mlx4_eq *eq; 567 struct mlx4_icm_table table; 568 struct mlx4_icm_table cmpt_table; 569 int have_irq; 570 u8 inta_pin; 571}; 572 573struct mlx4_srq_table { 574 struct mlx4_bitmap bitmap; 575 spinlock_t lock; 576 struct radix_tree_root tree; 577 struct mlx4_icm_table table; 578 struct mlx4_icm_table cmpt_table; 579}; 580 581struct mlx4_qp_table { 582 struct mlx4_bitmap bitmap; 583 u32 rdmarc_base; 584 int rdmarc_shift; 585 spinlock_t lock; 586 struct mlx4_icm_table qp_table; 587 struct mlx4_icm_table auxc_table; 588 struct mlx4_icm_table altc_table; 589 struct mlx4_icm_table rdmarc_table; 590 struct mlx4_icm_table cmpt_table; 591}; 592 593struct mlx4_mcg_table { 594 struct mutex mutex; 595 struct mlx4_bitmap bitmap; 596 struct mlx4_icm_table table; 597}; 598 599struct mlx4_catas_err { 600 u32 __iomem *map; 601 struct timer_list timer; 602 struct list_head list; 603}; 604 605#define MLX4_MAX_MAC_NUM 128 606#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 607 608struct mlx4_mac_table { 609 __be64 entries[MLX4_MAX_MAC_NUM]; 610 int refs[MLX4_MAX_MAC_NUM]; 611 struct mutex mutex; 612 int total; 613 int max; 614}; 615 616#define MLX4_MAX_VLAN_NUM 128 617#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 618 619struct mlx4_vlan_table { 620 __be32 entries[MLX4_MAX_VLAN_NUM]; 621 int refs[MLX4_MAX_VLAN_NUM]; 622 struct mutex mutex; 623 int total; 624 int max; 625}; 626 627struct mlx4_mac_entry { 628 u64 mac; 629}; 630 631struct mlx4_port_info { 632 struct mlx4_dev *dev; 633 int port; 634 char dev_name[16]; 635 struct device_attribute port_attr; 636 enum mlx4_port_type tmp_type; 637 struct mlx4_mac_table mac_table; 638 struct radix_tree_root mac_tree; 639 struct mlx4_vlan_table vlan_table; 640 int base_qpn; 641}; 642 643struct mlx4_sense { 644 struct mlx4_dev *dev; 645 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 646 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 647 struct delayed_work sense_poll; 648}; 649 650struct mlx4_msix_ctl { 651 u64 pool_bm; 652 spinlock_t pool_lock; 653}; 654 655struct mlx4_steer { 656 struct list_head promisc_qps[MLX4_NUM_STEERS]; 657 struct list_head steer_entries[MLX4_NUM_STEERS]; 658 struct list_head high_prios; 659}; 660 661struct mlx4_priv { 662 struct mlx4_dev dev; 663 664 struct list_head dev_list; 665 struct list_head ctx_list; 666 spinlock_t ctx_lock; 667 668 struct list_head pgdir_list; 669 struct mutex pgdir_mutex; 670 671 struct mlx4_fw fw; 672 struct mlx4_cmd cmd; 673 struct mlx4_mfunc mfunc; 674 675 struct mlx4_bitmap pd_bitmap; 676 struct mlx4_bitmap xrcd_bitmap; 677 struct mlx4_uar_table uar_table; 678 struct mlx4_mr_table mr_table; 679 struct mlx4_cq_table cq_table; 680 struct mlx4_eq_table eq_table; 681 struct mlx4_srq_table srq_table; 682 struct mlx4_qp_table qp_table; 683 struct mlx4_mcg_table mcg_table; 684 struct mlx4_bitmap counters_bitmap; 685 686 struct mlx4_catas_err catas_err; 687 688 void __iomem *clr_base; 689 690 struct mlx4_uar driver_uar; 691 void __iomem *kar; 692 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 693 struct mlx4_sense sense; 694 struct mutex port_mutex; 695 struct mlx4_msix_ctl msix_ctl; 696 struct mlx4_steer *steer; 697 struct list_head bf_list; 698 struct mutex bf_mutex; 699 struct io_mapping *bf_mapping; 700 int reserved_mtts; 701}; 702 703static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 704{ 705 return container_of(dev, struct mlx4_priv, dev); 706} 707 708#define MLX4_SENSE_RANGE (HZ * 3) 709 710extern struct workqueue_struct *mlx4_wq; 711 712u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 713void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); 714u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); 715void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); 716u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 717int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 718 u32 reserved_bot, u32 resetrved_top); 719void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 720 721int mlx4_reset(struct mlx4_dev *dev); 722 723int mlx4_alloc_eq_table(struct mlx4_dev *dev); 724void mlx4_free_eq_table(struct mlx4_dev *dev); 725 726int mlx4_init_pd_table(struct mlx4_dev *dev); 727int mlx4_init_xrcd_table(struct mlx4_dev *dev); 728int mlx4_init_uar_table(struct mlx4_dev *dev); 729int mlx4_init_mr_table(struct mlx4_dev *dev); 730int mlx4_init_eq_table(struct mlx4_dev *dev); 731int mlx4_init_cq_table(struct mlx4_dev *dev); 732int mlx4_init_qp_table(struct mlx4_dev *dev); 733int mlx4_init_srq_table(struct mlx4_dev *dev); 734int mlx4_init_mcg_table(struct mlx4_dev *dev); 735 736void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 737void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 738void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 739void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 740void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 741void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 742void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 743void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 744void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 745int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); 746void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 747int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 748void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 749int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 750void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 751int __mlx4_mr_reserve(struct mlx4_dev *dev); 752void __mlx4_mr_release(struct mlx4_dev *dev, u32 index); 753int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index); 754void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index); 755u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 756void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 757 758int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 759 struct mlx4_vhcr *vhcr, 760 struct mlx4_cmd_mailbox *inbox, 761 struct mlx4_cmd_mailbox *outbox, 762 struct mlx4_cmd_info *cmd); 763int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 764 struct mlx4_vhcr *vhcr, 765 struct mlx4_cmd_mailbox *inbox, 766 struct mlx4_cmd_mailbox *outbox, 767 struct mlx4_cmd_info *cmd); 768int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 769 struct mlx4_vhcr *vhcr, 770 struct mlx4_cmd_mailbox *inbox, 771 struct mlx4_cmd_mailbox *outbox, 772 struct mlx4_cmd_info *cmd); 773int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 774 struct mlx4_vhcr *vhcr, 775 struct mlx4_cmd_mailbox *inbox, 776 struct mlx4_cmd_mailbox *outbox, 777 struct mlx4_cmd_info *cmd); 778int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 779 struct mlx4_vhcr *vhcr, 780 struct mlx4_cmd_mailbox *inbox, 781 struct mlx4_cmd_mailbox *outbox, 782 struct mlx4_cmd_info *cmd); 783int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 784 struct mlx4_vhcr *vhcr, 785 struct mlx4_cmd_mailbox *inbox, 786 struct mlx4_cmd_mailbox *outbox, 787 struct mlx4_cmd_info *cmd); 788int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 789 struct mlx4_vhcr *vhcr, 790 struct mlx4_cmd_mailbox *inbox, 791 struct mlx4_cmd_mailbox *outbox, 792 struct mlx4_cmd_info *cmd); 793int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 794 int *base); 795void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 796int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 797void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 798int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 799int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 800 int start_index, int npages, u64 *page_list); 801 802void mlx4_start_catas_poll(struct mlx4_dev *dev); 803void mlx4_stop_catas_poll(struct mlx4_dev *dev); 804void mlx4_catas_init(void); 805int mlx4_restart_one(struct pci_dev *pdev); 806int mlx4_register_device(struct mlx4_dev *dev); 807void mlx4_unregister_device(struct mlx4_dev *dev); 808void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port); 809 810struct mlx4_dev_cap; 811struct mlx4_init_hca_param; 812 813u64 mlx4_make_profile(struct mlx4_dev *dev, 814 struct mlx4_profile *request, 815 struct mlx4_dev_cap *dev_cap, 816 struct mlx4_init_hca_param *init_hca); 817void mlx4_master_comm_channel(struct work_struct *work); 818void mlx4_gen_slave_eqe(struct work_struct *work); 819void mlx4_master_handle_slave_flr(struct work_struct *work); 820 821int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 822 struct mlx4_vhcr *vhcr, 823 struct mlx4_cmd_mailbox *inbox, 824 struct mlx4_cmd_mailbox *outbox, 825 struct mlx4_cmd_info *cmd); 826int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 827 struct mlx4_vhcr *vhcr, 828 struct mlx4_cmd_mailbox *inbox, 829 struct mlx4_cmd_mailbox *outbox, 830 struct mlx4_cmd_info *cmd); 831int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 832 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 833 struct mlx4_cmd_mailbox *outbox, 834 struct mlx4_cmd_info *cmd); 835int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 836 struct mlx4_vhcr *vhcr, 837 struct mlx4_cmd_mailbox *inbox, 838 struct mlx4_cmd_mailbox *outbox, 839 struct mlx4_cmd_info *cmd); 840int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 841 struct mlx4_vhcr *vhcr, 842 struct mlx4_cmd_mailbox *inbox, 843 struct mlx4_cmd_mailbox *outbox, 844 struct mlx4_cmd_info *cmd); 845int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 846 struct mlx4_vhcr *vhcr, 847 struct mlx4_cmd_mailbox *inbox, 848 struct mlx4_cmd_mailbox *outbox, 849 struct mlx4_cmd_info *cmd); 850int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 851 struct mlx4_vhcr *vhcr, 852 struct mlx4_cmd_mailbox *inbox, 853 struct mlx4_cmd_mailbox *outbox, 854 struct mlx4_cmd_info *cmd); 855int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 856 struct mlx4_vhcr *vhcr, 857 struct mlx4_cmd_mailbox *inbox, 858 struct mlx4_cmd_mailbox *outbox, 859 struct mlx4_cmd_info *cmd); 860int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 861 struct mlx4_vhcr *vhcr, 862 struct mlx4_cmd_mailbox *inbox, 863 struct mlx4_cmd_mailbox *outbox, 864 struct mlx4_cmd_info *cmd); 865int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 866 struct mlx4_vhcr *vhcr, 867 struct mlx4_cmd_mailbox *inbox, 868 struct mlx4_cmd_mailbox *outbox, 869 struct mlx4_cmd_info *cmd); 870int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 871 struct mlx4_vhcr *vhcr, 872 struct mlx4_cmd_mailbox *inbox, 873 struct mlx4_cmd_mailbox *outbox, 874 struct mlx4_cmd_info *cmd); 875int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 876 struct mlx4_vhcr *vhcr, 877 struct mlx4_cmd_mailbox *inbox, 878 struct mlx4_cmd_mailbox *outbox, 879 struct mlx4_cmd_info *cmd); 880int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 881 struct mlx4_vhcr *vhcr, 882 struct mlx4_cmd_mailbox *inbox, 883 struct mlx4_cmd_mailbox *outbox, 884 struct mlx4_cmd_info *cmd); 885int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 886 struct mlx4_vhcr *vhcr, 887 struct mlx4_cmd_mailbox *inbox, 888 struct mlx4_cmd_mailbox *outbox, 889 struct mlx4_cmd_info *cmd); 890int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 891 struct mlx4_vhcr *vhcr, 892 struct mlx4_cmd_mailbox *inbox, 893 struct mlx4_cmd_mailbox *outbox, 894 struct mlx4_cmd_info *cmd); 895int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 896 struct mlx4_vhcr *vhcr, 897 struct mlx4_cmd_mailbox *inbox, 898 struct mlx4_cmd_mailbox *outbox, 899 struct mlx4_cmd_info *cmd); 900int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 901 struct mlx4_vhcr *vhcr, 902 struct mlx4_cmd_mailbox *inbox, 903 struct mlx4_cmd_mailbox *outbox, 904 struct mlx4_cmd_info *cmd); 905int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 906 struct mlx4_vhcr *vhcr, 907 struct mlx4_cmd_mailbox *inbox, 908 struct mlx4_cmd_mailbox *outbox, 909 struct mlx4_cmd_info *cmd); 910 911int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 912 913int mlx4_cmd_init(struct mlx4_dev *dev); 914void mlx4_cmd_cleanup(struct mlx4_dev *dev); 915void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 916int mlx4_cmd_use_events(struct mlx4_dev *dev); 917void mlx4_cmd_use_polling(struct mlx4_dev *dev); 918 919void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 920void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 921 922void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 923 924void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 925 926void mlx4_handle_catas_err(struct mlx4_dev *dev); 927 928int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 929 enum mlx4_port_type *type); 930void mlx4_do_sense_ports(struct mlx4_dev *dev, 931 enum mlx4_port_type *stype, 932 enum mlx4_port_type *defaults); 933void mlx4_start_sense(struct mlx4_dev *dev); 934void mlx4_stop_sense(struct mlx4_dev *dev); 935void mlx4_sense_init(struct mlx4_dev *dev); 936int mlx4_check_port_params(struct mlx4_dev *dev, 937 enum mlx4_port_type *port_type); 938int mlx4_change_port_types(struct mlx4_dev *dev, 939 enum mlx4_port_type *port_types); 940 941void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 942void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 943 944int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); 945/* resource tracker functions*/ 946int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 947 enum mlx4_resource resource_type, 948 int resource_id, int *slave); 949void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 950int mlx4_init_resource_tracker(struct mlx4_dev *dev); 951 952void mlx4_free_resource_tracker(struct mlx4_dev *dev); 953 954int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 955 struct mlx4_vhcr *vhcr, 956 struct mlx4_cmd_mailbox *inbox, 957 struct mlx4_cmd_mailbox *outbox, 958 struct mlx4_cmd_info *cmd); 959int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 960 struct mlx4_vhcr *vhcr, 961 struct mlx4_cmd_mailbox *inbox, 962 struct mlx4_cmd_mailbox *outbox, 963 struct mlx4_cmd_info *cmd); 964int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 965 struct mlx4_vhcr *vhcr, 966 struct mlx4_cmd_mailbox *inbox, 967 struct mlx4_cmd_mailbox *outbox, 968 struct mlx4_cmd_info *cmd); 969int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 970 struct mlx4_vhcr *vhcr, 971 struct mlx4_cmd_mailbox *inbox, 972 struct mlx4_cmd_mailbox *outbox, 973 struct mlx4_cmd_info *cmd); 974int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 975int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port); 976 977 978int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 979 struct mlx4_vhcr *vhcr, 980 struct mlx4_cmd_mailbox *inbox, 981 struct mlx4_cmd_mailbox *outbox, 982 struct mlx4_cmd_info *cmd); 983 984int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 985 struct mlx4_vhcr *vhcr, 986 struct mlx4_cmd_mailbox *inbox, 987 struct mlx4_cmd_mailbox *outbox, 988 struct mlx4_cmd_info *cmd); 989int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 990 enum mlx4_protocol prot, enum mlx4_steer_type steer); 991int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 992 int block_mcast_loopback, enum mlx4_protocol prot, 993 enum mlx4_steer_type steer); 994int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 995 struct mlx4_vhcr *vhcr, 996 struct mlx4_cmd_mailbox *inbox, 997 struct mlx4_cmd_mailbox *outbox, 998 struct mlx4_cmd_info *cmd); 999int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1000 struct mlx4_vhcr *vhcr, 1001 struct mlx4_cmd_mailbox *inbox, 1002 struct mlx4_cmd_mailbox *outbox, 1003 struct mlx4_cmd_info *cmd); 1004int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1005 int port, void *buf); 1006int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1007 struct mlx4_cmd_mailbox *outbox); 1008int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1009 struct mlx4_vhcr *vhcr, 1010 struct mlx4_cmd_mailbox *inbox, 1011 struct mlx4_cmd_mailbox *outbox, 1012 struct mlx4_cmd_info *cmd); 1013int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1014 struct mlx4_vhcr *vhcr, 1015 struct mlx4_cmd_mailbox *inbox, 1016 struct mlx4_cmd_mailbox *outbox, 1017 struct mlx4_cmd_info *cmd); 1018int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1019 struct mlx4_vhcr *vhcr, 1020 struct mlx4_cmd_mailbox *inbox, 1021 struct mlx4_cmd_mailbox *outbox, 1022 struct mlx4_cmd_info *cmd); 1023 1024static inline void set_param_l(u64 *arg, u32 val) 1025{ 1026 *((u32 *)arg) = val; 1027} 1028 1029static inline void set_param_h(u64 *arg, u32 val) 1030{ 1031 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1032} 1033 1034static inline u32 get_param_l(u64 *arg) 1035{ 1036 return (u32) (*arg & 0xffffffff); 1037} 1038 1039static inline u32 get_param_h(u64 *arg) 1040{ 1041 return (u32)(*arg >> 32); 1042} 1043 1044static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1045{ 1046 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1047} 1048 1049#define NOT_MASKED_PD_BITS 17 1050 1051#endif /* MLX4_H */ 1052