mlx4.h revision f5311ac109b21c9b47118655a5b6d887bcc686f8
1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37#ifndef MLX4_H 38#define MLX4_H 39 40#include <linux/mutex.h> 41#include <linux/radix-tree.h> 42#include <linux/timer.h> 43#include <linux/semaphore.h> 44#include <linux/workqueue.h> 45 46#include <linux/mlx4/device.h> 47#include <linux/mlx4/driver.h> 48#include <linux/mlx4/doorbell.h> 49#include <linux/mlx4/cmd.h> 50 51#define DRV_NAME "mlx4_core" 52#define DRV_VERSION "1.0" 53#define DRV_RELDATE "July 14, 2011" 54 55enum { 56 MLX4_HCR_BASE = 0x80680, 57 MLX4_HCR_SIZE = 0x0001c, 58 MLX4_CLR_INT_SIZE = 0x00008, 59 MLX4_SLAVE_COMM_BASE = 0x0, 60 MLX4_COMM_PAGESIZE = 0x1000 61}; 62 63enum { 64 MLX4_MGM_ENTRY_SIZE = 0x100, 65 MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2), 66 MLX4_MTT_ENTRY_PER_SEG = 8 67}; 68 69enum { 70 MLX4_NUM_PDS = 1 << 15 71}; 72 73enum { 74 MLX4_CMPT_TYPE_QP = 0, 75 MLX4_CMPT_TYPE_SRQ = 1, 76 MLX4_CMPT_TYPE_CQ = 2, 77 MLX4_CMPT_TYPE_EQ = 3, 78 MLX4_CMPT_NUM_TYPE 79}; 80 81enum { 82 MLX4_CMPT_SHIFT = 24, 83 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 84}; 85 86enum mlx4_mr_state { 87 MLX4_MR_DISABLED = 0, 88 MLX4_MR_EN_HW, 89 MLX4_MR_EN_SW 90}; 91 92#define MLX4_COMM_TIME 10000 93enum { 94 MLX4_COMM_CMD_RESET, 95 MLX4_COMM_CMD_VHCR0, 96 MLX4_COMM_CMD_VHCR1, 97 MLX4_COMM_CMD_VHCR2, 98 MLX4_COMM_CMD_VHCR_EN, 99 MLX4_COMM_CMD_VHCR_POST, 100 MLX4_COMM_CMD_FLR = 254 101}; 102 103/*The flag indicates that the slave should delay the RESET cmd*/ 104#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 105/*indicates how many retries will be done if we are in the middle of FLR*/ 106#define NUM_OF_RESET_RETRIES 10 107#define SLEEP_TIME_IN_RESET (2 * 1000) 108enum mlx4_resource { 109 RES_QP, 110 RES_CQ, 111 RES_SRQ, 112 RES_XRCD, 113 RES_MPT, 114 RES_MTT, 115 RES_MAC, 116 RES_VLAN, 117 RES_EQ, 118 RES_COUNTER, 119 MLX4_NUM_OF_RESOURCE_TYPE 120}; 121 122enum mlx4_alloc_mode { 123 RES_OP_RESERVE, 124 RES_OP_RESERVE_AND_MAP, 125 RES_OP_MAP_ICM, 126}; 127 128 129/* 130 *Virtual HCR structures. 131 * mlx4_vhcr is the sw representation, in machine endianess 132 * 133 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 134 * to FW to go through communication channel. 135 * It is big endian, and has the same structure as the physical HCR 136 * used by command interface 137 */ 138struct mlx4_vhcr { 139 u64 in_param; 140 u64 out_param; 141 u32 in_modifier; 142 u32 errno; 143 u16 op; 144 u16 token; 145 u8 op_modifier; 146 u8 e_bit; 147}; 148 149struct mlx4_vhcr_cmd { 150 __be64 in_param; 151 __be32 in_modifier; 152 __be64 out_param; 153 __be16 token; 154 u16 reserved; 155 u8 status; 156 u8 flags; 157 __be16 opcode; 158}; 159 160struct mlx4_cmd_info { 161 u16 opcode; 162 bool has_inbox; 163 bool has_outbox; 164 bool out_is_imm; 165 bool encode_slave_id; 166 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 167 struct mlx4_cmd_mailbox *inbox); 168 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 169 struct mlx4_cmd_mailbox *inbox, 170 struct mlx4_cmd_mailbox *outbox, 171 struct mlx4_cmd_info *cmd); 172}; 173 174#ifdef CONFIG_MLX4_DEBUG 175extern int mlx4_debug_level; 176#else /* CONFIG_MLX4_DEBUG */ 177#define mlx4_debug_level (0) 178#endif /* CONFIG_MLX4_DEBUG */ 179 180#define mlx4_dbg(mdev, format, arg...) \ 181do { \ 182 if (mlx4_debug_level) \ 183 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 184} while (0) 185 186#define mlx4_err(mdev, format, arg...) \ 187 dev_err(&mdev->pdev->dev, format, ##arg) 188#define mlx4_info(mdev, format, arg...) \ 189 dev_info(&mdev->pdev->dev, format, ##arg) 190#define mlx4_warn(mdev, format, arg...) \ 191 dev_warn(&mdev->pdev->dev, format, ##arg) 192 193#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 194#define ALL_SLAVES 0xff 195 196struct mlx4_bitmap { 197 u32 last; 198 u32 top; 199 u32 max; 200 u32 reserved_top; 201 u32 mask; 202 u32 avail; 203 spinlock_t lock; 204 unsigned long *table; 205}; 206 207struct mlx4_buddy { 208 unsigned long **bits; 209 unsigned int *num_free; 210 int max_order; 211 spinlock_t lock; 212}; 213 214struct mlx4_icm; 215 216struct mlx4_icm_table { 217 u64 virt; 218 int num_icm; 219 int num_obj; 220 int obj_size; 221 int lowmem; 222 int coherent; 223 struct mutex mutex; 224 struct mlx4_icm **icm; 225}; 226 227struct mlx4_eqe { 228 u8 reserved1; 229 u8 type; 230 u8 reserved2; 231 u8 subtype; 232 union { 233 u32 raw[6]; 234 struct { 235 __be32 cqn; 236 } __packed comp; 237 struct { 238 u16 reserved1; 239 __be16 token; 240 u32 reserved2; 241 u8 reserved3[3]; 242 u8 status; 243 __be64 out_param; 244 } __packed cmd; 245 struct { 246 __be32 qpn; 247 } __packed qp; 248 struct { 249 __be32 srqn; 250 } __packed srq; 251 struct { 252 __be32 cqn; 253 u32 reserved1; 254 u8 reserved2[3]; 255 u8 syndrome; 256 } __packed cq_err; 257 struct { 258 u32 reserved1[2]; 259 __be32 port; 260 } __packed port_change; 261 struct { 262 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 263 u32 reserved; 264 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 265 } __packed comm_channel_arm; 266 struct { 267 u8 port; 268 u8 reserved[3]; 269 __be64 mac; 270 } __packed mac_update; 271 struct { 272 u8 port; 273 } __packed sw_event; 274 struct { 275 __be32 slave_id; 276 } __packed flr_event; 277 } event; 278 u8 slave_id; 279 u8 reserved3[2]; 280 u8 owner; 281} __packed; 282 283struct mlx4_eq { 284 struct mlx4_dev *dev; 285 void __iomem *doorbell; 286 int eqn; 287 u32 cons_index; 288 u16 irq; 289 u16 have_irq; 290 int nent; 291 struct mlx4_buf_list *page_list; 292 struct mlx4_mtt mtt; 293}; 294 295struct mlx4_slave_eqe { 296 u8 type; 297 u8 port; 298 u32 param; 299}; 300 301struct mlx4_slave_event_eq_info { 302 u32 eqn; 303 u16 token; 304 u64 event_type; 305}; 306 307struct mlx4_profile { 308 int num_qp; 309 int rdmarc_per_qp; 310 int num_srq; 311 int num_cq; 312 int num_mcg; 313 int num_mpt; 314 int num_mtt; 315}; 316 317struct mlx4_fw { 318 u64 clr_int_base; 319 u64 catas_offset; 320 u64 comm_base; 321 struct mlx4_icm *fw_icm; 322 struct mlx4_icm *aux_icm; 323 u32 catas_size; 324 u16 fw_pages; 325 u8 clr_int_bar; 326 u8 catas_bar; 327 u8 comm_bar; 328}; 329 330struct mlx4_comm { 331 u32 slave_write; 332 u32 slave_read; 333}; 334 335#define MGM_QPN_MASK 0x00FFFFFF 336#define MGM_BLCK_LB_BIT 30 337 338#define VLAN_FLTR_SIZE 128 339 340struct mlx4_vlan_fltr { 341 __be32 entry[VLAN_FLTR_SIZE]; 342}; 343 344struct mlx4_promisc_qp { 345 struct list_head list; 346 u32 qpn; 347}; 348 349struct mlx4_steer_index { 350 struct list_head list; 351 unsigned int index; 352 struct list_head duplicates; 353}; 354 355struct mlx4_mgm { 356 __be32 next_gid_index; 357 __be32 members_count; 358 u32 reserved[2]; 359 u8 gid[16]; 360 __be32 qp[MLX4_QP_PER_MGM]; 361}; 362 363struct mlx4_slave_state { 364 u8 comm_toggle; 365 u8 last_cmd; 366 u8 init_port_mask; 367 bool active; 368 u8 function; 369 dma_addr_t vhcr_dma; 370 u16 mtu[MLX4_MAX_PORTS + 1]; 371 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 372 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 373 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 374 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 375 struct mlx4_slave_event_eq_info event_eq; 376 u16 eq_pi; 377 u16 eq_ci; 378 spinlock_t lock; 379 /*initialized via the kzalloc*/ 380 u8 is_slave_going_down; 381 u32 cookie; 382}; 383 384struct slave_list { 385 struct mutex mutex; 386 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 387}; 388 389struct mlx4_resource_tracker { 390 spinlock_t lock; 391 /* tree for each resources */ 392 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 393 /* num_of_slave's lists, one per slave */ 394 struct slave_list *slave_list; 395}; 396 397#define SLAVE_EVENT_EQ_SIZE 128 398struct mlx4_slave_event_eq { 399 u32 eqn; 400 u32 cons; 401 u32 prod; 402 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 403}; 404 405struct mlx4_master_qp0_state { 406 int proxy_qp0_active; 407 int qp0_active; 408 int port_active; 409}; 410 411struct mlx4_mfunc_master_ctx { 412 struct mlx4_slave_state *slave_state; 413 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 414 int init_port_ref[MLX4_MAX_PORTS + 1]; 415 u16 max_mtu[MLX4_MAX_PORTS + 1]; 416 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 417 struct mlx4_resource_tracker res_tracker; 418 struct workqueue_struct *comm_wq; 419 struct work_struct comm_work; 420 struct work_struct slave_event_work; 421 struct work_struct slave_flr_event_work; 422 spinlock_t slave_state_lock; 423 __be32 comm_arm_bit_vector[4]; 424 struct mlx4_eqe cmd_eqe; 425 struct mlx4_slave_event_eq slave_eq; 426 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 427}; 428 429struct mlx4_mfunc { 430 struct mlx4_comm __iomem *comm; 431 struct mlx4_vhcr_cmd *vhcr; 432 dma_addr_t vhcr_dma; 433 434 struct mlx4_mfunc_master_ctx master; 435}; 436 437struct mlx4_cmd { 438 struct pci_pool *pool; 439 void __iomem *hcr; 440 struct mutex hcr_mutex; 441 struct semaphore poll_sem; 442 struct semaphore event_sem; 443 struct semaphore slave_sem; 444 int max_cmds; 445 spinlock_t context_lock; 446 int free_head; 447 struct mlx4_cmd_context *context; 448 u16 token_mask; 449 u8 use_events; 450 u8 toggle; 451 u8 comm_toggle; 452}; 453 454struct mlx4_uar_table { 455 struct mlx4_bitmap bitmap; 456}; 457 458struct mlx4_mr_table { 459 struct mlx4_bitmap mpt_bitmap; 460 struct mlx4_buddy mtt_buddy; 461 u64 mtt_base; 462 u64 mpt_base; 463 struct mlx4_icm_table mtt_table; 464 struct mlx4_icm_table dmpt_table; 465}; 466 467struct mlx4_cq_table { 468 struct mlx4_bitmap bitmap; 469 spinlock_t lock; 470 struct radix_tree_root tree; 471 struct mlx4_icm_table table; 472 struct mlx4_icm_table cmpt_table; 473}; 474 475struct mlx4_eq_table { 476 struct mlx4_bitmap bitmap; 477 char *irq_names; 478 void __iomem *clr_int; 479 void __iomem **uar_map; 480 u32 clr_mask; 481 struct mlx4_eq *eq; 482 struct mlx4_icm_table table; 483 struct mlx4_icm_table cmpt_table; 484 int have_irq; 485 u8 inta_pin; 486}; 487 488struct mlx4_srq_table { 489 struct mlx4_bitmap bitmap; 490 spinlock_t lock; 491 struct radix_tree_root tree; 492 struct mlx4_icm_table table; 493 struct mlx4_icm_table cmpt_table; 494}; 495 496struct mlx4_qp_table { 497 struct mlx4_bitmap bitmap; 498 u32 rdmarc_base; 499 int rdmarc_shift; 500 spinlock_t lock; 501 struct mlx4_icm_table qp_table; 502 struct mlx4_icm_table auxc_table; 503 struct mlx4_icm_table altc_table; 504 struct mlx4_icm_table rdmarc_table; 505 struct mlx4_icm_table cmpt_table; 506}; 507 508struct mlx4_mcg_table { 509 struct mutex mutex; 510 struct mlx4_bitmap bitmap; 511 struct mlx4_icm_table table; 512}; 513 514struct mlx4_catas_err { 515 u32 __iomem *map; 516 struct timer_list timer; 517 struct list_head list; 518}; 519 520#define MLX4_MAX_MAC_NUM 128 521#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 522 523struct mlx4_mac_table { 524 __be64 entries[MLX4_MAX_MAC_NUM]; 525 int refs[MLX4_MAX_MAC_NUM]; 526 struct mutex mutex; 527 int total; 528 int max; 529}; 530 531#define MLX4_MAX_VLAN_NUM 128 532#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 533 534struct mlx4_vlan_table { 535 __be32 entries[MLX4_MAX_VLAN_NUM]; 536 int refs[MLX4_MAX_VLAN_NUM]; 537 struct mutex mutex; 538 int total; 539 int max; 540}; 541 542struct mlx4_mac_entry { 543 u64 mac; 544}; 545 546struct mlx4_port_info { 547 struct mlx4_dev *dev; 548 int port; 549 char dev_name[16]; 550 struct device_attribute port_attr; 551 enum mlx4_port_type tmp_type; 552 struct mlx4_mac_table mac_table; 553 struct radix_tree_root mac_tree; 554 struct mlx4_vlan_table vlan_table; 555 int base_qpn; 556}; 557 558struct mlx4_sense { 559 struct mlx4_dev *dev; 560 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 561 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 562 struct delayed_work sense_poll; 563}; 564 565struct mlx4_msix_ctl { 566 u64 pool_bm; 567 spinlock_t pool_lock; 568}; 569 570struct mlx4_steer { 571 struct list_head promisc_qps[MLX4_NUM_STEERS]; 572 struct list_head steer_entries[MLX4_NUM_STEERS]; 573 struct list_head high_prios; 574}; 575 576struct mlx4_priv { 577 struct mlx4_dev dev; 578 579 struct list_head dev_list; 580 struct list_head ctx_list; 581 spinlock_t ctx_lock; 582 583 struct list_head pgdir_list; 584 struct mutex pgdir_mutex; 585 586 struct mlx4_fw fw; 587 struct mlx4_cmd cmd; 588 struct mlx4_mfunc mfunc; 589 590 struct mlx4_bitmap pd_bitmap; 591 struct mlx4_bitmap xrcd_bitmap; 592 struct mlx4_uar_table uar_table; 593 struct mlx4_mr_table mr_table; 594 struct mlx4_cq_table cq_table; 595 struct mlx4_eq_table eq_table; 596 struct mlx4_srq_table srq_table; 597 struct mlx4_qp_table qp_table; 598 struct mlx4_mcg_table mcg_table; 599 struct mlx4_bitmap counters_bitmap; 600 601 struct mlx4_catas_err catas_err; 602 603 void __iomem *clr_base; 604 605 struct mlx4_uar driver_uar; 606 void __iomem *kar; 607 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 608 struct mlx4_sense sense; 609 struct mutex port_mutex; 610 struct mlx4_msix_ctl msix_ctl; 611 struct mlx4_steer *steer; 612 struct list_head bf_list; 613 struct mutex bf_mutex; 614 struct io_mapping *bf_mapping; 615}; 616 617static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 618{ 619 return container_of(dev, struct mlx4_priv, dev); 620} 621 622#define MLX4_SENSE_RANGE (HZ * 3) 623 624extern struct workqueue_struct *mlx4_wq; 625 626u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 627void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); 628u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); 629void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); 630u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 631int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 632 u32 reserved_bot, u32 resetrved_top); 633void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 634 635int mlx4_reset(struct mlx4_dev *dev); 636 637int mlx4_alloc_eq_table(struct mlx4_dev *dev); 638void mlx4_free_eq_table(struct mlx4_dev *dev); 639 640int mlx4_init_pd_table(struct mlx4_dev *dev); 641int mlx4_init_xrcd_table(struct mlx4_dev *dev); 642int mlx4_init_uar_table(struct mlx4_dev *dev); 643int mlx4_init_mr_table(struct mlx4_dev *dev); 644int mlx4_init_eq_table(struct mlx4_dev *dev); 645int mlx4_init_cq_table(struct mlx4_dev *dev); 646int mlx4_init_qp_table(struct mlx4_dev *dev); 647int mlx4_init_srq_table(struct mlx4_dev *dev); 648int mlx4_init_mcg_table(struct mlx4_dev *dev); 649 650void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 651void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 652void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 653void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 654void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 655void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 656void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 657void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 658void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 659 660int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 661 struct mlx4_vhcr *vhcr, 662 struct mlx4_cmd_mailbox *inbox, 663 struct mlx4_cmd_mailbox *outbox, 664 struct mlx4_cmd_info *cmd); 665int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 666 struct mlx4_vhcr *vhcr, 667 struct mlx4_cmd_mailbox *inbox, 668 struct mlx4_cmd_mailbox *outbox, 669 struct mlx4_cmd_info *cmd); 670int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 671 struct mlx4_vhcr *vhcr, 672 struct mlx4_cmd_mailbox *inbox, 673 struct mlx4_cmd_mailbox *outbox, 674 struct mlx4_cmd_info *cmd); 675int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 676 struct mlx4_vhcr *vhcr, 677 struct mlx4_cmd_mailbox *inbox, 678 struct mlx4_cmd_mailbox *outbox, 679 struct mlx4_cmd_info *cmd); 680int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 681 struct mlx4_vhcr *vhcr, 682 struct mlx4_cmd_mailbox *inbox, 683 struct mlx4_cmd_mailbox *outbox, 684 struct mlx4_cmd_info *cmd); 685int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 686 struct mlx4_vhcr *vhcr, 687 struct mlx4_cmd_mailbox *inbox, 688 struct mlx4_cmd_mailbox *outbox, 689 struct mlx4_cmd_info *cmd); 690int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 691 struct mlx4_vhcr *vhcr, 692 struct mlx4_cmd_mailbox *inbox, 693 struct mlx4_cmd_mailbox *outbox, 694 struct mlx4_cmd_info *cmd); 695 696void mlx4_start_catas_poll(struct mlx4_dev *dev); 697void mlx4_stop_catas_poll(struct mlx4_dev *dev); 698void mlx4_catas_init(void); 699int mlx4_restart_one(struct pci_dev *pdev); 700int mlx4_register_device(struct mlx4_dev *dev); 701void mlx4_unregister_device(struct mlx4_dev *dev); 702void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port); 703 704struct mlx4_dev_cap; 705struct mlx4_init_hca_param; 706 707u64 mlx4_make_profile(struct mlx4_dev *dev, 708 struct mlx4_profile *request, 709 struct mlx4_dev_cap *dev_cap, 710 struct mlx4_init_hca_param *init_hca); 711void mlx4_master_comm_channel(struct work_struct *work); 712void mlx4_gen_slave_eqe(struct work_struct *work); 713void mlx4_master_handle_slave_flr(struct work_struct *work); 714 715int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 716 struct mlx4_vhcr *vhcr, 717 struct mlx4_cmd_mailbox *inbox, 718 struct mlx4_cmd_mailbox *outbox, 719 struct mlx4_cmd_info *cmd); 720int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 721 struct mlx4_vhcr *vhcr, 722 struct mlx4_cmd_mailbox *inbox, 723 struct mlx4_cmd_mailbox *outbox, 724 struct mlx4_cmd_info *cmd); 725int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 726 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 727 struct mlx4_cmd_mailbox *outbox, 728 struct mlx4_cmd_info *cmd); 729int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 730 struct mlx4_vhcr *vhcr, 731 struct mlx4_cmd_mailbox *inbox, 732 struct mlx4_cmd_mailbox *outbox, 733 struct mlx4_cmd_info *cmd); 734int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 735 struct mlx4_vhcr *vhcr, 736 struct mlx4_cmd_mailbox *inbox, 737 struct mlx4_cmd_mailbox *outbox, 738 struct mlx4_cmd_info *cmd); 739int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 740 struct mlx4_vhcr *vhcr, 741 struct mlx4_cmd_mailbox *inbox, 742 struct mlx4_cmd_mailbox *outbox, 743 struct mlx4_cmd_info *cmd); 744int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 745 struct mlx4_vhcr *vhcr, 746 struct mlx4_cmd_mailbox *inbox, 747 struct mlx4_cmd_mailbox *outbox, 748 struct mlx4_cmd_info *cmd); 749int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 750 struct mlx4_vhcr *vhcr, 751 struct mlx4_cmd_mailbox *inbox, 752 struct mlx4_cmd_mailbox *outbox, 753 struct mlx4_cmd_info *cmd); 754int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 755 struct mlx4_vhcr *vhcr, 756 struct mlx4_cmd_mailbox *inbox, 757 struct mlx4_cmd_mailbox *outbox, 758 struct mlx4_cmd_info *cmd); 759int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 760 struct mlx4_vhcr *vhcr, 761 struct mlx4_cmd_mailbox *inbox, 762 struct mlx4_cmd_mailbox *outbox, 763 struct mlx4_cmd_info *cmd); 764int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 765 struct mlx4_vhcr *vhcr, 766 struct mlx4_cmd_mailbox *inbox, 767 struct mlx4_cmd_mailbox *outbox, 768 struct mlx4_cmd_info *cmd); 769int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 770 struct mlx4_vhcr *vhcr, 771 struct mlx4_cmd_mailbox *inbox, 772 struct mlx4_cmd_mailbox *outbox, 773 struct mlx4_cmd_info *cmd); 774int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 775 struct mlx4_vhcr *vhcr, 776 struct mlx4_cmd_mailbox *inbox, 777 struct mlx4_cmd_mailbox *outbox, 778 struct mlx4_cmd_info *cmd); 779int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 780 struct mlx4_vhcr *vhcr, 781 struct mlx4_cmd_mailbox *inbox, 782 struct mlx4_cmd_mailbox *outbox, 783 struct mlx4_cmd_info *cmd); 784int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 785 struct mlx4_vhcr *vhcr, 786 struct mlx4_cmd_mailbox *inbox, 787 struct mlx4_cmd_mailbox *outbox, 788 struct mlx4_cmd_info *cmd); 789int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 790 struct mlx4_vhcr *vhcr, 791 struct mlx4_cmd_mailbox *inbox, 792 struct mlx4_cmd_mailbox *outbox, 793 struct mlx4_cmd_info *cmd); 794int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 795 struct mlx4_vhcr *vhcr, 796 struct mlx4_cmd_mailbox *inbox, 797 struct mlx4_cmd_mailbox *outbox, 798 struct mlx4_cmd_info *cmd); 799int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 800 struct mlx4_vhcr *vhcr, 801 struct mlx4_cmd_mailbox *inbox, 802 struct mlx4_cmd_mailbox *outbox, 803 struct mlx4_cmd_info *cmd); 804 805int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 806 807int mlx4_cmd_init(struct mlx4_dev *dev); 808void mlx4_cmd_cleanup(struct mlx4_dev *dev); 809void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 810int mlx4_cmd_use_events(struct mlx4_dev *dev); 811void mlx4_cmd_use_polling(struct mlx4_dev *dev); 812 813void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 814void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 815 816void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 817 818void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 819 820void mlx4_handle_catas_err(struct mlx4_dev *dev); 821 822int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 823 enum mlx4_port_type *type); 824void mlx4_do_sense_ports(struct mlx4_dev *dev, 825 enum mlx4_port_type *stype, 826 enum mlx4_port_type *defaults); 827void mlx4_start_sense(struct mlx4_dev *dev); 828void mlx4_stop_sense(struct mlx4_dev *dev); 829void mlx4_sense_init(struct mlx4_dev *dev); 830int mlx4_check_port_params(struct mlx4_dev *dev, 831 enum mlx4_port_type *port_type); 832int mlx4_change_port_types(struct mlx4_dev *dev, 833 enum mlx4_port_type *port_types); 834 835void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 836void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 837 838int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); 839/* resource tracker functions*/ 840int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 841 enum mlx4_resource resource_type, 842 int resource_id, int *slave); 843void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 844int mlx4_init_resource_tracker(struct mlx4_dev *dev); 845 846void mlx4_free_resource_tracker(struct mlx4_dev *dev); 847 848int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 849 struct mlx4_vhcr *vhcr, 850 struct mlx4_cmd_mailbox *inbox, 851 struct mlx4_cmd_mailbox *outbox, 852 struct mlx4_cmd_info *cmd); 853int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 854 struct mlx4_vhcr *vhcr, 855 struct mlx4_cmd_mailbox *inbox, 856 struct mlx4_cmd_mailbox *outbox, 857 struct mlx4_cmd_info *cmd); 858int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 859 struct mlx4_vhcr *vhcr, 860 struct mlx4_cmd_mailbox *inbox, 861 struct mlx4_cmd_mailbox *outbox, 862 struct mlx4_cmd_info *cmd); 863int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 864 struct mlx4_vhcr *vhcr, 865 struct mlx4_cmd_mailbox *inbox, 866 struct mlx4_cmd_mailbox *outbox, 867 struct mlx4_cmd_info *cmd); 868int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 869int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port); 870 871 872int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 873 struct mlx4_vhcr *vhcr, 874 struct mlx4_cmd_mailbox *inbox, 875 struct mlx4_cmd_mailbox *outbox, 876 struct mlx4_cmd_info *cmd); 877 878int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 879 struct mlx4_vhcr *vhcr, 880 struct mlx4_cmd_mailbox *inbox, 881 struct mlx4_cmd_mailbox *outbox, 882 struct mlx4_cmd_info *cmd); 883int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 884 enum mlx4_protocol prot, enum mlx4_steer_type steer); 885int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 886 int block_mcast_loopback, enum mlx4_protocol prot, 887 enum mlx4_steer_type steer); 888int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 889 struct mlx4_vhcr *vhcr, 890 struct mlx4_cmd_mailbox *inbox, 891 struct mlx4_cmd_mailbox *outbox, 892 struct mlx4_cmd_info *cmd); 893int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 894 struct mlx4_vhcr *vhcr, 895 struct mlx4_cmd_mailbox *inbox, 896 struct mlx4_cmd_mailbox *outbox, 897 struct mlx4_cmd_info *cmd); 898int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 899 int port, void *buf); 900int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 901 struct mlx4_cmd_mailbox *outbox); 902int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 903 struct mlx4_vhcr *vhcr, 904 struct mlx4_cmd_mailbox *inbox, 905 struct mlx4_cmd_mailbox *outbox, 906 struct mlx4_cmd_info *cmd); 907int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 908 struct mlx4_vhcr *vhcr, 909 struct mlx4_cmd_mailbox *inbox, 910 struct mlx4_cmd_mailbox *outbox, 911 struct mlx4_cmd_info *cmd); 912int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 913 struct mlx4_vhcr *vhcr, 914 struct mlx4_cmd_mailbox *inbox, 915 struct mlx4_cmd_mailbox *outbox, 916 struct mlx4_cmd_info *cmd); 917 918#define NOT_MASKED_PD_BITS 17 919 920#endif /* MLX4_H */ 921