1113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/****************************************************************************** 2113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * This software may be used and distributed according to the terms of 3113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the GNU General Public License (GPL), incorporated herein by reference. 4113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Drivers based on or derived from this code fall under the GPL and must 5113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * retain the authorship, copyright and license notice. This file is not 6113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * a complete program and may only be used when the entire operating 7113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * system is licensed under the GPL. 8113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See the file COPYING in this distribution for more information. 9113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 10926bd900b192986ccb742177b1492e8523579a35Jon Mason * vxge-traffic.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O 11113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Virtualized Server Adapter. 12926bd900b192986ccb742177b1492e8523579a35Jon Mason * Copyright(c) 2002-2010 Exar Corp. 13113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ******************************************************************************/ 14113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa#include <linux/etherdevice.h> 1570c71606190e9115e5f8363bfcd164c582eb314aPaul Gortmaker#include <linux/prefetch.h> 16113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 17113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa#include "vxge-traffic.h" 18113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa#include "vxge-config.h" 19113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa#include "vxge-main.h" 20113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 21113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 22113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_intr_enable - Enable vpath interrupts. 23113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Virtual Path handle. 24113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 25113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Enable vpath interrupts. The function is to be executed the last in 26113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vpath initialization sequence. 27113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 28113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_vpath_intr_disable() 29113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 30113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_vpath_intr_enable(struct __vxge_hw_vpath_handle *vp) 31113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 32113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64; 33113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 34113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_virtualpath *vpath; 35113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_vpath_reg __iomem *vp_reg; 36113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 37113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vp == NULL) { 38113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 39113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 40113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 41113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 42113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vpath = vp->vpath; 43113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 44113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { 45113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_VPATH_NOT_OPEN; 46113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 47113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 48113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 49113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vp_reg = vpath->vp_reg; 50113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 51113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg); 52113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 53113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 54113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->general_errors_reg); 55113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 56113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 57113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->pci_config_errors_reg); 58113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 59113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 60113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->mrpcim_to_vpath_alarm_reg); 61113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 62113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 63113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->srpcim_to_vpath_alarm_reg); 64113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 65113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 66113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->vpath_ppif_int_status); 67113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 68113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 69113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->srpcim_msg_to_vpath_reg); 70113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 71113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 72113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->vpath_pcipif_int_status); 73113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 74113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 75113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->prc_alarm_reg); 76113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 77113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 78113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->wrdma_alarm_status); 79113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 80113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 81113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->asic_ntwk_vp_err_reg); 82113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 83113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 84113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->xgmac_vp_int_status); 85113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 86113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = readq(&vp_reg->vpath_general_int_status); 87113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 88113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* Mask unwanted interrupts */ 89113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 90113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 91113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->vpath_pcipif_int_mask); 92113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 93113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 94113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->srpcim_msg_to_vpath_mask); 95113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 96113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 97113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->srpcim_to_vpath_alarm_mask); 98113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 99113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 100113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->mrpcim_to_vpath_alarm_mask); 101113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 102113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 103113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->pci_config_errors_mask); 104113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 105113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* Unmask the individual interrupts */ 106113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 107113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW| 108113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW| 109113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ| 110113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR), 0, 32), 111113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->general_errors_mask); 112113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 113113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 114113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (u32)vxge_bVALn((VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR| 115113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR| 116113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON| 117113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON| 118113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR| 119d77dd8d27e73a9277096453eb901aae0bfd4ca3croel kluin VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR), 0, 32), 120113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->kdfcctl_errors_mask); 121113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 122113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask); 123113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 124113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 125113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (u32)vxge_bVALn(VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, 0, 32), 126113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->prc_alarm_mask); 127113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 128113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask); 129113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask); 130113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 131113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vpath->hldev->first_vp_id != vpath->vp_id) 132113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 133113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->asic_ntwk_vp_err_mask); 134113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa else 135113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(( 136113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT | 137113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK), 0, 32), 138113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->asic_ntwk_vp_err_mask); 139113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 140113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper(0, 141113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->vpath_general_int_mask); 142113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 143113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 144113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 145113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 146113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 147113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 148113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_intr_disable - Disable vpath interrupts. 149113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Virtual Path handle. 150113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 151113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Disable vpath interrupts. The function is to be executed the last in 152113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vpath initialization sequence. 153113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 154113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_vpath_intr_enable() 155113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 156113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_vpath_intr_disable( 157113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_vpath_handle *vp) 158113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 159113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64; 160113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 161113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_virtualpath *vpath; 162113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 163113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_vpath_reg __iomem *vp_reg; 164113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vp == NULL) { 165113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 166113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 167113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 168113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 169113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vpath = vp->vpath; 170113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 171113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { 172113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_VPATH_NOT_OPEN; 173113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 174113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 175113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vp_reg = vpath->vp_reg; 176113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 177113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 178113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (u32)VXGE_HW_INTR_MASK_ALL, 179113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->vpath_general_int_mask); 180113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 181113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = VXGE_HW_TIM_CLR_INT_EN_VP(1 << (16 - vpath->vp_id)); 182113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 183113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask); 184113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 185113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 186113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->general_errors_mask); 187113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 188113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 189113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->pci_config_errors_mask); 190113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 191113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 192113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->mrpcim_to_vpath_alarm_mask); 193113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 194113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 195113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->srpcim_to_vpath_alarm_mask); 196113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 197113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 198113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->vpath_ppif_int_mask); 199113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 200113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 201113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->srpcim_msg_to_vpath_mask); 202113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 203113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 204113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->vpath_pcipif_int_mask); 205113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 206113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 207113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->wrdma_alarm_mask); 208113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 209113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 210113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->prc_alarm_mask); 211113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 212113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 213113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->xgmac_vp_int_mask); 214113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 215113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL, 216113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->asic_ntwk_vp_err_mask); 217113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 218113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 219113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 220113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 221113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 22216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Masonvoid vxge_hw_vpath_tti_ci_set(struct __vxge_hw_fifo *fifo) 22316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason{ 22416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason struct vxge_hw_vpath_reg __iomem *vp_reg; 22516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason struct vxge_hw_vp_config *config; 22616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason u64 val64; 22716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 22816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason if (fifo->config->enable != VXGE_HW_FIFO_ENABLE) 22916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason return; 23016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 23116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason vp_reg = fifo->vp_reg; 23216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason config = container_of(fifo->config, struct vxge_hw_vp_config, fifo); 23316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 23416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) { 23516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE; 23616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); 23716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; 23816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason fifo->tim_tti_cfg1_saved = val64; 23916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); 24016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason } 24116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason} 24216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 24316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Masonvoid vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring) 24416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason{ 24516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason u64 val64 = ring->tim_rti_cfg1_saved; 24616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 24716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; 24816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason ring->tim_rti_cfg1_saved = val64; 24916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason writeq(val64, &ring->vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); 25016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason} 25116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 25216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Masonvoid vxge_hw_vpath_dynamic_tti_rtimer_set(struct __vxge_hw_fifo *fifo) 25316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason{ 25416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason u64 val64 = fifo->tim_tti_cfg3_saved; 25516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason u64 timer = (fifo->rtimer * 1000) / 272; 25616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 25716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff); 25816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason if (timer) 25916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) | 26016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(5); 26116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 26216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason writeq(val64, &fifo->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); 26316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason /* tti_cfg3_saved is not updated again because it is 26416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * initialized at one place only - init time. 26516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason */ 26616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason} 26716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 26816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Masonvoid vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring) 26916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason{ 27016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason u64 val64 = ring->tim_rti_cfg3_saved; 27116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason u64 timer = (ring->rtimer * 1000) / 272; 27216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 27316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff); 27416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason if (timer) 27516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) | 27616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(4); 27716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 27816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason writeq(val64, &ring->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); 27916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason /* rti_cfg3_saved is not updated again because it is 28016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * initialized at one place only - init time. 28116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason */ 28216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason} 28316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 284113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 285113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_channel_msix_mask - Mask MSIX Vector. 286113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @channeh: Channel for rx or tx handle 287113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @msix_id: MSIX ID 288113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 289113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * The function masks the msix interrupt for the given msix_id 290113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 291113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: 0 292113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 293113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id) 294113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 295113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 296113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 297b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnur (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 298113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &channel->common_reg->set_msix_mask_vect[msix_id%4]); 299113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 300113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 301113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 302113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_channel_msix_unmask - Unmask the MSIX Vector. 303113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @channeh: Channel for rx or tx handle 304113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @msix_id: MSI ID 305113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 306113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * The function unmasks the msix interrupt for the given msix_id 307113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 308113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: 0 309113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 310113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid 311113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id) 312113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 313113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 314113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 315b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnur (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 316113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &channel->common_reg->clear_msix_mask_vect[msix_id%4]); 317113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 318113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 319113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 32016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * vxge_hw_channel_msix_clear - Unmask the MSIX Vector. 32116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * @channel: Channel for rx or tx handle 32216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * @msix_id: MSI ID 32316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * 32416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * The function unmasks the msix interrupt for the given msix_id 32516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * if configured in MSIX oneshot mode 32616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * 32716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * Returns: 0 32816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason */ 32916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Masonvoid vxge_hw_channel_msix_clear(struct __vxge_hw_channel *channel, int msix_id) 33016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason{ 33116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason __vxge_hw_pio_mem_write32_upper( 33216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 33316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason &channel->common_reg->clr_msix_one_shot_vec[msix_id % 4]); 33416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason} 33516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 33616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason/** 337113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_device_set_intr_type - Updates the configuration 338113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * with new interrupt type. 339113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @hldev: HW device handle. 340113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @intr_mode: New interrupt type 341113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 342113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepau32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *hldev, u32 intr_mode) 343113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 344113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 345113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if ((intr_mode != VXGE_HW_INTR_MODE_IRQLINE) && 346113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (intr_mode != VXGE_HW_INTR_MODE_MSIX) && 347113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) && 348113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (intr_mode != VXGE_HW_INTR_MODE_DEF)) 349113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa intr_mode = VXGE_HW_INTR_MODE_IRQLINE; 350113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 351113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa hldev->config.intr_mode = intr_mode; 352113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return intr_mode; 353113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 354113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 355113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 356113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_device_intr_enable - Enable interrupts. 357113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @hldev: HW device handle. 358113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @op: One of the enum vxge_hw_device_intr enumerated values specifying 359113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the type(s) of interrupts to enable. 360113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 361113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Enable Titan interrupts. The function is to be executed the last in 362113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Titan initialization sequence. 363113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 364113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_device_intr_disable() 365113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 366113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev) 367113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 368113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 i; 369113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64; 370113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 val32; 371113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 372eb5f10c21badd967aa466fd4f7eddfc724c8cb64Sreenivasa Honnur vxge_hw_device_mask_all(hldev); 373eb5f10c21badd967aa466fd4f7eddfc724c8cb64Sreenivasa Honnur 374113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 375113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 376113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (!(hldev->vpaths_deployed & vxge_mBIT(i))) 377113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa continue; 378113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 379113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_vpath_intr_enable( 380113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i])); 381113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 382113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 383113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE) { 384113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | 385113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]; 386113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 387113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (val64 != 0) { 388113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(val64, &hldev->common_reg->tim_int_status0); 389113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 390113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(~val64, &hldev->common_reg->tim_int_mask0); 391113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 392113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 393113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | 394113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]; 395113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 396113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (val32 != 0) { 397113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper(val32, 398113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->tim_int_status1); 399113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 400113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper(~val32, 401113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->tim_int_mask1); 402113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 403113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 404113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 405113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = readq(&hldev->common_reg->titan_general_int_status); 406113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 407113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_device_unmask_all(hldev); 408113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 409113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 410113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 411113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_device_intr_disable - Disable Titan interrupts. 412113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @hldev: HW device handle. 413113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @op: One of the enum vxge_hw_device_intr enumerated values specifying 414113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the type(s) of interrupts to disable. 415113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 416113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Disable Titan interrupts. 417113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 418113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_device_intr_enable() 419113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 420113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev) 421113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 422113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 i; 423113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 424113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_device_mask_all(hldev); 425113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 426113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* mask all the tim interrupts */ 427113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0); 428113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32, 429113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->tim_int_mask1); 430113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 431113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 432113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 433113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (!(hldev->vpaths_deployed & vxge_mBIT(i))) 434113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa continue; 435113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 436113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_vpath_intr_disable( 437113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i])); 438113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 439113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 440113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 441113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 442113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_device_mask_all - Mask all device interrupts. 443113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @hldev: HW device handle. 444113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 445113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Mask all device interrupts. 446113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 447113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_device_unmask_all() 448113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 449113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_device_mask_all(struct __vxge_hw_device *hldev) 450113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 451113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64; 452113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 453113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM | 454113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC; 455113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 456113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 457113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->titan_mask_all_int); 458113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 459113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 460113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 461113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_device_unmask_all - Unmask all device interrupts. 462113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @hldev: HW device handle. 463113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 464113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Unmask all device interrupts. 465113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 466113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_device_mask_all() 467113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 468113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev) 469113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 470113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64 = 0; 471113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 472113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE) 473113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC; 474113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 475113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 476113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->titan_mask_all_int); 477113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 478113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 479113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 480113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_device_flush_io - Flush io writes. 481113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @hldev: HW device handle. 482113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 483113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * The function performs a read operation to flush io writes. 484113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 485113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: void 486113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 487113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_device_flush_io(struct __vxge_hw_device *hldev) 488113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 489113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 val32; 490113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 491113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val32 = readl(&hldev->common_reg->titan_general_int_status); 492113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 493113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 494113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 495113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * __vxge_hw_device_handle_error - Handle error 496113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @hldev: HW device 497113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp_id: Vpath Id 498113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @type: Error type. Please see enum vxge_hw_event{} 499113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 500113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Handle error. 501113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 50242821a5b393e36f5c0b267473d59d375578df7ecstephen hemmingerstatic enum vxge_hw_status 503528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason__vxge_hw_device_handle_error(struct __vxge_hw_device *hldev, u32 vp_id, 504528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_event type) 505113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 506113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa switch (type) { 507113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_UNKNOWN: 508113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa break; 509113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_RESET_START: 510113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_RESET_COMPLETE: 511113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_LINK_DOWN: 512113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_LINK_UP: 513113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto out; 514113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_ALARM_CLEARED: 515113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto out; 516113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_ECCERR: 517113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_MRPCIM_ECCERR: 518113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto out; 519113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_FIFO_ERR: 520113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_VPATH_ERR: 521113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_CRITICAL_ERR: 522113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_SERR: 523113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa break; 524113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_SRPCIM_SERR: 525113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_MRPCIM_SERR: 526113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto out; 527113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_EVENT_SLOT_FREEZE: 528113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa break; 529113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa default: 530113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_assert(0); 531113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto out; 532113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 533113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 534113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* notify driver */ 535956a206620fa048afdcd8ab714ac3cf6a9e884b7stephen hemminger if (hldev->uld_callbacks->crit_err) 536956a206620fa048afdcd8ab714ac3cf6a9e884b7stephen hemminger hldev->uld_callbacks->crit_err( 537113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (struct __vxge_hw_device *)hldev, 538113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa type, vp_id); 539113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaout: 540113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 541113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return VXGE_HW_OK; 542113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 543113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 544528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/* 545528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * __vxge_hw_device_handle_link_down_ind 546528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @hldev: HW device handle. 547113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 548528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Link down indication handler. The function is invoked by HW when 549528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Titan indicates that the link is down. 550113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 551528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonstatic enum vxge_hw_status 552528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason__vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev) 553113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 554528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason /* 555528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * If the previous link state is not down, return. 556528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 557528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (hldev->link_state == VXGE_HW_LINK_DOWN) 558528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 559113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 560528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->link_state = VXGE_HW_LINK_DOWN; 561113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 562528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason /* notify driver */ 563956a206620fa048afdcd8ab714ac3cf6a9e884b7stephen hemminger if (hldev->uld_callbacks->link_down) 564956a206620fa048afdcd8ab714ac3cf6a9e884b7stephen hemminger hldev->uld_callbacks->link_down(hldev); 565528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 566528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_OK; 567113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 568113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 569113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 570528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * __vxge_hw_device_handle_link_up_ind 571528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @hldev: HW device handle. 572113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 573528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Link up indication handler. The function is invoked by HW when 574528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Titan indicates that the link is up for programmable amount of time. 575113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 57642821a5b393e36f5c0b267473d59d375578df7ecstephen hemmingerstatic enum vxge_hw_status 577528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason__vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev) 578113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 579528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason /* 580528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * If the previous link state is not down, return. 581528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 582528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (hldev->link_state == VXGE_HW_LINK_UP) 583528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 584113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 585528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->link_state = VXGE_HW_LINK_UP; 586113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 587528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason /* notify driver */ 588956a206620fa048afdcd8ab714ac3cf6a9e884b7stephen hemminger if (hldev->uld_callbacks->link_up) 589956a206620fa048afdcd8ab714ac3cf6a9e884b7stephen hemminger hldev->uld_callbacks->link_up(hldev); 590528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 591528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_OK; 592113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 593113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 594113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 595528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * __vxge_hw_vpath_alarm_process - Process Alarms. 596528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vpath: Virtual Path. 597528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @skip_alarms: Do not clear the alarms 598113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 599528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Process vpath alarms. 600113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 601113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 602528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonstatic enum vxge_hw_status 603528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason__vxge_hw_vpath_alarm_process(struct __vxge_hw_virtualpath *vpath, 604528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u32 skip_alarms) 605113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 606528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 val64; 607528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 alarm_status; 608528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 pic_status; 609528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_device *hldev = NULL; 610528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_event alarm_event = VXGE_HW_EVENT_UNKNOWN; 611528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 mask64; 612528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct vxge_hw_vpath_stats_sw_info *sw_stats; 613528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct vxge_hw_vpath_reg __iomem *vp_reg; 614528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 615528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (vpath == NULL) { 616528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN, 617528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 618528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto out2; 619528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 620528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 621528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev = vpath->hldev; 622528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason vp_reg = vpath->vp_reg; 623528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_status = readq(&vp_reg->vpath_general_int_status); 624528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 625528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (alarm_status == VXGE_HW_ALL_FOXES) { 626528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_SLOT_FREEZE, 627528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 628528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto out; 629528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 630528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 631528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats = vpath->sw_stats; 632528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 633528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (alarm_status & ~( 634528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT | 635528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT | 636528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT | 637528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) { 638528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.unknown_alarms++; 639528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 640528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN, 641528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 642528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto out; 643528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 644528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 645528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) { 646528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 647528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vp_reg->xgmac_vp_int_status); 648528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 649528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (val64 & 650528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) { 651528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 652528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vp_reg->asic_ntwk_vp_err_reg); 653528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 654528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (((val64 & 655528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) && 656528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (!(val64 & 657528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) || 658528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ((val64 & 659528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) && 660528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (!(val64 & 661528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) 662528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ))) { 663528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.network_sustained_fault++; 664528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 665528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq( 666528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT, 667528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &vp_reg->asic_ntwk_vp_err_mask); 668528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 669528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason __vxge_hw_device_handle_link_down_ind(hldev); 670528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 671528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_LINK_DOWN, alarm_event); 672528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 673528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 674528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (((val64 & 675528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) && 676528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (!(val64 & 677528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) || 678528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ((val64 & 679528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) && 680528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (!(val64 & 681528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) 682528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ))) { 683528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 684528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.network_sustained_ok++; 685528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 686528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq( 687528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK, 688528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &vp_reg->asic_ntwk_vp_err_mask); 689528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 690528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason __vxge_hw_device_handle_link_up_ind(hldev); 691528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 692528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_LINK_UP, alarm_event); 693528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 694528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 695528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(VXGE_HW_INTR_MASK_ALL, 696528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &vp_reg->asic_ntwk_vp_err_reg); 697528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 698528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 699528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_ALARM_CLEARED, alarm_event); 700528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 701528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (skip_alarms) 702528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_OK; 703528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 704528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 705528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 706528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT) { 707528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 708528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason pic_status = readq(&vp_reg->vpath_ppif_int_status); 709528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 710528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (pic_status & 711528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT) { 712528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 713528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vp_reg->general_errors_reg); 714528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason mask64 = readq(&vp_reg->general_errors_mask); 715528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 716528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & 717528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET) & 718528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) { 719528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.ini_serr_det++; 720528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 721528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 722528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_SERR, alarm_event); 723528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 724528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 725528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & 726528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) & 727528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) { 728528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.dblgen_fifo0_overflow++; 729528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 730528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 731528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_FIFO_ERR, alarm_event); 732528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 733528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 734528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & 735528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) & 736528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) 737528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.statsb_pif_chain_error++; 738528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 739528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & 740528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ) & 741528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) 742528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.statsb_drop_timeout++; 743528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 744528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & 745528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) & 746528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) 747528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.target_illegal_access++; 748528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 749528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (!skip_alarms) { 750528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(VXGE_HW_INTR_MASK_ALL, 751528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &vp_reg->general_errors_reg); 752528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 753528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_ALARM_CLEARED, 754528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 755528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 756528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 757528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 758528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (pic_status & 759528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT) { 760528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 761528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vp_reg->kdfcctl_errors_reg); 762528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason mask64 = readq(&vp_reg->kdfcctl_errors_mask); 763528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 764528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & 765528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) & 766528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) { 767528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.kdfcctl_fifo0_overwrite++; 768528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 769528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 770528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_FIFO_ERR, 771528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 772528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 773528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 774528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & 775528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) & 776528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) { 777528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.kdfcctl_fifo0_poison++; 778528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 779528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 780528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_FIFO_ERR, 781528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 782528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 783528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 784528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & 785528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) & 786528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) { 787528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.kdfcctl_fifo0_dma_error++; 788528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 789528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 790528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_FIFO_ERR, 791528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 792528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 793528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 794528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (!skip_alarms) { 795528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(VXGE_HW_INTR_MASK_ALL, 796528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &vp_reg->kdfcctl_errors_reg); 797528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 798528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_ALARM_CLEARED, 799528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 800528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 801528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 802528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 803528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 804528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 805528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT) { 806528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 807528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vp_reg->wrdma_alarm_status); 808528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 809528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (val64 & VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) { 810528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 811528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vp_reg->prc_alarm_reg); 812528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason mask64 = readq(&vp_reg->prc_alarm_mask); 813528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 814528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP)& 815528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) 816528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.prc_ring_bumps++; 817528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 818528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) & 819528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ~mask64) { 820528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.prc_rxdcm_sc_err++; 821528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 822528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 823528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_VPATH_ERR, 824528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 825528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 826528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 827528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT) 828528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason & ~mask64) { 829528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.prc_rxdcm_sc_abort++; 830528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 831528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 832528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_VPATH_ERR, 833528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 834528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 835528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 836528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR) 837528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason & ~mask64) { 838528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason sw_stats->error_stats.prc_quanta_size_err++; 839528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 840528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 841528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_VPATH_ERR, 842528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 843528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 844528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 845528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (!skip_alarms) { 846528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(VXGE_HW_INTR_MASK_ALL, 847528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &vp_reg->prc_alarm_reg); 848528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event = VXGE_HW_SET_LEVEL( 849528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_EVENT_ALARM_CLEARED, 850528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason alarm_event); 851528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 852528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 853528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 854528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonout: 855528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->stats.sw_dev_err_stats.vpath_alarms++; 856528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonout2: 857528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((alarm_event == VXGE_HW_EVENT_ALARM_CLEARED) || 858528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (alarm_event == VXGE_HW_EVENT_UNKNOWN)) 859528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_OK; 860528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 861528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason __vxge_hw_device_handle_error(hldev, vpath->vp_id, alarm_event); 862528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 863528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (alarm_event == VXGE_HW_EVENT_SERR) 864528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_ERR_CRITICAL; 865528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 866528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return (alarm_event == VXGE_HW_EVENT_SLOT_FREEZE) ? 867528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ERR_SLOT_FREEZE : 868528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (alarm_event == VXGE_HW_EVENT_FIFO_ERR) ? VXGE_HW_ERR_FIFO : 869528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_ERR_VPATH; 870528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 871528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 872528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/** 873528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_device_begin_irq - Begin IRQ processing. 874528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @hldev: HW device handle. 875528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @skip_alarms: Do not clear the alarms 876528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @reason: "Reason" for the interrupt, the value of Titan's 877528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * general_int_status register. 878528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 879528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * The function performs two actions, It first checks whether (shared IRQ) the 880528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * interrupt was raised by the device. Next, it masks the device interrupts. 881528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 882528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Note: 883528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_device_begin_irq() does not flush MMIO writes through the 884528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * bridge. Therefore, two back-to-back interrupts are potentially possible. 885528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 886528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Returns: 0, if the interrupt is not "ours" (note that in this case the 887528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * device remain enabled). 888528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter 889528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * status. 890528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 891528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev, 892528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u32 skip_alarms, u64 *reason) 893528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 894528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u32 i; 895528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 val64; 896528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 adapter_status; 897528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 vpath_mask; 898528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_status ret = VXGE_HW_OK; 899528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 900528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&hldev->common_reg->titan_general_int_status); 901528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 902528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (unlikely(!val64)) { 903528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason /* not Titan interrupt */ 904528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason *reason = 0; 905528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ret = VXGE_HW_ERR_WRONG_IRQ; 906528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 907528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 908528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 909528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (unlikely(val64 == VXGE_HW_ALL_FOXES)) { 910528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 911528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason adapter_status = readq(&hldev->common_reg->adapter_status); 912528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 913528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (adapter_status == VXGE_HW_ALL_FOXES) { 914528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 915528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason __vxge_hw_device_handle_error(hldev, 916528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason NULL_VPID, VXGE_HW_EVENT_SLOT_FREEZE); 917528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason *reason = 0; 918528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ret = VXGE_HW_ERR_SLOT_FREEZE; 919528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 920528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 921528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 922528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 923528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->stats.sw_dev_info_stats.total_intr_cnt++; 924528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 925528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason *reason = val64; 926528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 927528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason vpath_mask = hldev->vpaths_deployed >> 928528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (64 - VXGE_HW_MAX_VIRTUAL_PATHS); 929528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 930528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (val64 & 931528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(vpath_mask)) { 932528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->stats.sw_dev_info_stats.traffic_intr_cnt++; 933528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 934528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_OK; 935528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 936528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 937528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt++; 938528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 939528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (unlikely(val64 & 940528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) { 941528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 942528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_status error_level = VXGE_HW_OK; 943528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 944528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->stats.sw_dev_err_stats.vpath_alarms++; 945528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 946528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 947528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 948528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (!(hldev->vpaths_deployed & vxge_mBIT(i))) 949528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason continue; 950528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 951528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ret = __vxge_hw_vpath_alarm_process( 952528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &hldev->virtual_paths[i], skip_alarms); 953528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 954528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason error_level = VXGE_HW_SET_LEVEL(ret, error_level); 955528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 956528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (unlikely((ret == VXGE_HW_ERR_CRITICAL) || 957528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (ret == VXGE_HW_ERR_SLOT_FREEZE))) 958528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason break; 959528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 960528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 961528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason ret = error_level; 962528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 963528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 964528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return ret; 965528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 966528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 967528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/** 968528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the 969528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * condition that has caused the Tx and RX interrupt. 970528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @hldev: HW device. 971528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 972528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Acknowledge (that is, clear) the condition that has caused 973528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * the Tx and Rx interrupt. 974528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * See also: vxge_hw_device_begin_irq(), 975528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx(). 976528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 977528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonvoid vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev) 978528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 979528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 980528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) || 981528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) { 982528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | 983528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]), 984528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &hldev->common_reg->tim_int_status0); 985528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 986528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 987528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) || 988528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) { 989528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason __vxge_hw_pio_mem_write32_upper( 990528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | 991528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]), 992528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason &hldev->common_reg->tim_int_status1); 993528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 994528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 995528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 996528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/* 997528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_channel_dtr_alloc - Allocate a dtr from the channel 998528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @channel: Channel 999528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @dtrh: Buffer to return the DTR pointer 1000528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 1001528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Allocates a dtr from the reserve array. If the reserve array is empty, 1002528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * it swaps the reserve and free arrays. 1003528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 1004528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 1005528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonstatic enum vxge_hw_status 1006528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonvxge_hw_channel_dtr_alloc(struct __vxge_hw_channel *channel, void **dtrh) 1007528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 1008528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason void **tmp_arr; 1009528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1010528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (channel->reserve_ptr - channel->reserve_top > 0) { 1011528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason_alloc_after_swap: 1012528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason *dtrh = channel->reserve_arr[--channel->reserve_ptr]; 1013528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1014528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_OK; 1015528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 1016528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1017528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason /* switch between empty and full arrays */ 1018528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1019528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason /* the idea behind such a design is that by having free and reserved 1020528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * arrays separated we basically separated irq and non-irq parts. 1021528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * i.e. no additional lock need to be done when we free a resource */ 1022528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1023528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (channel->length - channel->free_ptr > 0) { 1024528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1025528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason tmp_arr = channel->reserve_arr; 1026528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason channel->reserve_arr = channel->free_arr; 1027528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason channel->free_arr = tmp_arr; 1028528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason channel->reserve_ptr = channel->length; 1029528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason channel->reserve_top = channel->free_ptr; 1030528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason channel->free_ptr = channel->length; 1031528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1032528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason channel->stats->reserve_free_swaps_cnt++; 1033528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1034528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto _alloc_after_swap; 1035528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 1036528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1037528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason channel->stats->full_cnt++; 1038528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1039528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason *dtrh = NULL; 1040528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_INF_OUT_OF_DESCRIPTORS; 1041528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 1042528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1043528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/* 1044528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_channel_dtr_post - Post a dtr to the channel 1045528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @channelh: Channel 1046528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @dtrh: DTR pointer 1047528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 1048528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Posts a dtr to work array. 1049528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 1050528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 1051528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonstatic void 1052528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonvxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh) 1053528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 1054528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason vxge_assert(channel->work_arr[channel->post_index] == NULL); 1055528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1056113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel->work_arr[channel->post_index++] = dtrh; 1057113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1058113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* wrap-around */ 1059113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (channel->post_index == channel->length) 1060113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel->post_index = 0; 1061113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1062113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1063113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 1064113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_channel_dtr_try_complete - Returns next completed dtr 1065113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @channel: Channel 1066113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @dtr: Buffer to return the next completed DTR pointer 1067113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1068113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns the next completed dtr with out removing it from work array 1069113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1070113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1071113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid 1072113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel, void **dtrh) 1073113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1074113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_assert(channel->compl_index < channel->length); 1075113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1076113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa *dtrh = channel->work_arr[channel->compl_index]; 10773f23e436d241ac1cf50a659228a5a0e1e6572c1aBenjamin LaHaise prefetch(*dtrh); 1078113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1079113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1080113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 1081113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_channel_dtr_complete - Removes next completed dtr from the work array 1082113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @channel: Channel handle 1083113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1084113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Removes the next completed dtr from work array 1085113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1086113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1087113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel) 1088113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1089113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel->work_arr[channel->compl_index] = NULL; 1090113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1091113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* wrap-around */ 1092113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (++channel->compl_index == channel->length) 1093113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel->compl_index = 0; 1094113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1095113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel->stats->total_compl_cnt++; 1096113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1097113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1098113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 1099113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_channel_dtr_free - Frees a dtr 1100113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @channel: Channel handle 1101113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @dtr: DTR pointer 1102113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1103113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns the dtr to free array 1104113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1105113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1106113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh) 1107113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1108113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel->free_arr[--channel->free_ptr] = dtrh; 1109113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1110113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1111113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 1112113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_channel_dtr_count 1113113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @channel: Channel handle. Obtained via vxge_hw_channel_open(). 1114113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 111525985edcedea6396277003854657b5f3cb31a628Lucas De Marchi * Retrieve number of DTRs available. This function can not be called 1116113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * from data path. ring_initial_replenishi() is the only user. 1117113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1118113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaint vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel) 1119113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1120113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return (channel->reserve_ptr - channel->reserve_top) + 1121113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (channel->length - channel->free_ptr); 1122113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1123113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1124113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1125113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_reserve - Reserve ring descriptor. 1126113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 1127113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @rxdh: Reserved descriptor. On success HW fills this "out" parameter 1128113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * with a valid handle. 1129113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1130113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Reserve Rx descriptor for the subsequent filling-in driver 1131113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * and posting on the corresponding channel (@channelh) 1132113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * via vxge_hw_ring_rxd_post(). 1133113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1134113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: VXGE_HW_OK - success. 1135113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available. 1136113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1137113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1138113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_ring_rxd_reserve(struct __vxge_hw_ring *ring, 1139113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa void **rxdh) 1140113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1141113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status; 1142113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1143113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1144113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &ring->channel; 1145113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1146113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = vxge_hw_channel_dtr_alloc(channel, rxdh); 1147113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1148113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (status == VXGE_HW_OK) { 1149113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_ring_rxd_1 *rxdp = 1150113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (struct vxge_hw_ring_rxd_1 *)*rxdh; 1151113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1152113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa rxdp->control_0 = rxdp->control_1 = 0; 1153113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1154113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1155113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1156113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1157113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1158113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1159113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_free - Free descriptor. 1160113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 1161113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @rxdh: Descriptor handle. 1162113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1163113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Free the reserved descriptor. This operation is "symmetrical" to 1164113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_reserve. The "free-ing" completes the descriptor's 1165113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * lifecycle. 1166113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1167113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * After free-ing (see vxge_hw_ring_rxd_free()) the descriptor again can 1168113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * be: 1169113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1170113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * - reserved (vxge_hw_ring_rxd_reserve); 1171113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1172113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * - posted (vxge_hw_ring_rxd_post); 1173113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1174113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * - completed (vxge_hw_ring_rxd_next_completed); 1175113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1176113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * - and recycled again (vxge_hw_ring_rxd_free). 1177113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1178113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * For alternative state transitions and more details please refer to 1179113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the design doc. 1180113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1181113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1182113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_ring_rxd_free(struct __vxge_hw_ring *ring, void *rxdh) 1183113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1184113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1185113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1186113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &ring->channel; 1187113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1188113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_free(channel, rxdh); 1189113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1190113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1191113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1192113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1193113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_pre_post - Prepare rxd and post 1194113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 1195113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @rxdh: Descriptor handle. 1196113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1197113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * This routine prepares a rxd and posts 1198113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1199113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_ring_rxd_pre_post(struct __vxge_hw_ring *ring, void *rxdh) 1200113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1201113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1202113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1203113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &ring->channel; 1204113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1205113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_post(channel, rxdh); 1206113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1207113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1208113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1209113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_post_post - Process rxd after post. 1210113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 1211113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @rxdh: Descriptor handle. 1212113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1213113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Processes rxd after post 1214113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1215113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_ring_rxd_post_post(struct __vxge_hw_ring *ring, void *rxdh) 1216113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1217113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; 1218113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1219113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1220113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &ring->channel; 1221113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 122218dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER; 1223113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1224113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (ring->stats->common_stats.usage_cnt > 0) 1225113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->stats->common_stats.usage_cnt--; 1226113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1227113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1228113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1229113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_post - Post descriptor on the ring. 1230113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 1231113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @rxdh: Descriptor obtained via vxge_hw_ring_rxd_reserve(). 1232113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1233113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Post descriptor on the ring. 1234113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Prior to posting the descriptor should be filled in accordance with 1235113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Host/Titan interface specification for a given service (LL, etc.). 1236113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1237113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1238113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring, void *rxdh) 1239113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1240113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; 1241113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1242113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1243113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &ring->channel; 1244113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1245113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa wmb(); 124618dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER; 1247113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1248113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_post(channel, rxdh); 1249113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1250113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (ring->stats->common_stats.usage_cnt > 0) 1251113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->stats->common_stats.usage_cnt--; 1252113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1253113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1254113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1255113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_post_post_wmb - Process rxd after post with memory barrier. 1256113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 1257113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @rxdh: Descriptor handle. 1258113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1259113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Processes rxd after post with memory barrier. 1260113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1261113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_ring_rxd_post_post_wmb(struct __vxge_hw_ring *ring, void *rxdh) 1262113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1263113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa wmb(); 1264113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_ring_rxd_post_post(ring, rxdh); 1265113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1266113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1267113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1268113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_next_completed - Get the _next_ completed descriptor. 1269113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 1270113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @rxdh: Descriptor handle. Returned by HW. 1271113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @t_code: Transfer code, as per Titan User Guide, 1272113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Receive Descriptor Format. Returned by HW. 1273113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1274113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Retrieve the _next_ completed descriptor. 1275113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * HW uses ring callback (*vxge_hw_ring_callback_f) to notifiy 1276113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * driver of new completed descriptors. After that 1277113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the driver can use vxge_hw_ring_rxd_next_completed to retrieve the rest 1278113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * completions (the very first completion is passed by HW via 1279113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_callback_f). 1280113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1281113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Implementation-wise, the driver is free to call 1282113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_rxd_next_completed either immediately from inside the 1283113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * ring callback, or in a deferred fashion and separate (from HW) 1284113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * context. 1285113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1286113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Non-zero @t_code means failure to fill-in receive buffer(s) 1287113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * of the descriptor. 1288113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * For instance, parity error detected during the data transfer. 1289113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * In this case Titan will complete the descriptor and indicate 1290113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * for the host that the received data is not to be used. 1291113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * For details please refer to Titan User Guide. 1292113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1293113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: VXGE_HW_OK - success. 1294113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors 1295113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * are currently available for processing. 1296113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1297113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_ring_callback_f{}, 1298113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_rxd_next_completed(), enum vxge_hw_status{}. 1299113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1300113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_ring_rxd_next_completed( 1301113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_ring *ring, void **rxdh, u8 *t_code) 1302113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1303113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1304113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_ring_rxd_1 *rxdp; 1305113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 130618dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur u64 control_0, own; 1307113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1308113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &ring->channel; 1309113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1310113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_try_complete(channel, rxdh); 1311113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 131243d620c82985b19008d87a437b4cf83f356264f7Joe Perches rxdp = *rxdh; 1313113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (rxdp == NULL) { 1314113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; 1315113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1316113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1317113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 131818dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur control_0 = rxdp->control_0; 131918dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur own = control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER; 132018dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur *t_code = (u8)VXGE_HW_RING_RXD_T_CODE_GET(control_0); 132118dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur 1322113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* check whether it is not the end */ 1323a7dd6027e55992dd7c409a71a4a2b576fda2f7c2Dan Carpenter if (!own || *t_code == VXGE_HW_RING_T_CODE_FRM_DROP) { 1324113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1325113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_assert(((struct vxge_hw_ring_rxd_1 *)rxdp)->host_control != 1326113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 0); 1327113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1328113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ++ring->cmpl_cnt; 1329113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_complete(channel); 1330113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1331113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_assert(*t_code != VXGE_HW_RING_RXD_T_CODE_UNUSED); 1332113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1333113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->stats->common_stats.usage_cnt++; 1334113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (ring->stats->common_stats.usage_max < 1335113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->stats->common_stats.usage_cnt) 1336113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->stats->common_stats.usage_max = 1337113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->stats->common_stats.usage_cnt; 1338113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1339113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_OK; 1340113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1341113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1342113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1343113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* reset it. since we don't want to return 1344113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * garbage to the driver */ 1345113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa *rxdh = NULL; 1346113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; 1347113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1348113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1349113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1350113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1351113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1352113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_ring_handle_tcode - Handle transfer code. 1353113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 1354113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @rxdh: Descriptor handle. 1355113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @t_code: One of the enumerated (and documented in the Titan user guide) 1356113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * "transfer codes". 1357113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1358113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Handle descriptor's transfer code. The latter comes with each completed 1359113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * descriptor. 1360113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1361113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: one of the enum vxge_hw_status{} enumerated types. 1362113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_OK - for success. 1363113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_ERR_CRITICAL - when encounters critical error. 1364113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1365113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_ring_handle_tcode( 1366113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_ring *ring, void *rxdh, u8 t_code) 1367113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1368113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1369113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1370113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1371113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &ring->channel; 1372113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1373113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* If the t_code is not supported and if the 1374113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * t_code is other than 0x5 (unparseable packet 1375113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * such as unknown UPV6 header), Drop it !!! 1376113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1377113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 137818dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur if (t_code == VXGE_HW_RING_T_CODE_OK || 137918dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur t_code == VXGE_HW_RING_T_CODE_L3_PKT_ERR) { 1380113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_OK; 1381113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1382113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1383113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 138418dec74c16abaa92d663dfef64ee6503e085be89Sreenivasa Honnur if (t_code > VXGE_HW_RING_T_CODE_MULTI_ERR) { 1385113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_TCODE; 1386113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1387113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1388113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1389113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->stats->rxd_t_code_err_cnt[t_code]++; 1390113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1391113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1392113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1393113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1394113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1395113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * __vxge_hw_non_offload_db_post - Post non offload doorbell 1396113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1397113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifo: fifohandle 1398113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @txdl_ptr: The starting location of the TxDL in host memory 1399113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256) 1400113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @no_snoop: No snoop flags 1401113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1402113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * This function posts a non-offload doorbell to doorbell FIFO 1403113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1404113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1405113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepastatic void __vxge_hw_non_offload_db_post(struct __vxge_hw_fifo *fifo, 1406113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 txdl_ptr, u32 num_txds, u32 no_snoop) 1407113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1408113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1409113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1410113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &fifo->channel; 1411113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1412113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(VXGE_HW_NODBW_TYPE(VXGE_HW_NODBW_TYPE_NODBW) | 1413113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_NODBW_LAST_TXD_NUMBER(num_txds) | 1414113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_NODBW_GET_NO_SNOOP(no_snoop), 1415113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &fifo->nofl_db->control_0); 1416113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1417ff1b974cf30b282f90993ab658e59b73c152c0b8Benjamin LaHaise mmiowb(); 1418113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1419113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr); 1420113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1421ff1b974cf30b282f90993ab658e59b73c152c0b8Benjamin LaHaise mmiowb(); 1422113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1423113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1424113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1425113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_free_txdl_count_get - returns the number of txdls available in 1426113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the fifo 1427113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifoh: Handle to the fifo object used for non offload send 1428113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1429113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepau32 vxge_hw_fifo_free_txdl_count_get(struct __vxge_hw_fifo *fifoh) 1430113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1431113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return vxge_hw_channel_dtr_count(&fifoh->channel); 1432113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1433113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1434113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1435113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_txdl_reserve - Reserve fifo descriptor. 1436113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifoh: Handle to the fifo object used for non offload send 1437113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @txdlh: Reserved descriptor. On success HW fills this "out" parameter 1438113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * with a valid handle. 1439113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @txdl_priv: Buffer to return the pointer to per txdl space 1440113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1441113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Reserve a single TxDL (that is, fifo descriptor) 1442113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * for the subsequent filling-in by driver) 1443113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * and posting on the corresponding channel (@channelh) 1444113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * via vxge_hw_fifo_txdl_post(). 1445113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1446113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Note: it is the responsibility of driver to reserve multiple descriptors 1447113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor 1448113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * carries up to configured number (fifo.max_frags) of contiguous buffers. 1449113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1450113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: VXGE_HW_OK - success; 1451113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available 1452113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1453113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1454113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_fifo_txdl_reserve( 1455113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_fifo *fifo, 1456113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa void **txdlh, void **txdl_priv) 1457113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1458113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1459113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status; 1460113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa int i; 1461113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1462113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &fifo->channel; 1463113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1464113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = vxge_hw_channel_dtr_alloc(channel, txdlh); 1465113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1466113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (status == VXGE_HW_OK) { 1467113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_fifo_txd *txdp = 1468113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (struct vxge_hw_fifo_txd *)*txdlh; 1469113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_fifo_txdl_priv *priv; 1470113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1471113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa priv = __vxge_hw_fifo_txdl_priv(fifo, txdp); 1472113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1473113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* reset the TxDL's private */ 1474113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa priv->align_dma_offset = 0; 1475113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa priv->align_vaddr_start = priv->align_vaddr; 1476113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa priv->align_used_frags = 0; 1477113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa priv->frags = 0; 1478113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa priv->alloc_frags = fifo->config->max_frags; 1479113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa priv->next_txdl_priv = NULL; 1480113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1481113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa *txdl_priv = (void *)(size_t)txdp->host_control; 1482113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1483113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa for (i = 0; i < fifo->config->max_frags; i++) { 1484113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp = ((struct vxge_hw_fifo_txd *)*txdlh) + i; 1485113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp->control_0 = txdp->control_1 = 0; 1486113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1487113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1488113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1489113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1490113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1491113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1492113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1493113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the 1494113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * descriptor. 1495113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifo: Handle to the fifo object used for non offload send 1496113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @txdlh: Descriptor handle. 1497113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @frag_idx: Index of the data buffer in the caller's scatter-gather list 1498113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * (of buffers). 1499113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @dma_pointer: DMA address of the data buffer referenced by @frag_idx. 1500113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @size: Size of the data buffer (in bytes). 1501113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1502113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * This API is part of the preparation of the transmit descriptor for posting 1503113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include 1504113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_txdl_mss_set() and vxge_hw_fifo_txdl_cksum_set_bits(). 1505113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * All three APIs fill in the fields of the fifo descriptor, 1506113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * in accordance with the Titan specification. 1507113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1508113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1509113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo, 1510113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa void *txdlh, u32 frag_idx, 1511113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa dma_addr_t dma_pointer, u32 size) 1512113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1513113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_fifo_txdl_priv *txdl_priv; 1514113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_fifo_txd *txdp, *txdp_last; 1515113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1516113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1517113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &fifo->channel; 1518113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1519113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh); 1520113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp = (struct vxge_hw_fifo_txd *)txdlh + txdl_priv->frags; 1521113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1522113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (frag_idx != 0) 1523113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp->control_0 = txdp->control_1 = 0; 1524113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa else { 1525113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE( 1526113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST); 1527113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp->control_1 |= fifo->interrupt_type; 1528113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_NUMBER( 1529113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->tx_intr_num); 1530113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (txdl_priv->frags) { 1531113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp_last = (struct vxge_hw_fifo_txd *)txdlh + 1532113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (txdl_priv->frags - 1); 1533113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp_last->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE( 1534113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_FIFO_TXD_GATHER_CODE_LAST); 1535113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1536113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1537113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1538113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_assert(frag_idx < txdl_priv->alloc_frags); 1539113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1540113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp->buffer_pointer = (u64)dma_pointer; 1541113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(size); 1542113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->stats->total_buffers++; 1543113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdl_priv->frags++; 1544113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1545113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1546113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1547113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel. 1548113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifo: Handle to the fifo object used for non offload send 1549113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @txdlh: Descriptor obtained via vxge_hw_fifo_txdl_reserve() 1550113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @frags: Number of contiguous buffers that are part of a single 1551113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * transmit operation. 1552113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1553113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Post descriptor on the 'fifo' type channel for transmission. 1554113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Prior to posting the descriptor should be filled in accordance with 1555113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Host/Titan interface specification for a given service (LL, etc.). 1556113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1557113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1558113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo, void *txdlh) 1559113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1560113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_fifo_txdl_priv *txdl_priv; 1561113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_fifo_txd *txdp_last; 1562113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_fifo_txd *txdp_first; 1563113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1564113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1565113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &fifo->channel; 1566113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1567113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh); 156843d620c82985b19008d87a437b4cf83f356264f7Joe Perches txdp_first = txdlh; 1569113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1570113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp_last = (struct vxge_hw_fifo_txd *)txdlh + (txdl_priv->frags - 1); 1571113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp_last->control_0 |= 1572113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_FIFO_TXD_GATHER_CODE(VXGE_HW_FIFO_TXD_GATHER_CODE_LAST); 1573113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdp_first->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER; 1574113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1575113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_post(&fifo->channel, txdlh); 1576113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1577113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_non_offload_db_post(fifo, 1578a4a987d82258f55c4bc4ab0156fb20a2b3fa4f41Sreenivasa Honnur (u64)txdl_priv->dma_addr, 1579113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdl_priv->frags - 1, 1580113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->no_snoop_bits); 1581113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1582113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->stats->total_posts++; 1583113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->stats->common_stats.usage_cnt++; 1584113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (fifo->stats->common_stats.usage_max < 1585113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->stats->common_stats.usage_cnt) 1586113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->stats->common_stats.usage_max = 1587113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->stats->common_stats.usage_cnt; 1588113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1589113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1590113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1591113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_txdl_next_completed - Retrieve next completed descriptor. 1592113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifo: Handle to the fifo object used for non offload send 1593113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @txdlh: Descriptor handle. Returned by HW. 1594113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @t_code: Transfer code, as per Titan User Guide, 1595113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Transmit Descriptor Format. 1596113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returned by HW. 1597113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1598113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Retrieve the _next_ completed descriptor. 1599113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * HW uses channel callback (*vxge_hw_channel_callback_f) to notifiy 1600113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * driver of new completed descriptors. After that 1601113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the driver can use vxge_hw_fifo_txdl_next_completed to retrieve the rest 1602113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * completions (the very first completion is passed by HW via 1603113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_channel_callback_f). 1604113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1605113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Implementation-wise, the driver is free to call 1606113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_txdl_next_completed either immediately from inside the 1607113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * channel callback, or in a deferred fashion and separate (from HW) 1608113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * context. 1609113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1610113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Non-zero @t_code means failure to process the descriptor. 1611113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * The failure could happen, for instance, when the link is 1612113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * down, in which case Titan completes the descriptor because it 1613113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * is not able to send the data out. 1614113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1615113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * For details please refer to Titan User Guide. 1616113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1617113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: VXGE_HW_OK - success. 1618113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors 1619113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * are currently available for processing. 1620113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1621113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1622113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_fifo_txdl_next_completed( 1623113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_fifo *fifo, void **txdlh, 1624113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_fifo_tcode *t_code) 1625113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1626113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1627113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_fifo_txd *txdp; 1628113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1629113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1630113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &fifo->channel; 1631113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1632113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_try_complete(channel, txdlh); 1633113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 163443d620c82985b19008d87a437b4cf83f356264f7Joe Perches txdp = *txdlh; 1635113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (txdp == NULL) { 1636113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; 1637113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1638113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1639113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1640113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* check whether host owns it */ 1641113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)) { 1642113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1643113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_assert(txdp->host_control != 0); 1644113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1645113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_complete(channel); 1646113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1647113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa *t_code = (u8)VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0); 1648113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1649113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (fifo->stats->common_stats.usage_cnt > 0) 1650113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->stats->common_stats.usage_cnt--; 1651113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1652113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_OK; 1653113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1654113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1655113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1656113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* no more completions */ 1657113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa *txdlh = NULL; 1658113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; 1659113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1660113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1661113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1662113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1663113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1664113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_handle_tcode - Handle transfer code. 1665113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifo: Handle to the fifo object used for non offload send 1666113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @txdlh: Descriptor handle. 1667113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @t_code: One of the enumerated (and documented in the Titan user guide) 1668113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * "transfer codes". 1669113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1670113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Handle descriptor's transfer code. The latter comes with each completed 1671113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * descriptor. 1672113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1673113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: one of the enum vxge_hw_status{} enumerated types. 1674113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_OK - for success. 1675113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_ERR_CRITICAL - when encounters critical error. 1676113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1677113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_fifo_handle_tcode(struct __vxge_hw_fifo *fifo, 1678113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa void *txdlh, 1679113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_fifo_tcode t_code) 1680113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1681113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1682113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1683113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1684113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &fifo->channel; 1685113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1686113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (((t_code & 0x7) < 0) || ((t_code & 0x7) > 0x4)) { 1687113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_TCODE; 1688113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1689113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1690113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1691113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa fifo->stats->txd_t_code_err_cnt[t_code]++; 1692113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1693113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1694113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1695113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1696113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1697113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_txdl_free - Free descriptor. 1698113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifo: Handle to the fifo object used for non offload send 1699113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @txdlh: Descriptor handle. 1700113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1701113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Free the reserved descriptor. This operation is "symmetrical" to 1702113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_fifo_txdl_reserve. The "free-ing" completes the descriptor's 1703113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * lifecycle. 1704113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1705113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * After free-ing (see vxge_hw_fifo_txdl_free()) the descriptor again can 1706113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * be: 1707113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1708113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * - reserved (vxge_hw_fifo_txdl_reserve); 1709113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1710113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * - posted (vxge_hw_fifo_txdl_post); 1711113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1712113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * - completed (vxge_hw_fifo_txdl_next_completed); 1713113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1714113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * - and recycled again (vxge_hw_fifo_txdl_free). 1715113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1716113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * For alternative state transitions and more details please refer to 1717113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the design doc. 1718113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1719113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1720113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_fifo_txdl_free(struct __vxge_hw_fifo *fifo, void *txdlh) 1721113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1722113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_fifo_txdl_priv *txdl_priv; 1723113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 max_frags; 1724113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 1725113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1726113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &fifo->channel; 1727113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1728113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, 1729113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (struct vxge_hw_fifo_txd *)txdlh); 1730113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1731113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa max_frags = fifo->config->max_frags; 1732113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1733113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa vxge_hw_channel_dtr_free(channel, txdlh); 1734113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1735113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1736113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1737113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_mac_addr_add - Add the mac address entry for this vpath 1738113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * to MAC address table. 1739113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Vpath handle. 1740113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @macaddr: MAC address to be added for this vpath into the list 1741113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @macaddr_mask: MAC address mask for macaddr 1742113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @duplicate_mode: Duplicate MAC address add mode. Please see 1743113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * enum vxge_hw_vpath_mac_addr_add_mode{} 1744113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1745113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Adds the given mac address and mac address mask into the list for this 1746113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vpath. 1747113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * see also: vxge_hw_vpath_mac_addr_delete, vxge_hw_vpath_mac_addr_get and 1748113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_mac_addr_get_next 1749113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1750113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1751113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status 1752113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavxge_hw_vpath_mac_addr_add( 1753113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_vpath_handle *vp, 1754113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u8 (macaddr)[ETH_ALEN], 1755113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u8 (macaddr_mask)[ETH_ALEN], 1756113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode) 1757113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1758113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 i; 1759113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 data1 = 0ULL; 1760113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 data2 = 0ULL; 1761113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1762113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1763113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vp == NULL) { 1764113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 1765113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1766113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1767113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1768113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa for (i = 0; i < ETH_ALEN; i++) { 1769113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa data1 <<= 8; 1770113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa data1 |= (u8)macaddr[i]; 1771113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1772113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa data2 <<= 8; 1773113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa data2 |= (u8)macaddr_mask[i]; 1774113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1775113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1776113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa switch (duplicate_mode) { 1777113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE: 1778113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa i = 0; 1779113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa break; 1780113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE: 1781113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa i = 1; 1782113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa break; 1783113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa case VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE: 1784113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa i = 2; 1785113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa break; 1786113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa default: 1787113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa i = 0; 1788113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa break; 1789113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1790113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1791113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = __vxge_hw_vpath_rts_table_set(vp, 1792113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY, 1793113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, 1794113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 0, 1795113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1), 1796113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2)| 1797113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(i)); 1798113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1799113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1800113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1801113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1802113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1803113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_mac_addr_get - Get the first mac address entry for this vpath 1804113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * from MAC address table. 1805113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Vpath handle. 1806113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @macaddr: First MAC address entry for this vpath in the list 1807113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @macaddr_mask: MAC address mask for macaddr 1808113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1809113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns the first mac address and mac address mask in the list for this 1810113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vpath. 1811113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * see also: vxge_hw_vpath_mac_addr_get_next 1812113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1813113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1814113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status 1815113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavxge_hw_vpath_mac_addr_get( 1816113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_vpath_handle *vp, 1817113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u8 (macaddr)[ETH_ALEN], 1818113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u8 (macaddr_mask)[ETH_ALEN]) 1819113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1820113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 i; 1821113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 data1 = 0ULL; 1822113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 data2 = 0ULL; 1823113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1824113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1825113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vp == NULL) { 1826113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 1827113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1828113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1829113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1830113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = __vxge_hw_vpath_rts_table_get(vp, 1831113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY, 1832113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, 1833113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 0, &data1, &data2); 1834113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1835113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (status != VXGE_HW_OK) 1836113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1837113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1838113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1); 1839113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1840113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2); 1841113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1842113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa for (i = ETH_ALEN; i > 0; i--) { 1843113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa macaddr[i-1] = (u8)(data1 & 0xFF); 1844113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa data1 >>= 8; 1845113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1846113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa macaddr_mask[i-1] = (u8)(data2 & 0xFF); 1847113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa data2 >>= 8; 1848113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1849113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1850113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1851113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1852113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1853113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1854113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_mac_addr_get_next - Get the next mac address entry for this 1855113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vpath 1856113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * from MAC address table. 1857113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Vpath handle. 1858113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @macaddr: Next MAC address entry for this vpath in the list 1859113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @macaddr_mask: MAC address mask for macaddr 1860113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1861113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns the next mac address and mac address mask in the list for this 1862113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vpath. 1863113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * see also: vxge_hw_vpath_mac_addr_get 1864113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1865113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1866113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status 1867113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavxge_hw_vpath_mac_addr_get_next( 1868113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_vpath_handle *vp, 1869113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u8 (macaddr)[ETH_ALEN], 1870113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u8 (macaddr_mask)[ETH_ALEN]) 1871113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1872113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 i; 1873113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 data1 = 0ULL; 1874113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 data2 = 0ULL; 1875113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1876113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1877113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vp == NULL) { 1878113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 1879113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1880113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1881113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1882113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = __vxge_hw_vpath_rts_table_get(vp, 1883113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY, 1884113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, 1885113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 0, &data1, &data2); 1886113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1887113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (status != VXGE_HW_OK) 1888113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1889113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1890528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1); 1891113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1892528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2); 1893113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1894528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason for (i = ETH_ALEN; i > 0; i--) { 1895528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason macaddr[i-1] = (u8)(data1 & 0xFF); 1896528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason data1 >>= 8; 1897113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1898528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason macaddr_mask[i-1] = (u8)(data2 & 0xFF); 1899528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason data2 >>= 8; 1900113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1901528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1902113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1903113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1904113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1905113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1906528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/** 1907528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_mac_addr_delete - Delete the mac address entry for this vpath 1908528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * to MAC address table. 1909113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Vpath handle. 1910528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @macaddr: MAC address to be added for this vpath into the list 1911528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @macaddr_mask: MAC address mask for macaddr 1912528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 1913528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Delete the given mac address and mac address mask into the list for this 1914528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vpath. 1915528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * see also: vxge_hw_vpath_mac_addr_add, vxge_hw_vpath_mac_addr_get and 1916528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_mac_addr_get_next 1917113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1918113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1919528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status 1920528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonvxge_hw_vpath_mac_addr_delete( 1921528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_vpath_handle *vp, 1922528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u8 (macaddr)[ETH_ALEN], 1923528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u8 (macaddr_mask)[ETH_ALEN]) 1924113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1925528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u32 i; 1926528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 data1 = 0ULL; 1927528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 data2 = 0ULL; 1928113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1929113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1930528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (vp == NULL) { 1931113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 1932113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1933113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1934113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1935528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason for (i = 0; i < ETH_ALEN; i++) { 1936528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason data1 <<= 8; 1937528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason data1 |= (u8)macaddr[i]; 1938113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1939528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason data2 <<= 8; 1940528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason data2 |= (u8)macaddr_mask[i]; 1941113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1942528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 1943528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = __vxge_hw_vpath_rts_table_set(vp, 1944528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY, 1945528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, 1946528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 0, 1947528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1), 1948528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2)); 1949113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1950113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1951113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1952113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1953113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1954528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_vid_add - Add the vlan id entry for this vpath 1955528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * to vlan id table. 1956113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Vpath handle. 1957528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vid: vlan id to be added for this vpath into the list 1958113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1959528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Adds the given vlan id into the list for this vpath. 1960528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * see also: vxge_hw_vpath_vid_delete, vxge_hw_vpath_vid_get and 1961528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_vid_get_next 1962113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1963113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1964528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status 1965528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonvxge_hw_vpath_vid_add(struct __vxge_hw_vpath_handle *vp, u64 vid) 1966113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1967113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1968113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1969528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (vp == NULL) { 1970113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 1971113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 1972113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 1973113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1974528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = __vxge_hw_vpath_rts_table_set(vp, 1975528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY, 1976528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID, 1977528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0); 1978113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 1979113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 1980113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 1981113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1982113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 1983528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_vid_get - Get the first vid entry for this vpath 1984528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * from vlan id table. 1985113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Vpath handle. 1986528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vid: Buffer to return vlan id 1987113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1988528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Returns the first vlan id in the list for this vpath. 1989528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * see also: vxge_hw_vpath_vid_get_next 1990113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 1991113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 1992113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status 1993528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonvxge_hw_vpath_vid_get(struct __vxge_hw_vpath_handle *vp, u64 *vid) 1994113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 1995528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 data; 1996113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 1997113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 1998528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (vp == NULL) { 1999113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 2000113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 2001113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2002113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2003528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = __vxge_hw_vpath_rts_table_get(vp, 2004528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY, 2005528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID, 2006528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 0, vid, &data); 2007113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2008528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason *vid = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid); 2009113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 2010113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 2011113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2012113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2013528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/** 2014528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_vid_delete - Delete the vlan id entry for this vpath 2015528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * to vlan id table. 2016528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vp: Vpath handle. 2017528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vid: vlan id to be added for this vpath into the list 2018113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2019528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Adds the given vlan id into the list for this vpath. 2020528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * see also: vxge_hw_vpath_vid_add, vxge_hw_vpath_vid_get and 2021528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_vid_get_next 2022113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2023113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2024528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status 2025528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonvxge_hw_vpath_vid_delete(struct __vxge_hw_vpath_handle *vp, u64 vid) 2026113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2027528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_status status = VXGE_HW_OK; 2028113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2029528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (vp == NULL) { 2030528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = VXGE_HW_ERR_INVALID_HANDLE; 2031528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 2032113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2033113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2034528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = __vxge_hw_vpath_rts_table_set(vp, 2035528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY, 2036528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID, 2037528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason 0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0); 2038528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 2039528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return status; 2040528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 2041113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2042528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/** 2043528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_promisc_enable - Enable promiscuous mode. 2044528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vp: Vpath handle. 2045528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2046528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Enable promiscuous mode of Titan-e operation. 2047528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2048528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * See also: vxge_hw_vpath_promisc_disable(). 2049528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 2050528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status vxge_hw_vpath_promisc_enable( 2051528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_vpath_handle *vp) 2052528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 2053528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 val64; 2054528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_virtualpath *vpath; 2055528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_status status = VXGE_HW_OK; 2056113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2057528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((vp == NULL) || (vp->vpath->ringh == NULL)) { 2058528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = VXGE_HW_ERR_INVALID_HANDLE; 2059528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 2060528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 2061113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2062528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason vpath = vp->vpath; 2063113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 206425985edcedea6396277003854657b5f3cb31a628Lucas De Marchi /* Enable promiscuous mode for function 0 only */ 2065528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (!(vpath->hldev->access_rights & 2066528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) 2067528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return VXGE_HW_OK; 2068113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2069528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vpath->vp_reg->rxmac_vcfg0); 2070113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2071528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (!(val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN)) { 2072113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2073528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 |= VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN | 2074528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN | 2075528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RXMAC_VCFG0_BCAST_EN | 2076528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RXMAC_VCFG0_ALL_VID_EN; 2077113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2078528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(val64, &vpath->vp_reg->rxmac_vcfg0); 2079528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 2080528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 2081528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return status; 2082528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 2083113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2084528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/** 2085528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_promisc_disable - Disable promiscuous mode. 2086528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vp: Vpath handle. 2087528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2088528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Disable promiscuous mode of Titan-e operation. 2089528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2090528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * See also: vxge_hw_vpath_promisc_enable(). 2091528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 2092528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status vxge_hw_vpath_promisc_disable( 2093528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_vpath_handle *vp) 2094528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 2095528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 val64; 2096528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_virtualpath *vpath; 2097528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_status status = VXGE_HW_OK; 2098113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2099528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((vp == NULL) || (vp->vpath->ringh == NULL)) { 2100528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = VXGE_HW_ERR_INVALID_HANDLE; 2101528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 2102528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 2103113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2104528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason vpath = vp->vpath; 2105113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2106528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vpath->vp_reg->rxmac_vcfg0); 2107113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2108528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) { 2109113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2110528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 &= ~(VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN | 2111528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN | 2112528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason VXGE_HW_RXMAC_VCFG0_ALL_VID_EN); 2113113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2114528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(val64, &vpath->vp_reg->rxmac_vcfg0); 2115113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2116528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 2117528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return status; 2118528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 2119113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2120528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/* 2121528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_bcast_enable - Enable broadcast 2122528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vp: Vpath handle. 2123528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2124528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Enable receiving broadcasts. 2125528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 2126528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status vxge_hw_vpath_bcast_enable( 2127528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_vpath_handle *vp) 2128528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 2129528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 val64; 2130528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_virtualpath *vpath; 2131528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_status status = VXGE_HW_OK; 2132113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2133528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((vp == NULL) || (vp->vpath->ringh == NULL)) { 2134528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = VXGE_HW_ERR_INVALID_HANDLE; 2135528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 2136528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 2137113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2138528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason vpath = vp->vpath; 2139113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2140528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vpath->vp_reg->rxmac_vcfg0); 2141113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2142528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (!(val64 & VXGE_HW_RXMAC_VCFG0_BCAST_EN)) { 2143528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 |= VXGE_HW_RXMAC_VCFG0_BCAST_EN; 2144528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(val64, &vpath->vp_reg->rxmac_vcfg0); 2145528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 2146528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 2147528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return status; 2148528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 2149113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2150528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/** 2151528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_mcast_enable - Enable multicast addresses. 2152528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vp: Vpath handle. 2153528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2154528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Enable Titan-e multicast addresses. 2155528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Returns: VXGE_HW_OK on success. 2156528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2157528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 2158528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status vxge_hw_vpath_mcast_enable( 2159528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_vpath_handle *vp) 2160528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 2161528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 val64; 2162528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_virtualpath *vpath; 2163528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_status status = VXGE_HW_OK; 2164113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2165528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((vp == NULL) || (vp->vpath->ringh == NULL)) { 2166528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = VXGE_HW_ERR_INVALID_HANDLE; 2167528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 2168528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 2169113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2170528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason vpath = vp->vpath; 2171113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2172528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vpath->vp_reg->rxmac_vcfg0); 2173113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2174528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (!(val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN)) { 2175528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 |= VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN; 2176528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(val64, &vpath->vp_reg->rxmac_vcfg0); 2177528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 2178528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 2179528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return status; 2180528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason} 2181113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2182528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason/** 2183528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * vxge_hw_vpath_mcast_disable - Disable multicast addresses. 2184528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * @vp: Vpath handle. 2185528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2186528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Disable Titan-e multicast addresses. 2187528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * Returns: VXGE_HW_OK - success. 2188528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * VXGE_HW_ERR_INVALID_HANDLE - Invalid handle 2189528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason * 2190528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason */ 2191528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonenum vxge_hw_status 2192528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonvxge_hw_vpath_mcast_disable(struct __vxge_hw_vpath_handle *vp) 2193528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason{ 2194528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason u64 val64; 2195528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason struct __vxge_hw_virtualpath *vpath; 2196528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason enum vxge_hw_status status = VXGE_HW_OK; 2197113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2198528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if ((vp == NULL) || (vp->vpath->ringh == NULL)) { 2199528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason status = VXGE_HW_ERR_INVALID_HANDLE; 2200528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason goto exit; 2201113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2202113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2203528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason vpath = vp->vpath; 2204113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2205528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 = readq(&vpath->vp_reg->rxmac_vcfg0); 2206113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2207528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason if (val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) { 2208528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason val64 &= ~VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN; 2209528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason writeq(val64, &vpath->vp_reg->rxmac_vcfg0); 2210528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason } 2211528f727279ae840db8a06c94f5e82cdaeb00da6fJon Masonexit: 2212528f727279ae840db8a06c94f5e82cdaeb00da6fJon Mason return status; 2213113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2214113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2215113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/* 2216113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_alarm_process - Process Alarms. 2217113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vpath: Virtual Path. 2218113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @skip_alarms: Do not clear the alarms 2219113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2220113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Process vpath alarms. 2221113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2222113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2223113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_vpath_alarm_process( 2224113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_vpath_handle *vp, 2225113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 skip_alarms) 2226113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2227113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 2228113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2229113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vp == NULL) { 2230113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_ERR_INVALID_HANDLE; 2231113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa goto exit; 2232113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2233113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2234113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = __vxge_hw_vpath_alarm_process(vp->vpath, skip_alarms); 2235113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaexit: 2236113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 2237113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2238113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2239113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 2240113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_msix_set - Associate MSIX vectors with TIM interrupts and 2241113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * alrms 2242113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Virtual Path handle. 2243113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @tim_msix_id: MSIX vectors associated with VXGE_HW_MAX_INTR_PER_VP number of 2244113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * interrupts(Can be repeated). If fifo or ring are not enabled 2245113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the MSIX vector for that should be set to 0 2246113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @alarm_msix_id: MSIX vector for alarm. 2247113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2248113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * This API will associate a given MSIX vector numbers with the four TIM 2249113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * interrupts and alarm interrupt. 2250113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2251b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnurvoid 2252113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id, 2253113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa int alarm_msix_id) 2254113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2255113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64; 2256113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_virtualpath *vpath = vp->vpath; 2257113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg; 2258b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnur u32 vp_id = vp->vpath->vp_id; 2259113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2260113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI( 2261b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnur (vp_id * 4) + tim_msix_id[0]) | 2262113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI( 2263b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnur (vp_id * 4) + tim_msix_id[1]); 2264113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2265113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(val64, &vp_reg->interrupt_cfg0); 2266113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2267113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG( 2268b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnur (vpath->hldev->first_vp_id * 4) + alarm_msix_id), 2269113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &vp_reg->interrupt_cfg2); 2270113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2271113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (vpath->hldev->config.intr_mode == 2272113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) { 2273113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn( 227416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN, 227516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 0, 32), &vp_reg->one_shot_vect0_en); 227616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn( 2277113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN, 2278113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 0, 32), &vp_reg->one_shot_vect1_en); 2279113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn( 2280113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN, 2281113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 0, 32), &vp_reg->one_shot_vect2_en); 2282113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2283113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2284113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2285113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 2286113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_msix_mask - Mask MSIX Vector. 2287113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Virtual Path handle. 2288113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @msix_id: MSIX ID 2289113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2290113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * The function masks the msix interrupt for the given msix_id 2291113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2292113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: 0, 2293113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range 2294113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * status. 2295113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: 2296113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2297113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid 2298113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id) 2299113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2300113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_device *hldev = vp->vpath->hldev; 2301113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 2302b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnur (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 2303113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->set_msix_mask_vect[msix_id % 4]); 2304113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2305113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2306113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 230716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * vxge_hw_vpath_msix_clear - Clear MSIX Vector. 230816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * @vp: Virtual Path handle. 230916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * @msix_id: MSI ID 231016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * 231116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * The function clears the msix interrupt for the given msix_id 231216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * 231316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * Returns: 0, 231416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range 231516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * status. 231616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason * See also: 231716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason */ 231816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Masonvoid vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id) 231916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason{ 232016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason struct __vxge_hw_device *hldev = vp->vpath->hldev; 232116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 232216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason if ((hldev->config.intr_mode == VXGE_HW_INTR_MODE_MSIX_ONE_SHOT)) 232316fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason __vxge_hw_pio_mem_write32_upper( 232416fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason (u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32), 232516fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason &hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]); 232616fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason else 232716fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason __vxge_hw_pio_mem_write32_upper( 232816fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason (u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32), 232916fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason &hldev->common_reg->clear_msix_mask_vect[msix_id % 4]); 233016fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason} 233116fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason 233216fded7da2cefc619ece0d44f8df76b533c43fd2Jon Mason/** 2333113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_msix_unmask - Unmask the MSIX Vector. 2334113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Virtual Path handle. 2335113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @msix_id: MSI ID 2336113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2337113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * The function unmasks the msix interrupt for the given msix_id 2338113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2339113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: 0, 2340113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range 2341113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * status. 2342113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: 2343113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2344113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid 2345113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id) 2346113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2347113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_device *hldev = vp->vpath->hldev; 2348113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 2349b59c94571a6593c71a78bbcebb42982099154938Sreenivasa Honnur (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 2350113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->clear_msix_mask_vect[msix_id%4]); 2351113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2352113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2353113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 2354113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_inta_mask_tx_rx - Mask Tx and Rx interrupts. 2355113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Virtual Path handle. 2356113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2357113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Mask Tx and Rx vpath interrupts. 2358113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2359113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_vpath_inta_mask_tx_rx() 2360113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2361113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_vpath_inta_mask_tx_rx(struct __vxge_hw_vpath_handle *vp) 2362113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2363113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 tim_int_mask0[4] = {[0 ...3] = 0}; 2364113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 tim_int_mask1[4] = {[0 ...3] = 0}; 2365113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64; 2366113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_device *hldev = vp->vpath->hldev; 2367113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2368113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0, 2369113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa tim_int_mask1, vp->vpath->vp_id); 2370113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2371113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = readq(&hldev->common_reg->tim_int_mask0); 2372113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2373113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) || 2374113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) { 2375113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | 2376113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa tim_int_mask0[VXGE_HW_VPATH_INTR_RX] | val64), 2377113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->tim_int_mask0); 2378113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2379113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2380113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = readl(&hldev->common_reg->tim_int_mask1); 2381113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2382113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) || 2383113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) { 2384113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 2385113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | 2386113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa tim_int_mask1[VXGE_HW_VPATH_INTR_RX] | val64), 2387113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->tim_int_mask1); 2388113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2389113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2390113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2391113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 2392113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_inta_unmask_tx_rx - Unmask Tx and Rx interrupts. 2393113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @vp: Virtual Path handle. 2394113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2395113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Unmask Tx and Rx vpath interrupts. 2396113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2397113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_vpath_inta_mask_tx_rx() 2398113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2399113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepavoid vxge_hw_vpath_inta_unmask_tx_rx(struct __vxge_hw_vpath_handle *vp) 2400113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2401113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 tim_int_mask0[4] = {[0 ...3] = 0}; 2402113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u32 tim_int_mask1[4] = {[0 ...3] = 0}; 2403113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64; 2404113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_device *hldev = vp->vpath->hldev; 2405113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2406113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0, 2407113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa tim_int_mask1, vp->vpath->vp_id); 2408113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2409113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = readq(&hldev->common_reg->tim_int_mask0); 2410113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2411113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) || 2412113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) { 2413113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq((~(tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | 2414113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa tim_int_mask0[VXGE_HW_VPATH_INTR_RX])) & val64, 2415113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->tim_int_mask0); 2416113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2417113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2418113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) || 2419113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) { 2420113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa __vxge_hw_pio_mem_write32_upper( 2421113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa (~(tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | 2422113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa tim_int_mask1[VXGE_HW_VPATH_INTR_RX])) & val64, 2423113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &hldev->common_reg->tim_int_mask1); 2424113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2425113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2426113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2427113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 2428113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed 2429113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * descriptors and process the same. 2430113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @ring: Handle to the ring object used for receive 2431113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2432113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * The function polls the Rx for the completed descriptors and calls 2433113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the driver via supplied completion callback. 2434113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2435113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: VXGE_HW_OK, if the polling is completed successful. 2436113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed 2437113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * descriptors available which are yet to be processed. 2438113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2439113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * See also: vxge_hw_vpath_poll_rx() 2440113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2441113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ring) 2442113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2443113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u8 t_code; 2444113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 2445113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa void *first_rxdh; 2446113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa u64 val64 = 0; 2447113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa int new_count = 0; 2448113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2449113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->cmpl_cnt = 0; 2450113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2451113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = vxge_hw_ring_rxd_next_completed(ring, &first_rxdh, &t_code); 2452113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (status == VXGE_HW_OK) 2453113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->callback(ring, first_rxdh, 2454113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa t_code, ring->channel.userdata); 2455113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2456113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (ring->cmpl_cnt != 0) { 2457113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->doorbell_cnt += ring->cmpl_cnt; 2458113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (ring->doorbell_cnt >= ring->rxds_limit) { 2459113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* 2460113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Each RxD is of 4 qwords, update the number of 2461113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * qwords replenished 2462113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2463113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa new_count = (ring->doorbell_cnt * 4); 2464113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2465113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* For each block add 4 more qwords */ 2466113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->total_db_cnt += ring->doorbell_cnt; 2467113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (ring->total_db_cnt >= ring->rxds_per_block) { 2468113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa new_count += 4; 2469113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa /* Reset total count */ 2470113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->total_db_cnt %= ring->rxds_per_block; 2471113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2472113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(new_count), 2473113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &ring->vp_reg->prc_rxd_doorbell); 2474113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa val64 = 2475113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa readl(&ring->common_reg->titan_general_int_status); 2476113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa ring->doorbell_cnt = 0; 2477113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2478113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa } 2479113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2480113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 2481113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2482113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2483113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa/** 2484113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process 2485113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the same. 2486113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * @fifo: Handle to the fifo object used for non offload send 2487113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 248898f45da247c5b8023d4f3677d65f21b64692f543Jon Mason * The function polls the Tx for the completed descriptors and calls 2489113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * the driver via supplied completion callback. 2490113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * 2491113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * Returns: VXGE_HW_OK, if the polling is completed successful. 2492113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed 2493113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa * descriptors available which are yet to be processed. 2494113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa */ 2495113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepaenum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo, 2496ff67df55f6bde9de5e508bf1f09509c843accd54Benjamin LaHaise struct sk_buff ***skb_ptr, int nr_skb, 2497ff67df55f6bde9de5e508bf1f09509c843accd54Benjamin LaHaise int *more) 2498113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa{ 2499113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_fifo_tcode t_code; 2500113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa void *first_txdlh; 2501113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa enum vxge_hw_status status = VXGE_HW_OK; 2502113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa struct __vxge_hw_channel *channel; 2503113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2504113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa channel = &fifo->channel; 2505113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2506113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = vxge_hw_fifo_txdl_next_completed(fifo, 2507113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa &first_txdlh, &t_code); 2508113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa if (status == VXGE_HW_OK) 2509ff67df55f6bde9de5e508bf1f09509c843accd54Benjamin LaHaise if (fifo->callback(fifo, first_txdlh, t_code, 2510ff67df55f6bde9de5e508bf1f09509c843accd54Benjamin LaHaise channel->userdata, skb_ptr, nr_skb, more) != VXGE_HW_OK) 2511113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa status = VXGE_HW_COMPLETIONS_REMAIN; 2512113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa 2513113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa return status; 2514113241321dcd19f36d53f2af46a4734855ca0cc0Ramkrishna Vepa} 2515