r6040.c revision 853d5dc95b41babb7001934becad9c944738d8e3
1/* 2 * RDC R6040 Fast Ethernet MAC support 3 * 4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw> 5 * Copyright (C) 2007 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us> 7 * Florian Fainelli <florian@openwrt.org> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 2 12 * of the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the 21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA. 23*/ 24 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/moduleparam.h> 28#include <linux/string.h> 29#include <linux/timer.h> 30#include <linux/errno.h> 31#include <linux/ioport.h> 32#include <linux/interrupt.h> 33#include <linux/pci.h> 34#include <linux/netdevice.h> 35#include <linux/etherdevice.h> 36#include <linux/skbuff.h> 37#include <linux/init.h> 38#include <linux/delay.h> 39#include <linux/mii.h> 40#include <linux/ethtool.h> 41#include <linux/crc32.h> 42#include <linux/spinlock.h> 43#include <linux/bitops.h> 44#include <linux/io.h> 45#include <linux/irq.h> 46#include <linux/uaccess.h> 47#include <linux/phy.h> 48 49#include <asm/processor.h> 50 51#define DRV_NAME "r6040" 52#define DRV_VERSION "0.28" 53#define DRV_RELDATE "07Oct2011" 54 55/* Time in jiffies before concluding the transmitter is hung. */ 56#define TX_TIMEOUT (6000 * HZ / 1000) 57 58/* RDC MAC I/O Size */ 59#define R6040_IO_SIZE 256 60 61/* MAX RDC MAC */ 62#define MAX_MAC 2 63 64/* MAC registers */ 65#define MCR0 0x00 /* Control register 0 */ 66#define MCR0_RCVEN 0x0002 /* Receive enable */ 67#define MCR0_PROMISC 0x0020 /* Promiscuous mode */ 68#define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */ 69#define MCR0_XMTEN 0x1000 /* Transmission enable */ 70#define MCR0_FD 0x8000 /* Full/Half duplex */ 71#define MCR1 0x04 /* Control register 1 */ 72#define MAC_RST 0x0001 /* Reset the MAC */ 73#define MBCR 0x08 /* Bus control */ 74#define MT_ICR 0x0C /* TX interrupt control */ 75#define MR_ICR 0x10 /* RX interrupt control */ 76#define MTPR 0x14 /* TX poll command register */ 77#define MR_BSR 0x18 /* RX buffer size */ 78#define MR_DCR 0x1A /* RX descriptor control */ 79#define MLSR 0x1C /* Last status */ 80#define MMDIO 0x20 /* MDIO control register */ 81#define MDIO_WRITE 0x4000 /* MDIO write */ 82#define MDIO_READ 0x2000 /* MDIO read */ 83#define MMRD 0x24 /* MDIO read data register */ 84#define MMWD 0x28 /* MDIO write data register */ 85#define MTD_SA0 0x2C /* TX descriptor start address 0 */ 86#define MTD_SA1 0x30 /* TX descriptor start address 1 */ 87#define MRD_SA0 0x34 /* RX descriptor start address 0 */ 88#define MRD_SA1 0x38 /* RX descriptor start address 1 */ 89#define MISR 0x3C /* Status register */ 90#define MIER 0x40 /* INT enable register */ 91#define MSK_INT 0x0000 /* Mask off interrupts */ 92#define RX_FINISH 0x0001 /* RX finished */ 93#define RX_NO_DESC 0x0002 /* No RX descriptor available */ 94#define RX_FIFO_FULL 0x0004 /* RX FIFO full */ 95#define RX_EARLY 0x0008 /* RX early */ 96#define TX_FINISH 0x0010 /* TX finished */ 97#define TX_EARLY 0x0080 /* TX early */ 98#define EVENT_OVRFL 0x0100 /* Event counter overflow */ 99#define LINK_CHANGED 0x0200 /* PHY link changed */ 100#define ME_CISR 0x44 /* Event counter INT status */ 101#define ME_CIER 0x48 /* Event counter INT enable */ 102#define MR_CNT 0x50 /* Successfully received packet counter */ 103#define ME_CNT0 0x52 /* Event counter 0 */ 104#define ME_CNT1 0x54 /* Event counter 1 */ 105#define ME_CNT2 0x56 /* Event counter 2 */ 106#define ME_CNT3 0x58 /* Event counter 3 */ 107#define MT_CNT 0x5A /* Successfully transmit packet counter */ 108#define ME_CNT4 0x5C /* Event counter 4 */ 109#define MP_CNT 0x5E /* Pause frame counter register */ 110#define MAR0 0x60 /* Hash table 0 */ 111#define MAR1 0x62 /* Hash table 1 */ 112#define MAR2 0x64 /* Hash table 2 */ 113#define MAR3 0x66 /* Hash table 3 */ 114#define MID_0L 0x68 /* Multicast address MID0 Low */ 115#define MID_0M 0x6A /* Multicast address MID0 Medium */ 116#define MID_0H 0x6C /* Multicast address MID0 High */ 117#define MID_1L 0x70 /* MID1 Low */ 118#define MID_1M 0x72 /* MID1 Medium */ 119#define MID_1H 0x74 /* MID1 High */ 120#define MID_2L 0x78 /* MID2 Low */ 121#define MID_2M 0x7A /* MID2 Medium */ 122#define MID_2H 0x7C /* MID2 High */ 123#define MID_3L 0x80 /* MID3 Low */ 124#define MID_3M 0x82 /* MID3 Medium */ 125#define MID_3H 0x84 /* MID3 High */ 126#define PHY_CC 0x88 /* PHY status change configuration register */ 127#define PHY_ST 0x8A /* PHY status register */ 128#define MAC_SM 0xAC /* MAC status machine */ 129#define MAC_SM_RST 0x0002 /* MAC status machine reset */ 130#define MAC_ID 0xBE /* Identifier register */ 131 132#define TX_DCNT 0x80 /* TX descriptor count */ 133#define RX_DCNT 0x80 /* RX descriptor count */ 134#define MAX_BUF_SIZE 0x600 135#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor)) 136#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor)) 137#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ 138#define MCAST_MAX 3 /* Max number multicast addresses to filter */ 139 140/* Descriptor status */ 141#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */ 142#define DSC_RX_OK 0x4000 /* RX was successful */ 143#define DSC_RX_ERR 0x0800 /* RX PHY error */ 144#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */ 145#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */ 146#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */ 147#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */ 148#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */ 149#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */ 150#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */ 151#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */ 152#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */ 153#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */ 154 155MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>," 156 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>," 157 "Florian Fainelli <florian@openwrt.org>"); 158MODULE_LICENSE("GPL"); 159MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver"); 160MODULE_VERSION(DRV_VERSION " " DRV_RELDATE); 161 162/* RX and TX interrupts that we handle */ 163#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH) 164#define TX_INTS (TX_FINISH) 165#define INT_MASK (RX_INTS | TX_INTS) 166 167struct r6040_descriptor { 168 u16 status, len; /* 0-3 */ 169 __le32 buf; /* 4-7 */ 170 __le32 ndesc; /* 8-B */ 171 u32 rev1; /* C-F */ 172 char *vbufp; /* 10-13 */ 173 struct r6040_descriptor *vndescp; /* 14-17 */ 174 struct sk_buff *skb_ptr; /* 18-1B */ 175 u32 rev2; /* 1C-1F */ 176} __aligned(32); 177 178struct r6040_private { 179 spinlock_t lock; /* driver lock */ 180 struct pci_dev *pdev; 181 struct r6040_descriptor *rx_insert_ptr; 182 struct r6040_descriptor *rx_remove_ptr; 183 struct r6040_descriptor *tx_insert_ptr; 184 struct r6040_descriptor *tx_remove_ptr; 185 struct r6040_descriptor *rx_ring; 186 struct r6040_descriptor *tx_ring; 187 dma_addr_t rx_ring_dma; 188 dma_addr_t tx_ring_dma; 189 u16 tx_free_desc; 190 u16 mcr0, mcr1; 191 struct net_device *dev; 192 struct mii_bus *mii_bus; 193 struct napi_struct napi; 194 void __iomem *base; 195 struct phy_device *phydev; 196 int old_link; 197 int old_duplex; 198}; 199 200static char version[] __devinitdata = DRV_NAME 201 ": RDC R6040 NAPI net driver," 202 "version "DRV_VERSION " (" DRV_RELDATE ")"; 203 204/* Read a word data from PHY Chip */ 205static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg) 206{ 207 int limit = 2048; 208 u16 cmd; 209 210 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO); 211 /* Wait for the read bit to be cleared */ 212 while (limit--) { 213 cmd = ioread16(ioaddr + MMDIO); 214 if (!(cmd & MDIO_READ)) 215 break; 216 } 217 218 return ioread16(ioaddr + MMRD); 219} 220 221/* Write a word data from PHY Chip */ 222static void r6040_phy_write(void __iomem *ioaddr, 223 int phy_addr, int reg, u16 val) 224{ 225 int limit = 2048; 226 u16 cmd; 227 228 iowrite16(val, ioaddr + MMWD); 229 /* Write the command to the MDIO bus */ 230 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO); 231 /* Wait for the write bit to be cleared */ 232 while (limit--) { 233 cmd = ioread16(ioaddr + MMDIO); 234 if (!(cmd & MDIO_WRITE)) 235 break; 236 } 237} 238 239static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg) 240{ 241 struct net_device *dev = bus->priv; 242 struct r6040_private *lp = netdev_priv(dev); 243 void __iomem *ioaddr = lp->base; 244 245 return r6040_phy_read(ioaddr, phy_addr, reg); 246} 247 248static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr, 249 int reg, u16 value) 250{ 251 struct net_device *dev = bus->priv; 252 struct r6040_private *lp = netdev_priv(dev); 253 void __iomem *ioaddr = lp->base; 254 255 r6040_phy_write(ioaddr, phy_addr, reg, value); 256 257 return 0; 258} 259 260static int r6040_mdiobus_reset(struct mii_bus *bus) 261{ 262 return 0; 263} 264 265static void r6040_free_txbufs(struct net_device *dev) 266{ 267 struct r6040_private *lp = netdev_priv(dev); 268 int i; 269 270 for (i = 0; i < TX_DCNT; i++) { 271 if (lp->tx_insert_ptr->skb_ptr) { 272 pci_unmap_single(lp->pdev, 273 le32_to_cpu(lp->tx_insert_ptr->buf), 274 MAX_BUF_SIZE, PCI_DMA_TODEVICE); 275 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr); 276 lp->tx_insert_ptr->skb_ptr = NULL; 277 } 278 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp; 279 } 280} 281 282static void r6040_free_rxbufs(struct net_device *dev) 283{ 284 struct r6040_private *lp = netdev_priv(dev); 285 int i; 286 287 for (i = 0; i < RX_DCNT; i++) { 288 if (lp->rx_insert_ptr->skb_ptr) { 289 pci_unmap_single(lp->pdev, 290 le32_to_cpu(lp->rx_insert_ptr->buf), 291 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE); 292 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr); 293 lp->rx_insert_ptr->skb_ptr = NULL; 294 } 295 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp; 296 } 297} 298 299static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring, 300 dma_addr_t desc_dma, int size) 301{ 302 struct r6040_descriptor *desc = desc_ring; 303 dma_addr_t mapping = desc_dma; 304 305 while (size-- > 0) { 306 mapping += sizeof(*desc); 307 desc->ndesc = cpu_to_le32(mapping); 308 desc->vndescp = desc + 1; 309 desc++; 310 } 311 desc--; 312 desc->ndesc = cpu_to_le32(desc_dma); 313 desc->vndescp = desc_ring; 314} 315 316static void r6040_init_txbufs(struct net_device *dev) 317{ 318 struct r6040_private *lp = netdev_priv(dev); 319 320 lp->tx_free_desc = TX_DCNT; 321 322 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring; 323 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT); 324} 325 326static int r6040_alloc_rxbufs(struct net_device *dev) 327{ 328 struct r6040_private *lp = netdev_priv(dev); 329 struct r6040_descriptor *desc; 330 struct sk_buff *skb; 331 int rc; 332 333 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring; 334 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT); 335 336 /* Allocate skbs for the rx descriptors */ 337 desc = lp->rx_ring; 338 do { 339 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE); 340 if (!skb) { 341 netdev_err(dev, "failed to alloc skb for rx\n"); 342 rc = -ENOMEM; 343 goto err_exit; 344 } 345 desc->skb_ptr = skb; 346 desc->buf = cpu_to_le32(pci_map_single(lp->pdev, 347 desc->skb_ptr->data, 348 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); 349 desc->status = DSC_OWNER_MAC; 350 desc = desc->vndescp; 351 } while (desc != lp->rx_ring); 352 353 return 0; 354 355err_exit: 356 /* Deallocate all previously allocated skbs */ 357 r6040_free_rxbufs(dev); 358 return rc; 359} 360 361static void r6040_init_mac_regs(struct net_device *dev) 362{ 363 struct r6040_private *lp = netdev_priv(dev); 364 void __iomem *ioaddr = lp->base; 365 int limit = 2048; 366 u16 cmd; 367 368 /* Mask Off Interrupt */ 369 iowrite16(MSK_INT, ioaddr + MIER); 370 371 /* Reset RDC MAC */ 372 iowrite16(MAC_RST, ioaddr + MCR1); 373 while (limit--) { 374 cmd = ioread16(ioaddr + MCR1); 375 if (cmd & MAC_RST) 376 break; 377 } 378 /* Reset internal state machine */ 379 iowrite16(MAC_SM_RST, ioaddr + MAC_SM); 380 iowrite16(0, ioaddr + MAC_SM); 381 mdelay(5); 382 383 /* MAC Bus Control Register */ 384 iowrite16(MBCR_DEFAULT, ioaddr + MBCR); 385 386 /* Buffer Size Register */ 387 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR); 388 389 /* Write TX ring start address */ 390 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0); 391 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1); 392 393 /* Write RX ring start address */ 394 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0); 395 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1); 396 397 /* Set interrupt waiting time and packet numbers */ 398 iowrite16(0, ioaddr + MT_ICR); 399 iowrite16(0, ioaddr + MR_ICR); 400 401 /* Enable interrupts */ 402 iowrite16(INT_MASK, ioaddr + MIER); 403 404 /* Enable TX and RX */ 405 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr); 406 407 /* Let TX poll the descriptors 408 * we may got called by r6040_tx_timeout which has left 409 * some unsent tx buffers */ 410 iowrite16(0x01, ioaddr + MTPR); 411} 412 413static void r6040_tx_timeout(struct net_device *dev) 414{ 415 struct r6040_private *priv = netdev_priv(dev); 416 void __iomem *ioaddr = priv->base; 417 418 netdev_warn(dev, "transmit timed out, int enable %4.4x " 419 "status %4.4x\n", 420 ioread16(ioaddr + MIER), 421 ioread16(ioaddr + MISR)); 422 423 dev->stats.tx_errors++; 424 425 /* Reset MAC and re-init all registers */ 426 r6040_init_mac_regs(dev); 427} 428 429static struct net_device_stats *r6040_get_stats(struct net_device *dev) 430{ 431 struct r6040_private *priv = netdev_priv(dev); 432 void __iomem *ioaddr = priv->base; 433 unsigned long flags; 434 435 spin_lock_irqsave(&priv->lock, flags); 436 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1); 437 dev->stats.multicast += ioread8(ioaddr + ME_CNT0); 438 spin_unlock_irqrestore(&priv->lock, flags); 439 440 return &dev->stats; 441} 442 443/* Stop RDC MAC and Free the allocated resource */ 444static void r6040_down(struct net_device *dev) 445{ 446 struct r6040_private *lp = netdev_priv(dev); 447 void __iomem *ioaddr = lp->base; 448 int limit = 2048; 449 u16 *adrp; 450 u16 cmd; 451 452 /* Stop MAC */ 453 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */ 454 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */ 455 while (limit--) { 456 cmd = ioread16(ioaddr + MCR1); 457 if (cmd & MAC_RST) 458 break; 459 } 460 461 /* Restore MAC Address to MIDx */ 462 adrp = (u16 *) dev->dev_addr; 463 iowrite16(adrp[0], ioaddr + MID_0L); 464 iowrite16(adrp[1], ioaddr + MID_0M); 465 iowrite16(adrp[2], ioaddr + MID_0H); 466 467 phy_stop(lp->phydev); 468} 469 470static int r6040_close(struct net_device *dev) 471{ 472 struct r6040_private *lp = netdev_priv(dev); 473 struct pci_dev *pdev = lp->pdev; 474 475 spin_lock_irq(&lp->lock); 476 napi_disable(&lp->napi); 477 netif_stop_queue(dev); 478 r6040_down(dev); 479 480 free_irq(dev->irq, dev); 481 482 /* Free RX buffer */ 483 r6040_free_rxbufs(dev); 484 485 /* Free TX buffer */ 486 r6040_free_txbufs(dev); 487 488 spin_unlock_irq(&lp->lock); 489 490 /* Free Descriptor memory */ 491 if (lp->rx_ring) { 492 pci_free_consistent(pdev, 493 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma); 494 lp->rx_ring = NULL; 495 } 496 497 if (lp->tx_ring) { 498 pci_free_consistent(pdev, 499 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma); 500 lp->tx_ring = NULL; 501 } 502 503 return 0; 504} 505 506static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 507{ 508 struct r6040_private *lp = netdev_priv(dev); 509 510 if (!lp->phydev) 511 return -EINVAL; 512 513 return phy_mii_ioctl(lp->phydev, rq, cmd); 514} 515 516static int r6040_rx(struct net_device *dev, int limit) 517{ 518 struct r6040_private *priv = netdev_priv(dev); 519 struct r6040_descriptor *descptr = priv->rx_remove_ptr; 520 struct sk_buff *skb_ptr, *new_skb; 521 int count = 0; 522 u16 err; 523 524 /* Limit not reached and the descriptor belongs to the CPU */ 525 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) { 526 /* Read the descriptor status */ 527 err = descptr->status; 528 /* Global error status set */ 529 if (err & DSC_RX_ERR) { 530 /* RX dribble */ 531 if (err & DSC_RX_ERR_DRI) 532 dev->stats.rx_frame_errors++; 533 /* Buffer length exceeded */ 534 if (err & DSC_RX_ERR_BUF) 535 dev->stats.rx_length_errors++; 536 /* Packet too long */ 537 if (err & DSC_RX_ERR_LONG) 538 dev->stats.rx_length_errors++; 539 /* Packet < 64 bytes */ 540 if (err & DSC_RX_ERR_RUNT) 541 dev->stats.rx_length_errors++; 542 /* CRC error */ 543 if (err & DSC_RX_ERR_CRC) { 544 spin_lock(&priv->lock); 545 dev->stats.rx_crc_errors++; 546 spin_unlock(&priv->lock); 547 } 548 goto next_descr; 549 } 550 551 /* Packet successfully received */ 552 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE); 553 if (!new_skb) { 554 dev->stats.rx_dropped++; 555 goto next_descr; 556 } 557 skb_ptr = descptr->skb_ptr; 558 skb_ptr->dev = priv->dev; 559 560 /* Do not count the CRC */ 561 skb_put(skb_ptr, descptr->len - 4); 562 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf), 563 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE); 564 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev); 565 566 /* Send to upper layer */ 567 netif_receive_skb(skb_ptr); 568 dev->stats.rx_packets++; 569 dev->stats.rx_bytes += descptr->len - 4; 570 571 /* put new skb into descriptor */ 572 descptr->skb_ptr = new_skb; 573 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev, 574 descptr->skb_ptr->data, 575 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); 576 577next_descr: 578 /* put the descriptor back to the MAC */ 579 descptr->status = DSC_OWNER_MAC; 580 descptr = descptr->vndescp; 581 count++; 582 } 583 priv->rx_remove_ptr = descptr; 584 585 return count; 586} 587 588static void r6040_tx(struct net_device *dev) 589{ 590 struct r6040_private *priv = netdev_priv(dev); 591 struct r6040_descriptor *descptr; 592 void __iomem *ioaddr = priv->base; 593 struct sk_buff *skb_ptr; 594 u16 err; 595 596 spin_lock(&priv->lock); 597 descptr = priv->tx_remove_ptr; 598 while (priv->tx_free_desc < TX_DCNT) { 599 /* Check for errors */ 600 err = ioread16(ioaddr + MLSR); 601 602 if (err & 0x0200) 603 dev->stats.rx_fifo_errors++; 604 if (err & (0x2000 | 0x4000)) 605 dev->stats.tx_carrier_errors++; 606 607 if (descptr->status & DSC_OWNER_MAC) 608 break; /* Not complete */ 609 skb_ptr = descptr->skb_ptr; 610 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf), 611 skb_ptr->len, PCI_DMA_TODEVICE); 612 /* Free buffer */ 613 dev_kfree_skb_irq(skb_ptr); 614 descptr->skb_ptr = NULL; 615 /* To next descriptor */ 616 descptr = descptr->vndescp; 617 priv->tx_free_desc++; 618 } 619 priv->tx_remove_ptr = descptr; 620 621 if (priv->tx_free_desc) 622 netif_wake_queue(dev); 623 spin_unlock(&priv->lock); 624} 625 626static int r6040_poll(struct napi_struct *napi, int budget) 627{ 628 struct r6040_private *priv = 629 container_of(napi, struct r6040_private, napi); 630 struct net_device *dev = priv->dev; 631 void __iomem *ioaddr = priv->base; 632 int work_done; 633 634 work_done = r6040_rx(dev, budget); 635 636 if (work_done < budget) { 637 napi_complete(napi); 638 /* Enable RX interrupt */ 639 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER); 640 } 641 return work_done; 642} 643 644/* The RDC interrupt handler. */ 645static irqreturn_t r6040_interrupt(int irq, void *dev_id) 646{ 647 struct net_device *dev = dev_id; 648 struct r6040_private *lp = netdev_priv(dev); 649 void __iomem *ioaddr = lp->base; 650 u16 misr, status; 651 652 /* Save MIER */ 653 misr = ioread16(ioaddr + MIER); 654 /* Mask off RDC MAC interrupt */ 655 iowrite16(MSK_INT, ioaddr + MIER); 656 /* Read MISR status and clear */ 657 status = ioread16(ioaddr + MISR); 658 659 if (status == 0x0000 || status == 0xffff) { 660 /* Restore RDC MAC interrupt */ 661 iowrite16(misr, ioaddr + MIER); 662 return IRQ_NONE; 663 } 664 665 /* RX interrupt request */ 666 if (status & RX_INTS) { 667 if (status & RX_NO_DESC) { 668 /* RX descriptor unavailable */ 669 dev->stats.rx_dropped++; 670 dev->stats.rx_missed_errors++; 671 } 672 if (status & RX_FIFO_FULL) 673 dev->stats.rx_fifo_errors++; 674 675 if (likely(napi_schedule_prep(&lp->napi))) { 676 /* Mask off RX interrupt */ 677 misr &= ~RX_INTS; 678 __napi_schedule(&lp->napi); 679 } 680 } 681 682 /* TX interrupt request */ 683 if (status & TX_INTS) 684 r6040_tx(dev); 685 686 /* Restore RDC MAC interrupt */ 687 iowrite16(misr, ioaddr + MIER); 688 689 return IRQ_HANDLED; 690} 691 692#ifdef CONFIG_NET_POLL_CONTROLLER 693static void r6040_poll_controller(struct net_device *dev) 694{ 695 disable_irq(dev->irq); 696 r6040_interrupt(dev->irq, dev); 697 enable_irq(dev->irq); 698} 699#endif 700 701/* Init RDC MAC */ 702static int r6040_up(struct net_device *dev) 703{ 704 struct r6040_private *lp = netdev_priv(dev); 705 void __iomem *ioaddr = lp->base; 706 int ret; 707 708 /* Initialise and alloc RX/TX buffers */ 709 r6040_init_txbufs(dev); 710 ret = r6040_alloc_rxbufs(dev); 711 if (ret) 712 return ret; 713 714 /* improve performance (by RDC guys) */ 715 r6040_phy_write(ioaddr, 30, 17, 716 (r6040_phy_read(ioaddr, 30, 17) | 0x4000)); 717 r6040_phy_write(ioaddr, 30, 17, 718 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000)); 719 r6040_phy_write(ioaddr, 0, 19, 0x0000); 720 r6040_phy_write(ioaddr, 0, 30, 0x01F0); 721 722 /* Initialize all MAC registers */ 723 r6040_init_mac_regs(dev); 724 725 phy_start(lp->phydev); 726 727 return 0; 728} 729 730 731/* Read/set MAC address routines */ 732static void r6040_mac_address(struct net_device *dev) 733{ 734 struct r6040_private *lp = netdev_priv(dev); 735 void __iomem *ioaddr = lp->base; 736 u16 *adrp; 737 738 /* MAC operation register */ 739 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset MAC */ 740 iowrite16(MAC_SM_RST, ioaddr + MAC_SM); /* Reset internal state machine */ 741 iowrite16(0, ioaddr + MAC_SM); 742 mdelay(5); 743 744 /* Restore MAC Address */ 745 adrp = (u16 *) dev->dev_addr; 746 iowrite16(adrp[0], ioaddr + MID_0L); 747 iowrite16(adrp[1], ioaddr + MID_0M); 748 iowrite16(adrp[2], ioaddr + MID_0H); 749 750 /* Store MAC Address in perm_addr */ 751 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN); 752} 753 754static int r6040_open(struct net_device *dev) 755{ 756 struct r6040_private *lp = netdev_priv(dev); 757 int ret; 758 759 /* Request IRQ and Register interrupt handler */ 760 ret = request_irq(dev->irq, r6040_interrupt, 761 IRQF_SHARED, dev->name, dev); 762 if (ret) 763 goto out; 764 765 /* Set MAC address */ 766 r6040_mac_address(dev); 767 768 /* Allocate Descriptor memory */ 769 lp->rx_ring = 770 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma); 771 if (!lp->rx_ring) { 772 ret = -ENOMEM; 773 goto err_free_irq; 774 } 775 776 lp->tx_ring = 777 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma); 778 if (!lp->tx_ring) { 779 ret = -ENOMEM; 780 goto err_free_rx_ring; 781 } 782 783 ret = r6040_up(dev); 784 if (ret) 785 goto err_free_tx_ring; 786 787 napi_enable(&lp->napi); 788 netif_start_queue(dev); 789 790 return 0; 791 792err_free_tx_ring: 793 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring, 794 lp->tx_ring_dma); 795err_free_rx_ring: 796 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring, 797 lp->rx_ring_dma); 798err_free_irq: 799 free_irq(dev->irq, dev); 800out: 801 return ret; 802} 803 804static netdev_tx_t r6040_start_xmit(struct sk_buff *skb, 805 struct net_device *dev) 806{ 807 struct r6040_private *lp = netdev_priv(dev); 808 struct r6040_descriptor *descptr; 809 void __iomem *ioaddr = lp->base; 810 unsigned long flags; 811 812 /* Critical Section */ 813 spin_lock_irqsave(&lp->lock, flags); 814 815 /* TX resource check */ 816 if (!lp->tx_free_desc) { 817 spin_unlock_irqrestore(&lp->lock, flags); 818 netif_stop_queue(dev); 819 netdev_err(dev, ": no tx descriptor\n"); 820 return NETDEV_TX_BUSY; 821 } 822 823 /* Statistic Counter */ 824 dev->stats.tx_packets++; 825 dev->stats.tx_bytes += skb->len; 826 /* Set TX descriptor & Transmit it */ 827 lp->tx_free_desc--; 828 descptr = lp->tx_insert_ptr; 829 if (skb->len < MISR) 830 descptr->len = MISR; 831 else 832 descptr->len = skb->len; 833 834 descptr->skb_ptr = skb; 835 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, 836 skb->data, skb->len, PCI_DMA_TODEVICE)); 837 descptr->status = DSC_OWNER_MAC; 838 839 skb_tx_timestamp(skb); 840 841 /* Trigger the MAC to check the TX descriptor */ 842 iowrite16(0x01, ioaddr + MTPR); 843 lp->tx_insert_ptr = descptr->vndescp; 844 845 /* If no tx resource, stop */ 846 if (!lp->tx_free_desc) 847 netif_stop_queue(dev); 848 849 spin_unlock_irqrestore(&lp->lock, flags); 850 851 return NETDEV_TX_OK; 852} 853 854static void r6040_multicast_list(struct net_device *dev) 855{ 856 struct r6040_private *lp = netdev_priv(dev); 857 void __iomem *ioaddr = lp->base; 858 unsigned long flags; 859 struct netdev_hw_addr *ha; 860 int i; 861 u16 *adrp; 862 u16 hash_table[4] = { 0 }; 863 864 spin_lock_irqsave(&lp->lock, flags); 865 866 /* Keep our MAC Address */ 867 adrp = (u16 *)dev->dev_addr; 868 iowrite16(adrp[0], ioaddr + MID_0L); 869 iowrite16(adrp[1], ioaddr + MID_0M); 870 iowrite16(adrp[2], ioaddr + MID_0H); 871 872 /* Clear AMCP & PROM bits */ 873 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN); 874 875 /* Promiscuous mode */ 876 if (dev->flags & IFF_PROMISC) 877 lp->mcr0 |= MCR0_PROMISC; 878 879 /* Enable multicast hash table function to 880 * receive all multicast packets. */ 881 else if (dev->flags & IFF_ALLMULTI) { 882 lp->mcr0 |= MCR0_HASH_EN; 883 884 for (i = 0; i < MCAST_MAX ; i++) { 885 iowrite16(0, ioaddr + MID_1L + 8 * i); 886 iowrite16(0, ioaddr + MID_1M + 8 * i); 887 iowrite16(0, ioaddr + MID_1H + 8 * i); 888 } 889 890 for (i = 0; i < 4; i++) 891 hash_table[i] = 0xffff; 892 } 893 /* Use internal multicast address registers if the number of 894 * multicast addresses is not greater than MCAST_MAX. */ 895 else if (netdev_mc_count(dev) <= MCAST_MAX) { 896 i = 0; 897 netdev_for_each_mc_addr(ha, dev) { 898 u16 *adrp = (u16 *) ha->addr; 899 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i); 900 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i); 901 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i); 902 i++; 903 } 904 while (i < MCAST_MAX) { 905 iowrite16(0, ioaddr + MID_1L + 8 * i); 906 iowrite16(0, ioaddr + MID_1M + 8 * i); 907 iowrite16(0, ioaddr + MID_1H + 8 * i); 908 i++; 909 } 910 } 911 /* Otherwise, Enable multicast hash table function. */ 912 else { 913 u32 crc; 914 915 lp->mcr0 |= MCR0_HASH_EN; 916 917 for (i = 0; i < MCAST_MAX ; i++) { 918 iowrite16(0, ioaddr + MID_1L + 8 * i); 919 iowrite16(0, ioaddr + MID_1M + 8 * i); 920 iowrite16(0, ioaddr + MID_1H + 8 * i); 921 } 922 923 /* Build multicast hash table */ 924 netdev_for_each_mc_addr(ha, dev) { 925 u8 *addrs = ha->addr; 926 927 crc = ether_crc(ETH_ALEN, addrs); 928 crc >>= 26; 929 hash_table[crc >> 4] |= 1 << (crc & 0xf); 930 } 931 } 932 933 iowrite16(lp->mcr0, ioaddr + MCR0); 934 935 /* Fill the MAC hash tables with their values */ 936 if (lp->mcr0 & MCR0_HASH_EN) { 937 iowrite16(hash_table[0], ioaddr + MAR0); 938 iowrite16(hash_table[1], ioaddr + MAR1); 939 iowrite16(hash_table[2], ioaddr + MAR2); 940 iowrite16(hash_table[3], ioaddr + MAR3); 941 } 942 943 spin_unlock_irqrestore(&lp->lock, flags); 944} 945 946static void netdev_get_drvinfo(struct net_device *dev, 947 struct ethtool_drvinfo *info) 948{ 949 struct r6040_private *rp = netdev_priv(dev); 950 951 strcpy(info->driver, DRV_NAME); 952 strcpy(info->version, DRV_VERSION); 953 strcpy(info->bus_info, pci_name(rp->pdev)); 954} 955 956static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 957{ 958 struct r6040_private *rp = netdev_priv(dev); 959 960 return phy_ethtool_gset(rp->phydev, cmd); 961} 962 963static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 964{ 965 struct r6040_private *rp = netdev_priv(dev); 966 967 return phy_ethtool_sset(rp->phydev, cmd); 968} 969 970static const struct ethtool_ops netdev_ethtool_ops = { 971 .get_drvinfo = netdev_get_drvinfo, 972 .get_settings = netdev_get_settings, 973 .set_settings = netdev_set_settings, 974 .get_link = ethtool_op_get_link, 975}; 976 977static const struct net_device_ops r6040_netdev_ops = { 978 .ndo_open = r6040_open, 979 .ndo_stop = r6040_close, 980 .ndo_start_xmit = r6040_start_xmit, 981 .ndo_get_stats = r6040_get_stats, 982 .ndo_set_rx_mode = r6040_multicast_list, 983 .ndo_change_mtu = eth_change_mtu, 984 .ndo_validate_addr = eth_validate_addr, 985 .ndo_set_mac_address = eth_mac_addr, 986 .ndo_do_ioctl = r6040_ioctl, 987 .ndo_tx_timeout = r6040_tx_timeout, 988#ifdef CONFIG_NET_POLL_CONTROLLER 989 .ndo_poll_controller = r6040_poll_controller, 990#endif 991}; 992 993static void r6040_adjust_link(struct net_device *dev) 994{ 995 struct r6040_private *lp = netdev_priv(dev); 996 struct phy_device *phydev = lp->phydev; 997 int status_changed = 0; 998 void __iomem *ioaddr = lp->base; 999 1000 BUG_ON(!phydev); 1001 1002 if (lp->old_link != phydev->link) { 1003 status_changed = 1; 1004 lp->old_link = phydev->link; 1005 } 1006 1007 /* reflect duplex change */ 1008 if (phydev->link && (lp->old_duplex != phydev->duplex)) { 1009 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0); 1010 iowrite16(lp->mcr0, ioaddr); 1011 1012 status_changed = 1; 1013 lp->old_duplex = phydev->duplex; 1014 } 1015 1016 if (status_changed) { 1017 pr_info("%s: link %s", dev->name, phydev->link ? 1018 "UP" : "DOWN"); 1019 if (phydev->link) 1020 pr_cont(" - %d/%s", phydev->speed, 1021 DUPLEX_FULL == phydev->duplex ? "full" : "half"); 1022 pr_cont("\n"); 1023 } 1024} 1025 1026static int r6040_mii_probe(struct net_device *dev) 1027{ 1028 struct r6040_private *lp = netdev_priv(dev); 1029 struct phy_device *phydev = NULL; 1030 1031 phydev = phy_find_first(lp->mii_bus); 1032 if (!phydev) { 1033 dev_err(&lp->pdev->dev, "no PHY found\n"); 1034 return -ENODEV; 1035 } 1036 1037 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link, 1038 0, PHY_INTERFACE_MODE_MII); 1039 1040 if (IS_ERR(phydev)) { 1041 dev_err(&lp->pdev->dev, "could not attach to PHY\n"); 1042 return PTR_ERR(phydev); 1043 } 1044 1045 /* mask with MAC supported features */ 1046 phydev->supported &= (SUPPORTED_10baseT_Half 1047 | SUPPORTED_10baseT_Full 1048 | SUPPORTED_100baseT_Half 1049 | SUPPORTED_100baseT_Full 1050 | SUPPORTED_Autoneg 1051 | SUPPORTED_MII 1052 | SUPPORTED_TP); 1053 1054 phydev->advertising = phydev->supported; 1055 lp->phydev = phydev; 1056 lp->old_link = 0; 1057 lp->old_duplex = -1; 1058 1059 dev_info(&lp->pdev->dev, "attached PHY driver [%s] " 1060 "(mii_bus:phy_addr=%s)\n", 1061 phydev->drv->name, dev_name(&phydev->dev)); 1062 1063 return 0; 1064} 1065 1066static int __devinit r6040_init_one(struct pci_dev *pdev, 1067 const struct pci_device_id *ent) 1068{ 1069 struct net_device *dev; 1070 struct r6040_private *lp; 1071 void __iomem *ioaddr; 1072 int err, io_size = R6040_IO_SIZE; 1073 static int card_idx = -1; 1074 int bar = 0; 1075 u16 *adrp; 1076 int i; 1077 1078 pr_info("%s\n", version); 1079 1080 err = pci_enable_device(pdev); 1081 if (err) 1082 goto err_out; 1083 1084 /* this should always be supported */ 1085 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1086 if (err) { 1087 dev_err(&pdev->dev, "32-bit PCI DMA addresses" 1088 "not supported by the card\n"); 1089 goto err_out; 1090 } 1091 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1092 if (err) { 1093 dev_err(&pdev->dev, "32-bit PCI DMA addresses" 1094 "not supported by the card\n"); 1095 goto err_out; 1096 } 1097 1098 /* IO Size check */ 1099 if (pci_resource_len(pdev, bar) < io_size) { 1100 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n"); 1101 err = -EIO; 1102 goto err_out; 1103 } 1104 1105 pci_set_master(pdev); 1106 1107 dev = alloc_etherdev(sizeof(struct r6040_private)); 1108 if (!dev) { 1109 dev_err(&pdev->dev, "Failed to allocate etherdev\n"); 1110 err = -ENOMEM; 1111 goto err_out; 1112 } 1113 SET_NETDEV_DEV(dev, &pdev->dev); 1114 lp = netdev_priv(dev); 1115 1116 err = pci_request_regions(pdev, DRV_NAME); 1117 1118 if (err) { 1119 dev_err(&pdev->dev, "Failed to request PCI regions\n"); 1120 goto err_out_free_dev; 1121 } 1122 1123 ioaddr = pci_iomap(pdev, bar, io_size); 1124 if (!ioaddr) { 1125 dev_err(&pdev->dev, "ioremap failed for device\n"); 1126 err = -EIO; 1127 goto err_out_free_res; 1128 } 1129 /* If PHY status change register is still set to zero it means the 1130 * bootloader didn't initialize it */ 1131 if (ioread16(ioaddr + PHY_CC) == 0) 1132 iowrite16(0x9f07, ioaddr + PHY_CC); 1133 1134 /* Init system & device */ 1135 lp->base = ioaddr; 1136 dev->irq = pdev->irq; 1137 1138 spin_lock_init(&lp->lock); 1139 pci_set_drvdata(pdev, dev); 1140 1141 /* Set MAC address */ 1142 card_idx++; 1143 1144 adrp = (u16 *)dev->dev_addr; 1145 adrp[0] = ioread16(ioaddr + MID_0L); 1146 adrp[1] = ioread16(ioaddr + MID_0M); 1147 adrp[2] = ioread16(ioaddr + MID_0H); 1148 1149 /* Some bootloader/BIOSes do not initialize 1150 * MAC address, warn about that */ 1151 if (!(adrp[0] || adrp[1] || adrp[2])) { 1152 netdev_warn(dev, "MAC address not initialized, " 1153 "generating random\n"); 1154 random_ether_addr(dev->dev_addr); 1155 } 1156 1157 /* Link new device into r6040_root_dev */ 1158 lp->pdev = pdev; 1159 lp->dev = dev; 1160 1161 /* Init RDC private data */ 1162 lp->mcr0 = MCR0_XMTEN | MCR0; 1163 1164 /* The RDC-specific entries in the device structure. */ 1165 dev->netdev_ops = &r6040_netdev_ops; 1166 dev->ethtool_ops = &netdev_ethtool_ops; 1167 dev->watchdog_timeo = TX_TIMEOUT; 1168 1169 netif_napi_add(dev, &lp->napi, r6040_poll, 64); 1170 1171 lp->mii_bus = mdiobus_alloc(); 1172 if (!lp->mii_bus) { 1173 dev_err(&pdev->dev, "mdiobus_alloc() failed\n"); 1174 err = -ENOMEM; 1175 goto err_out_unmap; 1176 } 1177 1178 lp->mii_bus->priv = dev; 1179 lp->mii_bus->read = r6040_mdiobus_read; 1180 lp->mii_bus->write = r6040_mdiobus_write; 1181 lp->mii_bus->reset = r6040_mdiobus_reset; 1182 lp->mii_bus->name = "r6040_eth_mii"; 1183 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1184 dev_name(&pdev->dev), card_idx); 1185 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); 1186 if (!lp->mii_bus->irq) { 1187 dev_err(&pdev->dev, "mii_bus irq allocation failed\n"); 1188 err = -ENOMEM; 1189 goto err_out_mdio; 1190 } 1191 1192 for (i = 0; i < PHY_MAX_ADDR; i++) 1193 lp->mii_bus->irq[i] = PHY_POLL; 1194 1195 err = mdiobus_register(lp->mii_bus); 1196 if (err) { 1197 dev_err(&pdev->dev, "failed to register MII bus\n"); 1198 goto err_out_mdio_irq; 1199 } 1200 1201 err = r6040_mii_probe(dev); 1202 if (err) { 1203 dev_err(&pdev->dev, "failed to probe MII bus\n"); 1204 goto err_out_mdio_unregister; 1205 } 1206 1207 /* Register net device. After this dev->name assign */ 1208 err = register_netdev(dev); 1209 if (err) { 1210 dev_err(&pdev->dev, "Failed to register net device\n"); 1211 goto err_out_mdio_unregister; 1212 } 1213 return 0; 1214 1215err_out_mdio_unregister: 1216 mdiobus_unregister(lp->mii_bus); 1217err_out_mdio_irq: 1218 kfree(lp->mii_bus->irq); 1219err_out_mdio: 1220 mdiobus_free(lp->mii_bus); 1221err_out_unmap: 1222 pci_iounmap(pdev, ioaddr); 1223err_out_free_res: 1224 pci_release_regions(pdev); 1225err_out_free_dev: 1226 free_netdev(dev); 1227err_out: 1228 return err; 1229} 1230 1231static void __devexit r6040_remove_one(struct pci_dev *pdev) 1232{ 1233 struct net_device *dev = pci_get_drvdata(pdev); 1234 struct r6040_private *lp = netdev_priv(dev); 1235 1236 unregister_netdev(dev); 1237 mdiobus_unregister(lp->mii_bus); 1238 kfree(lp->mii_bus->irq); 1239 mdiobus_free(lp->mii_bus); 1240 pci_release_regions(pdev); 1241 free_netdev(dev); 1242 pci_disable_device(pdev); 1243 pci_set_drvdata(pdev, NULL); 1244} 1245 1246 1247static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = { 1248 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) }, 1249 { 0 } 1250}; 1251MODULE_DEVICE_TABLE(pci, r6040_pci_tbl); 1252 1253static struct pci_driver r6040_driver = { 1254 .name = DRV_NAME, 1255 .id_table = r6040_pci_tbl, 1256 .probe = r6040_init_one, 1257 .remove = __devexit_p(r6040_remove_one), 1258}; 1259 1260 1261static int __init r6040_init(void) 1262{ 1263 return pci_register_driver(&r6040_driver); 1264} 1265 1266 1267static void __exit r6040_cleanup(void) 1268{ 1269 pci_unregister_driver(&r6040_driver); 1270} 1271 1272module_init(r6040_init); 1273module_exit(r6040_cleanup); 1274