tc35815.c revision f2cedb63df14342ad40a8b5b324fc5d94a60b665
1/* 2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux. 3 * 4 * Based on skelton.c by Donald Becker. 5 * 6 * This driver is a replacement of older and less maintained version. 7 * This is a header of the older version: 8 * -----<snip>----- 9 * Copyright 2001 MontaVista Software Inc. 10 * Author: MontaVista Software, Inc. 11 * ahennessy@mvista.com 12 * Copyright (C) 2000-2001 Toshiba Corporation 13 * static const char *version = 14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n"; 15 * -----<snip>----- 16 * 17 * This file is subject to the terms and conditions of the GNU General Public 18 * License. See the file "COPYING" in the main directory of this archive 19 * for more details. 20 * 21 * (C) Copyright TOSHIBA CORPORATION 2004-2005 22 * All Rights Reserved. 23 */ 24 25#define DRV_VERSION "1.39" 26static const char *version = "tc35815.c:v" DRV_VERSION "\n"; 27#define MODNAME "tc35815" 28 29#include <linux/module.h> 30#include <linux/kernel.h> 31#include <linux/types.h> 32#include <linux/fcntl.h> 33#include <linux/interrupt.h> 34#include <linux/ioport.h> 35#include <linux/in.h> 36#include <linux/if_vlan.h> 37#include <linux/slab.h> 38#include <linux/string.h> 39#include <linux/spinlock.h> 40#include <linux/errno.h> 41#include <linux/init.h> 42#include <linux/netdevice.h> 43#include <linux/etherdevice.h> 44#include <linux/skbuff.h> 45#include <linux/delay.h> 46#include <linux/pci.h> 47#include <linux/phy.h> 48#include <linux/workqueue.h> 49#include <linux/platform_device.h> 50#include <linux/prefetch.h> 51#include <asm/io.h> 52#include <asm/byteorder.h> 53 54enum tc35815_chiptype { 55 TC35815CF = 0, 56 TC35815_NWU, 57 TC35815_TX4939, 58}; 59 60/* indexed by tc35815_chiptype, above */ 61static const struct { 62 const char *name; 63} chip_info[] __devinitdata = { 64 { "TOSHIBA TC35815CF 10/100BaseTX" }, 65 { "TOSHIBA TC35815 with Wake on LAN" }, 66 { "TOSHIBA TC35815/TX4939" }, 67}; 68 69static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = { 70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF }, 71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU }, 72 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 }, 73 {0,} 74}; 75MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl); 76 77/* see MODULE_PARM_DESC */ 78static struct tc35815_options { 79 int speed; 80 int duplex; 81} options; 82 83/* 84 * Registers 85 */ 86struct tc35815_regs { 87 __u32 DMA_Ctl; /* 0x00 */ 88 __u32 TxFrmPtr; 89 __u32 TxThrsh; 90 __u32 TxPollCtr; 91 __u32 BLFrmPtr; 92 __u32 RxFragSize; 93 __u32 Int_En; 94 __u32 FDA_Bas; 95 __u32 FDA_Lim; /* 0x20 */ 96 __u32 Int_Src; 97 __u32 unused0[2]; 98 __u32 PauseCnt; 99 __u32 RemPauCnt; 100 __u32 TxCtlFrmStat; 101 __u32 unused1; 102 __u32 MAC_Ctl; /* 0x40 */ 103 __u32 CAM_Ctl; 104 __u32 Tx_Ctl; 105 __u32 Tx_Stat; 106 __u32 Rx_Ctl; 107 __u32 Rx_Stat; 108 __u32 MD_Data; 109 __u32 MD_CA; 110 __u32 CAM_Adr; /* 0x60 */ 111 __u32 CAM_Data; 112 __u32 CAM_Ena; 113 __u32 PROM_Ctl; 114 __u32 PROM_Data; 115 __u32 Algn_Cnt; 116 __u32 CRC_Cnt; 117 __u32 Miss_Cnt; 118}; 119 120/* 121 * Bit assignments 122 */ 123/* DMA_Ctl bit assign ------------------------------------------------------- */ 124#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */ 125#define DMA_RxAlign_1 0x00400000 126#define DMA_RxAlign_2 0x00800000 127#define DMA_RxAlign_3 0x00c00000 128#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */ 129#define DMA_IntMask 0x00040000 /* 1:Interrupt mask */ 130#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ 131#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */ 132#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */ 133#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */ 134#define DMA_TestMode 0x00002000 /* 1:Test Mode */ 135#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */ 136#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */ 137 138/* RxFragSize bit assign ---------------------------------------------------- */ 139#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */ 140#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ 141 142/* MAC_Ctl bit assign ------------------------------------------------------- */ 143#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */ 144#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ 145#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */ 146#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */ 147#define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */ 148#define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/ 149#define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */ 150#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */ 151#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */ 152#define MAC_Reset 0x00000004 /* 1:Software Reset */ 153#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */ 154#define MAC_HaltReq 0x00000001 /* 1:Halt request */ 155 156/* PROM_Ctl bit assign ------------------------------------------------------ */ 157#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */ 158#define PROM_Read 0x00004000 /*10:Read operation */ 159#define PROM_Write 0x00002000 /*01:Write operation */ 160#define PROM_Erase 0x00006000 /*11:Erase operation */ 161 /*00:Enable or Disable Writting, */ 162 /* as specified in PROM_Addr. */ 163#define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */ 164 /*00xxxx: disable */ 165 166/* CAM_Ctl bit assign ------------------------------------------------------- */ 167#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */ 168#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/ 169 /* accept other */ 170#define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */ 171#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */ 172#define CAM_StationAcc 0x00000001 /* 1:unicast accept */ 173 174/* CAM_Ena bit assign ------------------------------------------------------- */ 175#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */ 176#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */ 177#define CAM_Ena_Bit(index) (1 << (index)) 178#define CAM_ENTRY_DESTINATION 0 179#define CAM_ENTRY_SOURCE 1 180#define CAM_ENTRY_MACCTL 20 181 182/* Tx_Ctl bit assign -------------------------------------------------------- */ 183#define Tx_En 0x00000001 /* 1:Transmit enable */ 184#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ 185#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */ 186#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */ 187#define Tx_FBack 0x00000010 /* 1:Fast Back-off */ 188#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */ 189#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */ 190#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */ 191#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */ 192#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */ 193#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ 194#define Tx_EnComp 0x00004000 /* 1:Enable Completion */ 195 196/* Tx_Stat bit assign ------------------------------------------------------- */ 197#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ 198#define Tx_ExColl 0x00000010 /* Excessive Collision */ 199#define Tx_TXDefer 0x00000020 /* Transmit Defered */ 200#define Tx_Paused 0x00000040 /* Transmit Paused */ 201#define Tx_IntTx 0x00000080 /* Interrupt on Tx */ 202#define Tx_Under 0x00000100 /* Underrun */ 203#define Tx_Defer 0x00000200 /* Deferral */ 204#define Tx_NCarr 0x00000400 /* No Carrier */ 205#define Tx_10Stat 0x00000800 /* 10Mbps Status */ 206#define Tx_LateColl 0x00001000 /* Late Collision */ 207#define Tx_TxPar 0x00002000 /* Tx Parity Error */ 208#define Tx_Comp 0x00004000 /* Completion */ 209#define Tx_Halted 0x00008000 /* Tx Halted */ 210#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ 211 212/* Rx_Ctl bit assign -------------------------------------------------------- */ 213#define Rx_EnGood 0x00004000 /* 1:Enable Good */ 214#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ 215#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */ 216#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */ 217#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */ 218#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */ 219#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */ 220#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */ 221#define Rx_ShortEn 0x00000008 /* 1:Short Enable */ 222#define Rx_LongEn 0x00000004 /* 1:Long Enable */ 223#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */ 224#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ 225 226/* Rx_Stat bit assign ------------------------------------------------------- */ 227#define Rx_Halted 0x00008000 /* Rx Halted */ 228#define Rx_Good 0x00004000 /* Rx Good */ 229#define Rx_RxPar 0x00002000 /* Rx Parity Error */ 230#define Rx_TypePkt 0x00001000 /* Rx Type Packet */ 231#define Rx_LongErr 0x00000800 /* Rx Long Error */ 232#define Rx_Over 0x00000400 /* Rx Overflow */ 233#define Rx_CRCErr 0x00000200 /* Rx CRC Error */ 234#define Rx_Align 0x00000100 /* Rx Alignment Error */ 235#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */ 236#define Rx_IntRx 0x00000040 /* Rx Interrupt */ 237#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */ 238#define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */ 239 240#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */ 241 242/* Int_En bit assign -------------------------------------------------------- */ 243#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */ 244#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */ 245#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */ 246#define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */ 247#define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */ 248#define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */ 249#define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */ 250#define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */ 251#define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */ 252#define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */ 253#define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */ 254#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */ 255 /* Exhausted Enable */ 256 257/* Int_Src bit assign ------------------------------------------------------- */ 258#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */ 259#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */ 260#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */ 261#define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */ 262#define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */ 263#define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */ 264#define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */ 265#define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */ 266#define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */ 267#define Int_SWInt 0x00000020 /* 1:Software request & Clear */ 268#define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */ 269#define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */ 270#define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */ 271#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */ 272#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */ 273 274/* MD_CA bit assign --------------------------------------------------------- */ 275#define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */ 276#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */ 277#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */ 278 279 280/* 281 * Descriptors 282 */ 283 284/* Frame descripter */ 285struct FDesc { 286 volatile __u32 FDNext; 287 volatile __u32 FDSystem; 288 volatile __u32 FDStat; 289 volatile __u32 FDCtl; 290}; 291 292/* Buffer descripter */ 293struct BDesc { 294 volatile __u32 BuffData; 295 volatile __u32 BDCtl; 296}; 297 298#define FD_ALIGN 16 299 300/* Frame Descripter bit assign ---------------------------------------------- */ 301#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */ 302#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ 303#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */ 304#define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */ 305#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */ 306#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */ 307#define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */ 308#define FD_FrmOpt_Packing 0x04000000 /* Rx only */ 309#define FD_CownsFD 0x80000000 /* FD Controller owner bit */ 310#define FD_Next_EOL 0x00000001 /* FD EOL indicator */ 311#define FD_BDCnt_SHIFT 16 312 313/* Buffer Descripter bit assign --------------------------------------------- */ 314#define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */ 315#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */ 316#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ 317#define BD_CownsBD 0x80000000 /* BD Controller owner bit */ 318#define BD_RxBDID_SHIFT 16 319#define BD_RxBDSeqN_SHIFT 24 320 321 322/* Some useful constants. */ 323 324#define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \ 325 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \ 326 Tx_En) /* maybe 0x7b01 */ 327/* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */ 328#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \ 329 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */ 330#define INT_EN_CMD (Int_NRAbtEn | \ 331 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \ 332 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \ 333 Int_STargAbtEn | \ 334 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/ 335#define DMA_CTL_CMD DMA_BURST_SIZE 336#define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF) 337 338/* Tuning parameters */ 339#define DMA_BURST_SIZE 32 340#define TX_THRESHOLD 1024 341/* used threshold with packet max byte for low pci transfer ability.*/ 342#define TX_THRESHOLD_MAX 1536 343/* setting threshold max value when overrun error occurred this count. */ 344#define TX_THRESHOLD_KEEP_LIMIT 10 345 346/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */ 347#define FD_PAGE_NUM 4 348#define RX_BUF_NUM 128 /* < 256 */ 349#define RX_FD_NUM 256 /* >= 32 */ 350#define TX_FD_NUM 128 351#if RX_CTL_CMD & Rx_LongEn 352#define RX_BUF_SIZE PAGE_SIZE 353#elif RX_CTL_CMD & Rx_StripCRC 354#define RX_BUF_SIZE \ 355 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN) 356#else 357#define RX_BUF_SIZE \ 358 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN) 359#endif 360#define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */ 361#define NAPI_WEIGHT 16 362 363struct TxFD { 364 struct FDesc fd; 365 struct BDesc bd; 366 struct BDesc unused; 367}; 368 369struct RxFD { 370 struct FDesc fd; 371 struct BDesc bd[0]; /* variable length */ 372}; 373 374struct FrFD { 375 struct FDesc fd; 376 struct BDesc bd[RX_BUF_NUM]; 377}; 378 379 380#define tc_readl(addr) ioread32(addr) 381#define tc_writel(d, addr) iowrite32(d, addr) 382 383#define TC35815_TX_TIMEOUT msecs_to_jiffies(400) 384 385/* Information that need to be kept for each controller. */ 386struct tc35815_local { 387 struct pci_dev *pci_dev; 388 389 struct net_device *dev; 390 struct napi_struct napi; 391 392 /* statistics */ 393 struct { 394 int max_tx_qlen; 395 int tx_ints; 396 int rx_ints; 397 int tx_underrun; 398 } lstats; 399 400 /* Tx control lock. This protects the transmit buffer ring 401 * state along with the "tx full" state of the driver. This 402 * means all netif_queue flow control actions are protected 403 * by this lock as well. 404 */ 405 spinlock_t lock; 406 spinlock_t rx_lock; 407 408 struct mii_bus *mii_bus; 409 struct phy_device *phy_dev; 410 int duplex; 411 int speed; 412 int link; 413 struct work_struct restart_work; 414 415 /* 416 * Transmitting: Batch Mode. 417 * 1 BD in 1 TxFD. 418 * Receiving: Non-Packing Mode. 419 * 1 circular FD for Free Buffer List. 420 * RX_BUF_NUM BD in Free Buffer FD. 421 * One Free Buffer BD has ETH_FRAME_LEN data buffer. 422 */ 423 void *fd_buf; /* for TxFD, RxFD, FrFD */ 424 dma_addr_t fd_buf_dma; 425 struct TxFD *tfd_base; 426 unsigned int tfd_start; 427 unsigned int tfd_end; 428 struct RxFD *rfd_base; 429 struct RxFD *rfd_limit; 430 struct RxFD *rfd_cur; 431 struct FrFD *fbl_ptr; 432 unsigned int fbl_count; 433 struct { 434 struct sk_buff *skb; 435 dma_addr_t skb_dma; 436 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM]; 437 u32 msg_enable; 438 enum tc35815_chiptype chiptype; 439}; 440 441static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt) 442{ 443 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf); 444} 445#ifdef DEBUG 446static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus) 447{ 448 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma)); 449} 450#endif 451static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev, 452 struct pci_dev *hwdev, 453 dma_addr_t *dma_handle) 454{ 455 struct sk_buff *skb; 456 skb = netdev_alloc_skb(dev, RX_BUF_SIZE); 457 if (!skb) 458 return NULL; 459 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE, 460 PCI_DMA_FROMDEVICE); 461 if (pci_dma_mapping_error(hwdev, *dma_handle)) { 462 dev_kfree_skb_any(skb); 463 return NULL; 464 } 465 skb_reserve(skb, 2); /* make IP header 4byte aligned */ 466 return skb; 467} 468 469static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle) 470{ 471 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE, 472 PCI_DMA_FROMDEVICE); 473 dev_kfree_skb_any(skb); 474} 475 476/* Index to functions, as function prototypes. */ 477 478static int tc35815_open(struct net_device *dev); 479static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev); 480static irqreturn_t tc35815_interrupt(int irq, void *dev_id); 481static int tc35815_rx(struct net_device *dev, int limit); 482static int tc35815_poll(struct napi_struct *napi, int budget); 483static void tc35815_txdone(struct net_device *dev); 484static int tc35815_close(struct net_device *dev); 485static struct net_device_stats *tc35815_get_stats(struct net_device *dev); 486static void tc35815_set_multicast_list(struct net_device *dev); 487static void tc35815_tx_timeout(struct net_device *dev); 488static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 489#ifdef CONFIG_NET_POLL_CONTROLLER 490static void tc35815_poll_controller(struct net_device *dev); 491#endif 492static const struct ethtool_ops tc35815_ethtool_ops; 493 494/* Example routines you must write ;->. */ 495static void tc35815_chip_reset(struct net_device *dev); 496static void tc35815_chip_init(struct net_device *dev); 497 498#ifdef DEBUG 499static void panic_queues(struct net_device *dev); 500#endif 501 502static void tc35815_restart_work(struct work_struct *work); 503 504static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 505{ 506 struct net_device *dev = bus->priv; 507 struct tc35815_regs __iomem *tr = 508 (struct tc35815_regs __iomem *)dev->base_addr; 509 unsigned long timeout = jiffies + HZ; 510 511 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA); 512 udelay(12); /* it takes 32 x 400ns at least */ 513 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { 514 if (time_after(jiffies, timeout)) 515 return -EIO; 516 cpu_relax(); 517 } 518 return tc_readl(&tr->MD_Data) & 0xffff; 519} 520 521static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val) 522{ 523 struct net_device *dev = bus->priv; 524 struct tc35815_regs __iomem *tr = 525 (struct tc35815_regs __iomem *)dev->base_addr; 526 unsigned long timeout = jiffies + HZ; 527 528 tc_writel(val, &tr->MD_Data); 529 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f), 530 &tr->MD_CA); 531 udelay(12); /* it takes 32 x 400ns at least */ 532 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { 533 if (time_after(jiffies, timeout)) 534 return -EIO; 535 cpu_relax(); 536 } 537 return 0; 538} 539 540static void tc_handle_link_change(struct net_device *dev) 541{ 542 struct tc35815_local *lp = netdev_priv(dev); 543 struct phy_device *phydev = lp->phy_dev; 544 unsigned long flags; 545 int status_change = 0; 546 547 spin_lock_irqsave(&lp->lock, flags); 548 if (phydev->link && 549 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) { 550 struct tc35815_regs __iomem *tr = 551 (struct tc35815_regs __iomem *)dev->base_addr; 552 u32 reg; 553 554 reg = tc_readl(&tr->MAC_Ctl); 555 reg |= MAC_HaltReq; 556 tc_writel(reg, &tr->MAC_Ctl); 557 if (phydev->duplex == DUPLEX_FULL) 558 reg |= MAC_FullDup; 559 else 560 reg &= ~MAC_FullDup; 561 tc_writel(reg, &tr->MAC_Ctl); 562 reg &= ~MAC_HaltReq; 563 tc_writel(reg, &tr->MAC_Ctl); 564 565 /* 566 * TX4939 PCFG.SPEEDn bit will be changed on 567 * NETDEV_CHANGE event. 568 */ 569 /* 570 * WORKAROUND: enable LostCrS only if half duplex 571 * operation. 572 * (TX4939 does not have EnLCarr) 573 */ 574 if (phydev->duplex == DUPLEX_HALF && 575 lp->chiptype != TC35815_TX4939) 576 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr, 577 &tr->Tx_Ctl); 578 579 lp->speed = phydev->speed; 580 lp->duplex = phydev->duplex; 581 status_change = 1; 582 } 583 584 if (phydev->link != lp->link) { 585 if (phydev->link) { 586 /* delayed promiscuous enabling */ 587 if (dev->flags & IFF_PROMISC) 588 tc35815_set_multicast_list(dev); 589 } else { 590 lp->speed = 0; 591 lp->duplex = -1; 592 } 593 lp->link = phydev->link; 594 595 status_change = 1; 596 } 597 spin_unlock_irqrestore(&lp->lock, flags); 598 599 if (status_change && netif_msg_link(lp)) { 600 phy_print_status(phydev); 601 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n", 602 dev->name, 603 phy_read(phydev, MII_BMCR), 604 phy_read(phydev, MII_BMSR), 605 phy_read(phydev, MII_LPA)); 606 } 607} 608 609static int tc_mii_probe(struct net_device *dev) 610{ 611 struct tc35815_local *lp = netdev_priv(dev); 612 struct phy_device *phydev = NULL; 613 int phy_addr; 614 u32 dropmask; 615 616 /* find the first phy */ 617 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 618 if (lp->mii_bus->phy_map[phy_addr]) { 619 if (phydev) { 620 printk(KERN_ERR "%s: multiple PHYs found\n", 621 dev->name); 622 return -EINVAL; 623 } 624 phydev = lp->mii_bus->phy_map[phy_addr]; 625 break; 626 } 627 } 628 629 if (!phydev) { 630 printk(KERN_ERR "%s: no PHY found\n", dev->name); 631 return -ENODEV; 632 } 633 634 /* attach the mac to the phy */ 635 phydev = phy_connect(dev, dev_name(&phydev->dev), 636 &tc_handle_link_change, 0, 637 lp->chiptype == TC35815_TX4939 ? 638 PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII); 639 if (IS_ERR(phydev)) { 640 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); 641 return PTR_ERR(phydev); 642 } 643 printk(KERN_INFO "%s: attached PHY driver [%s] " 644 "(mii_bus:phy_addr=%s, id=%x)\n", 645 dev->name, phydev->drv->name, dev_name(&phydev->dev), 646 phydev->phy_id); 647 648 /* mask with MAC supported features */ 649 phydev->supported &= PHY_BASIC_FEATURES; 650 dropmask = 0; 651 if (options.speed == 10) 652 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full; 653 else if (options.speed == 100) 654 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full; 655 if (options.duplex == 1) 656 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full; 657 else if (options.duplex == 2) 658 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half; 659 phydev->supported &= ~dropmask; 660 phydev->advertising = phydev->supported; 661 662 lp->link = 0; 663 lp->speed = 0; 664 lp->duplex = -1; 665 lp->phy_dev = phydev; 666 667 return 0; 668} 669 670static int tc_mii_init(struct net_device *dev) 671{ 672 struct tc35815_local *lp = netdev_priv(dev); 673 int err; 674 int i; 675 676 lp->mii_bus = mdiobus_alloc(); 677 if (lp->mii_bus == NULL) { 678 err = -ENOMEM; 679 goto err_out; 680 } 681 682 lp->mii_bus->name = "tc35815_mii_bus"; 683 lp->mii_bus->read = tc_mdio_read; 684 lp->mii_bus->write = tc_mdio_write; 685 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 686 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn); 687 lp->mii_bus->priv = dev; 688 lp->mii_bus->parent = &lp->pci_dev->dev; 689 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 690 if (!lp->mii_bus->irq) { 691 err = -ENOMEM; 692 goto err_out_free_mii_bus; 693 } 694 695 for (i = 0; i < PHY_MAX_ADDR; i++) 696 lp->mii_bus->irq[i] = PHY_POLL; 697 698 err = mdiobus_register(lp->mii_bus); 699 if (err) 700 goto err_out_free_mdio_irq; 701 err = tc_mii_probe(dev); 702 if (err) 703 goto err_out_unregister_bus; 704 return 0; 705 706err_out_unregister_bus: 707 mdiobus_unregister(lp->mii_bus); 708err_out_free_mdio_irq: 709 kfree(lp->mii_bus->irq); 710err_out_free_mii_bus: 711 mdiobus_free(lp->mii_bus); 712err_out: 713 return err; 714} 715 716#ifdef CONFIG_CPU_TX49XX 717/* 718 * Find a platform_device providing a MAC address. The platform code 719 * should provide a "tc35815-mac" device with a MAC address in its 720 * platform_data. 721 */ 722static int __devinit tc35815_mac_match(struct device *dev, void *data) 723{ 724 struct platform_device *plat_dev = to_platform_device(dev); 725 struct pci_dev *pci_dev = data; 726 unsigned int id = pci_dev->irq; 727 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id; 728} 729 730static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev) 731{ 732 struct tc35815_local *lp = netdev_priv(dev); 733 struct device *pd = bus_find_device(&platform_bus_type, NULL, 734 lp->pci_dev, tc35815_mac_match); 735 if (pd) { 736 if (pd->platform_data) 737 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN); 738 put_device(pd); 739 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV; 740 } 741 return -ENODEV; 742} 743#else 744static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev) 745{ 746 return -ENODEV; 747} 748#endif 749 750static int __devinit tc35815_init_dev_addr(struct net_device *dev) 751{ 752 struct tc35815_regs __iomem *tr = 753 (struct tc35815_regs __iomem *)dev->base_addr; 754 int i; 755 756 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) 757 ; 758 for (i = 0; i < 6; i += 2) { 759 unsigned short data; 760 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl); 761 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) 762 ; 763 data = tc_readl(&tr->PROM_Data); 764 dev->dev_addr[i] = data & 0xff; 765 dev->dev_addr[i+1] = data >> 8; 766 } 767 if (!is_valid_ether_addr(dev->dev_addr)) 768 return tc35815_read_plat_dev_addr(dev); 769 return 0; 770} 771 772static const struct net_device_ops tc35815_netdev_ops = { 773 .ndo_open = tc35815_open, 774 .ndo_stop = tc35815_close, 775 .ndo_start_xmit = tc35815_send_packet, 776 .ndo_get_stats = tc35815_get_stats, 777 .ndo_set_rx_mode = tc35815_set_multicast_list, 778 .ndo_tx_timeout = tc35815_tx_timeout, 779 .ndo_do_ioctl = tc35815_ioctl, 780 .ndo_validate_addr = eth_validate_addr, 781 .ndo_change_mtu = eth_change_mtu, 782 .ndo_set_mac_address = eth_mac_addr, 783#ifdef CONFIG_NET_POLL_CONTROLLER 784 .ndo_poll_controller = tc35815_poll_controller, 785#endif 786}; 787 788static int __devinit tc35815_init_one(struct pci_dev *pdev, 789 const struct pci_device_id *ent) 790{ 791 void __iomem *ioaddr = NULL; 792 struct net_device *dev; 793 struct tc35815_local *lp; 794 int rc; 795 796 static int printed_version; 797 if (!printed_version++) { 798 printk(version); 799 dev_printk(KERN_DEBUG, &pdev->dev, 800 "speed:%d duplex:%d\n", 801 options.speed, options.duplex); 802 } 803 804 if (!pdev->irq) { 805 dev_warn(&pdev->dev, "no IRQ assigned.\n"); 806 return -ENODEV; 807 } 808 809 /* dev zeroed in alloc_etherdev */ 810 dev = alloc_etherdev(sizeof(*lp)); 811 if (dev == NULL) 812 return -ENOMEM; 813 814 SET_NETDEV_DEV(dev, &pdev->dev); 815 lp = netdev_priv(dev); 816 lp->dev = dev; 817 818 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 819 rc = pcim_enable_device(pdev); 820 if (rc) 821 goto err_out; 822 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME); 823 if (rc) 824 goto err_out; 825 pci_set_master(pdev); 826 ioaddr = pcim_iomap_table(pdev)[1]; 827 828 /* Initialize the device structure. */ 829 dev->netdev_ops = &tc35815_netdev_ops; 830 dev->ethtool_ops = &tc35815_ethtool_ops; 831 dev->watchdog_timeo = TC35815_TX_TIMEOUT; 832 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT); 833 834 dev->irq = pdev->irq; 835 dev->base_addr = (unsigned long)ioaddr; 836 837 INIT_WORK(&lp->restart_work, tc35815_restart_work); 838 spin_lock_init(&lp->lock); 839 spin_lock_init(&lp->rx_lock); 840 lp->pci_dev = pdev; 841 lp->chiptype = ent->driver_data; 842 843 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK; 844 pci_set_drvdata(pdev, dev); 845 846 /* Soft reset the chip. */ 847 tc35815_chip_reset(dev); 848 849 /* Retrieve the ethernet address. */ 850 if (tc35815_init_dev_addr(dev)) { 851 dev_warn(&pdev->dev, "not valid ether addr\n"); 852 eth_hw_addr_random(dev); 853 } 854 855 rc = register_netdev(dev); 856 if (rc) 857 goto err_out; 858 859 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 860 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n", 861 dev->name, 862 chip_info[ent->driver_data].name, 863 dev->base_addr, 864 dev->dev_addr, 865 dev->irq); 866 867 rc = tc_mii_init(dev); 868 if (rc) 869 goto err_out_unregister; 870 871 return 0; 872 873err_out_unregister: 874 unregister_netdev(dev); 875err_out: 876 free_netdev(dev); 877 return rc; 878} 879 880 881static void __devexit tc35815_remove_one(struct pci_dev *pdev) 882{ 883 struct net_device *dev = pci_get_drvdata(pdev); 884 struct tc35815_local *lp = netdev_priv(dev); 885 886 phy_disconnect(lp->phy_dev); 887 mdiobus_unregister(lp->mii_bus); 888 kfree(lp->mii_bus->irq); 889 mdiobus_free(lp->mii_bus); 890 unregister_netdev(dev); 891 free_netdev(dev); 892 pci_set_drvdata(pdev, NULL); 893} 894 895static int 896tc35815_init_queues(struct net_device *dev) 897{ 898 struct tc35815_local *lp = netdev_priv(dev); 899 int i; 900 unsigned long fd_addr; 901 902 if (!lp->fd_buf) { 903 BUG_ON(sizeof(struct FDesc) + 904 sizeof(struct BDesc) * RX_BUF_NUM + 905 sizeof(struct FDesc) * RX_FD_NUM + 906 sizeof(struct TxFD) * TX_FD_NUM > 907 PAGE_SIZE * FD_PAGE_NUM); 908 909 lp->fd_buf = pci_alloc_consistent(lp->pci_dev, 910 PAGE_SIZE * FD_PAGE_NUM, 911 &lp->fd_buf_dma); 912 if (!lp->fd_buf) 913 return -ENOMEM; 914 for (i = 0; i < RX_BUF_NUM; i++) { 915 lp->rx_skbs[i].skb = 916 alloc_rxbuf_skb(dev, lp->pci_dev, 917 &lp->rx_skbs[i].skb_dma); 918 if (!lp->rx_skbs[i].skb) { 919 while (--i >= 0) { 920 free_rxbuf_skb(lp->pci_dev, 921 lp->rx_skbs[i].skb, 922 lp->rx_skbs[i].skb_dma); 923 lp->rx_skbs[i].skb = NULL; 924 } 925 pci_free_consistent(lp->pci_dev, 926 PAGE_SIZE * FD_PAGE_NUM, 927 lp->fd_buf, 928 lp->fd_buf_dma); 929 lp->fd_buf = NULL; 930 return -ENOMEM; 931 } 932 } 933 printk(KERN_DEBUG "%s: FD buf %p DataBuf", 934 dev->name, lp->fd_buf); 935 printk("\n"); 936 } else { 937 for (i = 0; i < FD_PAGE_NUM; i++) 938 clear_page((void *)((unsigned long)lp->fd_buf + 939 i * PAGE_SIZE)); 940 } 941 fd_addr = (unsigned long)lp->fd_buf; 942 943 /* Free Descriptors (for Receive) */ 944 lp->rfd_base = (struct RxFD *)fd_addr; 945 fd_addr += sizeof(struct RxFD) * RX_FD_NUM; 946 for (i = 0; i < RX_FD_NUM; i++) 947 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD); 948 lp->rfd_cur = lp->rfd_base; 949 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1); 950 951 /* Transmit Descriptors */ 952 lp->tfd_base = (struct TxFD *)fd_addr; 953 fd_addr += sizeof(struct TxFD) * TX_FD_NUM; 954 for (i = 0; i < TX_FD_NUM; i++) { 955 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1])); 956 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 957 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0); 958 } 959 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0])); 960 lp->tfd_start = 0; 961 lp->tfd_end = 0; 962 963 /* Buffer List (for Receive) */ 964 lp->fbl_ptr = (struct FrFD *)fd_addr; 965 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr)); 966 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD); 967 /* 968 * move all allocated skbs to head of rx_skbs[] array. 969 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in 970 * tc35815_rx() had failed. 971 */ 972 lp->fbl_count = 0; 973 for (i = 0; i < RX_BUF_NUM; i++) { 974 if (lp->rx_skbs[i].skb) { 975 if (i != lp->fbl_count) { 976 lp->rx_skbs[lp->fbl_count].skb = 977 lp->rx_skbs[i].skb; 978 lp->rx_skbs[lp->fbl_count].skb_dma = 979 lp->rx_skbs[i].skb_dma; 980 } 981 lp->fbl_count++; 982 } 983 } 984 for (i = 0; i < RX_BUF_NUM; i++) { 985 if (i >= lp->fbl_count) { 986 lp->fbl_ptr->bd[i].BuffData = 0; 987 lp->fbl_ptr->bd[i].BDCtl = 0; 988 continue; 989 } 990 lp->fbl_ptr->bd[i].BuffData = 991 cpu_to_le32(lp->rx_skbs[i].skb_dma); 992 /* BDID is index of FrFD.bd[] */ 993 lp->fbl_ptr->bd[i].BDCtl = 994 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | 995 RX_BUF_SIZE); 996 } 997 998 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n", 999 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr); 1000 return 0; 1001} 1002 1003static void 1004tc35815_clear_queues(struct net_device *dev) 1005{ 1006 struct tc35815_local *lp = netdev_priv(dev); 1007 int i; 1008 1009 for (i = 0; i < TX_FD_NUM; i++) { 1010 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); 1011 struct sk_buff *skb = 1012 fdsystem != 0xffffffff ? 1013 lp->tx_skbs[fdsystem].skb : NULL; 1014#ifdef DEBUG 1015 if (lp->tx_skbs[i].skb != skb) { 1016 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); 1017 panic_queues(dev); 1018 } 1019#else 1020 BUG_ON(lp->tx_skbs[i].skb != skb); 1021#endif 1022 if (skb) { 1023 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); 1024 lp->tx_skbs[i].skb = NULL; 1025 lp->tx_skbs[i].skb_dma = 0; 1026 dev_kfree_skb_any(skb); 1027 } 1028 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 1029 } 1030 1031 tc35815_init_queues(dev); 1032} 1033 1034static void 1035tc35815_free_queues(struct net_device *dev) 1036{ 1037 struct tc35815_local *lp = netdev_priv(dev); 1038 int i; 1039 1040 if (lp->tfd_base) { 1041 for (i = 0; i < TX_FD_NUM; i++) { 1042 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); 1043 struct sk_buff *skb = 1044 fdsystem != 0xffffffff ? 1045 lp->tx_skbs[fdsystem].skb : NULL; 1046#ifdef DEBUG 1047 if (lp->tx_skbs[i].skb != skb) { 1048 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); 1049 panic_queues(dev); 1050 } 1051#else 1052 BUG_ON(lp->tx_skbs[i].skb != skb); 1053#endif 1054 if (skb) { 1055 dev_kfree_skb(skb); 1056 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); 1057 lp->tx_skbs[i].skb = NULL; 1058 lp->tx_skbs[i].skb_dma = 0; 1059 } 1060 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 1061 } 1062 } 1063 1064 lp->rfd_base = NULL; 1065 lp->rfd_limit = NULL; 1066 lp->rfd_cur = NULL; 1067 lp->fbl_ptr = NULL; 1068 1069 for (i = 0; i < RX_BUF_NUM; i++) { 1070 if (lp->rx_skbs[i].skb) { 1071 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb, 1072 lp->rx_skbs[i].skb_dma); 1073 lp->rx_skbs[i].skb = NULL; 1074 } 1075 } 1076 if (lp->fd_buf) { 1077 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM, 1078 lp->fd_buf, lp->fd_buf_dma); 1079 lp->fd_buf = NULL; 1080 } 1081} 1082 1083static void 1084dump_txfd(struct TxFD *fd) 1085{ 1086 printk("TxFD(%p): %08x %08x %08x %08x\n", fd, 1087 le32_to_cpu(fd->fd.FDNext), 1088 le32_to_cpu(fd->fd.FDSystem), 1089 le32_to_cpu(fd->fd.FDStat), 1090 le32_to_cpu(fd->fd.FDCtl)); 1091 printk("BD: "); 1092 printk(" %08x %08x", 1093 le32_to_cpu(fd->bd.BuffData), 1094 le32_to_cpu(fd->bd.BDCtl)); 1095 printk("\n"); 1096} 1097 1098static int 1099dump_rxfd(struct RxFD *fd) 1100{ 1101 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; 1102 if (bd_count > 8) 1103 bd_count = 8; 1104 printk("RxFD(%p): %08x %08x %08x %08x\n", fd, 1105 le32_to_cpu(fd->fd.FDNext), 1106 le32_to_cpu(fd->fd.FDSystem), 1107 le32_to_cpu(fd->fd.FDStat), 1108 le32_to_cpu(fd->fd.FDCtl)); 1109 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD) 1110 return 0; 1111 printk("BD: "); 1112 for (i = 0; i < bd_count; i++) 1113 printk(" %08x %08x", 1114 le32_to_cpu(fd->bd[i].BuffData), 1115 le32_to_cpu(fd->bd[i].BDCtl)); 1116 printk("\n"); 1117 return bd_count; 1118} 1119 1120#ifdef DEBUG 1121static void 1122dump_frfd(struct FrFD *fd) 1123{ 1124 int i; 1125 printk("FrFD(%p): %08x %08x %08x %08x\n", fd, 1126 le32_to_cpu(fd->fd.FDNext), 1127 le32_to_cpu(fd->fd.FDSystem), 1128 le32_to_cpu(fd->fd.FDStat), 1129 le32_to_cpu(fd->fd.FDCtl)); 1130 printk("BD: "); 1131 for (i = 0; i < RX_BUF_NUM; i++) 1132 printk(" %08x %08x", 1133 le32_to_cpu(fd->bd[i].BuffData), 1134 le32_to_cpu(fd->bd[i].BDCtl)); 1135 printk("\n"); 1136} 1137 1138static void 1139panic_queues(struct net_device *dev) 1140{ 1141 struct tc35815_local *lp = netdev_priv(dev); 1142 int i; 1143 1144 printk("TxFD base %p, start %u, end %u\n", 1145 lp->tfd_base, lp->tfd_start, lp->tfd_end); 1146 printk("RxFD base %p limit %p cur %p\n", 1147 lp->rfd_base, lp->rfd_limit, lp->rfd_cur); 1148 printk("FrFD %p\n", lp->fbl_ptr); 1149 for (i = 0; i < TX_FD_NUM; i++) 1150 dump_txfd(&lp->tfd_base[i]); 1151 for (i = 0; i < RX_FD_NUM; i++) { 1152 int bd_count = dump_rxfd(&lp->rfd_base[i]); 1153 i += (bd_count + 1) / 2; /* skip BDs */ 1154 } 1155 dump_frfd(lp->fbl_ptr); 1156 panic("%s: Illegal queue state.", dev->name); 1157} 1158#endif 1159 1160static void print_eth(const u8 *add) 1161{ 1162 printk(KERN_DEBUG "print_eth(%p)\n", add); 1163 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n", 1164 add + 6, add, add[12], add[13]); 1165} 1166 1167static int tc35815_tx_full(struct net_device *dev) 1168{ 1169 struct tc35815_local *lp = netdev_priv(dev); 1170 return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end; 1171} 1172 1173static void tc35815_restart(struct net_device *dev) 1174{ 1175 struct tc35815_local *lp = netdev_priv(dev); 1176 1177 if (lp->phy_dev) { 1178 int timeout; 1179 1180 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET); 1181 timeout = 100; 1182 while (--timeout) { 1183 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET)) 1184 break; 1185 udelay(1); 1186 } 1187 if (!timeout) 1188 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name); 1189 } 1190 1191 spin_lock_bh(&lp->rx_lock); 1192 spin_lock_irq(&lp->lock); 1193 tc35815_chip_reset(dev); 1194 tc35815_clear_queues(dev); 1195 tc35815_chip_init(dev); 1196 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */ 1197 tc35815_set_multicast_list(dev); 1198 spin_unlock_irq(&lp->lock); 1199 spin_unlock_bh(&lp->rx_lock); 1200 1201 netif_wake_queue(dev); 1202} 1203 1204static void tc35815_restart_work(struct work_struct *work) 1205{ 1206 struct tc35815_local *lp = 1207 container_of(work, struct tc35815_local, restart_work); 1208 struct net_device *dev = lp->dev; 1209 1210 tc35815_restart(dev); 1211} 1212 1213static void tc35815_schedule_restart(struct net_device *dev) 1214{ 1215 struct tc35815_local *lp = netdev_priv(dev); 1216 struct tc35815_regs __iomem *tr = 1217 (struct tc35815_regs __iomem *)dev->base_addr; 1218 unsigned long flags; 1219 1220 /* disable interrupts */ 1221 spin_lock_irqsave(&lp->lock, flags); 1222 tc_writel(0, &tr->Int_En); 1223 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl); 1224 schedule_work(&lp->restart_work); 1225 spin_unlock_irqrestore(&lp->lock, flags); 1226} 1227 1228static void tc35815_tx_timeout(struct net_device *dev) 1229{ 1230 struct tc35815_regs __iomem *tr = 1231 (struct tc35815_regs __iomem *)dev->base_addr; 1232 1233 printk(KERN_WARNING "%s: transmit timed out, status %#x\n", 1234 dev->name, tc_readl(&tr->Tx_Stat)); 1235 1236 /* Try to restart the adaptor. */ 1237 tc35815_schedule_restart(dev); 1238 dev->stats.tx_errors++; 1239} 1240 1241/* 1242 * Open/initialize the controller. This is called (in the current kernel) 1243 * sometime after booting when the 'ifconfig' program is run. 1244 * 1245 * This routine should set everything up anew at each open, even 1246 * registers that "should" only need to be set once at boot, so that 1247 * there is non-reboot way to recover if something goes wrong. 1248 */ 1249static int 1250tc35815_open(struct net_device *dev) 1251{ 1252 struct tc35815_local *lp = netdev_priv(dev); 1253 1254 /* 1255 * This is used if the interrupt line can turned off (shared). 1256 * See 3c503.c for an example of selecting the IRQ at config-time. 1257 */ 1258 if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED, 1259 dev->name, dev)) 1260 return -EAGAIN; 1261 1262 tc35815_chip_reset(dev); 1263 1264 if (tc35815_init_queues(dev) != 0) { 1265 free_irq(dev->irq, dev); 1266 return -EAGAIN; 1267 } 1268 1269 napi_enable(&lp->napi); 1270 1271 /* Reset the hardware here. Don't forget to set the station address. */ 1272 spin_lock_irq(&lp->lock); 1273 tc35815_chip_init(dev); 1274 spin_unlock_irq(&lp->lock); 1275 1276 netif_carrier_off(dev); 1277 /* schedule a link state check */ 1278 phy_start(lp->phy_dev); 1279 1280 /* We are now ready to accept transmit requeusts from 1281 * the queueing layer of the networking. 1282 */ 1283 netif_start_queue(dev); 1284 1285 return 0; 1286} 1287 1288/* This will only be invoked if your driver is _not_ in XOFF state. 1289 * What this means is that you need not check it, and that this 1290 * invariant will hold if you make sure that the netif_*_queue() 1291 * calls are done at the proper times. 1292 */ 1293static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev) 1294{ 1295 struct tc35815_local *lp = netdev_priv(dev); 1296 struct TxFD *txfd; 1297 unsigned long flags; 1298 1299 /* If some error occurs while trying to transmit this 1300 * packet, you should return '1' from this function. 1301 * In such a case you _may not_ do anything to the 1302 * SKB, it is still owned by the network queueing 1303 * layer when an error is returned. This means you 1304 * may not modify any SKB fields, you may not free 1305 * the SKB, etc. 1306 */ 1307 1308 /* This is the most common case for modern hardware. 1309 * The spinlock protects this code from the TX complete 1310 * hardware interrupt handler. Queue flow control is 1311 * thus managed under this lock as well. 1312 */ 1313 spin_lock_irqsave(&lp->lock, flags); 1314 1315 /* failsafe... (handle txdone now if half of FDs are used) */ 1316 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM > 1317 TX_FD_NUM / 2) 1318 tc35815_txdone(dev); 1319 1320 if (netif_msg_pktdata(lp)) 1321 print_eth(skb->data); 1322#ifdef DEBUG 1323 if (lp->tx_skbs[lp->tfd_start].skb) { 1324 printk("%s: tx_skbs conflict.\n", dev->name); 1325 panic_queues(dev); 1326 } 1327#else 1328 BUG_ON(lp->tx_skbs[lp->tfd_start].skb); 1329#endif 1330 lp->tx_skbs[lp->tfd_start].skb = skb; 1331 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 1332 1333 /*add to ring */ 1334 txfd = &lp->tfd_base[lp->tfd_start]; 1335 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma); 1336 txfd->bd.BDCtl = cpu_to_le32(skb->len); 1337 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start); 1338 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT)); 1339 1340 if (lp->tfd_start == lp->tfd_end) { 1341 struct tc35815_regs __iomem *tr = 1342 (struct tc35815_regs __iomem *)dev->base_addr; 1343 /* Start DMA Transmitter. */ 1344 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL); 1345 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); 1346 if (netif_msg_tx_queued(lp)) { 1347 printk("%s: starting TxFD.\n", dev->name); 1348 dump_txfd(txfd); 1349 } 1350 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); 1351 } else { 1352 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL); 1353 if (netif_msg_tx_queued(lp)) { 1354 printk("%s: queueing TxFD.\n", dev->name); 1355 dump_txfd(txfd); 1356 } 1357 } 1358 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM; 1359 1360 /* If we just used up the very last entry in the 1361 * TX ring on this device, tell the queueing 1362 * layer to send no more. 1363 */ 1364 if (tc35815_tx_full(dev)) { 1365 if (netif_msg_tx_queued(lp)) 1366 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name); 1367 netif_stop_queue(dev); 1368 } 1369 1370 /* When the TX completion hw interrupt arrives, this 1371 * is when the transmit statistics are updated. 1372 */ 1373 1374 spin_unlock_irqrestore(&lp->lock, flags); 1375 return NETDEV_TX_OK; 1376} 1377 1378#define FATAL_ERROR_INT \ 1379 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt) 1380static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status) 1381{ 1382 static int count; 1383 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):", 1384 dev->name, status); 1385 if (status & Int_IntPCI) 1386 printk(" IntPCI"); 1387 if (status & Int_DmParErr) 1388 printk(" DmParErr"); 1389 if (status & Int_IntNRAbt) 1390 printk(" IntNRAbt"); 1391 printk("\n"); 1392 if (count++ > 100) 1393 panic("%s: Too many fatal errors.", dev->name); 1394 printk(KERN_WARNING "%s: Resetting ...\n", dev->name); 1395 /* Try to restart the adaptor. */ 1396 tc35815_schedule_restart(dev); 1397} 1398 1399static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit) 1400{ 1401 struct tc35815_local *lp = netdev_priv(dev); 1402 int ret = -1; 1403 1404 /* Fatal errors... */ 1405 if (status & FATAL_ERROR_INT) { 1406 tc35815_fatal_error_interrupt(dev, status); 1407 return 0; 1408 } 1409 /* recoverable errors */ 1410 if (status & Int_IntFDAEx) { 1411 if (netif_msg_rx_err(lp)) 1412 dev_warn(&dev->dev, 1413 "Free Descriptor Area Exhausted (%#x).\n", 1414 status); 1415 dev->stats.rx_dropped++; 1416 ret = 0; 1417 } 1418 if (status & Int_IntBLEx) { 1419 if (netif_msg_rx_err(lp)) 1420 dev_warn(&dev->dev, 1421 "Buffer List Exhausted (%#x).\n", 1422 status); 1423 dev->stats.rx_dropped++; 1424 ret = 0; 1425 } 1426 if (status & Int_IntExBD) { 1427 if (netif_msg_rx_err(lp)) 1428 dev_warn(&dev->dev, 1429 "Excessive Buffer Descriptiors (%#x).\n", 1430 status); 1431 dev->stats.rx_length_errors++; 1432 ret = 0; 1433 } 1434 1435 /* normal notification */ 1436 if (status & Int_IntMacRx) { 1437 /* Got a packet(s). */ 1438 ret = tc35815_rx(dev, limit); 1439 lp->lstats.rx_ints++; 1440 } 1441 if (status & Int_IntMacTx) { 1442 /* Transmit complete. */ 1443 lp->lstats.tx_ints++; 1444 spin_lock_irq(&lp->lock); 1445 tc35815_txdone(dev); 1446 spin_unlock_irq(&lp->lock); 1447 if (ret < 0) 1448 ret = 0; 1449 } 1450 return ret; 1451} 1452 1453/* 1454 * The typical workload of the driver: 1455 * Handle the network interface interrupts. 1456 */ 1457static irqreturn_t tc35815_interrupt(int irq, void *dev_id) 1458{ 1459 struct net_device *dev = dev_id; 1460 struct tc35815_local *lp = netdev_priv(dev); 1461 struct tc35815_regs __iomem *tr = 1462 (struct tc35815_regs __iomem *)dev->base_addr; 1463 u32 dmactl = tc_readl(&tr->DMA_Ctl); 1464 1465 if (!(dmactl & DMA_IntMask)) { 1466 /* disable interrupts */ 1467 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl); 1468 if (napi_schedule_prep(&lp->napi)) 1469 __napi_schedule(&lp->napi); 1470 else { 1471 printk(KERN_ERR "%s: interrupt taken in poll\n", 1472 dev->name); 1473 BUG(); 1474 } 1475 (void)tc_readl(&tr->Int_Src); /* flush */ 1476 return IRQ_HANDLED; 1477 } 1478 return IRQ_NONE; 1479} 1480 1481#ifdef CONFIG_NET_POLL_CONTROLLER 1482static void tc35815_poll_controller(struct net_device *dev) 1483{ 1484 disable_irq(dev->irq); 1485 tc35815_interrupt(dev->irq, dev); 1486 enable_irq(dev->irq); 1487} 1488#endif 1489 1490/* We have a good packet(s), get it/them out of the buffers. */ 1491static int 1492tc35815_rx(struct net_device *dev, int limit) 1493{ 1494 struct tc35815_local *lp = netdev_priv(dev); 1495 unsigned int fdctl; 1496 int i; 1497 int received = 0; 1498 1499 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) { 1500 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat); 1501 int pkt_len = fdctl & FD_FDLength_MASK; 1502 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; 1503#ifdef DEBUG 1504 struct RxFD *next_rfd; 1505#endif 1506#if (RX_CTL_CMD & Rx_StripCRC) == 0 1507 pkt_len -= ETH_FCS_LEN; 1508#endif 1509 1510 if (netif_msg_rx_status(lp)) 1511 dump_rxfd(lp->rfd_cur); 1512 if (status & Rx_Good) { 1513 struct sk_buff *skb; 1514 unsigned char *data; 1515 int cur_bd; 1516 1517 if (--limit < 0) 1518 break; 1519 BUG_ON(bd_count > 1); 1520 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl) 1521 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; 1522#ifdef DEBUG 1523 if (cur_bd >= RX_BUF_NUM) { 1524 printk("%s: invalid BDID.\n", dev->name); 1525 panic_queues(dev); 1526 } 1527 BUG_ON(lp->rx_skbs[cur_bd].skb_dma != 1528 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3)); 1529 if (!lp->rx_skbs[cur_bd].skb) { 1530 printk("%s: NULL skb.\n", dev->name); 1531 panic_queues(dev); 1532 } 1533#else 1534 BUG_ON(cur_bd >= RX_BUF_NUM); 1535#endif 1536 skb = lp->rx_skbs[cur_bd].skb; 1537 prefetch(skb->data); 1538 lp->rx_skbs[cur_bd].skb = NULL; 1539 pci_unmap_single(lp->pci_dev, 1540 lp->rx_skbs[cur_bd].skb_dma, 1541 RX_BUF_SIZE, PCI_DMA_FROMDEVICE); 1542 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN) 1543 memmove(skb->data, skb->data - NET_IP_ALIGN, 1544 pkt_len); 1545 data = skb_put(skb, pkt_len); 1546 if (netif_msg_pktdata(lp)) 1547 print_eth(data); 1548 skb->protocol = eth_type_trans(skb, dev); 1549 netif_receive_skb(skb); 1550 received++; 1551 dev->stats.rx_packets++; 1552 dev->stats.rx_bytes += pkt_len; 1553 } else { 1554 dev->stats.rx_errors++; 1555 if (netif_msg_rx_err(lp)) 1556 dev_info(&dev->dev, "Rx error (status %x)\n", 1557 status & Rx_Stat_Mask); 1558 /* WORKAROUND: LongErr and CRCErr means Overflow. */ 1559 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) { 1560 status &= ~(Rx_LongErr|Rx_CRCErr); 1561 status |= Rx_Over; 1562 } 1563 if (status & Rx_LongErr) 1564 dev->stats.rx_length_errors++; 1565 if (status & Rx_Over) 1566 dev->stats.rx_fifo_errors++; 1567 if (status & Rx_CRCErr) 1568 dev->stats.rx_crc_errors++; 1569 if (status & Rx_Align) 1570 dev->stats.rx_frame_errors++; 1571 } 1572 1573 if (bd_count > 0) { 1574 /* put Free Buffer back to controller */ 1575 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl); 1576 unsigned char id = 1577 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; 1578#ifdef DEBUG 1579 if (id >= RX_BUF_NUM) { 1580 printk("%s: invalid BDID.\n", dev->name); 1581 panic_queues(dev); 1582 } 1583#else 1584 BUG_ON(id >= RX_BUF_NUM); 1585#endif 1586 /* free old buffers */ 1587 lp->fbl_count--; 1588 while (lp->fbl_count < RX_BUF_NUM) 1589 { 1590 unsigned char curid = 1591 (id + 1 + lp->fbl_count) % RX_BUF_NUM; 1592 struct BDesc *bd = &lp->fbl_ptr->bd[curid]; 1593#ifdef DEBUG 1594 bdctl = le32_to_cpu(bd->BDCtl); 1595 if (bdctl & BD_CownsBD) { 1596 printk("%s: Freeing invalid BD.\n", 1597 dev->name); 1598 panic_queues(dev); 1599 } 1600#endif 1601 /* pass BD to controller */ 1602 if (!lp->rx_skbs[curid].skb) { 1603 lp->rx_skbs[curid].skb = 1604 alloc_rxbuf_skb(dev, 1605 lp->pci_dev, 1606 &lp->rx_skbs[curid].skb_dma); 1607 if (!lp->rx_skbs[curid].skb) 1608 break; /* try on next reception */ 1609 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma); 1610 } 1611 /* Note: BDLength was modified by chip. */ 1612 bd->BDCtl = cpu_to_le32(BD_CownsBD | 1613 (curid << BD_RxBDID_SHIFT) | 1614 RX_BUF_SIZE); 1615 lp->fbl_count++; 1616 } 1617 } 1618 1619 /* put RxFD back to controller */ 1620#ifdef DEBUG 1621 next_rfd = fd_bus_to_virt(lp, 1622 le32_to_cpu(lp->rfd_cur->fd.FDNext)); 1623 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) { 1624 printk("%s: RxFD FDNext invalid.\n", dev->name); 1625 panic_queues(dev); 1626 } 1627#endif 1628 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) { 1629 /* pass FD to controller */ 1630#ifdef DEBUG 1631 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); 1632#else 1633 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL); 1634#endif 1635 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD); 1636 lp->rfd_cur++; 1637 } 1638 if (lp->rfd_cur > lp->rfd_limit) 1639 lp->rfd_cur = lp->rfd_base; 1640#ifdef DEBUG 1641 if (lp->rfd_cur != next_rfd) 1642 printk("rfd_cur = %p, next_rfd %p\n", 1643 lp->rfd_cur, next_rfd); 1644#endif 1645 } 1646 1647 return received; 1648} 1649 1650static int tc35815_poll(struct napi_struct *napi, int budget) 1651{ 1652 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi); 1653 struct net_device *dev = lp->dev; 1654 struct tc35815_regs __iomem *tr = 1655 (struct tc35815_regs __iomem *)dev->base_addr; 1656 int received = 0, handled; 1657 u32 status; 1658 1659 spin_lock(&lp->rx_lock); 1660 status = tc_readl(&tr->Int_Src); 1661 do { 1662 /* BLEx, FDAEx will be cleared later */ 1663 tc_writel(status & ~(Int_BLEx | Int_FDAEx), 1664 &tr->Int_Src); /* write to clear */ 1665 1666 handled = tc35815_do_interrupt(dev, status, budget - received); 1667 if (status & (Int_BLEx | Int_FDAEx)) 1668 tc_writel(status & (Int_BLEx | Int_FDAEx), 1669 &tr->Int_Src); 1670 if (handled >= 0) { 1671 received += handled; 1672 if (received >= budget) 1673 break; 1674 } 1675 status = tc_readl(&tr->Int_Src); 1676 } while (status); 1677 spin_unlock(&lp->rx_lock); 1678 1679 if (received < budget) { 1680 napi_complete(napi); 1681 /* enable interrupts */ 1682 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl); 1683 } 1684 return received; 1685} 1686 1687#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr) 1688 1689static void 1690tc35815_check_tx_stat(struct net_device *dev, int status) 1691{ 1692 struct tc35815_local *lp = netdev_priv(dev); 1693 const char *msg = NULL; 1694 1695 /* count collisions */ 1696 if (status & Tx_ExColl) 1697 dev->stats.collisions += 16; 1698 if (status & Tx_TxColl_MASK) 1699 dev->stats.collisions += status & Tx_TxColl_MASK; 1700 1701 /* TX4939 does not have NCarr */ 1702 if (lp->chiptype == TC35815_TX4939) 1703 status &= ~Tx_NCarr; 1704 /* WORKAROUND: ignore LostCrS in full duplex operation */ 1705 if (!lp->link || lp->duplex == DUPLEX_FULL) 1706 status &= ~Tx_NCarr; 1707 1708 if (!(status & TX_STA_ERR)) { 1709 /* no error. */ 1710 dev->stats.tx_packets++; 1711 return; 1712 } 1713 1714 dev->stats.tx_errors++; 1715 if (status & Tx_ExColl) { 1716 dev->stats.tx_aborted_errors++; 1717 msg = "Excessive Collision."; 1718 } 1719 if (status & Tx_Under) { 1720 dev->stats.tx_fifo_errors++; 1721 msg = "Tx FIFO Underrun."; 1722 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) { 1723 lp->lstats.tx_underrun++; 1724 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) { 1725 struct tc35815_regs __iomem *tr = 1726 (struct tc35815_regs __iomem *)dev->base_addr; 1727 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh); 1728 msg = "Tx FIFO Underrun.Change Tx threshold to max."; 1729 } 1730 } 1731 } 1732 if (status & Tx_Defer) { 1733 dev->stats.tx_fifo_errors++; 1734 msg = "Excessive Deferral."; 1735 } 1736 if (status & Tx_NCarr) { 1737 dev->stats.tx_carrier_errors++; 1738 msg = "Lost Carrier Sense."; 1739 } 1740 if (status & Tx_LateColl) { 1741 dev->stats.tx_aborted_errors++; 1742 msg = "Late Collision."; 1743 } 1744 if (status & Tx_TxPar) { 1745 dev->stats.tx_fifo_errors++; 1746 msg = "Transmit Parity Error."; 1747 } 1748 if (status & Tx_SQErr) { 1749 dev->stats.tx_heartbeat_errors++; 1750 msg = "Signal Quality Error."; 1751 } 1752 if (msg && netif_msg_tx_err(lp)) 1753 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status); 1754} 1755 1756/* This handles TX complete events posted by the device 1757 * via interrupts. 1758 */ 1759static void 1760tc35815_txdone(struct net_device *dev) 1761{ 1762 struct tc35815_local *lp = netdev_priv(dev); 1763 struct TxFD *txfd; 1764 unsigned int fdctl; 1765 1766 txfd = &lp->tfd_base[lp->tfd_end]; 1767 while (lp->tfd_start != lp->tfd_end && 1768 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) { 1769 int status = le32_to_cpu(txfd->fd.FDStat); 1770 struct sk_buff *skb; 1771 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext); 1772 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem); 1773 1774 if (netif_msg_tx_done(lp)) { 1775 printk("%s: complete TxFD.\n", dev->name); 1776 dump_txfd(txfd); 1777 } 1778 tc35815_check_tx_stat(dev, status); 1779 1780 skb = fdsystem != 0xffffffff ? 1781 lp->tx_skbs[fdsystem].skb : NULL; 1782#ifdef DEBUG 1783 if (lp->tx_skbs[lp->tfd_end].skb != skb) { 1784 printk("%s: tx_skbs mismatch.\n", dev->name); 1785 panic_queues(dev); 1786 } 1787#else 1788 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb); 1789#endif 1790 if (skb) { 1791 dev->stats.tx_bytes += skb->len; 1792 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE); 1793 lp->tx_skbs[lp->tfd_end].skb = NULL; 1794 lp->tx_skbs[lp->tfd_end].skb_dma = 0; 1795 dev_kfree_skb_any(skb); 1796 } 1797 txfd->fd.FDSystem = cpu_to_le32(0xffffffff); 1798 1799 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM; 1800 txfd = &lp->tfd_base[lp->tfd_end]; 1801#ifdef DEBUG 1802 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) { 1803 printk("%s: TxFD FDNext invalid.\n", dev->name); 1804 panic_queues(dev); 1805 } 1806#endif 1807 if (fdnext & FD_Next_EOL) { 1808 /* DMA Transmitter has been stopping... */ 1809 if (lp->tfd_end != lp->tfd_start) { 1810 struct tc35815_regs __iomem *tr = 1811 (struct tc35815_regs __iomem *)dev->base_addr; 1812 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM; 1813 struct TxFD *txhead = &lp->tfd_base[head]; 1814 int qlen = (lp->tfd_start + TX_FD_NUM 1815 - lp->tfd_end) % TX_FD_NUM; 1816 1817#ifdef DEBUG 1818 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) { 1819 printk("%s: TxFD FDCtl invalid.\n", dev->name); 1820 panic_queues(dev); 1821 } 1822#endif 1823 /* log max queue length */ 1824 if (lp->lstats.max_tx_qlen < qlen) 1825 lp->lstats.max_tx_qlen = qlen; 1826 1827 1828 /* start DMA Transmitter again */ 1829 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL); 1830 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); 1831 if (netif_msg_tx_queued(lp)) { 1832 printk("%s: start TxFD on queue.\n", 1833 dev->name); 1834 dump_txfd(txfd); 1835 } 1836 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); 1837 } 1838 break; 1839 } 1840 } 1841 1842 /* If we had stopped the queue due to a "tx full" 1843 * condition, and space has now been made available, 1844 * wake up the queue. 1845 */ 1846 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev)) 1847 netif_wake_queue(dev); 1848} 1849 1850/* The inverse routine to tc35815_open(). */ 1851static int 1852tc35815_close(struct net_device *dev) 1853{ 1854 struct tc35815_local *lp = netdev_priv(dev); 1855 1856 netif_stop_queue(dev); 1857 napi_disable(&lp->napi); 1858 if (lp->phy_dev) 1859 phy_stop(lp->phy_dev); 1860 cancel_work_sync(&lp->restart_work); 1861 1862 /* Flush the Tx and disable Rx here. */ 1863 tc35815_chip_reset(dev); 1864 free_irq(dev->irq, dev); 1865 1866 tc35815_free_queues(dev); 1867 1868 return 0; 1869 1870} 1871 1872/* 1873 * Get the current statistics. 1874 * This may be called with the card open or closed. 1875 */ 1876static struct net_device_stats *tc35815_get_stats(struct net_device *dev) 1877{ 1878 struct tc35815_regs __iomem *tr = 1879 (struct tc35815_regs __iomem *)dev->base_addr; 1880 if (netif_running(dev)) 1881 /* Update the statistics from the device registers. */ 1882 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt); 1883 1884 return &dev->stats; 1885} 1886 1887static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr) 1888{ 1889 struct tc35815_local *lp = netdev_priv(dev); 1890 struct tc35815_regs __iomem *tr = 1891 (struct tc35815_regs __iomem *)dev->base_addr; 1892 int cam_index = index * 6; 1893 u32 cam_data; 1894 u32 saved_addr; 1895 1896 saved_addr = tc_readl(&tr->CAM_Adr); 1897 1898 if (netif_msg_hw(lp)) 1899 printk(KERN_DEBUG "%s: CAM %d: %pM\n", 1900 dev->name, index, addr); 1901 if (index & 1) { 1902 /* read modify write */ 1903 tc_writel(cam_index - 2, &tr->CAM_Adr); 1904 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000; 1905 cam_data |= addr[0] << 8 | addr[1]; 1906 tc_writel(cam_data, &tr->CAM_Data); 1907 /* write whole word */ 1908 tc_writel(cam_index + 2, &tr->CAM_Adr); 1909 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; 1910 tc_writel(cam_data, &tr->CAM_Data); 1911 } else { 1912 /* write whole word */ 1913 tc_writel(cam_index, &tr->CAM_Adr); 1914 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 1915 tc_writel(cam_data, &tr->CAM_Data); 1916 /* read modify write */ 1917 tc_writel(cam_index + 4, &tr->CAM_Adr); 1918 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff; 1919 cam_data |= addr[4] << 24 | (addr[5] << 16); 1920 tc_writel(cam_data, &tr->CAM_Data); 1921 } 1922 1923 tc_writel(saved_addr, &tr->CAM_Adr); 1924} 1925 1926 1927/* 1928 * Set or clear the multicast filter for this adaptor. 1929 * num_addrs == -1 Promiscuous mode, receive all packets 1930 * num_addrs == 0 Normal mode, clear multicast list 1931 * num_addrs > 0 Multicast mode, receive normal and MC packets, 1932 * and do best-effort filtering. 1933 */ 1934static void 1935tc35815_set_multicast_list(struct net_device *dev) 1936{ 1937 struct tc35815_regs __iomem *tr = 1938 (struct tc35815_regs __iomem *)dev->base_addr; 1939 1940 if (dev->flags & IFF_PROMISC) { 1941 /* With some (all?) 100MHalf HUB, controller will hang 1942 * if we enabled promiscuous mode before linkup... */ 1943 struct tc35815_local *lp = netdev_priv(dev); 1944 1945 if (!lp->link) 1946 return; 1947 /* Enable promiscuous mode */ 1948 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl); 1949 } else if ((dev->flags & IFF_ALLMULTI) || 1950 netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) { 1951 /* CAM 0, 1, 20 are reserved. */ 1952 /* Disable promiscuous mode, use normal mode. */ 1953 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl); 1954 } else if (!netdev_mc_empty(dev)) { 1955 struct netdev_hw_addr *ha; 1956 int i; 1957 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE); 1958 1959 tc_writel(0, &tr->CAM_Ctl); 1960 /* Walk the address list, and load the filter */ 1961 i = 0; 1962 netdev_for_each_mc_addr(ha, dev) { 1963 /* entry 0,1 is reserved. */ 1964 tc35815_set_cam_entry(dev, i + 2, ha->addr); 1965 ena_bits |= CAM_Ena_Bit(i + 2); 1966 i++; 1967 } 1968 tc_writel(ena_bits, &tr->CAM_Ena); 1969 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 1970 } else { 1971 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); 1972 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 1973 } 1974} 1975 1976static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1977{ 1978 struct tc35815_local *lp = netdev_priv(dev); 1979 strcpy(info->driver, MODNAME); 1980 strcpy(info->version, DRV_VERSION); 1981 strcpy(info->bus_info, pci_name(lp->pci_dev)); 1982} 1983 1984static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1985{ 1986 struct tc35815_local *lp = netdev_priv(dev); 1987 1988 if (!lp->phy_dev) 1989 return -ENODEV; 1990 return phy_ethtool_gset(lp->phy_dev, cmd); 1991} 1992 1993static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1994{ 1995 struct tc35815_local *lp = netdev_priv(dev); 1996 1997 if (!lp->phy_dev) 1998 return -ENODEV; 1999 return phy_ethtool_sset(lp->phy_dev, cmd); 2000} 2001 2002static u32 tc35815_get_msglevel(struct net_device *dev) 2003{ 2004 struct tc35815_local *lp = netdev_priv(dev); 2005 return lp->msg_enable; 2006} 2007 2008static void tc35815_set_msglevel(struct net_device *dev, u32 datum) 2009{ 2010 struct tc35815_local *lp = netdev_priv(dev); 2011 lp->msg_enable = datum; 2012} 2013 2014static int tc35815_get_sset_count(struct net_device *dev, int sset) 2015{ 2016 struct tc35815_local *lp = netdev_priv(dev); 2017 2018 switch (sset) { 2019 case ETH_SS_STATS: 2020 return sizeof(lp->lstats) / sizeof(int); 2021 default: 2022 return -EOPNOTSUPP; 2023 } 2024} 2025 2026static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2027{ 2028 struct tc35815_local *lp = netdev_priv(dev); 2029 data[0] = lp->lstats.max_tx_qlen; 2030 data[1] = lp->lstats.tx_ints; 2031 data[2] = lp->lstats.rx_ints; 2032 data[3] = lp->lstats.tx_underrun; 2033} 2034 2035static struct { 2036 const char str[ETH_GSTRING_LEN]; 2037} ethtool_stats_keys[] = { 2038 { "max_tx_qlen" }, 2039 { "tx_ints" }, 2040 { "rx_ints" }, 2041 { "tx_underrun" }, 2042}; 2043 2044static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2045{ 2046 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2047} 2048 2049static const struct ethtool_ops tc35815_ethtool_ops = { 2050 .get_drvinfo = tc35815_get_drvinfo, 2051 .get_settings = tc35815_get_settings, 2052 .set_settings = tc35815_set_settings, 2053 .get_link = ethtool_op_get_link, 2054 .get_msglevel = tc35815_get_msglevel, 2055 .set_msglevel = tc35815_set_msglevel, 2056 .get_strings = tc35815_get_strings, 2057 .get_sset_count = tc35815_get_sset_count, 2058 .get_ethtool_stats = tc35815_get_ethtool_stats, 2059}; 2060 2061static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2062{ 2063 struct tc35815_local *lp = netdev_priv(dev); 2064 2065 if (!netif_running(dev)) 2066 return -EINVAL; 2067 if (!lp->phy_dev) 2068 return -ENODEV; 2069 return phy_mii_ioctl(lp->phy_dev, rq, cmd); 2070} 2071 2072static void tc35815_chip_reset(struct net_device *dev) 2073{ 2074 struct tc35815_regs __iomem *tr = 2075 (struct tc35815_regs __iomem *)dev->base_addr; 2076 int i; 2077 /* reset the controller */ 2078 tc_writel(MAC_Reset, &tr->MAC_Ctl); 2079 udelay(4); /* 3200ns */ 2080 i = 0; 2081 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) { 2082 if (i++ > 100) { 2083 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name); 2084 break; 2085 } 2086 mdelay(1); 2087 } 2088 tc_writel(0, &tr->MAC_Ctl); 2089 2090 /* initialize registers to default value */ 2091 tc_writel(0, &tr->DMA_Ctl); 2092 tc_writel(0, &tr->TxThrsh); 2093 tc_writel(0, &tr->TxPollCtr); 2094 tc_writel(0, &tr->RxFragSize); 2095 tc_writel(0, &tr->Int_En); 2096 tc_writel(0, &tr->FDA_Bas); 2097 tc_writel(0, &tr->FDA_Lim); 2098 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */ 2099 tc_writel(0, &tr->CAM_Ctl); 2100 tc_writel(0, &tr->Tx_Ctl); 2101 tc_writel(0, &tr->Rx_Ctl); 2102 tc_writel(0, &tr->CAM_Ena); 2103 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */ 2104 2105 /* initialize internal SRAM */ 2106 tc_writel(DMA_TestMode, &tr->DMA_Ctl); 2107 for (i = 0; i < 0x1000; i += 4) { 2108 tc_writel(i, &tr->CAM_Adr); 2109 tc_writel(0, &tr->CAM_Data); 2110 } 2111 tc_writel(0, &tr->DMA_Ctl); 2112} 2113 2114static void tc35815_chip_init(struct net_device *dev) 2115{ 2116 struct tc35815_local *lp = netdev_priv(dev); 2117 struct tc35815_regs __iomem *tr = 2118 (struct tc35815_regs __iomem *)dev->base_addr; 2119 unsigned long txctl = TX_CTL_CMD; 2120 2121 /* load station address to CAM */ 2122 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr); 2123 2124 /* Enable CAM (broadcast and unicast) */ 2125 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); 2126 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 2127 2128 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */ 2129 if (HAVE_DMA_RXALIGN(lp)) 2130 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl); 2131 else 2132 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl); 2133 tc_writel(0, &tr->TxPollCtr); /* Batch mode */ 2134 tc_writel(TX_THRESHOLD, &tr->TxThrsh); 2135 tc_writel(INT_EN_CMD, &tr->Int_En); 2136 2137 /* set queues */ 2138 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas); 2139 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base, 2140 &tr->FDA_Lim); 2141 /* 2142 * Activation method: 2143 * First, enable the MAC Transmitter and the DMA Receive circuits. 2144 * Then enable the DMA Transmitter and the MAC Receive circuits. 2145 */ 2146 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */ 2147 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */ 2148 2149 /* start MAC transmitter */ 2150 /* TX4939 does not have EnLCarr */ 2151 if (lp->chiptype == TC35815_TX4939) 2152 txctl &= ~Tx_EnLCarr; 2153 /* WORKAROUND: ignore LostCrS in full duplex operation */ 2154 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL) 2155 txctl &= ~Tx_EnLCarr; 2156 tc_writel(txctl, &tr->Tx_Ctl); 2157} 2158 2159#ifdef CONFIG_PM 2160static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state) 2161{ 2162 struct net_device *dev = pci_get_drvdata(pdev); 2163 struct tc35815_local *lp = netdev_priv(dev); 2164 unsigned long flags; 2165 2166 pci_save_state(pdev); 2167 if (!netif_running(dev)) 2168 return 0; 2169 netif_device_detach(dev); 2170 if (lp->phy_dev) 2171 phy_stop(lp->phy_dev); 2172 spin_lock_irqsave(&lp->lock, flags); 2173 tc35815_chip_reset(dev); 2174 spin_unlock_irqrestore(&lp->lock, flags); 2175 pci_set_power_state(pdev, PCI_D3hot); 2176 return 0; 2177} 2178 2179static int tc35815_resume(struct pci_dev *pdev) 2180{ 2181 struct net_device *dev = pci_get_drvdata(pdev); 2182 struct tc35815_local *lp = netdev_priv(dev); 2183 2184 pci_restore_state(pdev); 2185 if (!netif_running(dev)) 2186 return 0; 2187 pci_set_power_state(pdev, PCI_D0); 2188 tc35815_restart(dev); 2189 netif_carrier_off(dev); 2190 if (lp->phy_dev) 2191 phy_start(lp->phy_dev); 2192 netif_device_attach(dev); 2193 return 0; 2194} 2195#endif /* CONFIG_PM */ 2196 2197static struct pci_driver tc35815_pci_driver = { 2198 .name = MODNAME, 2199 .id_table = tc35815_pci_tbl, 2200 .probe = tc35815_init_one, 2201 .remove = __devexit_p(tc35815_remove_one), 2202#ifdef CONFIG_PM 2203 .suspend = tc35815_suspend, 2204 .resume = tc35815_resume, 2205#endif 2206}; 2207 2208module_param_named(speed, options.speed, int, 0); 2209MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps"); 2210module_param_named(duplex, options.duplex, int, 0); 2211MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full"); 2212 2213static int __init tc35815_init_module(void) 2214{ 2215 return pci_register_driver(&tc35815_pci_driver); 2216} 2217 2218static void __exit tc35815_cleanup_module(void) 2219{ 2220 pci_unregister_driver(&tc35815_pci_driver); 2221} 2222 2223module_init(tc35815_init_module); 2224module_exit(tc35815_cleanup_module); 2225 2226MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver"); 2227MODULE_LICENSE("GPL"); 2228