11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/****************************************************************************** 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (C)Copyright 1998,1999 SysKonnect, 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * a business unit of Schneider & Koch & Co. Datensysteme GmbH. 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License as published by 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the Free Software Foundation; either version 2 of the License, or 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (at your option) any later version. 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The information in this file is provided "AS IS" without warranty. 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ******************************************************************************/ 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef _SKFBI_H_ 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define _SKFBI_H_ 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 19af096046f63a065b692018cd4b8f5e7525c3e56aJeff Garzik * FDDI-Fx (x := {I(SA), P(CI)}) 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address calculation & function defines 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*--------------------------------------------------------------------------*/ 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef PCI 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (DV) = only defined for Da Vinci 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (ML) = only defined for Monalisa 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Configuration Space header 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */ 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_COMMAND 0x04 /* 16 bit Command */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_STATUS 0x06 /* 16 bit Status */ 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_REV_ID 0x08 /* 8 bit Revision ID */ 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */ 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */ 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_HEADER_T 0x0e /* 8 bit Header Type */ 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BIST 0x0f /* 8 bit Built-in selftest */ 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Byte 18..2b: Reserved */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */ 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */ 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */ 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Byte 34..33: Reserved */ 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_CAP_PTR 0x34 /* 8 bit (ML) Capabilities Ptr */ 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Byte 35..3b: Reserved */ 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */ 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */ 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */ 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */ 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Device Dependent Region */ 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_OUR_REG 0x40 /* 32 bit (DV) Our Register */ 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_OUR_REG_1 0x40 /* 32 bit (ML) Our Register 1 */ 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_OUR_REG_2 0x44 /* 32 bit (ML) Our Register 2 */ 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Power Management Region */ 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_CAP_ID 0x48 /* 8 bit (ML) Power Management Cap. ID */ 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_NITEM 0x49 /* 8 bit (ML) Next Item Ptr */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_CAP_REG 0x4a /* 16 bit (ML) Power Management Capabilities */ 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_CTL_STS 0x4c /* 16 bit (ML) Power Manag. Control/Status */ 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Byte 0x4e: Reserved */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_DAT_REG 0x4f /* 8 bit (ML) Power Manag. Data Register */ 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* VPD Region */ 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VPD_CAP_ID 0x50 /* 8 bit (ML) VPD Cap. ID */ 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VPD_NITEM 0x51 /* 8 bit (ML) Next Item Ptr */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VPD_ADR_REG 0x52 /* 16 bit (ML) VPD Address Register */ 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VPD_DAT_REG 0x54 /* 32 bit (ML) VPD Data Register */ 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Byte 58..ff: Reserved */ 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * I2C Address (PCI Config) 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: The temperature and voltage sensors are relocated on a different 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * I2C bus. 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */ 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Define Bits and Values of the registers 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_VENDOR_ID 16 bit Vendor ID */ 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_DEVICE_ID 16 bit Device ID */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Values for Vendor ID and Device ID shall be patched into the code */ 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_COMMAND 16 bit Command */ 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_FBTEN 0x0200 /* Bit 9: Fast Back-To-Back enable */ 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_SERREN 0x0100 /* Bit 8: SERR enable */ 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_ADSTEP 0x0080 /* Bit 7: Address Stepping */ 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PERREN 0x0040 /* Bit 6: Parity Report Response enable */ 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VGA_SNOOP 0x0020 /* Bit 5: VGA palette snoop */ 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MWIEN 0x0010 /* Bit 4: Memory write an inv cycl ena */ 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_SCYCEN 0x0008 /* Bit 3: Special Cycle enable */ 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BMEN 0x0004 /* Bit 2: Bus Master enable */ 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEMEN 0x0002 /* Bit 1: Memory Space Access enable */ 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_IOEN 0x0001 /* Bit 0: IO Space Access enable */ 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_STATUS 16 bit Status */ 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PERR 0x8000 /* Bit 15: Parity Error */ 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_SERR 0x4000 /* Bit 14: Signaled SERR */ 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_RMABORT 0x2000 /* Bit 13: Received Master Abort */ 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_RTABORT 0x1000 /* Bit 12: Received Target Abort */ 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_STABORT 0x0800 /* Bit 11: Sent Target Abort */ 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DEVSEL 0x0600 /* Bit 10..9: DEVSEL Timing */ 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DEV_FAST (0<<9) /* fast */ 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DEV_MEDIUM (1<<9) /* medium */ 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DEV_SLOW (2<<9) /* slow */ 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DATAPERR 0x0100 /* Bit 8: DATA Parity error detected */ 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_FB2BCAP 0x0080 /* Bit 7: Fast Back-to-Back Capability */ 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_UDF 0x0040 /* Bit 6: User Defined Features */ 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_66MHZCAP 0x0020 /* Bit 5: 66 MHz PCI bus clock capable */ 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_NEWCAP 0x0010 /* Bit 4: New cap. list implemented */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_ERRBITS (PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR) 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_REV_ID 8 bit Revision ID */ 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_CLASS_CODE 24 bit Class Code */ 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Byte 2: Base Class (02) */ 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Byte 1: SubClass (02) */ 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Byte 0: Programming Interface (00) */ 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_CACHE_LSZ 8 bit Cache Line Size */ 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Possible values: 0,2,4,8,16 */ 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_LAT_TIM 8 bit Latency Timer */ 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_HEADER_T 8 bit Header Type */ 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_HD_MF_DEV 0x80 /* Bit 7: 0= single, 1= multi-func dev */ 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */ 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_BIST 8 bit Built-in selftest */ 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BIST_CAP 0x80 /* Bit 7: BIST Capable */ 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BIST_ST 0x40 /* Bit 6: Start BIST */ 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BIST_RET 0x0f /* Bit 3..0: Completion Code */ 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_BASE_1ST 32 bit 1st Base address */ 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEMSIZE 0x800L /* use 2 kB Memory Base */ 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11: Memory Base Address */ 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4: Memory Size Req. */ 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PREFEN 0x00000008L /* Bit 3: Prefetchable */ 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEM_TYP 0x00000006L /* Bit 2..1: Memory Type */ 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEM32BIT (0<<1) /* Base addr anywhere in 32 Bit range */ 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEM1M (1<<1) /* Base addr below 1 MegaByte */ 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEM64BIT (2<<1) /* Base addr anywhere in 64 Bit range */ 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_MEMSPACE 0x00000001L /* Bit 0: Memory Space Indic. */ 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_BASE_2ND 32 bit 2nd Base address */ 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_IOBASE 0xffffff00L /* Bit 31..8: I/O Base address */ 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_IOSIZE 0x000000fcL /* Bit 7..2: I/O Size Requirements */ 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_IOSPACE 0x00000001L /* Bit 0: I/O Space Indicator */ 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_SUB_VID 16 bit Subsystem Vendor ID */ 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_SUB_ID 16 bit Subsystem ID */ 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */ 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st) */ 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_ROMBASZ 0x0001c000L /* Bit 16..14: Treat as BASE or SIZE */ 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_ROMSIZE 0x00003800L /* Bit 13..11: ROM Size Requirements */ 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_ROMEN 0x00000001L /* Bit 0: Address Decode enable */ 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_CAP_PTR 8 bit New Capabilities Pointers */ 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_IRQ_LINE 8 bit Interrupt Line */ 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_IRQ_PIN 8 bit Interrupt Pin */ 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_MIN_GNT 8 bit Min_Gnt */ 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_MAX_LAT 8 bit Max_Lat */ 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Device Dependent Region */ 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_OUR_REG (DV) 32 bit Our Register */ 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_OUR_REG_1 (ML) 32 bit Our Register 1 */ 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 31..29: reserved */ 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PATCH_DIR (3L<<27) /*(DV) Bit 28..27: Ext Patchs direction */ 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PATCH_DIR_0 (1L<<27) /*(DV) Type of the pins EXT_PATCHS<1..0> */ 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PATCH_DIR_1 (1L<<28) /* 0 = input */ 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 1 = output */ 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EXT_PATCHS (3L<<25) /*(DV) Bit 26..25: Extended Patches */ 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EXT_PATCH_0 (1L<<25) /*(DV) */ 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EXT_PATCH_1 (1L<<26) /* CLK for MicroWire (ML) */ 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VIO (1L<<25) /*(ML) */ 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */ 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 1 = Don't boot with ROM */ 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0 = Boot with ROM */ 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */ 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */ 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 1 = Map Flash to Memory */ 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0 = Disable all addr. decoding */ 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */ 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PAGE_16 (0L<<20) /* 16 k pages */ 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PAGE_32K (1L<<20) /* 32 k pages */ 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PAGE_64K (2L<<20) /* 64 k pages */ 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PAGE_128K (3L<<20) /* 128 k pages */ 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 19: reserved (ML) and (DV) */ 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */ 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 15: reserved */ 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */ 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */ 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */ 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */ 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */ 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */ 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_BYTE_SWAP (1L<<8) /*(DV) Bit 8: Byte Swap in DATA */ 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_SKEW_DAS (0xfL<<4) /* Bit 7..4: Skew Ctrl, DAS Ext */ 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */ 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_OUR_REG_2 (ML) 32 bit Our Register 2 (Monalisa only) */ 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VPD_WR_TH (0xffL<<24) /* Bit 24..31 VPD Write Threshold */ 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DEV_SEL (0x7fL<<17) /* Bit 17..23 EEPROM Device Select */ 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 14..16 VPD ROM Size */ 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 12..13 reserved */ 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PATCH_DIR2 (0xfL<<8) /* Bit 8..11 Ext Patchs dir 2..5 */ 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PATCH_DIR_2 (1L<<8) /* Bit 8 CS for MicroWire */ 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PATCH_DIR_3 (1L<<9) 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PATCH_DIR_4 (1L<<10) 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PATCH_DIR_5 (1L<<11) 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EXT_PATCHS2 (0xfL<<4) /* Bit 4..7 Extended Patches */ 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EXT_PATCH_2 (1L<<4) /* Bit 4 CS for MicroWire */ 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EXT_PATCH_3 (1L<<5) 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EXT_PATCH_4 (1L<<6) 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EXT_PATCH_5 (1L<<7) 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3 Enable Dummy Read */ 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_REV_DESC (1L<<2) /* Bit 2 Reverse Desc. Bytes */ 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_USEADDR64 (1L<<1) /* Bit 1 Use 64 Bit Addresse */ 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_USEDATA64 (1L<<0) /* Bit 0 Use 64 Bit Data bus ext*/ 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Power Management Region */ 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_PM_CAP_ID 8 bit (ML) Power Management Cap. ID */ 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_PM_NITEM 8 bit (ML) Next Item Ptr */ 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_PM_CAP_REG 16 bit (ML) Power Management Capabilities*/ 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PME_SUP (0x1f<<11) /* Bit 11..15 PM Manag. Event Support*/ 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_D2_SUB (1<<10) /* Bit 10 D2 Support Bit */ 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_D1_SUB (1<<9) /* Bit 9 D1 Support Bit */ 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 6..8 reserved */ 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_DSI (1<<5) /* Bit 5 Device Specific Init.*/ 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_APS (1<<4) /* Bit 4 Auxialiary Power Src */ 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PME_CLOCK (1<<3) /* Bit 3 PM Event Clock */ 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_VER (7<<0) /* Bit 0..2 PM PCI Spec. version */ 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_PM_CTL_STS 16 bit (ML) Power Manag. Control/Status */ 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PME_STATUS (1<<15) /* Bit 15 PFA doesn't sup. PME#*/ 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_DAT_SCL (3<<13) /* Bit 13..14 dat reg Scaling factor */ 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 9..12 PM data selector field */ 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 7.. 2 reserved */ 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_STATE (3<<0) /* Bit 0.. 1 Power Management State */ 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */ 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */ 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_STATE_D2 (2<<0) /* D2: not supported */ 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PM_STATE_D3 (3<<0) /* D3: HOT, Power Down and Reset */ 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_PM_DAT_REG 8 bit (ML) Power Manag. Data Register */ 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* VPD Region */ 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_VPD_CAP_ID 8 bit (ML) VPD Cap. ID */ 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_VPD_NITEM 8 bit (ML) Next Item Ptr */ 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_VPD_ADR_REG 16 bit (ML) VPD Address Register */ 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VPD_FLAG (1<<15) /* Bit 15 starts VPD rd/wd cycle*/ 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI_VPD_DAT_REG 32 bit (ML) VPD Data Register */ 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Control Register File: 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 0 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_RAP 0x0000 /* 8 bit register address port */ 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x0001 - 0x0003: reserved */ 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_CTRL 0x0004 /* 8 bit control register */ 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_DAS 0x0005 /* 8 Bit control register (DAS) */ 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_LED 0x0006 /* 8 Bit LED register */ 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_TST_CTRL 0x0007 /* 8 bit test control register */ 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_ISRC 0x0008 /* 32 bit Interrupt source register */ 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_IMSK 0x000c /* 32 bit Interrupt mask register */ 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_CMDREG1 0x0010 /* write command reg 1 instruction */ 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_CMDREG2 0x0014 /* write command reg 2 instruction */ 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */ 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */ 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */ 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */ 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_MARR 0x0020 /* r/w the memory read addr register */ 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_MARW 0x0024 /* r/w the memory write addr register*/ 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */ 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */ 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_MDREG3 0x0030 /* r/w Mode Register 3 */ 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */ 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */ 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */ 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */ 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_IVR 0x0044 /* read Interrupt Vector register */ 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_IMR 0x0048 /* r/w Interrupt mask register */ 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 0x4c Hidden */ 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_CNTRL_A 0x0050 /* control register A (r/w) */ 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_CNTRL_B 0x0054 /* control register B (r/w) */ 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_INTR_MASK 0x0058 /* interrupt mask (r/w) */ 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_XMIT_VECTOR 0x005c /* transmit vector register (r/w) */ 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_STATUS_A 0x0060 /* status register A (read only) */ 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_STATUS_B 0x0064 /* status register B (read only) */ 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_CNTRL_C 0x0068 /* control register C (r/w) */ 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_MDREG1 0x006c /* r/w Mode Register 1 */ 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */ 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/ 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */ 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */ 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 1 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - completely empty (this is the RAP Block window) 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: if RAP = 1 this page is reserved 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 2 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */ 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */ 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */ 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */ 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */ 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */ 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */ 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */ 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_CONN_TYP 0x0108 /* 8 bit Connector type */ 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_PMD_TYP 0x0109 /* 8 bit PMD type */ 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x010a - 0x010b: reserved */ 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Eprom registers are currently of no use */ 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */ 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */ 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */ 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */ 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */ 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */ 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x0115 - 0x0117: reserved */ 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_LD_CRTL 0x0118 /* 8 bit loader control */ 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_LD_TEST 0x0119 /* 8 bit loader test */ 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x011a - 0x011f: reserved */ 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_TI_INI 0x0120 /* 32 bit Timer init value */ 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_TI_VAL 0x0124 /* 32 bit Timer value */ 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_TI_CRTL 0x0128 /* 8 bit Timer control */ 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */ 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x012a - 0x012f: reserved */ 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */ 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */ 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */ 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */ 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x013a - 0x013f: reserved */ 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_RTM_INI 0x0140 /* 32 bit RTM init value */ 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_RTM_VAL 0x0144 /* 32 bit RTM value */ 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */ 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */ 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */ 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */ 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */ 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */ 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x0156: reserved */ 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */ 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */ 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */ 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */ 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */ 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */ 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */ 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x016a - 0x017f: reserved */ 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 3 3731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This is a copy of the Configuration register file (lower half) 3761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B3_CFG_SPC 0x180 3781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 4 3811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */ 3831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_DA 0x0210 /* 32 bit current rec desc address */ 3841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */ 3851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */ 3861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */ 3871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_F 0x0220 /* 32 bit flag register */ 3881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */ 3891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */ 3901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */ 3911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */ 3921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */ 3931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */ 3941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_T3 0x022c /* 32 bit Test Register 3 */ 3951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */ 3961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */ 3971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x0238 - 0x023f: reserved */ 3981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Receive queue 2 is removed on Monalisa */ 3991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */ 4001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */ 4011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */ 4021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */ 4031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */ 4041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_F 0x0260 /* 32 bit flag register (q2) */ 4051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */ 4061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */ 4071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */ 4081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */ 4091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */ 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */ 4111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */ 4121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x0270 - 0x027c: reserved */ 4131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 5 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */ 4181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */ 4191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */ 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */ 4211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */ 4221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */ 4231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */ 4241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */ 4251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */ 4261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */ 4271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */ 4281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */ 4291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */ 4301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */ 4311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */ 4321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x02b8 - 0x02bc: reserved */ 4331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */ 4341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */ 4351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */ 4361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */ 4371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */ 4381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */ 4391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */ 4401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */ 4411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */ 4421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */ 4431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */ 4441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */ 4451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */ 4461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */ 4471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */ 4481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x02f8 - 0x02fc: reserved */ 4491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 6 4521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* External PLC-S registers (SN2 compatibility for DV) */ 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* External registers (ML) */ 4551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define B6_EXT_REG 0x300 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 7 4591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* DAS PLC-S Registers */ 4611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bank 8 - 15 4641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* IFCP registers */ 4661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*---------------------------------------------------------------------------*/ 4681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Definitions of the Bits in the registers */ 4691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_RAP 16 bit register address port */ 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RAP_RAP 0x0f /* Bit 3..0: 0 = block0, .., f = block15 */ 4721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_CTRL 8 bit control register */ 4741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_FDDI_CLR (1<<7) /* Bit 7: (ML) Clear FDDI Reset */ 4751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_FDDI_SET (1<<6) /* Bit 6: (ML) Set FDDI Reset */ 4761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_HPI_CLR (1<<5) /* Bit 5: Clear HPI SM reset */ 4771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_HPI_SET (1<<4) /* Bit 4: Set HPI SM reset */ 4781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */ 4791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_MRST_SET (1<<2) /* Bit 2: Set Master reset */ 4801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_RST_CLR (1<<1) /* Bit 1: Clear Software reset */ 4811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_RST_SET (1<<0) /* Bit 0: Set Software reset */ 4821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_DAS 8 Bit control register (DAS) */ 4841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */ 4851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/ 4861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 5..4: reserved */ 4871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DAS_AVAIL (1<<3) /* Bit 3: 1 = DAS, 0 = SAS */ 4881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DAS_BYP_ST (1<<2) /* Bit 2: 1 = avail,SAS, 0 = not avail */ 4891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DAS_BYP_INS (1<<1) /* Bit 1: 1 = insert Bypass */ 4901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DAS_BYP_RMV (1<<0) /* Bit 0: 1 = remove Bypass */ 4911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_LED 8 Bit LED register */ 4931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 7..6: reserved */ 4941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_2_ON (1<<5) /* Bit 5: 1 = switch LED_2 on (left,gn)*/ 4951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_2_OFF (1<<4) /* Bit 4: 1 = switch LED_2 off */ 4961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_1_ON (1<<3) /* Bit 3: 1 = switch LED_1 on (mid,yel)*/ 4971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_1_OFF (1<<2) /* Bit 2: 1 = switch LED_1 off */ 4981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_0_ON (1<<1) /* Bit 1: 1 = switch LED_0 on (rght,gn)*/ 4991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_0_OFF (1<<0) /* Bit 0: 1 = switch LED_0 off */ 5001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* This hardware defines are very ugly therefore we define some others */ 5011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_GA_ON LED_2_ON /* S port = A port */ 5031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_GA_OFF LED_2_OFF /* S port = A port */ 5041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_MY_ON LED_1_ON 5051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_MY_OFF LED_1_OFF 5061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_GB_ON LED_0_ON 5071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_GB_OFF LED_0_OFF 5081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_TST_CTRL 8 bit test control register */ 5101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RE. */ 5111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR. */ 5121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RE. */ 5131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR. */ 5141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */ 5151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */ 5161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */ 5171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */ 5181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_ISRC 32 bit Interrupt source register */ 5201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 31..28: reserved */ 5211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ 5221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ 5231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ 5241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */ 5251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* PERR, RMABORT, RTABORT DATAPERR */ 5261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ 5271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* RMABORT, RTABORT, DATAPERR */ 5281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */ 5291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */ 5301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: The DAS is our First Port (!=PA) 5321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */ 5341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ 5351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ 5361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ 5371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ 5381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Receive Queue 1 */ 5391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ 5401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ 5411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ 5421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ 5431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Receive Queue 2 */ 5441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ 5451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ 5461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ 5471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ 5481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Asynchronous Transmit queue */ 5491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 7: reserved */ 5501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ 5521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ 5531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Synchronous Transmit queue */ 5541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 3: reserved */ 5551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ 5561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ 5571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Define all valid interrupt source Bits from GET_ISR () 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ALL_IRSR 0x01ffff77L /* (DV) */ 5631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ALL_IRSR_ML 0x0ffff077L /* (ML) */ 5641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_IMSK 32 bit Interrupt mask register */ 5671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The Bit definnition of this register are the same as of the interrupt 5691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * source register. These definition are directly derived from the Hardware 5701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * spec. 5711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 31..28: reserved */ 5731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ 5741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ 5751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ 5761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */ 5771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* PERR, RMABORT, RTABORT DATAPERR */ 5781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ 5791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* RMABORT, RTABORT, DATAPERR */ 5801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */ 5811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */ 5821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */ 5831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ 5841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ 5851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ 5861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ 5871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Receive Queue 1 */ 5881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ 5891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ 5901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ 5911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ 5921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Receive Queue 2 */ 5931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ 5941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ 5951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ 5961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ 5971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Asynchronous Transmit queue */ 5981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 7: reserved */ 5991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ 6001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ 6011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ 6021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Synchronous Transmit queue */ 6031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 3: reserved */ 6041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ 6051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ 6061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ 6071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ 6091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */ 6101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */ 6111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */ 6121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */ 6131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */ 6141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_MAC_0 8 bit MAC address Byte 0 */ 6161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_MAC_1 8 bit MAC address Byte 1 */ 6171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_MAC_2 8 bit MAC address Byte 2 */ 6181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_MAC_3 8 bit MAC address Byte 3 */ 6191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_MAC_4 8 bit MAC address Byte 4 */ 6201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_MAC_5 8 bit MAC address Byte 5 */ 6211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */ 6221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */ 6231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_CONN_TYP 8 bit Connector type */ 6251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_PMD_TYP 8 bit PMD type */ 6261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Values of connector and PMD type comply to SysKonnect internal std */ 6271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The EPROM register are currently of no use */ 6291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_E_0 8 bit EPROM Byte 0 */ 6301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_E_1 8 bit EPROM Byte 1 */ 6311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_E_2 8 bit EPROM Byte 2 */ 6321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_E_3 8 bit EPROM Byte 3 */ 6331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_FAR 32 bit Flash-Prom Address Register/Counter */ 6351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */ 6361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_FDP 8 bit Flash-Prom Data Port */ 6381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_LD_CRTL 8 bit loader control */ 6401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bits are currently reserved */ 6411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_LD_TEST 8 bit loader test */ 6431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */ 6441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */ 6451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */ 6461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LD_START (1<<0) /* Bit 0: Start loading FPROM */ 6471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_TI_INI 32 bit Timer init value */ 6491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_TI_VAL 32 bit Timer value */ 6501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_TI_CRTL 8 bit Timer control */ 6511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_TI_TEST 8 Bit Timer Test */ 6521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_WDOG_INI 32 bit Watchdog init value */ 6531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_WDOG_VAL 32 bit Watchdog value */ 6541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_WDOG_CRTL 8 bit Watchdog control */ 6551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_WDOG_TEST 8 Bit Watchdog Test */ 6561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_RTM_INI 32 bit RTM init value */ 6571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_RTM_VAL 32 bit RTM value */ 6581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_RTM_CRTL 8 bit RTM control */ 6591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_RTM_TEST 8 Bit RTM Test */ 6601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_<TIM>_CRTL 8 bit <TIM> control */ 6611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */ 6621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */ 6631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */ 6641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */ 6651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_TOK_CT (1<<4) /* Bit 4: Get the Token Counter (RTM) */ 6661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TIM_RES_TOK (1<<3) /* Bit 3: RTM Status: 1 == restricted */ 6671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TIM_ALARM (1<<3) /* Bit 3: Timer Alarm (WDOG) */ 6681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TIM_START (1<<2) /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/ 6691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TIM_STOP (1<<1) /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */ 6701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */ 6711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_<TIM>_TEST 8 Bit <TIM> Test */ 6721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */ 6731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */ 6741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */ 6751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */ 6771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */ 6781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */ 6791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 7..5: reserved */ 6801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_CL_I2C_IRQ (1<<4) /* Bit 4: Clear I2C IRQ */ 6811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_ST_SW_IRQ (1<<3) /* Bit 3: Set IRQ SW Request */ 6821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_CL_SW_IRQ (1<<2) /* Bit 2: Clear IRQ SW Request */ 6831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_STOP_DONE (1<<1) /* Bit 1: Stop Master is finished */ 6841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CTRL_STOP_MAST (1<<0) /* Bit 0: Command Bit to stop the master*/ 6851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */ 6871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 7..3: reserved */ 6881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IF_I2C_DATA_DIR (1<<2) /* Bit 2: direction of IF_I2C_DATA*/ 6891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IF_I2C_DATA (1<<1) /* Bit 1: I2C Data Port */ 6901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IF_I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */ 6911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 0x0156: reserved */ 6931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */ 6941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 7..4: reserved */ 6951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* force the following error on */ 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* the next master read/write */ 6971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */ 6981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */ 6991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */ 7001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */ 7011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */ 7031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */ 7041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be read/written*/ 7051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_DEV_SEL (0x7fL<<9) /* Bit 9..15: I2C Device Select */ 7061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 5.. 8: reserved */ 7071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */ 7081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */ 7091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/ 7101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ 7111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ 7121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ 7131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ 7141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */ 7151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */ 7161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */ 7171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_STOP_BIT (1<<0) /* Bit 0: Interrupt I2C transfer */ 7181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 7201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * I2C Addresses 7211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 7221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The temperature sensor and the voltage sensor are on the same I2C bus. 7231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1 7241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * in PCI_OUR_REG 1. 7251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 7261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define I2C_ADDR_TEMP 0x90 /* I2C Address Temperature Sensor */ 7271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */ 7291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_D 4*32 bit current receive Descriptor (q1) */ 7311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_DA 32 bit current rec desc address (q1) */ 7321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_AC 32 bit current receive Address Count (q1) */ 7331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_BC 32 bit current receive Byte Counter (q1) */ 7341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */ 7351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_F 32 bit flag register (q1) */ 7361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_T1 32 bit Test Register 1 (q1) */ 7371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_T2 32 bit Test Register 2 (q1) */ 7381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R1_T3 32 bit Test Register 3 (q1) */ 7391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_D 4*32 bit current receive Descriptor (q2) */ 7401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_DA 32 bit current rec desc address (q2) */ 7411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_AC 32 bit current receive Address Count (q2) */ 7421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_BC 32 bit current receive Byte Counter (q2) */ 7431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */ 7441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_F 32 bit flag register (q2) */ 7451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_T1 32 bit Test Register 1 (q2) */ 7461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_T2 32 bit Test Register 2 (q2) */ 7471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_R2_T3 32 bit Test Register 3 (q2) */ 7481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_D 4*32 bit current receive Descriptor (xa) */ 7491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_DA 32 bit current rec desc address (xa) */ 7501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_AC 32 bit current receive Address Count (xa) */ 7511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_BC 32 bit current receive Byte Counter (xa) */ 7521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */ 7531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_F 32 bit flag register (xa) */ 7541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_T1 32 bit Test Register 1 (xa) */ 7551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_T2 32 bit Test Register 2 (xa) */ 7561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XA_T3 32 bit Test Register 3 (xa) */ 7571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_D 4*32 bit current receive Descriptor (xs) */ 7581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_DA 32 bit current rec desc address (xs) */ 7591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_AC 32 bit current receive Address Count (xs) */ 7601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_BC 32 bit current receive Byte Counter (xs) */ 7611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */ 7621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_F 32 bit flag register (xs) */ 7631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_T1 32 bit Test Register 1 (xs) */ 7641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_T2 32 bit Test Register 2 (xs) */ 7651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_XS_T3 32 bit Test Register 3 (xs) */ 7661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */ 7671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */ 7681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */ 7691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */ 7701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */ 7711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */ 7721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */ 7731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */ 7741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */ 7751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */ 7761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */ 7771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */ 7781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */ 7791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */ 7801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */ 7811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 7..5: reserved */ 7821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */ 7831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */ 7841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */ 7851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */ 7861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */ 7871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\ 7891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST) 7901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CSR_CLR_RESET (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\ 7911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN) 7921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_<xx>_F 32 bit flag register (xx) */ 7951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 28..31: reserved */ 7961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */ 7971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */ 7981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */ 7991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/ 8001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 23: reserved */ 8011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/ 8021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 8..15: reserved */ 8031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */ 8041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FLAG_WATER 0x00001fL /* Bit 4..0:(DV) Level of req data tr.*/ 8051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_<xx>_T1 32 bit Test Register 1 (xx) */ 8071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Holds four State Machine control Bytes */ 8081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ 8091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ 8101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */ 8111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_CRTL_TR (0xffL<<0) /* Bit 7..0: Control Transfer SM */ 8121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */ 8141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */ 8151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */ 8161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */ 8171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The control status byte of each machine looks like ... */ 8181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */ 8191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_LOAD 0x08 /* Bit 3: Load the SM with SM_STATE */ 8201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */ 8211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */ 8221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_STEP 0x01 /* Bit 0: Step the State Machine */ 8231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The coding of the states */ 8251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */ 8261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */ 8271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */ 8281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */ 8291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */ 8301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */ 8311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */ 8321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_RD_IDLE 0x0 /* Read Desc. Idle Tr/Re */ 8341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_RD_LOAD 0x1 /* Read Desc. Load Tr/Re */ 8351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_RD_WAIT_TC 0x3 /* Read Desc. Wait_TC Tr/Re */ 8361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_RD_RST_EOF 0x6 /* Read Desc. Reset_EOF Re */ 8371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_RD_WDONE_R 0x2 /* Read Desc. Wait_Done Re */ 8381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_RD_WDONE_T 0x4 /* Read Desc. Wait_Done Tr */ 8391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_TR_IDLE 0x0 /* Trans. Data Idle Tr/Re */ 8411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_TR_LOAD 0x3 /* Trans. Data Load Tr/Re */ 8421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */ 8431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_TR_WAIT_TC 0x2 /* Trans. Data Wait_TC Tr/Re */ 8441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_TR_WDONE 0x4 /* Trans. Data Wait_Done Tr/Re */ 8451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_IDLE 0x0 /* Write Desc. Idle Tr/Re */ 8471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_ABLEN 0x1 /* Write Desc. Act_Buf_Length Tr/Re */ 8481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_LD_A4 0x2 /* Write Desc. Load_A4 Re */ 8491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_RES_OWN 0x2 /* Write Desc. Res_OWN Tr */ 8501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_WAIT_EOF 0x3 /* Write Desc. Wait_EOF Re */ 8511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_LD_N2C_R 0x4 /* Write Desc. Load_N2C Re */ 8521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_WAIT_TC_R 0x5 /* Write Desc. Wait_TC Re */ 8531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_WAIT_TC4 0x6 /* Write Desc. Wait_TC4 Re */ 8541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_LD_A_T 0x6 /* Write Desc. Load_A Tr */ 8551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_LD_A_R 0x7 /* Write Desc. Load_A Re */ 8561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_WAIT_TC_T 0x7 /* Write Desc. Wait_TC Tr */ 8571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_LD_N2C_T 0xc /* Write Desc. Load_N2C Tr */ 8581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_WDONE_T 0x9 /* Write Desc. Wait_Done Tr */ 8591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_WDONE_R 0xc /* Write Desc. Wait_Done Re */ 8601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */ 8611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */ 8621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_<xx>_T2 32 bit Test Register 2 (xx) */ 8641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Note: This register is only defined for the transmit queues */ 8651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 31..8: reserved */ 8661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define AC_TEST_ON (1<<7) /* Bit 7: Address Counter Test Mode on */ 8671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define AC_TEST_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/ 8681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BC_TEST_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */ 8691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BC_TEST_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */ 8701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TEST_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */ 8711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TEST_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */ 8721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TEST_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */ 8731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TEST_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */ 8741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* B5_<xx>_T3 32 bit Test Register 3 (xx) */ 8761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Note: This register is only defined for the transmit queues */ 8771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Bit 31..8: reserved */ 8781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define T3_MUX_2 (1<<7) /* Bit 7: (ML) Mux position MSB */ 8791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define T3_VRAM_2 (1<<6) /* Bit 6: (ML) Virtual RAM buffer addr MSB */ 8801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define T3_LOOP (1<<5) /* Bit 5: Set Loopback (Xmit) */ 8811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define T3_UNLOOP (1<<4) /* Bit 4: Unset Loopback (Xmit) */ 8821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define T3_MUX (3<<2) /* Bit 3..2: Mux position */ 8831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */ 8841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI card IDs */ 8861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 8871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: The following 4 byte definitions shall not be used! Use OEM Concept! 8881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 8891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VEND_ID0 0x48 /* PCI vendor ID (SysKonnect) */ 8901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_VEND_ID1 0x11 /* PCI vendor ID (SysKonnect) */ 8911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* (High byte) */ 8921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DEV_ID0 0x00 /* PCI device ID */ 8931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_DEV_ID1 0x40 /* PCI device ID (High byte) */ 8941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*#define PCI_CLASS 0x02*/ /* PCI class code: network device */ 8961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_NW_CLASS 0x02 /* PCI class code: network device */ 8971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_SUB_CLASS 0x02 /* PCI subclass ID: FDDI device */ 8981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_PROG_INTFC 0x00 /* PCI programming Interface (=0) */ 8991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address transmission from logical to physical offset address on board 9021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */ 9041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */ 9051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */ 9061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PRA(a) (B2_MAC_0 + (a)) /* configuration PROM (MAC address) */ 9071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * FlashProm specification 9101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_PAGES 0x20000L /* Every byte has a single page */ 9121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_FADDR 1 /* 1 byte per page */ 9131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Receive / Transmit Buffer Control word 9161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */ 9181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_STF (1L<<30) /* Start of Frame ? */ 9191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_EOF (1L<<29) /* End of Frame ? */ 9201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */ 9211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */ 9221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */ 9231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */ 9241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */ 9251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */ 9261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */ 9271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_CHECK 0x00550000L /* To identify the control word */ 9281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMU_BBC 0x0000FFFFL /* R/T Buffer Byte Count */ 9291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * physical address offset + IO-Port base address 9321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef MEM_MAPPED_IO 9341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ADDR(a) (char far *) smc->hw.iop+(a) 9351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a) 9361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 9371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \ 9381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ 9391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) 9401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \ 9411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ 9421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) 9431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 9441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Define a macro to access the configuration space 9471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */ 9491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */ 9511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Define some values needed for the MAC address (PROM) 9541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SA_MAC (0) /* start addr. MAC_AD within the PROM */ 9561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PRA_OFF (0) /* offset correction when 4th byte reading */ 9571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SKFDDI_PSZ 8 /* address PROM size */ 9591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */ 9611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */ 9621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */ 9631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */ 9641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Macro to read the PROM 9671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define READ_PROM(a) ((u_char)inp(a)) 9691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank) 9711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define VPP_ON() 9721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define VPP_OFF() 9731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: Values of the Interrupt Source Register are defined above 9761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ISR_A ADDR(B0_ISRC) 9781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_ISR() inpd(ISR_A) 9791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_ISR_SMP(iop) inpd((iop)+B0_ISRC) 9801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CHECK_ISR() (inpd(ISR_A) & inpd(ADDR(B0_IMSK))) 9811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CHECK_ISR_SMP(iop) (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK)) 9821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BUS_CHECK() 9841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 9861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * CLI_FBI: Disable Board Interrupts 9871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * STI_FBI: Enable Board Interrupts 9881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef UNIX 9901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLI_FBI() outpd(ADDR(B0_IMSK),0) 9911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 9921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0) 9931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 9941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef UNIX 9961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask) 9971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 9981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask) 9991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 10001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLI_FBI_SMP(iop) outpd((iop)+B0_IMSK,0) 10021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask) 10031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* PCI */ 10051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*--------------------------------------------------------------------------*/ 10061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 10081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 12 bit transfer (dword) counter: 10091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (ISA: 2*trc = number of byte) 10101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (EISA: 4*trc = number of byte) 10111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (MCA: 4*trc = number of byte) 10121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_TRANS (0x0fff) 10141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 10161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PC PIC 10171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MST_8259 (0x20) 10191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SLV_8259 (0xA0) 10201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TPS (18) /* ticks per second */ 10221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 10241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * error timer defs 10251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TN (4) /* number of supported timer = TN+1 */ 10271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SNPPND_TIME (5) /* buffer memory access over mem. data reg. */ 10281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_AD 0x405a0000 10301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MODR1 FM_A(FM_MDREG1) /* mode register 1 */ 10321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MODR2 FM_A(FM_MDREG2) /* mode register 2 */ 10331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CMDR1 FM_A(FM_CMDREG1) /* command register 1 */ 10351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CMDR2 FM_A(FM_CMDREG2) /* command register 2 */ 10361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 10391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * function defines 10401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask))) 10421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SET(io,mask) outpw((io),inpw(io)|(mask)) 10431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET(io,mask) (inpw(io)&(mask)) 10441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val)) 10451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 10471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PHY Port A (PA) = PLC 1 10481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * With SuperNet 3 PHY-A and PHY S are identical. 10491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg)) 10511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 10531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * set memory address register for write and read 10541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma)) 10561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma)) 10571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 10591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * read/write from/to memory data register 10601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* write double word */ 10621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\ 10631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds outpw(FM_A(FM_MDRL),(unsigned int)(dd)) 10641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef WINNT 10661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* read double word */ 10671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL))) 10681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* read FORMAC+ 32-bit status register */ 10701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L))) 10711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L))) 10721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef SUPERNET_3 10731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_ST3() (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L))) 10741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 10751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 10761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* read double word */ 10771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MDRR() inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL))) 10781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* read FORMAC+ 32-bit status register */ 10801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_ST1() inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L))) 10811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_ST2() inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L))) 10821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef SUPERNET_3 10831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GET_ST3() inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L))) 10841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 10851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 10861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Special timer macro for 82c54 */ 10881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* timer access over data bus bit 8..15 */ 10891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8) 10901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff) 10911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef DEBUG 10941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DB_MAC(mac,st) {if (debug_mac & 0x1)\ 10951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds printf("M") ;\ 10961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (debug_mac & 0x2)\ 10971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds printf("\tMAC %d status 0x%08lx\n",mac,st) ;\ 10981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (debug_mac & 0x4)\ 10991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dp_mac(mac,st) ;\ 11001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 11011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DB_PLC(p,iev) { if (debug_plc & 0x1)\ 11031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds printf("P") ;\ 11041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (debug_plc & 0x2)\ 11051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds printf("\tPLC %s Int 0x%04x\n", \ 11061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (p == PA) ? "A" : "B", iev) ;\ 11071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (debug_plc & 0x4)\ 11081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dp_plc(p,iev) ;\ 11091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 11101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DB_TIMER() { if (debug_timer & 0x1)\ 11121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds printf("T") ;\ 11131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (debug_timer & 0x2)\ 11141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds printf("\tTimer ISR\n") ;\ 11151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 11161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else /* no DEBUG */ 11181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DB_MAC(mac,st) 11201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DB_PLC(p,iev) 11211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DB_TIMER() 11221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* no DEBUG */ 11241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define INC_PTR(sp,cp,ep) if (++cp == ep) cp = sp 11261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 11271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * timer defs 11281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 11291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define COUNT(t) ((t)<<6) /* counter */ 11301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RW_OP(o) ((o)<<4) /* read/write operation */ 11311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TMODE(m) ((m)<<1) /* timer mode */ 11321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 1134