11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/********************************************************************* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Filename: ali-ircc.h 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Version: 0.5 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Description: Driver for the ALI M1535D and M1543C FIR Controller 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Status: Experimental. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Benjamin Kong <benjamin_kong@ali.com.tw> 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Created at: 2000/10/16 03:46PM 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Modified at: 2001/1/3 02:56PM 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Modified by: Benjamin Kong <benjamin_kong@ali.com.tw> 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (c) 2000 Benjamin Kong <benjamin_kong@ali.com.tw> 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * All Rights Reserved 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * modify it under the terms of the GNU General Public License as 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation; either version 2 of 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the License, or (at your option) any later version. 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ********************************************************************/ 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef ALI_IRCC_H 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ALI_IRCC_H 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/time.h> 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/spinlock.h> 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/pm.h> 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/types.h> 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/io.h> 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* SIR Register */ 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Usr definition of linux/serial_reg.h */ 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* FIR Register */ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK0 0x20 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK1 0x21 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK2 0x22 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK3 0x23 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_MCR 0x07 /* Master Control Register */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 0 */ 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_DR 0x00 /* Alias 0, FIR Data Register (R/W) */ 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_IER 0x01 /* Alias 1, FIR Interrupt Enable Register (R/W) */ 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_IIR 0x02 /* Alias 2, FIR Interrupt Identification Register (Read only) */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_LCR_A 0x03 /* Alias 3, FIR Line Control Register A (R/W) */ 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_LCR_B 0x04 /* Alias 4, FIR Line Control Register B (R/W) */ 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_LSR 0x05 /* Alias 5, FIR Line Status Register (R/W) */ 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_BSR 0x06 /* Alias 6, FIR Bus Status Register (Read only) */ 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 1 */ 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IER_FIFO 0x10 /* FIR FIFO Interrupt Enable */ 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IER_TIMER 0x20 /* Timer Interrupt Enable */ 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IER_EOM 0x40 /* End of Message Interrupt Enable */ 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IER_ACT 0x80 /* Active Frame Interrupt Enable */ 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 2 */ 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IIR_FIFO 0x10 /* FIR FIFO Interrupt */ 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IIR_TIMER 0x20 /* Timer Interrupt */ 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IIR_EOM 0x40 /* End of Message Interrupt */ 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IIR_ACT 0x80 /* Active Frame Interrupt */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 3 */ 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LCR_A_FIFO_RESET 0x80 /* FIFO Reset */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 4 */ 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LCR_B_BW 0x10 /* Brick Wall */ 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LCR_B_SIP 0x20 /* SIP Enable */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LCR_B_TX_MODE 0x40 /* Transmit Mode */ 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LCR_B_RX_MODE 0x80 /* Receive Mode */ 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 5 */ 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LSR_FIR_LSA 0x00 /* FIR Line Status Address */ 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LSR_FRAME_ABORT 0x08 /* Frame Abort */ 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LSR_CRC_ERROR 0x10 /* CRC Error */ 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LSR_SIZE_ERROR 0x20 /* Size Error */ 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LSR_FRAME_ERROR 0x40 /* Frame Error */ 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LSR_FIFO_UR 0x80 /* FIFO Underrun */ 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define LSR_FIFO_OR 0x80 /* FIFO Overrun */ 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 6 */ 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define BSR_FIFO_NOT_EMPTY 0x80 /* FIFO Not Empty */ 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 1 */ 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_CR 0x00 /* Alias 0, FIR Configuration Register (R/W) */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_FIFO_TR 0x01 /* Alias 1, FIR FIFO Threshold Register (R/W) */ 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_DMA_TR 0x02 /* Alias 2, FIR DMA Threshold Register (R/W) */ 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_TIMER_IIR 0x03 /* Alias 3, FIR Timer interrupt interval register (W/O) */ 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_FIFO_FR 0x03 /* Alias 3, FIR FIFO Flag register (R/O) */ 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_FIFO_RAR 0x04 /* Alias 4, FIR FIFO Read Address register (R/O) */ 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_FIFO_WAR 0x05 /* Alias 5, FIR FIFO Write Address register (R/O) */ 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_TR 0x06 /* Alias 6, Test REgister (W/O) */ 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 0 */ 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define CR_DMA_EN 0x01 /* DMA Enable */ 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define CR_DMA_BURST 0x02 /* DMA Burst Mode */ 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define CR_TIMER_EN 0x08 /* Timer Enable */ 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 3 */ 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define TIMER_IIR_500 0x00 /* 500 us */ 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define TIMER_IIR_1ms 0x01 /* 1 ms */ 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define TIMER_IIR_2ms 0x02 /* 2 ms */ 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define TIMER_IIR_4ms 0x03 /* 4 ms */ 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 2 */ 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_IRDA_CR 0x00 /* Alias 0, IrDA Control Register (R/W) */ 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_BOF_CR 0x01 /* Alias 1, BOF Count Register (R/W) */ 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_BW_CR 0x02 /* Alias 2, Brick Wall Count Register (R/W) */ 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_TX_DSR_HI 0x03 /* Alias 3, TX Data Size Register (high) (R/W) */ 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_TX_DSR_LO 0x04 /* Alias 4, TX Data Size Register (low) (R/W) */ 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_RX_DSR_HI 0x05 /* Alias 5, RX Data Size Register (high) (R/W) */ 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_RX_DSR_LO 0x06 /* Alias 6, RX Data Size Register (low) (R/W) */ 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Alias 0 */ 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IRDA_CR_HDLC1152 0x80 /* 1.152Mbps HDLC Select */ 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IRDA_CR_CRC 0X40 /* CRC Select. */ 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IRDA_CR_HDLC 0x20 /* HDLC select. */ 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IRDA_CR_HP_MODE 0x10 /* HP mode (read only) */ 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IRDA_CR_SD_ST 0x08 /* SD/MODE State. */ 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IRDA_CR_FIR_SIN 0x04 /* FIR SIN Select. */ 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IRDA_CR_ITTX_0 0x02 /* SOUT State. IRTX force to 0 */ 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds #define IRDA_CR_ITTX_1 0x03 /* SOUT State. IRTX force to 1 */ 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 3 */ 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_ID_VR 0x00 /* Alias 0, FIR ID Version Register (R/O) */ 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_MODULE_CR 0x01 /* Alias 1, FIR Module Control Register (R/W) */ 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_IO_BASE_HI 0x02 /* Alias 2, FIR Higher I/O Base Address Register (R/O) */ 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_IO_BASE_LO 0x03 /* Alias 3, FIR Lower I/O Base Address Register (R/O) */ 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_IRQ_CR 0x04 /* Alias 4, FIR IRQ Channel Register (R/O) */ 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FIR_DMA_CR 0x05 /* Alias 5, FIR DMA Channel Register (R/O) */ 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct ali_chip { 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds char *name; 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int cfg[2]; 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char entr1; 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char entr2; 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char cid_index; 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char cid_value; 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int (*probe)(struct ali_chip *chip, chipio_t *info); 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int (*init)(struct ali_chip *chip, chipio_t *info); 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldstypedef struct ali_chip ali_chip_t; 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* DMA modes needed */ 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */ 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */ 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_TX_WINDOW 7 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_RX_WINDOW 7 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TX_FIFO_Threshold 8 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_FIFO_Threshold 1 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TX_DMA_Threshold 1 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_DMA_Threshold 1 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* For storing entries in the status FIFO */ 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct st_fifo_entry { 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int status; 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int len; 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct st_fifo { 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct st_fifo_entry entries[MAX_RX_WINDOW]; 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int pending_bytes; 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int head; 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int tail; 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int len; 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct frame_cb { 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds void *start; /* Start of frame in DMA mem */ 176efad798b9f01300565f65058b153250cc49d58f2Paulius Zaleckas int len; /* Length of frame in DMA mem */ 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct tx_fifo { 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */ 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int ptr; /* Currently being sent */ 182efad798b9f01300565f65058b153250cc49d58f2Paulius Zaleckas int len; /* Length of queue */ 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int free; /* Next free slot */ 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds void *tail; /* Next free start in DMA mem */ 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Private data for each instance */ 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct ali_ircc_cb { 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct st_fifo st_fifo; /* Info about received frames */ 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct tx_fifo tx_fifo; /* Info about frames to be transmitted */ 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct net_device *netdev; /* Yes! we are some kind of netdevice */ 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct irlap_cb *irlap; /* The link layer we are binded to */ 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct qos_info qos; /* QoS capabilities for this device */ 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds chipio_t io; /* IrDA controller information */ 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iobuff_t tx_buff; /* Transmit buffer */ 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iobuff_t rx_buff; /* Receive buffer */ 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t tx_buff_dma; 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t rx_buff_dma; 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __u8 ier; /* Interrupt enable register */ 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __u8 InterruptID; /* Interrupt ID */ 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __u8 BusStatus; /* Bus Status */ 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __u8 LineStatus; /* Line Status */ 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char rcvFramesOverflow; 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct timeval stamp; 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct timeval now; 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds spinlock_t lock; /* For serializing operations */ 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __u32 new_speed; 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int index; /* Instance index */ 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char fifo_opti_buf; 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void switch_bank(int iobase, int bank) 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds outb(bank, iobase+FIR_MCR); 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* ALI_IRCC_H */ 229