pxaficp_ir.c revision c4bd01727380ce666aba987b3d7c0e838cb99bbe
1/* 2 * linux/drivers/net/irda/pxaficp_ir.c 3 * 4 * Based on sa1100_ir.c by Russell King 5 * 6 * Changes copyright (C) 2003-2005 MontaVista Software, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor 13 * 14 */ 15#include <linux/module.h> 16#include <linux/netdevice.h> 17#include <linux/etherdevice.h> 18#include <linux/platform_device.h> 19#include <linux/clk.h> 20#include <linux/gpio.h> 21 22#include <net/irda/irda.h> 23#include <net/irda/irmod.h> 24#include <net/irda/wrapper.h> 25#include <net/irda/irda_device.h> 26 27#include <mach/dma.h> 28#include <mach/irda.h> 29#include <mach/regs-uart.h> 30#include <mach/regs-ost.h> 31 32#define FICP __REG(0x40800000) /* Start of FICP area */ 33#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ 34#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ 35#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ 36#define ICDR __REG(0x4080000c) /* ICP Data Register */ 37#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ 38#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ 39 40#define ICCR0_AME (1 << 7) /* Address match enable */ 41#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ 42#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ 43#define ICCR0_RXE (1 << 4) /* Receive enable */ 44#define ICCR0_TXE (1 << 3) /* Transmit enable */ 45#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ 46#define ICCR0_LBM (1 << 1) /* Loopback mode */ 47#define ICCR0_ITR (1 << 0) /* IrDA transmission */ 48 49#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ 50#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ 51#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ 52#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ 53#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ 54#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ 55 56#ifdef CONFIG_PXA27x 57#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ 58#endif 59#define ICSR0_FRE (1 << 5) /* Framing error */ 60#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ 61#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ 62#define ICSR0_RAB (1 << 2) /* Receiver abort */ 63#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ 64#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ 65 66#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ 67#define ICSR1_CRE (1 << 5) /* CRC error */ 68#define ICSR1_EOF (1 << 4) /* End of frame */ 69#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ 70#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ 71#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ 72#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ 73 74#define IrSR_RXPL_NEG_IS_ZERO (1<<4) 75#define IrSR_RXPL_POS_IS_ZERO 0x0 76#define IrSR_TXPL_NEG_IS_ZERO (1<<3) 77#define IrSR_TXPL_POS_IS_ZERO 0x0 78#define IrSR_XMODE_PULSE_1_6 (1<<2) 79#define IrSR_XMODE_PULSE_3_16 0x0 80#define IrSR_RCVEIR_IR_MODE (1<<1) 81#define IrSR_RCVEIR_UART_MODE 0x0 82#define IrSR_XMITIR_IR_MODE (1<<0) 83#define IrSR_XMITIR_UART_MODE 0x0 84 85#define IrSR_IR_RECEIVE_ON (\ 86 IrSR_RXPL_NEG_IS_ZERO | \ 87 IrSR_TXPL_POS_IS_ZERO | \ 88 IrSR_XMODE_PULSE_3_16 | \ 89 IrSR_RCVEIR_IR_MODE | \ 90 IrSR_XMITIR_UART_MODE) 91 92#define IrSR_IR_TRANSMIT_ON (\ 93 IrSR_RXPL_NEG_IS_ZERO | \ 94 IrSR_TXPL_POS_IS_ZERO | \ 95 IrSR_XMODE_PULSE_3_16 | \ 96 IrSR_RCVEIR_UART_MODE | \ 97 IrSR_XMITIR_IR_MODE) 98 99struct pxa_irda { 100 int speed; 101 int newspeed; 102 unsigned long last_oscr; 103 104 unsigned char *dma_rx_buff; 105 unsigned char *dma_tx_buff; 106 dma_addr_t dma_rx_buff_phy; 107 dma_addr_t dma_tx_buff_phy; 108 unsigned int dma_tx_buff_len; 109 int txdma; 110 int rxdma; 111 112 struct irlap_cb *irlap; 113 struct qos_info qos; 114 115 iobuff_t tx_buff; 116 iobuff_t rx_buff; 117 118 struct device *dev; 119 struct pxaficp_platform_data *pdata; 120 struct clk *fir_clk; 121 struct clk *sir_clk; 122 struct clk *cur_clk; 123}; 124 125static inline void pxa_irda_disable_clk(struct pxa_irda *si) 126{ 127 if (si->cur_clk) 128 clk_disable(si->cur_clk); 129 si->cur_clk = NULL; 130} 131 132static inline void pxa_irda_enable_firclk(struct pxa_irda *si) 133{ 134 si->cur_clk = si->fir_clk; 135 clk_enable(si->fir_clk); 136} 137 138static inline void pxa_irda_enable_sirclk(struct pxa_irda *si) 139{ 140 si->cur_clk = si->sir_clk; 141 clk_enable(si->sir_clk); 142} 143 144 145#define IS_FIR(si) ((si)->speed >= 4000000) 146#define IRDA_FRAME_SIZE_LIMIT 2047 147 148inline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si) 149{ 150 DCSR(si->rxdma) = DCSR_NODESC; 151 DSADR(si->rxdma) = __PREG(ICDR); 152 DTADR(si->rxdma) = si->dma_rx_buff_phy; 153 DCMD(si->rxdma) = DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_WIDTH1 | DCMD_BURST32 | IRDA_FRAME_SIZE_LIMIT; 154 DCSR(si->rxdma) |= DCSR_RUN; 155} 156 157inline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si) 158{ 159 DCSR(si->txdma) = DCSR_NODESC; 160 DSADR(si->txdma) = si->dma_tx_buff_phy; 161 DTADR(si->txdma) = __PREG(ICDR); 162 DCMD(si->txdma) = DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_ENDIRQEN | DCMD_WIDTH1 | DCMD_BURST32 | si->dma_tx_buff_len; 163 DCSR(si->txdma) |= DCSR_RUN; 164} 165 166/* 167 * Set the IrDA communications mode. 168 */ 169static void pxa_irda_set_mode(struct pxa_irda *si, int mode) 170{ 171 if (si->pdata->transceiver_mode) 172 si->pdata->transceiver_mode(si->dev, mode); 173 else { 174 if (gpio_is_valid(si->pdata->gpio_pwdown)) 175 gpio_set_value(si->pdata->gpio_pwdown, 176 !(mode & IR_OFF) ^ 177 !si->pdata->gpio_pwdown_inverted); 178 pxa2xx_transceiver_mode(si->dev, mode); 179 } 180} 181 182/* 183 * Set the IrDA communications speed. 184 */ 185static int pxa_irda_set_speed(struct pxa_irda *si, int speed) 186{ 187 unsigned long flags; 188 unsigned int divisor; 189 190 switch (speed) { 191 case 9600: case 19200: case 38400: 192 case 57600: case 115200: 193 194 /* refer to PXA250/210 Developer's Manual 10-7 */ 195 /* BaudRate = 14.7456 MHz / (16*Divisor) */ 196 divisor = 14745600 / (16 * speed); 197 198 local_irq_save(flags); 199 200 if (IS_FIR(si)) { 201 /* stop RX DMA */ 202 DCSR(si->rxdma) &= ~DCSR_RUN; 203 /* disable FICP */ 204 ICCR0 = 0; 205 pxa_irda_disable_clk(si); 206 207 /* set board transceiver to SIR mode */ 208 pxa_irda_set_mode(si, IR_SIRMODE); 209 210 /* enable the STUART clock */ 211 pxa_irda_enable_sirclk(si); 212 } 213 214 /* disable STUART first */ 215 STIER = 0; 216 217 /* access DLL & DLH */ 218 STLCR |= LCR_DLAB; 219 STDLL = divisor & 0xff; 220 STDLH = divisor >> 8; 221 STLCR &= ~LCR_DLAB; 222 223 si->speed = speed; 224 STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6; 225 STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE; 226 227 local_irq_restore(flags); 228 break; 229 230 case 4000000: 231 local_irq_save(flags); 232 233 /* disable STUART */ 234 STIER = 0; 235 STISR = 0; 236 pxa_irda_disable_clk(si); 237 238 /* disable FICP first */ 239 ICCR0 = 0; 240 241 /* set board transceiver to FIR mode */ 242 pxa_irda_set_mode(si, IR_FIRMODE); 243 244 /* enable the FICP clock */ 245 pxa_irda_enable_firclk(si); 246 247 si->speed = speed; 248 pxa_irda_fir_dma_rx_start(si); 249 ICCR0 = ICCR0_ITR | ICCR0_RXE; 250 251 local_irq_restore(flags); 252 break; 253 254 default: 255 return -EINVAL; 256 } 257 258 return 0; 259} 260 261/* SIR interrupt service routine. */ 262static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id) 263{ 264 struct net_device *dev = dev_id; 265 struct pxa_irda *si = netdev_priv(dev); 266 int iir, lsr, data; 267 268 iir = STIIR; 269 270 switch (iir & 0x0F) { 271 case 0x06: /* Receiver Line Status */ 272 lsr = STLSR; 273 while (lsr & LSR_FIFOE) { 274 data = STRBR; 275 if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) { 276 printk(KERN_DEBUG "pxa_ir: sir receiving error\n"); 277 dev->stats.rx_errors++; 278 if (lsr & LSR_FE) 279 dev->stats.rx_frame_errors++; 280 if (lsr & LSR_OE) 281 dev->stats.rx_fifo_errors++; 282 } else { 283 dev->stats.rx_bytes++; 284 async_unwrap_char(dev, &dev->stats, 285 &si->rx_buff, data); 286 } 287 lsr = STLSR; 288 } 289 si->last_oscr = OSCR; 290 break; 291 292 case 0x04: /* Received Data Available */ 293 /* forth through */ 294 295 case 0x0C: /* Character Timeout Indication */ 296 do { 297 dev->stats.rx_bytes++; 298 async_unwrap_char(dev, &dev->stats, &si->rx_buff, STRBR); 299 } while (STLSR & LSR_DR); 300 si->last_oscr = OSCR; 301 break; 302 303 case 0x02: /* Transmit FIFO Data Request */ 304 while ((si->tx_buff.len) && (STLSR & LSR_TDRQ)) { 305 STTHR = *si->tx_buff.data++; 306 si->tx_buff.len -= 1; 307 } 308 309 if (si->tx_buff.len == 0) { 310 dev->stats.tx_packets++; 311 dev->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head; 312 313 /* We need to ensure that the transmitter has finished. */ 314 while ((STLSR & LSR_TEMT) == 0) 315 cpu_relax(); 316 si->last_oscr = OSCR; 317 318 /* 319 * Ok, we've finished transmitting. Now enable 320 * the receiver. Sometimes we get a receive IRQ 321 * immediately after a transmit... 322 */ 323 if (si->newspeed) { 324 pxa_irda_set_speed(si, si->newspeed); 325 si->newspeed = 0; 326 } else { 327 /* enable IR Receiver, disable IR Transmitter */ 328 STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6; 329 /* enable STUART and receive interrupts */ 330 STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE; 331 } 332 /* I'm hungry! */ 333 netif_wake_queue(dev); 334 } 335 break; 336 } 337 338 return IRQ_HANDLED; 339} 340 341/* FIR Receive DMA interrupt handler */ 342static void pxa_irda_fir_dma_rx_irq(int channel, void *data) 343{ 344 int dcsr = DCSR(channel); 345 346 DCSR(channel) = dcsr & ~DCSR_RUN; 347 348 printk(KERN_DEBUG "pxa_ir: fir rx dma bus error %#x\n", dcsr); 349} 350 351/* FIR Transmit DMA interrupt handler */ 352static void pxa_irda_fir_dma_tx_irq(int channel, void *data) 353{ 354 struct net_device *dev = data; 355 struct pxa_irda *si = netdev_priv(dev); 356 int dcsr; 357 358 dcsr = DCSR(channel); 359 DCSR(channel) = dcsr & ~DCSR_RUN; 360 361 if (dcsr & DCSR_ENDINTR) { 362 dev->stats.tx_packets++; 363 dev->stats.tx_bytes += si->dma_tx_buff_len; 364 } else { 365 dev->stats.tx_errors++; 366 } 367 368 while (ICSR1 & ICSR1_TBY) 369 cpu_relax(); 370 si->last_oscr = OSCR; 371 372 /* 373 * HACK: It looks like the TBY bit is dropped too soon. 374 * Without this delay things break. 375 */ 376 udelay(120); 377 378 if (si->newspeed) { 379 pxa_irda_set_speed(si, si->newspeed); 380 si->newspeed = 0; 381 } else { 382 int i = 64; 383 384 ICCR0 = 0; 385 pxa_irda_fir_dma_rx_start(si); 386 while ((ICSR1 & ICSR1_RNE) && i--) 387 (void)ICDR; 388 ICCR0 = ICCR0_ITR | ICCR0_RXE; 389 390 if (i < 0) 391 printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n"); 392 } 393 netif_wake_queue(dev); 394} 395 396/* EIF(Error in FIFO/End in Frame) handler for FIR */ 397static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev, int icsr0) 398{ 399 unsigned int len, stat, data; 400 401 /* Get the current data position. */ 402 len = DTADR(si->rxdma) - si->dma_rx_buff_phy; 403 404 do { 405 /* Read Status, and then Data. */ 406 stat = ICSR1; 407 rmb(); 408 data = ICDR; 409 410 if (stat & (ICSR1_CRE | ICSR1_ROR)) { 411 dev->stats.rx_errors++; 412 if (stat & ICSR1_CRE) { 413 printk(KERN_DEBUG "pxa_ir: fir receive CRC error\n"); 414 dev->stats.rx_crc_errors++; 415 } 416 if (stat & ICSR1_ROR) { 417 printk(KERN_DEBUG "pxa_ir: fir receive overrun\n"); 418 dev->stats.rx_over_errors++; 419 } 420 } else { 421 si->dma_rx_buff[len++] = data; 422 } 423 /* If we hit the end of frame, there's no point in continuing. */ 424 if (stat & ICSR1_EOF) 425 break; 426 } while (ICSR0 & ICSR0_EIF); 427 428 if (stat & ICSR1_EOF) { 429 /* end of frame. */ 430 struct sk_buff *skb; 431 432 if (icsr0 & ICSR0_FRE) { 433 printk(KERN_ERR "pxa_ir: dropping erroneous frame\n"); 434 dev->stats.rx_dropped++; 435 return; 436 } 437 438 skb = alloc_skb(len+1,GFP_ATOMIC); 439 if (!skb) { 440 printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n"); 441 dev->stats.rx_dropped++; 442 return; 443 } 444 445 /* Align IP header to 20 bytes */ 446 skb_reserve(skb, 1); 447 skb_copy_to_linear_data(skb, si->dma_rx_buff, len); 448 skb_put(skb, len); 449 450 /* Feed it to IrLAP */ 451 skb->dev = dev; 452 skb_reset_mac_header(skb); 453 skb->protocol = htons(ETH_P_IRDA); 454 netif_rx(skb); 455 456 dev->stats.rx_packets++; 457 dev->stats.rx_bytes += len; 458 } 459} 460 461/* FIR interrupt handler */ 462static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id) 463{ 464 struct net_device *dev = dev_id; 465 struct pxa_irda *si = netdev_priv(dev); 466 int icsr0, i = 64; 467 468 /* stop RX DMA */ 469 DCSR(si->rxdma) &= ~DCSR_RUN; 470 si->last_oscr = OSCR; 471 icsr0 = ICSR0; 472 473 if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) { 474 if (icsr0 & ICSR0_FRE) { 475 printk(KERN_DEBUG "pxa_ir: fir receive frame error\n"); 476 dev->stats.rx_frame_errors++; 477 } else { 478 printk(KERN_DEBUG "pxa_ir: fir receive abort\n"); 479 dev->stats.rx_errors++; 480 } 481 ICSR0 = icsr0 & (ICSR0_FRE | ICSR0_RAB); 482 } 483 484 if (icsr0 & ICSR0_EIF) { 485 /* An error in FIFO occured, or there is a end of frame */ 486 pxa_irda_fir_irq_eif(si, dev, icsr0); 487 } 488 489 ICCR0 = 0; 490 pxa_irda_fir_dma_rx_start(si); 491 while ((ICSR1 & ICSR1_RNE) && i--) 492 (void)ICDR; 493 ICCR0 = ICCR0_ITR | ICCR0_RXE; 494 495 if (i < 0) 496 printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n"); 497 498 return IRQ_HANDLED; 499} 500 501/* hard_xmit interface of irda device */ 502static int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) 503{ 504 struct pxa_irda *si = netdev_priv(dev); 505 int speed = irda_get_next_speed(skb); 506 507 /* 508 * Does this packet contain a request to change the interface 509 * speed? If so, remember it until we complete the transmission 510 * of this frame. 511 */ 512 if (speed != si->speed && speed != -1) 513 si->newspeed = speed; 514 515 /* 516 * If this is an empty frame, we can bypass a lot. 517 */ 518 if (skb->len == 0) { 519 if (si->newspeed) { 520 si->newspeed = 0; 521 pxa_irda_set_speed(si, speed); 522 } 523 dev_kfree_skb(skb); 524 return 0; 525 } 526 527 netif_stop_queue(dev); 528 529 if (!IS_FIR(si)) { 530 si->tx_buff.data = si->tx_buff.head; 531 si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, si->tx_buff.truesize); 532 533 /* Disable STUART interrupts and switch to transmit mode. */ 534 STIER = 0; 535 STISR = IrSR_IR_TRANSMIT_ON | IrSR_XMODE_PULSE_1_6; 536 537 /* enable STUART and transmit interrupts */ 538 STIER = IER_UUE | IER_TIE; 539 } else { 540 unsigned long mtt = irda_get_mtt(skb); 541 542 si->dma_tx_buff_len = skb->len; 543 skb_copy_from_linear_data(skb, si->dma_tx_buff, skb->len); 544 545 if (mtt) 546 while ((unsigned)(OSCR - si->last_oscr)/4 < mtt) 547 cpu_relax(); 548 549 /* stop RX DMA, disable FICP */ 550 DCSR(si->rxdma) &= ~DCSR_RUN; 551 ICCR0 = 0; 552 553 pxa_irda_fir_dma_tx_start(si); 554 ICCR0 = ICCR0_ITR | ICCR0_TXE; 555 } 556 557 dev_kfree_skb(skb); 558 dev->trans_start = jiffies; 559 return 0; 560} 561 562static int pxa_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) 563{ 564 struct if_irda_req *rq = (struct if_irda_req *)ifreq; 565 struct pxa_irda *si = netdev_priv(dev); 566 int ret; 567 568 switch (cmd) { 569 case SIOCSBANDWIDTH: 570 ret = -EPERM; 571 if (capable(CAP_NET_ADMIN)) { 572 /* 573 * We are unable to set the speed if the 574 * device is not running. 575 */ 576 if (netif_running(dev)) { 577 ret = pxa_irda_set_speed(si, 578 rq->ifr_baudrate); 579 } else { 580 printk(KERN_INFO "pxa_ir: SIOCSBANDWIDTH: !netif_running\n"); 581 ret = 0; 582 } 583 } 584 break; 585 586 case SIOCSMEDIABUSY: 587 ret = -EPERM; 588 if (capable(CAP_NET_ADMIN)) { 589 irda_device_set_media_busy(dev, TRUE); 590 ret = 0; 591 } 592 break; 593 594 case SIOCGRECEIVING: 595 ret = 0; 596 rq->ifr_receiving = IS_FIR(si) ? 0 597 : si->rx_buff.state != OUTSIDE_FRAME; 598 break; 599 600 default: 601 ret = -EOPNOTSUPP; 602 break; 603 } 604 605 return ret; 606} 607 608static void pxa_irda_startup(struct pxa_irda *si) 609{ 610 /* Disable STUART interrupts */ 611 STIER = 0; 612 /* enable STUART interrupt to the processor */ 613 STMCR = MCR_OUT2; 614 /* configure SIR frame format: StartBit - Data 7 ... Data 0 - Stop Bit */ 615 STLCR = LCR_WLS0 | LCR_WLS1; 616 /* enable FIFO, we use FIFO to improve performance */ 617 STFCR = FCR_TRFIFOE | FCR_ITL_32; 618 619 /* disable FICP */ 620 ICCR0 = 0; 621 /* configure FICP ICCR2 */ 622 ICCR2 = ICCR2_TXP | ICCR2_TRIG_32; 623 624 /* configure DMAC */ 625 DRCMR(17) = si->rxdma | DRCMR_MAPVLD; 626 DRCMR(18) = si->txdma | DRCMR_MAPVLD; 627 628 /* force SIR reinitialization */ 629 si->speed = 4000000; 630 pxa_irda_set_speed(si, 9600); 631 632 printk(KERN_DEBUG "pxa_ir: irda startup\n"); 633} 634 635static void pxa_irda_shutdown(struct pxa_irda *si) 636{ 637 unsigned long flags; 638 639 local_irq_save(flags); 640 641 /* disable STUART and interrupt */ 642 STIER = 0; 643 /* disable STUART SIR mode */ 644 STISR = 0; 645 646 /* disable DMA */ 647 DCSR(si->txdma) &= ~DCSR_RUN; 648 DCSR(si->rxdma) &= ~DCSR_RUN; 649 /* disable FICP */ 650 ICCR0 = 0; 651 652 /* disable the STUART or FICP clocks */ 653 pxa_irda_disable_clk(si); 654 655 DRCMR(17) = 0; 656 DRCMR(18) = 0; 657 658 local_irq_restore(flags); 659 660 /* power off board transceiver */ 661 pxa_irda_set_mode(si, IR_OFF); 662 663 printk(KERN_DEBUG "pxa_ir: irda shutdown\n"); 664} 665 666static int pxa_irda_start(struct net_device *dev) 667{ 668 struct pxa_irda *si = netdev_priv(dev); 669 int err; 670 671 si->speed = 9600; 672 673 err = request_irq(IRQ_STUART, pxa_irda_sir_irq, 0, dev->name, dev); 674 if (err) 675 goto err_irq1; 676 677 err = request_irq(IRQ_ICP, pxa_irda_fir_irq, 0, dev->name, dev); 678 if (err) 679 goto err_irq2; 680 681 /* 682 * The interrupt must remain disabled for now. 683 */ 684 disable_irq(IRQ_STUART); 685 disable_irq(IRQ_ICP); 686 687 err = -EBUSY; 688 si->rxdma = pxa_request_dma("FICP_RX",DMA_PRIO_LOW, pxa_irda_fir_dma_rx_irq, dev); 689 if (si->rxdma < 0) 690 goto err_rx_dma; 691 692 si->txdma = pxa_request_dma("FICP_TX",DMA_PRIO_LOW, pxa_irda_fir_dma_tx_irq, dev); 693 if (si->txdma < 0) 694 goto err_tx_dma; 695 696 err = -ENOMEM; 697 si->dma_rx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, 698 &si->dma_rx_buff_phy, GFP_KERNEL ); 699 if (!si->dma_rx_buff) 700 goto err_dma_rx_buff; 701 702 si->dma_tx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, 703 &si->dma_tx_buff_phy, GFP_KERNEL ); 704 if (!si->dma_tx_buff) 705 goto err_dma_tx_buff; 706 707 /* Setup the serial port for the initial speed. */ 708 pxa_irda_startup(si); 709 710 /* 711 * Open a new IrLAP layer instance. 712 */ 713 si->irlap = irlap_open(dev, &si->qos, "pxa"); 714 err = -ENOMEM; 715 if (!si->irlap) 716 goto err_irlap; 717 718 /* 719 * Now enable the interrupt and start the queue 720 */ 721 enable_irq(IRQ_STUART); 722 enable_irq(IRQ_ICP); 723 netif_start_queue(dev); 724 725 printk(KERN_DEBUG "pxa_ir: irda driver opened\n"); 726 727 return 0; 728 729err_irlap: 730 pxa_irda_shutdown(si); 731 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy); 732err_dma_tx_buff: 733 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy); 734err_dma_rx_buff: 735 pxa_free_dma(si->txdma); 736err_tx_dma: 737 pxa_free_dma(si->rxdma); 738err_rx_dma: 739 free_irq(IRQ_ICP, dev); 740err_irq2: 741 free_irq(IRQ_STUART, dev); 742err_irq1: 743 744 return err; 745} 746 747static int pxa_irda_stop(struct net_device *dev) 748{ 749 struct pxa_irda *si = netdev_priv(dev); 750 751 netif_stop_queue(dev); 752 753 pxa_irda_shutdown(si); 754 755 /* Stop IrLAP */ 756 if (si->irlap) { 757 irlap_close(si->irlap); 758 si->irlap = NULL; 759 } 760 761 free_irq(IRQ_STUART, dev); 762 free_irq(IRQ_ICP, dev); 763 764 pxa_free_dma(si->rxdma); 765 pxa_free_dma(si->txdma); 766 767 if (si->dma_rx_buff) 768 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy); 769 if (si->dma_tx_buff) 770 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy); 771 772 printk(KERN_DEBUG "pxa_ir: irda driver closed\n"); 773 return 0; 774} 775 776static int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state) 777{ 778 struct net_device *dev = platform_get_drvdata(_dev); 779 struct pxa_irda *si; 780 781 if (dev && netif_running(dev)) { 782 si = netdev_priv(dev); 783 netif_device_detach(dev); 784 pxa_irda_shutdown(si); 785 } 786 787 return 0; 788} 789 790static int pxa_irda_resume(struct platform_device *_dev) 791{ 792 struct net_device *dev = platform_get_drvdata(_dev); 793 struct pxa_irda *si; 794 795 if (dev && netif_running(dev)) { 796 si = netdev_priv(dev); 797 pxa_irda_startup(si); 798 netif_device_attach(dev); 799 netif_wake_queue(dev); 800 } 801 802 return 0; 803} 804 805 806static int pxa_irda_init_iobuf(iobuff_t *io, int size) 807{ 808 io->head = kmalloc(size, GFP_KERNEL | GFP_DMA); 809 if (io->head != NULL) { 810 io->truesize = size; 811 io->in_frame = FALSE; 812 io->state = OUTSIDE_FRAME; 813 io->data = io->head; 814 } 815 return io->head ? 0 : -ENOMEM; 816} 817 818static const struct net_device_ops pxa_irda_netdev_ops = { 819 .ndo_open = pxa_irda_start, 820 .ndo_stop = pxa_irda_stop, 821 .ndo_start_xmit = pxa_irda_hard_xmit, 822 .ndo_do_ioctl = pxa_irda_ioctl, 823}; 824 825static int pxa_irda_probe(struct platform_device *pdev) 826{ 827 struct net_device *dev; 828 struct pxa_irda *si; 829 unsigned int baudrate_mask; 830 int err; 831 832 if (!pdev->dev.platform_data) 833 return -ENODEV; 834 835 err = request_mem_region(__PREG(STUART), 0x24, "IrDA") ? 0 : -EBUSY; 836 if (err) 837 goto err_mem_1; 838 839 err = request_mem_region(__PREG(FICP), 0x1c, "IrDA") ? 0 : -EBUSY; 840 if (err) 841 goto err_mem_2; 842 843 dev = alloc_irdadev(sizeof(struct pxa_irda)); 844 if (!dev) 845 goto err_mem_3; 846 847 SET_NETDEV_DEV(dev, &pdev->dev); 848 si = netdev_priv(dev); 849 si->dev = &pdev->dev; 850 si->pdata = pdev->dev.platform_data; 851 852 si->sir_clk = clk_get(&pdev->dev, "UARTCLK"); 853 si->fir_clk = clk_get(&pdev->dev, "FICPCLK"); 854 if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) { 855 err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk); 856 goto err_mem_4; 857 } 858 859 /* 860 * Initialise the SIR buffers 861 */ 862 err = pxa_irda_init_iobuf(&si->rx_buff, 14384); 863 if (err) 864 goto err_mem_4; 865 err = pxa_irda_init_iobuf(&si->tx_buff, 4000); 866 if (err) 867 goto err_mem_5; 868 869 if (gpio_is_valid(si->pdata->gpio_pwdown)) { 870 err = gpio_request(si->pdata->gpio_pwdown, "IrDA switch"); 871 if (err) 872 goto err_startup; 873 err = gpio_direction_output(si->pdata->gpio_pwdown, 874 !si->pdata->gpio_pwdown_inverted); 875 if (err) { 876 gpio_free(si->pdata->gpio_pwdown); 877 goto err_startup; 878 } 879 } 880 881 if (si->pdata->startup) { 882 err = si->pdata->startup(si->dev); 883 if (err) 884 goto err_startup; 885 } 886 887 if (gpio_is_valid(si->pdata->gpio_pwdown) && si->pdata->startup) 888 dev_warn(si->dev, "gpio_pwdown and startup() both defined!\n"); 889 890 dev->netdev_ops = &pxa_irda_netdev_ops; 891 892 irda_init_max_qos_capabilies(&si->qos); 893 894 baudrate_mask = 0; 895 if (si->pdata->transceiver_cap & IR_SIRMODE) 896 baudrate_mask |= IR_9600|IR_19200|IR_38400|IR_57600|IR_115200; 897 if (si->pdata->transceiver_cap & IR_FIRMODE) 898 baudrate_mask |= IR_4000000 << 8; 899 900 si->qos.baud_rate.bits &= baudrate_mask; 901 si->qos.min_turn_time.bits = 7; /* 1ms or more */ 902 903 irda_qos_bits_to_value(&si->qos); 904 905 err = register_netdev(dev); 906 907 if (err == 0) 908 dev_set_drvdata(&pdev->dev, dev); 909 910 if (err) { 911 if (si->pdata->shutdown) 912 si->pdata->shutdown(si->dev); 913err_startup: 914 kfree(si->tx_buff.head); 915err_mem_5: 916 kfree(si->rx_buff.head); 917err_mem_4: 918 if (si->sir_clk && !IS_ERR(si->sir_clk)) 919 clk_put(si->sir_clk); 920 if (si->fir_clk && !IS_ERR(si->fir_clk)) 921 clk_put(si->fir_clk); 922 free_netdev(dev); 923err_mem_3: 924 release_mem_region(__PREG(FICP), 0x1c); 925err_mem_2: 926 release_mem_region(__PREG(STUART), 0x24); 927 } 928err_mem_1: 929 return err; 930} 931 932static int pxa_irda_remove(struct platform_device *_dev) 933{ 934 struct net_device *dev = platform_get_drvdata(_dev); 935 936 if (dev) { 937 struct pxa_irda *si = netdev_priv(dev); 938 unregister_netdev(dev); 939 if (gpio_is_valid(si->pdata->gpio_pwdown)) 940 gpio_free(si->pdata->gpio_pwdown); 941 if (si->pdata->shutdown) 942 si->pdata->shutdown(si->dev); 943 kfree(si->tx_buff.head); 944 kfree(si->rx_buff.head); 945 clk_put(si->fir_clk); 946 clk_put(si->sir_clk); 947 free_netdev(dev); 948 } 949 950 release_mem_region(__PREG(STUART), 0x24); 951 release_mem_region(__PREG(FICP), 0x1c); 952 953 return 0; 954} 955 956static struct platform_driver pxa_ir_driver = { 957 .driver = { 958 .name = "pxa2xx-ir", 959 .owner = THIS_MODULE, 960 }, 961 .probe = pxa_irda_probe, 962 .remove = pxa_irda_remove, 963 .suspend = pxa_irda_suspend, 964 .resume = pxa_irda_resume, 965}; 966 967static int __init pxa_irda_init(void) 968{ 969 return platform_driver_register(&pxa_ir_driver); 970} 971 972static void __exit pxa_irda_exit(void) 973{ 974 platform_driver_unregister(&pxa_ir_driver); 975} 976 977module_init(pxa_irda_init); 978module_exit(pxa_irda_exit); 979 980MODULE_LICENSE("GPL"); 981MODULE_ALIAS("platform:pxa2xx-ir"); 982