1 /*************************************************************************** 2 * 3 * Copyright (C) 2007-2008 SMSC 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 *****************************************************************************/ 20 21#ifndef _SMSC95XX_H 22#define _SMSC95XX_H 23 24/* Tx command words */ 25#define TX_CMD_A_DATA_OFFSET_ (0x001F0000) 26#define TX_CMD_A_FIRST_SEG_ (0x00002000) 27#define TX_CMD_A_LAST_SEG_ (0x00001000) 28#define TX_CMD_A_BUF_SIZE_ (0x000007FF) 29 30#define TX_CMD_B_CSUM_ENABLE (0x00004000) 31#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000) 32#define TX_CMD_B_DISABLE_PADDING_ (0x00001000) 33#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF) 34 35/* Rx status word */ 36#define RX_STS_FF_ (0x40000000) /* Filter Fail */ 37#define RX_STS_FL_ (0x3FFF0000) /* Frame Length */ 38#define RX_STS_ES_ (0x00008000) /* Error Summary */ 39#define RX_STS_BF_ (0x00002000) /* Broadcast Frame */ 40#define RX_STS_LE_ (0x00001000) /* Length Error */ 41#define RX_STS_RF_ (0x00000800) /* Runt Frame */ 42#define RX_STS_MF_ (0x00000400) /* Multicast Frame */ 43#define RX_STS_TL_ (0x00000080) /* Frame too long */ 44#define RX_STS_CS_ (0x00000040) /* Collision Seen */ 45#define RX_STS_FT_ (0x00000020) /* Frame Type */ 46#define RX_STS_RW_ (0x00000010) /* Receive Watchdog */ 47#define RX_STS_ME_ (0x00000008) /* Mii Error */ 48#define RX_STS_DB_ (0x00000004) /* Dribbling */ 49#define RX_STS_CRC_ (0x00000002) /* CRC Error */ 50 51/* SCSRs */ 52#define ID_REV (0x00) 53#define ID_REV_CHIP_ID_MASK_ (0xFFFF0000) 54#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 55#define ID_REV_CHIP_ID_9500_ (0x9500) 56 57#define INT_STS (0x08) 58#define INT_STS_TX_STOP_ (0x00020000) 59#define INT_STS_RX_STOP_ (0x00010000) 60#define INT_STS_PHY_INT_ (0x00008000) 61#define INT_STS_TXE_ (0x00004000) 62#define INT_STS_TDFU_ (0x00002000) 63#define INT_STS_TDFO_ (0x00001000) 64#define INT_STS_RXDF_ (0x00000800) 65#define INT_STS_GPIOS_ (0x000007FF) 66 67#define RX_CFG (0x0C) 68#define RX_FIFO_FLUSH_ (0x00000001) 69 70#define TX_CFG (0x10) 71#define TX_CFG_ON_ (0x00000004) 72#define TX_CFG_STOP_ (0x00000002) 73#define TX_CFG_FIFO_FLUSH_ (0x00000001) 74 75#define HW_CFG (0x14) 76#define HW_CFG_BIR_ (0x00001000) 77#define HW_CFG_LEDB_ (0x00000800) 78#define HW_CFG_RXDOFF_ (0x00000600) 79#define HW_CFG_DRP_ (0x00000040) 80#define HW_CFG_MEF_ (0x00000020) 81#define HW_CFG_LRST_ (0x00000008) 82#define HW_CFG_PSEL_ (0x00000004) 83#define HW_CFG_BCE_ (0x00000002) 84#define HW_CFG_SRST_ (0x00000001) 85 86#define PM_CTRL (0x20) 87#define PM_CTL_DEV_RDY_ (0x00000080) 88#define PM_CTL_SUS_MODE_ (0x00000060) 89#define PM_CTL_SUS_MODE_0 (0x00000000) 90#define PM_CTL_SUS_MODE_1 (0x00000020) 91#define PM_CTL_SUS_MODE_2 (0x00000060) 92#define PM_CTL_PHY_RST_ (0x00000010) 93#define PM_CTL_WOL_EN_ (0x00000008) 94#define PM_CTL_ED_EN_ (0x00000004) 95#define PM_CTL_WUPS_ (0x00000003) 96#define PM_CTL_WUPS_NO_ (0x00000000) 97#define PM_CTL_WUPS_ED_ (0x00000001) 98#define PM_CTL_WUPS_WOL_ (0x00000002) 99#define PM_CTL_WUPS_MULTI_ (0x00000003) 100 101#define LED_GPIO_CFG (0x24) 102#define LED_GPIO_CFG_SPD_LED (0x01000000) 103#define LED_GPIO_CFG_LNK_LED (0x00100000) 104#define LED_GPIO_CFG_FDX_LED (0x00010000) 105 106#define GPIO_CFG (0x28) 107 108#define AFC_CFG (0x2C) 109 110/* Hi watermark = 15.5Kb (~10 mtu pkts) */ 111/* low watermark = 3k (~2 mtu pkts) */ 112/* backpressure duration = ~ 350us */ 113/* Apply FC on any frame. */ 114#define AFC_CFG_DEFAULT (0x00F830A1) 115 116#define E2P_CMD (0x30) 117#define E2P_CMD_BUSY_ (0x80000000) 118#define E2P_CMD_MASK_ (0x70000000) 119#define E2P_CMD_READ_ (0x00000000) 120#define E2P_CMD_EWDS_ (0x10000000) 121#define E2P_CMD_EWEN_ (0x20000000) 122#define E2P_CMD_WRITE_ (0x30000000) 123#define E2P_CMD_WRAL_ (0x40000000) 124#define E2P_CMD_ERASE_ (0x50000000) 125#define E2P_CMD_ERAL_ (0x60000000) 126#define E2P_CMD_RELOAD_ (0x70000000) 127#define E2P_CMD_TIMEOUT_ (0x00000400) 128#define E2P_CMD_LOADED_ (0x00000200) 129#define E2P_CMD_ADDR_ (0x000001FF) 130 131#define MAX_EEPROM_SIZE (512) 132 133#define E2P_DATA (0x34) 134#define E2P_DATA_MASK_ (0x000000FF) 135 136#define BURST_CAP (0x38) 137 138#define GPIO_WAKE (0x64) 139 140#define INT_EP_CTL (0x68) 141#define INT_EP_CTL_INTEP_ (0x80000000) 142#define INT_EP_CTL_MACRTO_ (0x00080000) 143#define INT_EP_CTL_TX_STOP_ (0x00020000) 144#define INT_EP_CTL_RX_STOP_ (0x00010000) 145#define INT_EP_CTL_PHY_INT_ (0x00008000) 146#define INT_EP_CTL_TXE_ (0x00004000) 147#define INT_EP_CTL_TDFU_ (0x00002000) 148#define INT_EP_CTL_TDFO_ (0x00001000) 149#define INT_EP_CTL_RXDF_ (0x00000800) 150#define INT_EP_CTL_GPIOS_ (0x000007FF) 151 152#define BULK_IN_DLY (0x6C) 153 154/* MAC CSRs */ 155#define MAC_CR (0x100) 156#define MAC_CR_RXALL_ (0x80000000) 157#define MAC_CR_RCVOWN_ (0x00800000) 158#define MAC_CR_LOOPBK_ (0x00200000) 159#define MAC_CR_FDPX_ (0x00100000) 160#define MAC_CR_MCPAS_ (0x00080000) 161#define MAC_CR_PRMS_ (0x00040000) 162#define MAC_CR_INVFILT_ (0x00020000) 163#define MAC_CR_PASSBAD_ (0x00010000) 164#define MAC_CR_HFILT_ (0x00008000) 165#define MAC_CR_HPFILT_ (0x00002000) 166#define MAC_CR_LCOLL_ (0x00001000) 167#define MAC_CR_BCAST_ (0x00000800) 168#define MAC_CR_DISRTY_ (0x00000400) 169#define MAC_CR_PADSTR_ (0x00000100) 170#define MAC_CR_BOLMT_MASK (0x000000C0) 171#define MAC_CR_DFCHK_ (0x00000020) 172#define MAC_CR_TXEN_ (0x00000008) 173#define MAC_CR_RXEN_ (0x00000004) 174 175#define ADDRH (0x104) 176 177#define ADDRL (0x108) 178 179#define HASHH (0x10C) 180 181#define HASHL (0x110) 182 183#define MII_ADDR (0x114) 184#define MII_WRITE_ (0x02) 185#define MII_BUSY_ (0x01) 186#define MII_READ_ (0x00) /* ~of MII Write bit */ 187 188#define MII_DATA (0x118) 189 190#define FLOW (0x11C) 191#define FLOW_FCPT_ (0xFFFF0000) 192#define FLOW_FCPASS_ (0x00000004) 193#define FLOW_FCEN_ (0x00000002) 194#define FLOW_FCBSY_ (0x00000001) 195 196#define VLAN1 (0x120) 197 198#define VLAN2 (0x124) 199 200#define WUFF (0x128) 201 202#define WUCSR (0x12C) 203 204#define COE_CR (0x130) 205#define Tx_COE_EN_ (0x00010000) 206#define Rx_COE_MODE_ (0x00000002) 207#define Rx_COE_EN_ (0x00000001) 208 209/* Vendor-specific PHY Definitions */ 210 211/* Mode Control/Status Register */ 212#define PHY_MODE_CTRL_STS (17) 213#define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000) 214#define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002) 215 216#define SPECIAL_CTRL_STS (27) 217#define SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((u16)0x8000) 218#define SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((u16)0x4000) 219#define SPECIAL_CTRL_STS_AMDIX_STATE_ ((u16)0x2000) 220 221#define PHY_INT_SRC (29) 222#define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080) 223#define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040) 224#define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020) 225#define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010) 226 227#define PHY_INT_MASK (30) 228#define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080) 229#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 230#define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020) 231#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 232#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 233 PHY_INT_MASK_LINK_DOWN_) 234 235#define PHY_SPECIAL (31) 236#define PHY_SPECIAL_SPD_ ((u16)0x001C) 237#define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004) 238#define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014) 239#define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008) 240#define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018) 241 242/* USB Vendor Requests */ 243#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 244#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 245#define USB_VENDOR_REQUEST_GET_STATS 0xA2 246 247/* Interrupt Endpoint status word bitfields */ 248#define INT_ENP_TX_STOP_ ((u32)BIT(17)) 249#define INT_ENP_RX_STOP_ ((u32)BIT(16)) 250#define INT_ENP_PHY_INT_ ((u32)BIT(15)) 251#define INT_ENP_TXE_ ((u32)BIT(14)) 252#define INT_ENP_TDFU_ ((u32)BIT(13)) 253#define INT_ENP_TDFO_ ((u32)BIT(12)) 254#define INT_ENP_RXDF_ ((u32)BIT(11)) 255 256#endif /* _SMSC95XX_H */ 257