base.h revision c57ca81576e7ca0369ea52c9ac5f35d0f6ca1270
1/*- 2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 */ 37 38/* 39 * Defintions for the Atheros Wireless LAN controller driver. 40 */ 41#ifndef _DEV_ATH_ATHVAR_H 42#define _DEV_ATH_ATHVAR_H 43 44#include <linux/interrupt.h> 45#include <linux/list.h> 46#include <linux/wireless.h> 47#include <linux/if_ether.h> 48#include <linux/leds.h> 49 50#include "ath5k.h" 51#include "debug.h" 52 53#define ATH_RXBUF 40 /* number of RX buffers */ 54#define ATH_TXBUF 200 /* number of TX buffers */ 55#define ATH_BCBUF 1 /* number of beacon buffers */ 56 57struct ath5k_buf { 58 struct list_head list; 59 struct ath5k_desc *desc; /* virtual addr of desc */ 60 dma_addr_t daddr; /* physical addr of desc */ 61 struct sk_buff *skb; /* skbuff for buf */ 62 dma_addr_t skbaddr;/* physical addr of skb data */ 63}; 64 65/* 66 * Data transmit queue state. One of these exists for each 67 * hardware transmit queue. Packets sent to us from above 68 * are assigned to queues based on their priority. Not all 69 * devices support a complete set of hardware transmit queues. 70 * For those devices the array sc_ac2q will map multiple 71 * priorities to fewer hardware queues (typically all to one 72 * hardware queue). 73 */ 74struct ath5k_txq { 75 unsigned int qnum; /* hardware q number */ 76 u32 *link; /* link ptr in last TX desc */ 77 struct list_head q; /* transmit queue */ 78 spinlock_t lock; /* lock on q and link */ 79 bool setup; 80}; 81 82#define ATH5K_LED_MAX_NAME_LEN 31 83 84/* 85 * State for LED triggers 86 */ 87struct ath5k_led 88{ 89 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */ 90 struct ath5k_softc *sc; /* driver state */ 91 struct led_classdev led_dev; /* led classdev */ 92}; 93 94 95#if CHAN_DEBUG 96#define ATH_CHAN_MAX (26+26+26+200+200) 97#else 98#define ATH_CHAN_MAX (14+14+14+252+20) 99#endif 100 101/* Software Carrier, keeps track of the driver state 102 * associated with an instance of a device */ 103struct ath5k_softc { 104 struct pci_dev *pdev; /* for dma mapping */ 105 void __iomem *iobase; /* address of the device */ 106 struct mutex lock; /* dev-level lock */ 107 /* FIXME: how many does it really need? */ 108 struct ieee80211_tx_queue_stats tx_stats[16]; 109 struct ieee80211_low_level_stats ll_stats; 110 struct ieee80211_hw *hw; /* IEEE 802.11 common */ 111 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 112 struct ieee80211_channel channels[ATH_CHAN_MAX]; 113 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES]; 114 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES]; 115 enum nl80211_iftype opmode; 116 struct ath5k_hw *ah; /* Atheros HW */ 117 118 struct ieee80211_supported_band *curband; 119 120#ifdef CONFIG_ATH5K_DEBUG 121 struct ath5k_dbg_info debug; /* debug info */ 122#endif /* CONFIG_ATH5K_DEBUG */ 123 124 struct ath5k_buf *bufptr; /* allocated buffer ptr */ 125 struct ath5k_desc *desc; /* TX/RX descriptors */ 126 dma_addr_t desc_daddr; /* DMA (physical) address */ 127 size_t desc_len; /* size of TX/RX descriptors */ 128 u16 cachelsz; /* cache line size */ 129 130 DECLARE_BITMAP(status, 5); 131#define ATH_STAT_INVALID 0 /* disable hardware accesses */ 132#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */ 133#define ATH_STAT_PROMISC 2 134#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */ 135#define ATH_STAT_STARTED 4 /* opened & irqs enabled */ 136 137 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */ 138 unsigned int curmode; /* current phy mode */ 139 struct ieee80211_channel *curchan; /* current h/w channel */ 140 141 struct ieee80211_vif *vif; 142 143 enum ath5k_int imask; /* interrupt mask copy */ 144 145 DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ 146 147 u8 bssidmask[ETH_ALEN]; 148 149 unsigned int led_pin, /* GPIO pin for driving LED */ 150 led_on; /* pin setting for LED on */ 151 152 struct tasklet_struct restq; /* reset tasklet */ 153 154 unsigned int rxbufsize; /* rx size based on mtu */ 155 struct list_head rxbuf; /* receive buffer */ 156 spinlock_t rxbuflock; 157 u32 *rxlink; /* link ptr in last RX desc */ 158 struct tasklet_struct rxtq; /* rx intr tasklet */ 159 struct ath5k_led rx_led; /* rx led */ 160 161 struct list_head txbuf; /* transmit buffer */ 162 spinlock_t txbuflock; 163 unsigned int txbuf_len; /* buf count in txbuf list */ 164 struct ath5k_txq txqs[2]; /* beacon and tx */ 165 166 struct ath5k_txq *txq; /* beacon and tx*/ 167 struct tasklet_struct txtq; /* tx intr tasklet */ 168 struct ath5k_led tx_led; /* tx led */ 169 170 spinlock_t block; /* protects beacon */ 171 struct tasklet_struct beacontq; /* beacon intr tasklet */ 172 struct ath5k_buf *bbuf; /* beacon buffer */ 173 unsigned int bhalq, /* SW q for outgoing beacons */ 174 bmisscount, /* missed beacon transmits */ 175 bintval, /* beacon interval in TU */ 176 bsent; 177 unsigned int nexttbtt; /* next beacon time in TU */ 178 179 struct timer_list calib_tim; /* calibration timer */ 180 int power_level; /* Requested tx power in dbm */ 181 bool assoc; /* assocate state */ 182}; 183 184#define ath5k_hw_hasbssidmask(_ah) \ 185 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) 186#define ath5k_hw_hasveol(_ah) \ 187 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) 188 189#endif 190