desc.h revision da35111ad970081bdf6e848d1861c7d16e71079b
1/* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19/* 20 * Internal RX/TX descriptor structures 21 * (rX: reserved fields possibily used by future versions of the ar5k chipset) 22 */ 23 24/* 25 * common hardware RX control descriptor 26 */ 27struct ath5k_hw_rx_ctl { 28 u32 rx_control_0; /* RX control word 0 */ 29 u32 rx_control_1; /* RX control word 1 */ 30} __packed; 31 32/* RX control word 0 field/sflags */ 33#define AR5K_DESC_RX_CTL0 0x00000000 34 35/* RX control word 1 fields/flags */ 36#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff 37#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 38 39/* 40 * common hardware RX status descriptor 41 * 5210/11 and 5212 differ only in the flags defined below 42 */ 43struct ath5k_hw_rx_status { 44 u32 rx_status_0; /* RX status word 0 */ 45 u32 rx_status_1; /* RX status word 1 */ 46} __packed; 47 48/* 5210/5211 */ 49/* RX status word 0 fields/flags */ 50#define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff 51#define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 52#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 53#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15 54#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 55#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 56#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 57#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 58 59/* RX status word 1 fields/flags */ 60#define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 61#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 62#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004 63#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 64#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 65#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 66#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5 67#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 68#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 69#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9 70#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 71#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 72#define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 73 74/* 5212 */ 75/* RX status word 0 fields/flags */ 76#define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff 77#define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 78#define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 79#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 80#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15 81#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 82#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 83#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 84#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 85 86/* RX status word 1 fields/flags */ 87#define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 88#define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 89#define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004 90#define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 91#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010 92#define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020 93#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 94#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 95#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9 96#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 97#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 98#define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 99 100/* 101 * common hardware RX error descriptor 102 */ 103struct ath5k_hw_rx_error { 104 u32 rx_error_0; /* RX status word 0 */ 105 u32 rx_error_1; /* RX status word 1 */ 106} __packed; 107 108/* RX error word 0 fields/flags */ 109#define AR5K_RX_DESC_ERROR0 0x00000000 110 111/* RX error word 1 fields/flags */ 112#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 113#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 114 115/** 116 * enum ath5k_phy_error_code - PHY Error codes 117 */ 118enum ath5k_phy_error_code { 119 AR5K_RX_PHY_ERROR_UNDERRUN = 0, /* Transmit underrun */ 120 AR5K_RX_PHY_ERROR_TIMING = 1, /* Timing error */ 121 AR5K_RX_PHY_ERROR_PARITY = 2, /* Illegal parity */ 122 AR5K_RX_PHY_ERROR_RATE = 3, /* Illegal rate */ 123 AR5K_RX_PHY_ERROR_LENGTH = 4, /* Illegal length */ 124 AR5K_RX_PHY_ERROR_RADAR = 5, /* Radar detect */ 125 AR5K_RX_PHY_ERROR_SERVICE = 6, /* Illegal service */ 126 AR5K_RX_PHY_ERROR_TOR = 7, /* Transmit override receive */ 127 /* these are specific to the 5212 */ 128 AR5K_RX_PHY_ERROR_OFDM_TIMING = 17, 129 AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY = 18, 130 AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL = 19, 131 AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL = 20, 132 AR5K_RX_PHY_ERROR_OFDM_POWER_DROP = 21, 133 AR5K_RX_PHY_ERROR_OFDM_SERVICE = 22, 134 AR5K_RX_PHY_ERROR_OFDM_RESTART = 23, 135 AR5K_RX_PHY_ERROR_CCK_TIMING = 25, 136 AR5K_RX_PHY_ERROR_CCK_HEADER_CRC = 26, 137 AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL = 27, 138 AR5K_RX_PHY_ERROR_CCK_SERVICE = 30, 139 AR5K_RX_PHY_ERROR_CCK_RESTART = 31, 140}; 141 142/* 143 * 5210/5211 hardware 2-word TX control descriptor 144 */ 145struct ath5k_hw_2w_tx_ctl { 146 u32 tx_control_0; /* TX control word 0 */ 147 u32 tx_control_1; /* TX control word 1 */ 148} __packed; 149 150/* TX control word 0 fields/flags */ 151#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff 152#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ 153#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 154#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 155#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 156#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 157#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 158#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ 159#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ 160#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ 161#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 162#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 163#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 164 165#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT \ 166 (ah->ah_version == AR5K_AR5210 ? \ 167 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ 168 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) 169 170#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 171#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 172#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 173 174/* TX control word 1 fields/flags */ 175#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff 176#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 177#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 178#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 179 180#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX \ 181 (ah->ah_version == AR5K_AR5210 ? \ 182 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ 183 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) 184 185#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 186#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ 187#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 188#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ 189#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ 190 191/* Frame types */ 192#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 193#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 194#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 195#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c 196#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 197 198/* 199 * 5212 hardware 4-word TX control descriptor 200 */ 201struct ath5k_hw_4w_tx_ctl { 202 u32 tx_control_0; /* TX control word 0 */ 203 204#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff 205#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 206#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 207#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 208#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 209#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 210#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 211#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 212#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 213#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 214#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 215 216 u32 tx_control_1; /* TX control word 1 */ 217 218#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff 219#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 220#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 221#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 222#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 223#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 224#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 225#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 226#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 227#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 228#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 229#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 230#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 231 232 u32 tx_control_2; /* TX control word 2 */ 233 234#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff 235#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 236#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 237#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 238#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 239#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 240#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 241#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 242#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 243#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 244 245 u32 tx_control_3; /* TX control word 3 */ 246 247#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f 248#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 249#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 250#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 251#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 252#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 253#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 254#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 255#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 256} __packed; 257 258/* 259 * Common TX status descriptor 260 */ 261struct ath5k_hw_tx_status { 262 u32 tx_status_0; /* TX status word 0 */ 263 u32 tx_status_1; /* TX status word 1 */ 264} __packed; 265 266/* TX status word 0 fields/flags */ 267#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 268#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 269#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 270#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 271/*??? 272#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 273#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 274*/ 275#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 276#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 277/*??? 278#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 279#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 280*/ 281#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 282#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 283#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 284#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 285#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 286#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 287 288/* TX status word 1 fields/flags */ 289#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 290#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe 291#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 292#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 293#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 294#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 295#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 296#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 297#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 298 299/* 300 * 5210/5211 hardware TX descriptor 301 */ 302struct ath5k_hw_5210_tx_desc { 303 struct ath5k_hw_2w_tx_ctl tx_ctl; 304 struct ath5k_hw_tx_status tx_stat; 305} __packed; 306 307/* 308 * 5212 hardware TX descriptor 309 */ 310struct ath5k_hw_5212_tx_desc { 311 struct ath5k_hw_4w_tx_ctl tx_ctl; 312 struct ath5k_hw_tx_status tx_stat; 313} __packed; 314 315/* 316 * common hardware RX descriptor 317 */ 318struct ath5k_hw_all_rx_desc { 319 struct ath5k_hw_rx_ctl rx_ctl; 320 union { 321 struct ath5k_hw_rx_status rx_stat; 322 struct ath5k_hw_rx_error rx_err; 323 } u; 324} __packed; 325 326/* 327 * Atheros hardware descriptor 328 * This is read and written to by the hardware 329 */ 330struct ath5k_desc { 331 u32 ds_link; /* physical address of the next descriptor */ 332 u32 ds_data; /* physical address of data buffer (skb) */ 333 334 union { 335 struct ath5k_hw_5210_tx_desc ds_tx5210; 336 struct ath5k_hw_5212_tx_desc ds_tx5212; 337 struct ath5k_hw_all_rx_desc ds_rx; 338 } ud; 339} __packed; 340 341#define AR5K_RXDESC_INTREQ 0x0020 342 343#define AR5K_TXDESC_CLRDMASK 0x0001 344#define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ 345#define AR5K_TXDESC_RTSENA 0x0004 346#define AR5K_TXDESC_CTSENA 0x0008 347#define AR5K_TXDESC_INTREQ 0x0010 348#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ 349 350