1bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* 2bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Copyright (c) 2004-2010 Atheros Communications Inc. 31b2df4073447234034e2329f0df584c6346a8ec3Vasanthakumar Thiagarajan * Copyright (c) 2011 Qualcomm Atheros, Inc. 4bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 5bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 9bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 17bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 18bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#ifndef TARGET_H 19bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define TARGET_H 20bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 21bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_BOARD_DATA_SZ 1024 22bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_BOARD_EXT_DATA_SZ 768 23fb1ac2efa323de21bc83c1b3d326d06f8251ea4fPrasanna Kumar#define AR6003_BOARD_EXT_DATA_SZ_V2 1024 24bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 25d5720e59410578d00c1767d66b2b8dfeda91a08bKalle Valo#define AR6004_BOARD_DATA_SZ 6144 2631024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6004_BOARD_EXT_DATA_SZ 0 2731024d99003486c90c793dea58b55f7920f0488bKevin Fang 28bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RESET_CONTROL_ADDRESS 0x00000000 29bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RESET_CONTROL_COLD_RST 0x00000100 30bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RESET_CONTROL_MBOX_RST 0x00000004 31bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 32bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_CLOCK_STANDARD_S 0 33bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_CLOCK_STANDARD 0x00000003 34bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_CLOCK_ADDRESS 0x00000020 35bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 36bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CLOCK_CONTROL_ADDRESS 0x00000028 37bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CLOCK_CONTROL_LF_CLK32_S 2 38bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CLOCK_CONTROL_LF_CLK32 0x00000004 39bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 40bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define SYSTEM_SLEEP_ADDRESS 0x000000c4 41bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define SYSTEM_SLEEP_DISABLE_S 0 42bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define SYSTEM_SLEEP_DISABLE 0x00000001 43bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 44bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define LPO_CAL_ADDRESS 0x000000e0 45bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define LPO_CAL_ENABLE_S 20 46bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define LPO_CAL_ENABLE 0x00100000 47bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 48bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_PIN10_ADDRESS 0x00000050 49bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_PIN11_ADDRESS 0x00000054 50bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_PIN12_ADDRESS 0x00000058 51bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_PIN13_ADDRESS 0x0000005c 52bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 53bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_ADDRESS 0x00000400 54bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_ERROR_S 7 55bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_ERROR 0x00000080 56bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 57bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_CPU_S 6 58bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_CPU 0x00000040 59bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 60bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_COUNTER_S 4 61bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_COUNTER 0x00000010 62bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 63bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_INT_STATUS_ADDRESS 0x00000401 64bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 65bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_ADDRESS 0x00000402 66bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_WAKEUP_S 2 67bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_WAKEUP 0x00000004 68bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 69bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_RX_UNDERFLOW_S 1 70bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002 71bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 72bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_TX_OVERFLOW_S 0 73bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001 74bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 75bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_ADDRESS 0x00000403 76bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_COUNTER_S 0 77bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_COUNTER 0x000000ff 78bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 79bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 80bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 81bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_ADDRESS 0x00000418 82bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_ERROR_S 7 83bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_ERROR 0x00000080 84bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 85bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_CPU_S 6 86bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_CPU 0x00000040 87bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 88bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_INT_S 5 89bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_INT 0x00000020 90bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_COUNTER_S 4 91bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_COUNTER 0x00000010 92bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 93bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_MBOX_DATA_S 0 94bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f 95bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 96bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 97bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_INT_STATUS_ENABLE_BIT_S 0 98bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_INT_STATUS_ENABLE_BIT 0x000000ff 99bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 100bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a 101bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S 1 102bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002 103bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 104bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0 105bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001 106bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 107bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b 108bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_ENABLE_BIT_S 0 109bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff 110bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 111bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNT_ADDRESS 0x00000420 112bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 113bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNT_DEC_ADDRESS 0x00000440 114bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 115bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define WINDOW_DATA_ADDRESS 0x00000474 116bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 117bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define WINDOW_READ_ADDR_ADDRESS 0x0000047c 118bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_DBG_SEL_ADDRESS 0x00000483 119bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_DBG_ADDRESS 0x00000484 120bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 121bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define LOCAL_SCRATCH_ADDRESS 0x000000c0 122bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ATH6KL_OPTION_SLEEP_DISABLE 0x08 123bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 124bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RTC_BASE_ADDRESS 0x00004000 125bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_BASE_ADDRESS 0x00014000 126bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define MBOX_BASE_ADDRESS 0x00018000 127bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 128bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 129bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* real name of the register is unknown */ 130bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284) 131bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 132bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define SM(f, v) (((v) << f##_S) & f) 133bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define MS(f, v) (((v) & f) >> f##_S) 134bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 135bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* 136bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 137bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * host_interest structure. 138bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 139bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Host Interest is shared between Host and Target in order to coordinate 140bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * between the two, and is intended to remain constant (with additions only 141bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * at the end). 142bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 14331024d99003486c90c793dea58b55f7920f0488bKevin Fang#define ATH6KL_AR6003_HI_START_ADDR 0x00540600 14431024d99003486c90c793dea58b55f7920f0488bKevin Fang#define ATH6KL_AR6004_HI_START_ADDR 0x00400800 145bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 146bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* 147bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * These are items that the Host may need to access 148bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * via BMI or via the Diagnostic Window. The position 149bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * of items in this structure must remain constant. 150bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * across firmware revisions! 151bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 152bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Types for each item must be fixed size across target and host platforms. 153bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * The structure is used only to calculate offset for each register with 154bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * HI_ITEM() macro, no values are stored to it. 155bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 156bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * More items may be added at the end. 157bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 158bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valostruct host_interest { 159bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 160bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Pointer to application-defined area, if any. 161bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Set by Target application during startup. 162bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 163bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_app_host_interest; /* 0x00 */ 164bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 165bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Pointer to register dump area, valid after Target crash. */ 166bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_failure_state; /* 0x04 */ 167bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 168bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Pointer to debug logging header */ 169bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dbglog_hdr; /* 0x08 */ 170bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 171bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_unused1; /* 0x0c */ 172bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 173bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 174bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * General-purpose flag bits, similar to ATH6KL_OPTION_* flags. 175bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Can be used by application rather than by OS. 176bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 177bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_option_flag; /* 0x10 */ 178bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 179bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 180bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Boolean that determines whether or not to 181bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * display messages on the serial port. 182bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 183bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_serial_enable; /* 0x14 */ 184bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 185bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Start address of DataSet index, if any */ 186bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dset_list_head; /* 0x18 */ 187bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 188bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Override Target application start address */ 189bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_app_start; /* 0x1c */ 190bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 191bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Clock and voltage tuning */ 192bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_skip_clock_init; /* 0x20 */ 193bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_core_clock_setting; /* 0x24 */ 194bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_cpu_clock_setting; /* 0x28 */ 195bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_system_sleep_setting; /* 0x2c */ 196bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_xtal_control_setting; /* 0x30 */ 197bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 198bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 199bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_ref_voltage_trim_setting; /* 0x3c */ 200bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_clock_info; /* 0x40 */ 201bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 202bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 203bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Flash configuration overrides, used only 204bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * when firmware is not executing from flash. 205bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * (When using flash, modify the global variables 206bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * with equivalent names.) 207bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 208bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_bank0_addr_value; /* 0x44 */ 209bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_bank0_read_value; /* 0x48 */ 210bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_bank0_write_value; /* 0x4c */ 211bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_bank0_config_value; /* 0x50 */ 212bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 213bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Pointer to Board Data */ 214bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_board_data; /* 0x54 */ 215bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_board_data_initialized; /* 0x58 */ 216bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 217bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dset_ram_index_tbl; /* 0x5c */ 218bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 219bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_desired_baud_rate; /* 0x60 */ 220bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dbglog_config; /* 0x64 */ 221bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_end_ram_reserve_sz; /* 0x68 */ 222bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_mbox_io_block_sz; /* 0x6c */ 223bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 224bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_num_bpatch_streams; /* 0x70 -- unused */ 225bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_mbox_isr_yield_limit; /* 0x74 */ 226bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 227bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_refclk_hz; /* 0x78 */ 228bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_ext_clk_detected; /* 0x7c */ 229bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dbg_uart_txpin; /* 0x80 */ 230bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dbg_uart_rxpin; /* 0x84 */ 231bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_baud; /* 0x88 */ 232bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_pin_assignments; /* 0x8C */ 233bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 234bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts 235bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * pin 236bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 237bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_baud_scale_val; /* 0x90 */ 238bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_baud_step_val; /* 0x94 */ 239bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 240bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_allocram_start; /* 0x98 */ 241bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_allocram_sz; /* 0x9c */ 242bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_bridge_flags; /* 0xa0 */ 243bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_support_pins; /* 0xa4 */ 244bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 245bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * NOTE: byte [0] = RESET pin (bit 7 is polarity), 246bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * bytes[1]..bytes[3] are for future use 247bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 248bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 249bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 250bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 251bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * [31:16]: wakeup timeout in ms 252bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 253bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 254bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Pointer to extended board data */ 255bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_board_ext_data; /* 0xac */ 256bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_board_ext_data_config; /* 0xb0 */ 257bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 258bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 259bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Bit [0] : valid 260bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Bit[31:16: size 261bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 262bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 263bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * hi_reset_flag is used to do some stuff when target reset. 264bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * such as restore app_start after warm reset or 265bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * preserve host Interest area, or preserve ROM data, literals etc. 266bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 267bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_reset_flag; /* 0xb4 */ 268bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* indicate hi_reset_flag is valid */ 269bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_reset_flag_valid; /* 0xb8 */ 270bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ 271bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 272bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 0xbc - [31:0]: idle timeout in ms 273bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 274bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* ACS flags */ 275bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_acs_flags; /* 0xc0 */ 276bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_console_flags; /* 0xc4 */ 277bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_nvram_state; /* 0xc8 */ 278bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_option_flag2; /* 0xcc */ 279bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 280bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* If non-zero, override values sent to Host in WMI_READY event. */ 281bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_sw_version_override; /* 0xd0 */ 282bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_abi_version_override; /* 0xd4 */ 283bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 284bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 285bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Percentage of high priority RX traffic to total expected RX traffic - 286bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * applicable only to ar6004 287bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 288bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ 289bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 290bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* test applications flags */ 291bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_test_apps_related ; /* 0xdc */ 292bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* location of test script */ 293bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_ota_testscript; /* 0xe0 */ 294bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* location of CAL data */ 295bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_cal_data; /* 0xe4 */ 296bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Number of packet log buffers */ 297bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_pktlog_num_buffers; /* 0xe8 */ 298bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 299bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo} __packed; 300bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 301bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_ITEM(item) offsetof(struct host_interest, item) 302bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 303bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 304bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 305bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_MODE_IBSS 0x0 306bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_MODE_BSS_STA 0x1 307bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_MODE_AP 0x2 308bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 3096bbc7c35ed0fb61c7739e91d5ee7016455770511Jouni Malinen#define HI_OPTION_FW_SUBMODE_NONE 0x0 3106bbc7c35ed0fb61c7739e91d5ee7016455770511Jouni Malinen#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 3116bbc7c35ed0fb61c7739e91d5ee7016455770511Jouni Malinen#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 3126bbc7c35ed0fb61c7739e91d5ee7016455770511Jouni Malinen#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 3136bbc7c35ed0fb61c7739e91d5ee7016455770511Jouni Malinen 314bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_NUM_DEV_SHIFT 0x9 315bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 316bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_BRIDGE_SHIFT 0x04 317bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 318bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* Fw Mode/SubMode Mask 319bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo|------------------------------------------------------------------------------| 320bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo| SUB | SUB | SUB | SUB | | | | 321bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0| 322bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) 323bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo|------------------------------------------------------------------------------| 324bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo*/ 3257b85832dfbfaf09e793755041302d9e6d67cd39eVasanthakumar Thiagarajan#define HI_OPTION_FW_MODE_BITS 0x2 326bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_MODE_SHIFT 0xC 3277b85832dfbfaf09e793755041302d9e6d67cd39eVasanthakumar Thiagarajan 3287b85832dfbfaf09e793755041302d9e6d67cd39eVasanthakumar Thiagarajan#define HI_OPTION_FW_SUBMODE_BITS 0x2 3296bbc7c35ed0fb61c7739e91d5ee7016455770511Jouni Malinen#define HI_OPTION_FW_SUBMODE_SHIFT 0x14 330bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 331bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* Convert a Target virtual address into a Target physical address */ 33231024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) 33331024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6004_VTOP(vaddr) (vaddr) 33431024d99003486c90c793dea58b55f7920f0488bKevin Fang 33531024d99003486c90c793dea58b55f7920f0488bKevin Fang#define TARG_VTOP(target_type, vaddr) \ 33631024d99003486c90c793dea58b55f7920f0488bKevin Fang (((target_type) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ 33731024d99003486c90c793dea58b55f7920f0488bKevin Fang (((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0)) 338bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 339bdf5396be177b689c00ae6ebed00d13fafaed36eKalle Valo#define ATH6KL_FWLOG_PAYLOAD_SIZE 1500 340bdf5396be177b689c00ae6ebed00d13fafaed36eKalle Valo 341bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valostruct ath6kl_dbglog_buf { 342bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo __le32 next; 343bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo __le32 buffer_addr; 344bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo __le32 bufsize; 345bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo __le32 length; 346bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo __le32 count; 347bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo __le32 free; 348bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo} __packed; 349bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo 350bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valostruct ath6kl_dbglog_hdr { 351bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo __le32 dbuf_addr; 352bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo __le32 dropped; 353bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo} __packed; 354bc07ddb29a7b71ad009bcd84bee4c93908cf22b6Kalle Valo 355bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#endif 356