1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18
19static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
20{
21	if (fbin == AR5416_BCHAN_UNUSED)
22		return fbin;
23
24	return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
25}
26
27void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
28{
29        REG_WRITE(ah, reg, val);
30
31        if (ah->config.analog_shiftreg)
32		udelay(100);
33}
34
35void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
36			       u32 shift, u32 val)
37{
38	u32 regVal;
39
40	regVal = REG_READ(ah, reg) & ~mask;
41	regVal |= (val << shift) & mask;
42
43	REG_WRITE(ah, reg, regVal);
44
45	if (ah->config.analog_shiftreg)
46		udelay(100);
47}
48
49int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
50			     int16_t targetLeft, int16_t targetRight)
51{
52	int16_t rv;
53
54	if (srcRight == srcLeft) {
55		rv = targetLeft;
56	} else {
57		rv = (int16_t) (((target - srcLeft) * targetRight +
58				 (srcRight - target) * targetLeft) /
59				(srcRight - srcLeft));
60	}
61	return rv;
62}
63
64bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
65				    u16 *indexL, u16 *indexR)
66{
67	u16 i;
68
69	if (target <= pList[0]) {
70		*indexL = *indexR = 0;
71		return true;
72	}
73	if (target >= pList[listSize - 1]) {
74		*indexL = *indexR = (u16) (listSize - 1);
75		return true;
76	}
77
78	for (i = 0; i < listSize - 1; i++) {
79		if (pList[i] == target) {
80			*indexL = *indexR = i;
81			return true;
82		}
83		if (target < pList[i + 1]) {
84			*indexL = i;
85			*indexR = (u16) (i + 1);
86			return false;
87		}
88	}
89	return false;
90}
91
92void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
93				  int eep_start_loc, int size)
94{
95	int i = 0, j, addr;
96	u32 addrdata[8];
97	u32 data[8];
98
99	for (addr = 0; addr < size; addr++) {
100		addrdata[i] = AR5416_EEPROM_OFFSET +
101			((addr + eep_start_loc) << AR5416_EEPROM_S);
102		i++;
103		if (i == 8) {
104			REG_READ_MULTI(ah, addrdata, data, i);
105
106			for (j = 0; j < i; j++) {
107				*eep_data = data[j];
108				eep_data++;
109			}
110			i = 0;
111		}
112	}
113
114	if (i != 0) {
115		REG_READ_MULTI(ah, addrdata, data, i);
116
117		for (j = 0; j < i; j++) {
118			*eep_data = data[j];
119			eep_data++;
120		}
121	}
122}
123
124bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
125{
126	return common->bus_ops->eeprom_read(common, off, data);
127}
128
129void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
130			     u8 *pVpdList, u16 numIntercepts,
131			     u8 *pRetVpdList)
132{
133	u16 i, k;
134	u8 currPwr = pwrMin;
135	u16 idxL = 0, idxR = 0;
136
137	for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
138		ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
139					       numIntercepts, &(idxL),
140					       &(idxR));
141		if (idxR < 1)
142			idxR = 1;
143		if (idxL == numIntercepts - 1)
144			idxL = (u16) (numIntercepts - 2);
145		if (pPwrList[idxL] == pPwrList[idxR])
146			k = pVpdList[idxL];
147		else
148			k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
149				   (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
150				  (pPwrList[idxR] - pPwrList[idxL]));
151		pRetVpdList[i] = (u8) k;
152		currPwr += 2;
153	}
154}
155
156void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
157				       struct ath9k_channel *chan,
158				       struct cal_target_power_leg *powInfo,
159				       u16 numChannels,
160				       struct cal_target_power_leg *pNewPower,
161				       u16 numRates, bool isExtTarget)
162{
163	struct chan_centers centers;
164	u16 clo, chi;
165	int i;
166	int matchIndex = -1, lowIndex = -1;
167	u16 freq;
168
169	ath9k_hw_get_channel_centers(ah, chan, &centers);
170	freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
171
172	if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
173				       IS_CHAN_2GHZ(chan))) {
174		matchIndex = 0;
175	} else {
176		for (i = 0; (i < numChannels) &&
177			     (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
178			if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
179						       IS_CHAN_2GHZ(chan))) {
180				matchIndex = i;
181				break;
182			} else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
183						IS_CHAN_2GHZ(chan)) && i > 0 &&
184				   freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
185						IS_CHAN_2GHZ(chan))) {
186				lowIndex = i - 1;
187				break;
188			}
189		}
190		if ((matchIndex == -1) && (lowIndex == -1))
191			matchIndex = i - 1;
192	}
193
194	if (matchIndex != -1) {
195		*pNewPower = powInfo[matchIndex];
196	} else {
197		clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
198					 IS_CHAN_2GHZ(chan));
199		chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
200					 IS_CHAN_2GHZ(chan));
201
202		for (i = 0; i < numRates; i++) {
203			pNewPower->tPow2x[i] =
204				(u8)ath9k_hw_interpolate(freq, clo, chi,
205						powInfo[lowIndex].tPow2x[i],
206						powInfo[lowIndex + 1].tPow2x[i]);
207		}
208	}
209}
210
211void ath9k_hw_get_target_powers(struct ath_hw *ah,
212				struct ath9k_channel *chan,
213				struct cal_target_power_ht *powInfo,
214				u16 numChannels,
215				struct cal_target_power_ht *pNewPower,
216				u16 numRates, bool isHt40Target)
217{
218	struct chan_centers centers;
219	u16 clo, chi;
220	int i;
221	int matchIndex = -1, lowIndex = -1;
222	u16 freq;
223
224	ath9k_hw_get_channel_centers(ah, chan, &centers);
225	freq = isHt40Target ? centers.synth_center : centers.ctl_center;
226
227	if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
228		matchIndex = 0;
229	} else {
230		for (i = 0; (i < numChannels) &&
231			     (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
232			if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
233						       IS_CHAN_2GHZ(chan))) {
234				matchIndex = i;
235				break;
236			} else
237				if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
238						IS_CHAN_2GHZ(chan)) && i > 0 &&
239				    freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
240						IS_CHAN_2GHZ(chan))) {
241					lowIndex = i - 1;
242					break;
243				}
244		}
245		if ((matchIndex == -1) && (lowIndex == -1))
246			matchIndex = i - 1;
247	}
248
249	if (matchIndex != -1) {
250		*pNewPower = powInfo[matchIndex];
251	} else {
252		clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
253					 IS_CHAN_2GHZ(chan));
254		chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
255					 IS_CHAN_2GHZ(chan));
256
257		for (i = 0; i < numRates; i++) {
258			pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
259						clo, chi,
260						powInfo[lowIndex].tPow2x[i],
261						powInfo[lowIndex + 1].tPow2x[i]);
262		}
263	}
264}
265
266u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
267				bool is2GHz, int num_band_edges)
268{
269	u16 twiceMaxEdgePower = MAX_RATE_POWER;
270	int i;
271
272	for (i = 0; (i < num_band_edges) &&
273		     (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
274		if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
275			twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
276			break;
277		} else if ((i > 0) &&
278			   (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
279						      is2GHz))) {
280			if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
281					       is2GHz) < freq &&
282			    CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
283				twiceMaxEdgePower =
284					CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
285			}
286			break;
287		}
288	}
289
290	return twiceMaxEdgePower;
291}
292
293void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
294{
295	struct ath_common *common = ath9k_hw_common(ah);
296	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
297
298	switch (ar5416_get_ntxchains(ah->txchainmask)) {
299	case 1:
300		break;
301	case 2:
302		regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
303		break;
304	case 3:
305		regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
306		break;
307	default:
308		ath_dbg(common, EEPROM, "Invalid chainmask configuration\n");
309		break;
310	}
311}
312
313void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
314				struct ath9k_channel *chan,
315				void *pRawDataSet,
316				u8 *bChans, u16 availPiers,
317				u16 tPdGainOverlap,
318				u16 *pPdGainBoundaries, u8 *pPDADCValues,
319				u16 numXpdGains)
320{
321	int i, j, k;
322	int16_t ss;
323	u16 idxL = 0, idxR = 0, numPiers;
324	static u8 vpdTableL[AR5416_NUM_PD_GAINS]
325		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
326	static u8 vpdTableR[AR5416_NUM_PD_GAINS]
327		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
328	static u8 vpdTableI[AR5416_NUM_PD_GAINS]
329		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
330
331	u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
332	u8 minPwrT4[AR5416_NUM_PD_GAINS];
333	u8 maxPwrT4[AR5416_NUM_PD_GAINS];
334	int16_t vpdStep;
335	int16_t tmpVal;
336	u16 sizeCurrVpdTable, maxIndex, tgtIndex;
337	bool match;
338	int16_t minDelta = 0;
339	struct chan_centers centers;
340	int pdgain_boundary_default;
341	struct cal_data_per_freq *data_def = pRawDataSet;
342	struct cal_data_per_freq_4k *data_4k = pRawDataSet;
343	struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
344	bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
345	int intercepts;
346
347	if (AR_SREV_9287(ah))
348		intercepts = AR9287_PD_GAIN_ICEPTS;
349	else
350		intercepts = AR5416_PD_GAIN_ICEPTS;
351
352	memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
353	ath9k_hw_get_channel_centers(ah, chan, &centers);
354
355	for (numPiers = 0; numPiers < availPiers; numPiers++) {
356		if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
357			break;
358	}
359
360	match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
361							     IS_CHAN_2GHZ(chan)),
362					       bChans, numPiers, &idxL, &idxR);
363
364	if (match) {
365		if (AR_SREV_9287(ah)) {
366			/* FIXME: array overrun? */
367			for (i = 0; i < numXpdGains; i++) {
368				minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
369				maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
370				ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
371						data_9287[idxL].pwrPdg[i],
372						data_9287[idxL].vpdPdg[i],
373						intercepts,
374						vpdTableI[i]);
375			}
376		} else if (eeprom_4k) {
377			for (i = 0; i < numXpdGains; i++) {
378				minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
379				maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
380				ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
381						data_4k[idxL].pwrPdg[i],
382						data_4k[idxL].vpdPdg[i],
383						intercepts,
384						vpdTableI[i]);
385			}
386		} else {
387			for (i = 0; i < numXpdGains; i++) {
388				minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
389				maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
390				ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
391						data_def[idxL].pwrPdg[i],
392						data_def[idxL].vpdPdg[i],
393						intercepts,
394						vpdTableI[i]);
395			}
396		}
397	} else {
398		for (i = 0; i < numXpdGains; i++) {
399			if (AR_SREV_9287(ah)) {
400				pVpdL = data_9287[idxL].vpdPdg[i];
401				pPwrL = data_9287[idxL].pwrPdg[i];
402				pVpdR = data_9287[idxR].vpdPdg[i];
403				pPwrR = data_9287[idxR].pwrPdg[i];
404			} else if (eeprom_4k) {
405				pVpdL = data_4k[idxL].vpdPdg[i];
406				pPwrL = data_4k[idxL].pwrPdg[i];
407				pVpdR = data_4k[idxR].vpdPdg[i];
408				pPwrR = data_4k[idxR].pwrPdg[i];
409			} else {
410				pVpdL = data_def[idxL].vpdPdg[i];
411				pPwrL = data_def[idxL].pwrPdg[i];
412				pVpdR = data_def[idxR].vpdPdg[i];
413				pPwrR = data_def[idxR].pwrPdg[i];
414			}
415
416			minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
417
418			maxPwrT4[i] =
419				min(pPwrL[intercepts - 1],
420				    pPwrR[intercepts - 1]);
421
422
423			ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
424						pPwrL, pVpdL,
425						intercepts,
426						vpdTableL[i]);
427			ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
428						pPwrR, pVpdR,
429						intercepts,
430						vpdTableR[i]);
431
432			for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
433				vpdTableI[i][j] =
434					(u8)(ath9k_hw_interpolate((u16)
435					     FREQ2FBIN(centers.
436						       synth_center,
437						       IS_CHAN_2GHZ
438						       (chan)),
439					     bChans[idxL], bChans[idxR],
440					     vpdTableL[i][j], vpdTableR[i][j]));
441			}
442		}
443	}
444
445	k = 0;
446
447	for (i = 0; i < numXpdGains; i++) {
448		if (i == (numXpdGains - 1))
449			pPdGainBoundaries[i] =
450				(u16)(maxPwrT4[i] / 2);
451		else
452			pPdGainBoundaries[i] =
453				(u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
454
455		pPdGainBoundaries[i] =
456			min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
457
458		minDelta = 0;
459
460		if (i == 0) {
461			if (AR_SREV_9280_20_OR_LATER(ah))
462				ss = (int16_t)(0 - (minPwrT4[i] / 2));
463			else
464				ss = 0;
465		} else {
466			ss = (int16_t)((pPdGainBoundaries[i - 1] -
467					(minPwrT4[i] / 2)) -
468				       tPdGainOverlap + 1 + minDelta);
469		}
470		vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
471		vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
472
473		while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
474			tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
475			pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
476			ss++;
477		}
478
479		sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
480		tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
481				(minPwrT4[i] / 2));
482		maxIndex = (tgtIndex < sizeCurrVpdTable) ?
483			tgtIndex : sizeCurrVpdTable;
484
485		while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
486			pPDADCValues[k++] = vpdTableI[i][ss++];
487		}
488
489		vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
490				    vpdTableI[i][sizeCurrVpdTable - 2]);
491		vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
492
493		if (tgtIndex >= maxIndex) {
494			while ((ss <= tgtIndex) &&
495			       (k < (AR5416_NUM_PDADC_VALUES - 1))) {
496				tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
497						    (ss - maxIndex + 1) * vpdStep));
498				pPDADCValues[k++] = (u8)((tmpVal > 255) ?
499							 255 : tmpVal);
500				ss++;
501			}
502		}
503	}
504
505	if (eeprom_4k)
506		pdgain_boundary_default = 58;
507	else
508		pdgain_boundary_default = pPdGainBoundaries[i - 1];
509
510	while (i < AR5416_PD_GAINS_IN_MASK) {
511		pPdGainBoundaries[i] = pdgain_boundary_default;
512		i++;
513	}
514
515	while (k < AR5416_NUM_PDADC_VALUES) {
516		pPDADCValues[k] = pPDADCValues[k - 1];
517		k++;
518	}
519}
520
521int ath9k_hw_eeprom_init(struct ath_hw *ah)
522{
523	int status;
524
525	if (AR_SREV_9300_20_OR_LATER(ah))
526		ah->eep_ops = &eep_ar9300_ops;
527	else if (AR_SREV_9287(ah)) {
528		ah->eep_ops = &eep_ar9287_ops;
529	} else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
530		ah->eep_ops = &eep_4k_ops;
531	} else {
532		ah->eep_ops = &eep_def_ops;
533	}
534
535	if (!ah->eep_ops->fill_eeprom(ah))
536		return -EIO;
537
538	status = ah->eep_ops->check_eeprom(ah);
539
540	return status;
541}
542