htc_drv_init.c revision 4e63f768c3b85ae2b3ea6251231fd5cc46ec598d
1/* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "htc.h" 18 19MODULE_AUTHOR("Atheros Communications"); 20MODULE_LICENSE("Dual BSD/GPL"); 21MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices"); 22 23static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 24module_param_named(debug, ath9k_debug, uint, 0); 25MODULE_PARM_DESC(debug, "Debugging mask"); 26 27int htc_modparam_nohwcrypt; 28module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444); 29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 30 31#define CHAN2G(_freq, _idx) { \ 32 .center_freq = (_freq), \ 33 .hw_value = (_idx), \ 34 .max_power = 20, \ 35} 36 37#define CHAN5G(_freq, _idx) { \ 38 .band = IEEE80211_BAND_5GHZ, \ 39 .center_freq = (_freq), \ 40 .hw_value = (_idx), \ 41 .max_power = 20, \ 42} 43 44static struct ieee80211_channel ath9k_2ghz_channels[] = { 45 CHAN2G(2412, 0), /* Channel 1 */ 46 CHAN2G(2417, 1), /* Channel 2 */ 47 CHAN2G(2422, 2), /* Channel 3 */ 48 CHAN2G(2427, 3), /* Channel 4 */ 49 CHAN2G(2432, 4), /* Channel 5 */ 50 CHAN2G(2437, 5), /* Channel 6 */ 51 CHAN2G(2442, 6), /* Channel 7 */ 52 CHAN2G(2447, 7), /* Channel 8 */ 53 CHAN2G(2452, 8), /* Channel 9 */ 54 CHAN2G(2457, 9), /* Channel 10 */ 55 CHAN2G(2462, 10), /* Channel 11 */ 56 CHAN2G(2467, 11), /* Channel 12 */ 57 CHAN2G(2472, 12), /* Channel 13 */ 58 CHAN2G(2484, 13), /* Channel 14 */ 59}; 60 61static struct ieee80211_channel ath9k_5ghz_channels[] = { 62 /* _We_ call this UNII 1 */ 63 CHAN5G(5180, 14), /* Channel 36 */ 64 CHAN5G(5200, 15), /* Channel 40 */ 65 CHAN5G(5220, 16), /* Channel 44 */ 66 CHAN5G(5240, 17), /* Channel 48 */ 67 /* _We_ call this UNII 2 */ 68 CHAN5G(5260, 18), /* Channel 52 */ 69 CHAN5G(5280, 19), /* Channel 56 */ 70 CHAN5G(5300, 20), /* Channel 60 */ 71 CHAN5G(5320, 21), /* Channel 64 */ 72 /* _We_ call this "Middle band" */ 73 CHAN5G(5500, 22), /* Channel 100 */ 74 CHAN5G(5520, 23), /* Channel 104 */ 75 CHAN5G(5540, 24), /* Channel 108 */ 76 CHAN5G(5560, 25), /* Channel 112 */ 77 CHAN5G(5580, 26), /* Channel 116 */ 78 CHAN5G(5600, 27), /* Channel 120 */ 79 CHAN5G(5620, 28), /* Channel 124 */ 80 CHAN5G(5640, 29), /* Channel 128 */ 81 CHAN5G(5660, 30), /* Channel 132 */ 82 CHAN5G(5680, 31), /* Channel 136 */ 83 CHAN5G(5700, 32), /* Channel 140 */ 84 /* _We_ call this UNII 3 */ 85 CHAN5G(5745, 33), /* Channel 149 */ 86 CHAN5G(5765, 34), /* Channel 153 */ 87 CHAN5G(5785, 35), /* Channel 157 */ 88 CHAN5G(5805, 36), /* Channel 161 */ 89 CHAN5G(5825, 37), /* Channel 165 */ 90}; 91 92/* Atheros hardware rate code addition for short premble */ 93#define SHPCHECK(__hw_rate, __flags) \ 94 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0) 95 96#define RATE(_bitrate, _hw_rate, _flags) { \ 97 .bitrate = (_bitrate), \ 98 .flags = (_flags), \ 99 .hw_value = (_hw_rate), \ 100 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 101} 102 103static struct ieee80211_rate ath9k_legacy_rates[] = { 104 RATE(10, 0x1b, 0), 105 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */ 106 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */ 107 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */ 108 RATE(60, 0x0b, 0), 109 RATE(90, 0x0f, 0), 110 RATE(120, 0x0a, 0), 111 RATE(180, 0x0e, 0), 112 RATE(240, 0x09, 0), 113 RATE(360, 0x0d, 0), 114 RATE(480, 0x08, 0), 115 RATE(540, 0x0c, 0), 116}; 117 118static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv) 119{ 120 int time_left; 121 122 if (atomic_read(&priv->htc->tgt_ready) > 0) { 123 atomic_dec(&priv->htc->tgt_ready); 124 return 0; 125 } 126 127 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */ 128 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ); 129 if (!time_left) { 130 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n"); 131 return -ETIMEDOUT; 132 } 133 134 atomic_dec(&priv->htc->tgt_ready); 135 136 return 0; 137} 138 139static void ath9k_deinit_priv(struct ath9k_htc_priv *priv) 140{ 141 ath9k_htc_exit_debug(priv->ah); 142 ath9k_hw_deinit(priv->ah); 143 tasklet_kill(&priv->wmi_tasklet); 144 tasklet_kill(&priv->rx_tasklet); 145 tasklet_kill(&priv->tx_tasklet); 146 kfree(priv->ah); 147 priv->ah = NULL; 148} 149 150static void ath9k_deinit_device(struct ath9k_htc_priv *priv) 151{ 152 struct ieee80211_hw *hw = priv->hw; 153 154 wiphy_rfkill_stop_polling(hw->wiphy); 155 ath9k_deinit_leds(priv); 156 ieee80211_unregister_hw(hw); 157 ath9k_rx_cleanup(priv); 158 ath9k_tx_cleanup(priv); 159 ath9k_deinit_priv(priv); 160} 161 162static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv, 163 u16 service_id, 164 void (*tx) (void *, 165 struct sk_buff *, 166 enum htc_endpoint_id, 167 bool txok), 168 enum htc_endpoint_id *ep_id) 169{ 170 struct htc_service_connreq req; 171 172 memset(&req, 0, sizeof(struct htc_service_connreq)); 173 174 req.service_id = service_id; 175 req.ep_callbacks.priv = priv; 176 req.ep_callbacks.rx = ath9k_htc_rxep; 177 req.ep_callbacks.tx = tx; 178 179 return htc_connect_service(priv->htc, &req, ep_id); 180} 181 182static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid) 183{ 184 int ret; 185 186 /* WMI CMD*/ 187 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep); 188 if (ret) 189 goto err; 190 191 /* Beacon */ 192 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep, 193 &priv->beacon_ep); 194 if (ret) 195 goto err; 196 197 /* CAB */ 198 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep, 199 &priv->cab_ep); 200 if (ret) 201 goto err; 202 203 204 /* UAPSD */ 205 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep, 206 &priv->uapsd_ep); 207 if (ret) 208 goto err; 209 210 /* MGMT */ 211 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep, 212 &priv->mgmt_ep); 213 if (ret) 214 goto err; 215 216 /* DATA BE */ 217 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep, 218 &priv->data_be_ep); 219 if (ret) 220 goto err; 221 222 /* DATA BK */ 223 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep, 224 &priv->data_bk_ep); 225 if (ret) 226 goto err; 227 228 /* DATA VI */ 229 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep, 230 &priv->data_vi_ep); 231 if (ret) 232 goto err; 233 234 /* DATA VO */ 235 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep, 236 &priv->data_vo_ep); 237 if (ret) 238 goto err; 239 240 /* 241 * Setup required credits before initializing HTC. 242 * This is a bit hacky, but, since queuing is done in 243 * the HIF layer, shouldn't matter much. 244 */ 245 246 switch(devid) { 247 case 0x7010: 248 case 0x9018: 249 priv->htc->credits = 45; 250 break; 251 default: 252 priv->htc->credits = 33; 253 } 254 255 ret = htc_init(priv->htc); 256 if (ret) 257 goto err; 258 259 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n", 260 priv->htc->credits); 261 262 return 0; 263 264err: 265 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n"); 266 return ret; 267} 268 269static int ath9k_reg_notifier(struct wiphy *wiphy, 270 struct regulatory_request *request) 271{ 272 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 273 struct ath9k_htc_priv *priv = hw->priv; 274 275 return ath_reg_notifier_apply(wiphy, request, 276 ath9k_hw_regulatory(priv->ah)); 277} 278 279static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) 280{ 281 struct ath_hw *ah = (struct ath_hw *) hw_priv; 282 struct ath_common *common = ath9k_hw_common(ah); 283 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 284 __be32 val, reg = cpu_to_be32(reg_offset); 285 int r; 286 287 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID, 288 (u8 *) ®, sizeof(reg), 289 (u8 *) &val, sizeof(val), 290 100); 291 if (unlikely(r)) { 292 ath_print(common, ATH_DBG_WMI, 293 "REGISTER READ FAILED: (0x%04x, %d)\n", 294 reg_offset, r); 295 return -EIO; 296 } 297 298 return be32_to_cpu(val); 299} 300 301static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) 302{ 303 struct ath_hw *ah = (struct ath_hw *) hw_priv; 304 struct ath_common *common = ath9k_hw_common(ah); 305 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 306 __be32 buf[2] = { 307 cpu_to_be32(reg_offset), 308 cpu_to_be32(val), 309 }; 310 int r; 311 312 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 313 (u8 *) &buf, sizeof(buf), 314 (u8 *) &val, sizeof(val), 315 100); 316 if (unlikely(r)) { 317 ath_print(common, ATH_DBG_WMI, 318 "REGISTER WRITE FAILED:(0x%04x, %d)\n", 319 reg_offset, r); 320 } 321} 322 323static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) 324{ 325 struct ath_hw *ah = (struct ath_hw *) hw_priv; 326 struct ath_common *common = ath9k_hw_common(ah); 327 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 328 u32 rsp_status; 329 int r; 330 331 mutex_lock(&priv->wmi->multi_write_mutex); 332 333 /* Store the register/value */ 334 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg = 335 cpu_to_be32(reg_offset); 336 priv->wmi->multi_write[priv->wmi->multi_write_idx].val = 337 cpu_to_be32(val); 338 339 priv->wmi->multi_write_idx++; 340 341 /* If the buffer is full, send it out. */ 342 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) { 343 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 344 (u8 *) &priv->wmi->multi_write, 345 sizeof(struct register_write) * priv->wmi->multi_write_idx, 346 (u8 *) &rsp_status, sizeof(rsp_status), 347 100); 348 if (unlikely(r)) { 349 ath_print(common, ATH_DBG_WMI, 350 "REGISTER WRITE FAILED, multi len: %d\n", 351 priv->wmi->multi_write_idx); 352 } 353 priv->wmi->multi_write_idx = 0; 354 } 355 356 mutex_unlock(&priv->wmi->multi_write_mutex); 357} 358 359static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) 360{ 361 struct ath_hw *ah = (struct ath_hw *) hw_priv; 362 struct ath_common *common = ath9k_hw_common(ah); 363 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 364 365 if (atomic_read(&priv->wmi->mwrite_cnt)) 366 ath9k_regwrite_buffer(hw_priv, val, reg_offset); 367 else 368 ath9k_regwrite_single(hw_priv, val, reg_offset); 369} 370 371static void ath9k_enable_regwrite_buffer(void *hw_priv) 372{ 373 struct ath_hw *ah = (struct ath_hw *) hw_priv; 374 struct ath_common *common = ath9k_hw_common(ah); 375 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 376 377 atomic_inc(&priv->wmi->mwrite_cnt); 378} 379 380static void ath9k_disable_regwrite_buffer(void *hw_priv) 381{ 382 struct ath_hw *ah = (struct ath_hw *) hw_priv; 383 struct ath_common *common = ath9k_hw_common(ah); 384 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 385 386 atomic_dec(&priv->wmi->mwrite_cnt); 387} 388 389static void ath9k_regwrite_flush(void *hw_priv) 390{ 391 struct ath_hw *ah = (struct ath_hw *) hw_priv; 392 struct ath_common *common = ath9k_hw_common(ah); 393 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 394 u32 rsp_status; 395 int r; 396 397 mutex_lock(&priv->wmi->multi_write_mutex); 398 399 if (priv->wmi->multi_write_idx) { 400 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 401 (u8 *) &priv->wmi->multi_write, 402 sizeof(struct register_write) * priv->wmi->multi_write_idx, 403 (u8 *) &rsp_status, sizeof(rsp_status), 404 100); 405 if (unlikely(r)) { 406 ath_print(common, ATH_DBG_WMI, 407 "REGISTER WRITE FAILED, multi len: %d\n", 408 priv->wmi->multi_write_idx); 409 } 410 priv->wmi->multi_write_idx = 0; 411 } 412 413 mutex_unlock(&priv->wmi->multi_write_mutex); 414} 415 416static const struct ath_ops ath9k_common_ops = { 417 .read = ath9k_regread, 418 .write = ath9k_regwrite, 419 .enable_write_buffer = ath9k_enable_regwrite_buffer, 420 .disable_write_buffer = ath9k_disable_regwrite_buffer, 421 .write_flush = ath9k_regwrite_flush, 422}; 423 424static void ath_usb_read_cachesize(struct ath_common *common, int *csz) 425{ 426 *csz = L1_CACHE_BYTES >> 2; 427} 428 429static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data) 430{ 431 struct ath_hw *ah = (struct ath_hw *) common->ah; 432 433 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 434 435 if (!ath9k_hw_wait(ah, 436 AR_EEPROM_STATUS_DATA, 437 AR_EEPROM_STATUS_DATA_BUSY | 438 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 439 AH_WAIT_TIMEOUT)) 440 return false; 441 442 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), 443 AR_EEPROM_STATUS_DATA_VAL); 444 445 return true; 446} 447 448static const struct ath_bus_ops ath9k_usb_bus_ops = { 449 .ath_bus_type = ATH_USB, 450 .read_cachesize = ath_usb_read_cachesize, 451 .eeprom_read = ath_usb_eeprom_read, 452}; 453 454static void setup_ht_cap(struct ath9k_htc_priv *priv, 455 struct ieee80211_sta_ht_cap *ht_info) 456{ 457 struct ath_common *common = ath9k_hw_common(priv->ah); 458 u8 tx_streams, rx_streams; 459 int i; 460 461 ht_info->ht_supported = true; 462 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 463 IEEE80211_HT_CAP_SM_PS | 464 IEEE80211_HT_CAP_SGI_40 | 465 IEEE80211_HT_CAP_DSSSCCK40; 466 467 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 468 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 469 470 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 471 472 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 473 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 474 475 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 476 477 /* ath9k_htc supports only 1 or 2 stream devices */ 478 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); 479 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); 480 481 ath_print(common, ATH_DBG_CONFIG, 482 "TX streams %d, RX streams: %d\n", 483 tx_streams, rx_streams); 484 485 if (tx_streams != rx_streams) { 486 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 487 ht_info->mcs.tx_params |= ((tx_streams - 1) << 488 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 489 } 490 491 for (i = 0; i < rx_streams; i++) 492 ht_info->mcs.rx_mask[i] = 0xff; 493 494 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 495} 496 497static int ath9k_init_queues(struct ath9k_htc_priv *priv) 498{ 499 struct ath_common *common = ath9k_hw_common(priv->ah); 500 int i; 501 502 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++) 503 priv->hwq_map[i] = -1; 504 505 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah); 506 if (priv->beaconq == -1) { 507 ath_print(common, ATH_DBG_FATAL, 508 "Unable to setup BEACON xmit queue\n"); 509 goto err; 510 } 511 512 priv->cabq = ath9k_htc_cabq_setup(priv); 513 if (priv->cabq == -1) { 514 ath_print(common, ATH_DBG_FATAL, 515 "Unable to setup CAB xmit queue\n"); 516 goto err; 517 } 518 519 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) { 520 ath_print(common, ATH_DBG_FATAL, 521 "Unable to setup xmit queue for BE traffic\n"); 522 goto err; 523 } 524 525 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) { 526 ath_print(common, ATH_DBG_FATAL, 527 "Unable to setup xmit queue for BK traffic\n"); 528 goto err; 529 } 530 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) { 531 ath_print(common, ATH_DBG_FATAL, 532 "Unable to setup xmit queue for VI traffic\n"); 533 goto err; 534 } 535 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) { 536 ath_print(common, ATH_DBG_FATAL, 537 "Unable to setup xmit queue for VO traffic\n"); 538 goto err; 539 } 540 541 return 0; 542 543err: 544 return -EINVAL; 545} 546 547static void ath9k_init_crypto(struct ath9k_htc_priv *priv) 548{ 549 struct ath_common *common = ath9k_hw_common(priv->ah); 550 int i = 0; 551 552 /* Get the hardware key cache size. */ 553 common->keymax = priv->ah->caps.keycache_size; 554 if (common->keymax > ATH_KEYMAX) { 555 ath_print(common, ATH_DBG_ANY, 556 "Warning, using only %u entries in %u key cache\n", 557 ATH_KEYMAX, common->keymax); 558 common->keymax = ATH_KEYMAX; 559 } 560 561 /* 562 * Reset the key cache since some parts do not 563 * reset the contents on initial power up. 564 */ 565 for (i = 0; i < common->keymax; i++) 566 ath9k_hw_keyreset(priv->ah, (u16) i); 567} 568 569static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv) 570{ 571 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) { 572 priv->sbands[IEEE80211_BAND_2GHZ].channels = 573 ath9k_2ghz_channels; 574 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 575 priv->sbands[IEEE80211_BAND_2GHZ].n_channels = 576 ARRAY_SIZE(ath9k_2ghz_channels); 577 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 578 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 579 ARRAY_SIZE(ath9k_legacy_rates); 580 } 581 582 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) { 583 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels; 584 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 585 priv->sbands[IEEE80211_BAND_5GHZ].n_channels = 586 ARRAY_SIZE(ath9k_5ghz_channels); 587 priv->sbands[IEEE80211_BAND_5GHZ].bitrates = 588 ath9k_legacy_rates + 4; 589 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates = 590 ARRAY_SIZE(ath9k_legacy_rates) - 4; 591 } 592} 593 594static void ath9k_init_misc(struct ath9k_htc_priv *priv) 595{ 596 struct ath_common *common = ath9k_hw_common(priv->ah); 597 598 common->tx_chainmask = priv->ah->caps.tx_chainmask; 599 common->rx_chainmask = priv->ah->caps.rx_chainmask; 600 601 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 602 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 603 604 priv->ah->opmode = NL80211_IFTYPE_STATION; 605} 606 607static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid) 608{ 609 struct ath_hw *ah = NULL; 610 struct ath_common *common; 611 int ret = 0, csz = 0; 612 613 priv->op_flags |= OP_INVALID; 614 615 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 616 if (!ah) 617 return -ENOMEM; 618 619 ah->hw_version.devid = devid; 620 ah->hw_version.subsysid = 0; /* FIXME */ 621 priv->ah = ah; 622 623 common = ath9k_hw_common(ah); 624 common->ops = &ath9k_common_ops; 625 common->bus_ops = &ath9k_usb_bus_ops; 626 common->ah = ah; 627 common->hw = priv->hw; 628 common->priv = priv; 629 common->debug_mask = ath9k_debug; 630 631 spin_lock_init(&priv->wmi->wmi_lock); 632 spin_lock_init(&priv->beacon_lock); 633 spin_lock_init(&priv->tx_lock); 634 mutex_init(&priv->mutex); 635 mutex_init(&priv->htc_pm_lock); 636 tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet, 637 (unsigned long)priv); 638 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet, 639 (unsigned long)priv); 640 tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv); 641 INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work); 642 INIT_WORK(&priv->ps_work, ath9k_ps_work); 643 644 /* 645 * Cache line size is used to size and align various 646 * structures used to communicate with the hardware. 647 */ 648 ath_read_cachesize(common, &csz); 649 common->cachelsz = csz << 2; /* convert to bytes */ 650 651 ret = ath9k_hw_init(ah); 652 if (ret) { 653 ath_print(common, ATH_DBG_FATAL, 654 "Unable to initialize hardware; " 655 "initialization status: %d\n", ret); 656 goto err_hw; 657 } 658 659 ret = ath9k_htc_init_debug(ah); 660 if (ret) { 661 ath_print(common, ATH_DBG_FATAL, 662 "Unable to create debugfs files\n"); 663 goto err_debug; 664 } 665 666 ret = ath9k_init_queues(priv); 667 if (ret) 668 goto err_queues; 669 670 ath9k_init_crypto(priv); 671 ath9k_init_channels_rates(priv); 672 ath9k_init_misc(priv); 673 674 return 0; 675 676err_queues: 677 ath9k_htc_exit_debug(ah); 678err_debug: 679 ath9k_hw_deinit(ah); 680err_hw: 681 682 kfree(ah); 683 priv->ah = NULL; 684 685 return ret; 686} 687 688static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv, 689 struct ieee80211_hw *hw) 690{ 691 struct ath_common *common = ath9k_hw_common(priv->ah); 692 693 hw->flags = IEEE80211_HW_SIGNAL_DBM | 694 IEEE80211_HW_AMPDU_AGGREGATION | 695 IEEE80211_HW_SPECTRUM_MGMT | 696 IEEE80211_HW_HAS_RATE_CONTROL | 697 IEEE80211_HW_RX_INCLUDES_FCS | 698 IEEE80211_HW_SUPPORTS_PS | 699 IEEE80211_HW_PS_NULLFUNC_STACK; 700 701 hw->wiphy->interface_modes = 702 BIT(NL80211_IFTYPE_STATION) | 703 BIT(NL80211_IFTYPE_ADHOC); 704 705 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 706 707 hw->queues = 4; 708 hw->channel_change_time = 5000; 709 hw->max_listen_interval = 10; 710 hw->vif_data_size = sizeof(struct ath9k_htc_vif); 711 hw->sta_data_size = sizeof(struct ath9k_htc_sta); 712 713 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */ 714 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) + 715 sizeof(struct htc_frame_hdr) + 4; 716 717 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) 718 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 719 &priv->sbands[IEEE80211_BAND_2GHZ]; 720 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) 721 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 722 &priv->sbands[IEEE80211_BAND_5GHZ]; 723 724 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 725 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) 726 setup_ht_cap(priv, 727 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap); 728 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) 729 setup_ht_cap(priv, 730 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap); 731 } 732 733 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 734} 735 736static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid) 737{ 738 struct ieee80211_hw *hw = priv->hw; 739 struct ath_common *common; 740 struct ath_hw *ah; 741 int error = 0; 742 struct ath_regulatory *reg; 743 744 /* Bring up device */ 745 error = ath9k_init_priv(priv, devid); 746 if (error != 0) 747 goto err_init; 748 749 ah = priv->ah; 750 common = ath9k_hw_common(ah); 751 ath9k_set_hw_capab(priv, hw); 752 753 /* Initialize regulatory */ 754 error = ath_regd_init(&common->regulatory, priv->hw->wiphy, 755 ath9k_reg_notifier); 756 if (error) 757 goto err_regd; 758 759 reg = &common->regulatory; 760 761 /* Setup TX */ 762 error = ath9k_tx_init(priv); 763 if (error != 0) 764 goto err_tx; 765 766 /* Setup RX */ 767 error = ath9k_rx_init(priv); 768 if (error != 0) 769 goto err_rx; 770 771 /* Register with mac80211 */ 772 error = ieee80211_register_hw(hw); 773 if (error) 774 goto err_register; 775 776 /* Handle world regulatory */ 777 if (!ath_is_world_regd(reg)) { 778 error = regulatory_hint(hw->wiphy, reg->alpha2); 779 if (error) 780 goto err_world; 781 } 782 783 ath9k_init_leds(priv); 784 ath9k_start_rfkill_poll(priv); 785 786 return 0; 787 788err_world: 789 ieee80211_unregister_hw(hw); 790err_register: 791 ath9k_rx_cleanup(priv); 792err_rx: 793 ath9k_tx_cleanup(priv); 794err_tx: 795 /* Nothing */ 796err_regd: 797 ath9k_deinit_priv(priv); 798err_init: 799 return error; 800} 801 802int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev, 803 u16 devid) 804{ 805 struct ieee80211_hw *hw; 806 struct ath9k_htc_priv *priv; 807 int ret; 808 809 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops); 810 if (!hw) 811 return -ENOMEM; 812 813 priv = hw->priv; 814 priv->hw = hw; 815 priv->htc = htc_handle; 816 priv->dev = dev; 817 htc_handle->drv_priv = priv; 818 SET_IEEE80211_DEV(hw, priv->dev); 819 820 ret = ath9k_htc_wait_for_target(priv); 821 if (ret) 822 goto err_free; 823 824 priv->wmi = ath9k_init_wmi(priv); 825 if (!priv->wmi) { 826 ret = -EINVAL; 827 goto err_free; 828 } 829 830 ret = ath9k_init_htc_services(priv, devid); 831 if (ret) 832 goto err_init; 833 834 /* The device may have been unplugged earlier. */ 835 priv->op_flags &= ~OP_UNPLUGGED; 836 837 ret = ath9k_init_device(priv, devid); 838 if (ret) 839 goto err_init; 840 841 return 0; 842 843err_init: 844 ath9k_deinit_wmi(priv); 845err_free: 846 ieee80211_free_hw(hw); 847 return ret; 848} 849 850void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug) 851{ 852 if (htc_handle->drv_priv) { 853 854 /* Check if the device has been yanked out. */ 855 if (hotunplug) 856 htc_handle->drv_priv->op_flags |= OP_UNPLUGGED; 857 858 ath9k_deinit_device(htc_handle->drv_priv); 859 ath9k_deinit_wmi(htc_handle->drv_priv); 860 ieee80211_free_hw(htc_handle->drv_priv->hw); 861 } 862} 863 864#ifdef CONFIG_PM 865int ath9k_htc_resume(struct htc_target *htc_handle) 866{ 867 int ret; 868 869 ret = ath9k_htc_wait_for_target(htc_handle->drv_priv); 870 if (ret) 871 return ret; 872 873 ret = ath9k_init_htc_services(htc_handle->drv_priv, 874 htc_handle->drv_priv->ah->hw_version.devid); 875 return ret; 876} 877#endif 878 879static int __init ath9k_htc_init(void) 880{ 881 int error; 882 883 error = ath9k_htc_debug_create_root(); 884 if (error < 0) { 885 printk(KERN_ERR 886 "ath9k_htc: Unable to create debugfs root: %d\n", 887 error); 888 goto err_dbg; 889 } 890 891 error = ath9k_hif_usb_init(); 892 if (error < 0) { 893 printk(KERN_ERR 894 "ath9k_htc: No USB devices found," 895 " driver not installed.\n"); 896 error = -ENODEV; 897 goto err_usb; 898 } 899 900 return 0; 901 902err_usb: 903 ath9k_htc_debug_remove_root(); 904err_dbg: 905 return error; 906} 907module_init(ath9k_htc_init); 908 909static void __exit ath9k_htc_exit(void) 910{ 911 ath9k_hif_usb_exit(); 912 ath9k_htc_debug_remove_root(); 913 printk(KERN_INFO "ath9k_htc: Driver unloaded\n"); 914} 915module_exit(ath9k_htc_exit); 916