main.c revision 03b29773b613f10d2f97dbf0983f1c4c58507967
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 Some parts of the code in this file are derived from the ipw2200 12 driver Copyright(c) 2003 - 2004 Intel Corporation. 13 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; either version 2 of the License, or 17 (at your option) any later version. 18 19 This program is distributed in the hope that it will be useful, 20 but WITHOUT ANY WARRANTY; without even the implied warranty of 21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 GNU General Public License for more details. 23 24 You should have received a copy of the GNU General Public License 25 along with this program; see the file COPYING. If not, write to 26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 27 Boston, MA 02110-1301, USA. 28 29*/ 30 31#include <linux/delay.h> 32#include <linux/init.h> 33#include <linux/moduleparam.h> 34#include <linux/if_arp.h> 35#include <linux/etherdevice.h> 36#include <linux/version.h> 37#include <linux/firmware.h> 38#include <linux/wireless.h> 39#include <linux/workqueue.h> 40#include <linux/skbuff.h> 41#include <linux/dma-mapping.h> 42#include <asm/unaligned.h> 43 44#include "b43.h" 45#include "main.h" 46#include "debugfs.h" 47#include "phy.h" 48#include "dma.h" 49#include "sysfs.h" 50#include "xmit.h" 51#include "lo.h" 52#include "pcmcia.h" 53 54MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 55MODULE_AUTHOR("Martin Langer"); 56MODULE_AUTHOR("Stefano Brivio"); 57MODULE_AUTHOR("Michael Buesch"); 58MODULE_LICENSE("GPL"); 59 60 61static int modparam_bad_frames_preempt; 62module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 63MODULE_PARM_DESC(bad_frames_preempt, 64 "enable(1) / disable(0) Bad Frames Preemption"); 65 66static char modparam_fwpostfix[16]; 67module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 68MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 69 70static int modparam_hwpctl; 71module_param_named(hwpctl, modparam_hwpctl, int, 0444); 72MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 73 74static int modparam_nohwcrypt; 75module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 76MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 77 78static const struct ssb_device_id b43_ssb_tbl[] = { 79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 85 SSB_DEVTABLE_END 86}; 87 88MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 89 90/* Channel and ratetables are shared for all devices. 91 * They can't be const, because ieee80211 puts some precalculated 92 * data in there. This data is the same for all devices, so we don't 93 * get concurrency issues */ 94#define RATETAB_ENT(_rateid, _flags) \ 95 { \ 96 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \ 97 .val = (_rateid), \ 98 .val2 = (_rateid), \ 99 .flags = (_flags), \ 100 } 101static struct ieee80211_rate __b43_ratetable[] = { 102 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK), 103 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2), 104 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2), 105 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2), 106 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM), 107 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM), 108 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM), 109 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM), 110 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM), 111 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM), 112 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM), 113 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM), 114}; 115 116#define b43_a_ratetable (__b43_ratetable + 4) 117#define b43_a_ratetable_size 8 118#define b43_b_ratetable (__b43_ratetable + 0) 119#define b43_b_ratetable_size 4 120#define b43_g_ratetable (__b43_ratetable + 0) 121#define b43_g_ratetable_size 12 122 123#define CHANTAB_ENT(_chanid, _freq) \ 124 { \ 125 .chan = (_chanid), \ 126 .freq = (_freq), \ 127 .val = (_chanid), \ 128 .flag = IEEE80211_CHAN_W_SCAN | \ 129 IEEE80211_CHAN_W_ACTIVE_SCAN | \ 130 IEEE80211_CHAN_W_IBSS, \ 131 .power_level = 0xFF, \ 132 .antenna_max = 0xFF, \ 133 } 134static struct ieee80211_channel b43_bg_chantable[] = { 135 CHANTAB_ENT(1, 2412), 136 CHANTAB_ENT(2, 2417), 137 CHANTAB_ENT(3, 2422), 138 CHANTAB_ENT(4, 2427), 139 CHANTAB_ENT(5, 2432), 140 CHANTAB_ENT(6, 2437), 141 CHANTAB_ENT(7, 2442), 142 CHANTAB_ENT(8, 2447), 143 CHANTAB_ENT(9, 2452), 144 CHANTAB_ENT(10, 2457), 145 CHANTAB_ENT(11, 2462), 146 CHANTAB_ENT(12, 2467), 147 CHANTAB_ENT(13, 2472), 148 CHANTAB_ENT(14, 2484), 149}; 150 151#define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable) 152static struct ieee80211_channel b43_a_chantable[] = { 153 CHANTAB_ENT(36, 5180), 154 CHANTAB_ENT(40, 5200), 155 CHANTAB_ENT(44, 5220), 156 CHANTAB_ENT(48, 5240), 157 CHANTAB_ENT(52, 5260), 158 CHANTAB_ENT(56, 5280), 159 CHANTAB_ENT(60, 5300), 160 CHANTAB_ENT(64, 5320), 161 CHANTAB_ENT(149, 5745), 162 CHANTAB_ENT(153, 5765), 163 CHANTAB_ENT(157, 5785), 164 CHANTAB_ENT(161, 5805), 165 CHANTAB_ENT(165, 5825), 166}; 167 168#define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable) 169 170static void b43_wireless_core_exit(struct b43_wldev *dev); 171static int b43_wireless_core_init(struct b43_wldev *dev); 172static void b43_wireless_core_stop(struct b43_wldev *dev); 173static int b43_wireless_core_start(struct b43_wldev *dev); 174 175static int b43_ratelimit(struct b43_wl *wl) 176{ 177 if (!wl || !wl->current_dev) 178 return 1; 179 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 180 return 1; 181 /* We are up and running. 182 * Ratelimit the messages to avoid DoS over the net. */ 183 return net_ratelimit(); 184} 185 186void b43info(struct b43_wl *wl, const char *fmt, ...) 187{ 188 va_list args; 189 190 if (!b43_ratelimit(wl)) 191 return; 192 va_start(args, fmt); 193 printk(KERN_INFO "b43-%s: ", 194 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 195 vprintk(fmt, args); 196 va_end(args); 197} 198 199void b43err(struct b43_wl *wl, const char *fmt, ...) 200{ 201 va_list args; 202 203 if (!b43_ratelimit(wl)) 204 return; 205 va_start(args, fmt); 206 printk(KERN_ERR "b43-%s ERROR: ", 207 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 208 vprintk(fmt, args); 209 va_end(args); 210} 211 212void b43warn(struct b43_wl *wl, const char *fmt, ...) 213{ 214 va_list args; 215 216 if (!b43_ratelimit(wl)) 217 return; 218 va_start(args, fmt); 219 printk(KERN_WARNING "b43-%s warning: ", 220 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 221 vprintk(fmt, args); 222 va_end(args); 223} 224 225#if B43_DEBUG 226void b43dbg(struct b43_wl *wl, const char *fmt, ...) 227{ 228 va_list args; 229 230 va_start(args, fmt); 231 printk(KERN_DEBUG "b43-%s debug: ", 232 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 233 vprintk(fmt, args); 234 va_end(args); 235} 236#endif /* DEBUG */ 237 238static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 239{ 240 u32 macctl; 241 242 B43_WARN_ON(offset % 4 != 0); 243 244 macctl = b43_read32(dev, B43_MMIO_MACCTL); 245 if (macctl & B43_MACCTL_BE) 246 val = swab32(val); 247 248 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 249 mmiowb(); 250 b43_write32(dev, B43_MMIO_RAM_DATA, val); 251} 252 253static inline 254 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset) 255{ 256 u32 control; 257 258 /* "offset" is the WORD offset. */ 259 260 control = routing; 261 control <<= 16; 262 control |= offset; 263 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 264} 265 266u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 267{ 268 u32 ret; 269 270 if (routing == B43_SHM_SHARED) { 271 B43_WARN_ON(offset & 0x0001); 272 if (offset & 0x0003) { 273 /* Unaligned access */ 274 b43_shm_control_word(dev, routing, offset >> 2); 275 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 276 ret <<= 16; 277 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 278 ret |= b43_read16(dev, B43_MMIO_SHM_DATA); 279 280 return ret; 281 } 282 offset >>= 2; 283 } 284 b43_shm_control_word(dev, routing, offset); 285 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 286 287 return ret; 288} 289 290u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset) 291{ 292 u16 ret; 293 294 if (routing == B43_SHM_SHARED) { 295 B43_WARN_ON(offset & 0x0001); 296 if (offset & 0x0003) { 297 /* Unaligned access */ 298 b43_shm_control_word(dev, routing, offset >> 2); 299 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 300 301 return ret; 302 } 303 offset >>= 2; 304 } 305 b43_shm_control_word(dev, routing, offset); 306 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 307 308 return ret; 309} 310 311void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 312{ 313 if (routing == B43_SHM_SHARED) { 314 B43_WARN_ON(offset & 0x0001); 315 if (offset & 0x0003) { 316 /* Unaligned access */ 317 b43_shm_control_word(dev, routing, offset >> 2); 318 mmiowb(); 319 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 320 (value >> 16) & 0xffff); 321 mmiowb(); 322 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 323 mmiowb(); 324 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff); 325 return; 326 } 327 offset >>= 2; 328 } 329 b43_shm_control_word(dev, routing, offset); 330 mmiowb(); 331 b43_write32(dev, B43_MMIO_SHM_DATA, value); 332} 333 334void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 335{ 336 if (routing == B43_SHM_SHARED) { 337 B43_WARN_ON(offset & 0x0001); 338 if (offset & 0x0003) { 339 /* Unaligned access */ 340 b43_shm_control_word(dev, routing, offset >> 2); 341 mmiowb(); 342 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 343 return; 344 } 345 offset >>= 2; 346 } 347 b43_shm_control_word(dev, routing, offset); 348 mmiowb(); 349 b43_write16(dev, B43_MMIO_SHM_DATA, value); 350} 351 352/* Read HostFlags */ 353u32 b43_hf_read(struct b43_wldev * dev) 354{ 355 u32 ret; 356 357 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 358 ret <<= 16; 359 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 360 361 return ret; 362} 363 364/* Write HostFlags */ 365void b43_hf_write(struct b43_wldev *dev, u32 value) 366{ 367 b43_shm_write16(dev, B43_SHM_SHARED, 368 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF)); 369 b43_shm_write16(dev, B43_SHM_SHARED, 370 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16)); 371} 372 373void b43_tsf_read(struct b43_wldev *dev, u64 * tsf) 374{ 375 /* We need to be careful. As we read the TSF from multiple 376 * registers, we should take care of register overflows. 377 * In theory, the whole tsf read process should be atomic. 378 * We try to be atomic here, by restaring the read process, 379 * if any of the high registers changed (overflew). 380 */ 381 if (dev->dev->id.revision >= 3) { 382 u32 low, high, high2; 383 384 do { 385 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 386 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 387 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 388 } while (unlikely(high != high2)); 389 390 *tsf = high; 391 *tsf <<= 32; 392 *tsf |= low; 393 } else { 394 u64 tmp; 395 u16 v0, v1, v2, v3; 396 u16 test1, test2, test3; 397 398 do { 399 v3 = b43_read16(dev, B43_MMIO_TSF_3); 400 v2 = b43_read16(dev, B43_MMIO_TSF_2); 401 v1 = b43_read16(dev, B43_MMIO_TSF_1); 402 v0 = b43_read16(dev, B43_MMIO_TSF_0); 403 404 test3 = b43_read16(dev, B43_MMIO_TSF_3); 405 test2 = b43_read16(dev, B43_MMIO_TSF_2); 406 test1 = b43_read16(dev, B43_MMIO_TSF_1); 407 } while (v3 != test3 || v2 != test2 || v1 != test1); 408 409 *tsf = v3; 410 *tsf <<= 48; 411 tmp = v2; 412 tmp <<= 32; 413 *tsf |= tmp; 414 tmp = v1; 415 tmp <<= 16; 416 *tsf |= tmp; 417 *tsf |= v0; 418 } 419} 420 421static void b43_time_lock(struct b43_wldev *dev) 422{ 423 u32 macctl; 424 425 macctl = b43_read32(dev, B43_MMIO_MACCTL); 426 macctl |= B43_MACCTL_TBTTHOLD; 427 b43_write32(dev, B43_MMIO_MACCTL, macctl); 428 /* Commit the write */ 429 b43_read32(dev, B43_MMIO_MACCTL); 430} 431 432static void b43_time_unlock(struct b43_wldev *dev) 433{ 434 u32 macctl; 435 436 macctl = b43_read32(dev, B43_MMIO_MACCTL); 437 macctl &= ~B43_MACCTL_TBTTHOLD; 438 b43_write32(dev, B43_MMIO_MACCTL, macctl); 439 /* Commit the write */ 440 b43_read32(dev, B43_MMIO_MACCTL); 441} 442 443static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 444{ 445 /* Be careful with the in-progress timer. 446 * First zero out the low register, so we have a full 447 * register-overflow duration to complete the operation. 448 */ 449 if (dev->dev->id.revision >= 3) { 450 u32 lo = (tsf & 0x00000000FFFFFFFFULL); 451 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32; 452 453 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0); 454 mmiowb(); 455 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi); 456 mmiowb(); 457 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo); 458 } else { 459 u16 v0 = (tsf & 0x000000000000FFFFULL); 460 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16; 461 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32; 462 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; 463 464 b43_write16(dev, B43_MMIO_TSF_0, 0); 465 mmiowb(); 466 b43_write16(dev, B43_MMIO_TSF_3, v3); 467 mmiowb(); 468 b43_write16(dev, B43_MMIO_TSF_2, v2); 469 mmiowb(); 470 b43_write16(dev, B43_MMIO_TSF_1, v1); 471 mmiowb(); 472 b43_write16(dev, B43_MMIO_TSF_0, v0); 473 } 474} 475 476void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 477{ 478 b43_time_lock(dev); 479 b43_tsf_write_locked(dev, tsf); 480 b43_time_unlock(dev); 481} 482 483static 484void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac) 485{ 486 static const u8 zero_addr[ETH_ALEN] = { 0 }; 487 u16 data; 488 489 if (!mac) 490 mac = zero_addr; 491 492 offset |= 0x0020; 493 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 494 495 data = mac[0]; 496 data |= mac[1] << 8; 497 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 498 data = mac[2]; 499 data |= mac[3] << 8; 500 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 501 data = mac[4]; 502 data |= mac[5] << 8; 503 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 504} 505 506static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 507{ 508 const u8 *mac; 509 const u8 *bssid; 510 u8 mac_bssid[ETH_ALEN * 2]; 511 int i; 512 u32 tmp; 513 514 bssid = dev->wl->bssid; 515 mac = dev->wl->mac_addr; 516 517 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 518 519 memcpy(mac_bssid, mac, ETH_ALEN); 520 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 521 522 /* Write our MAC address and BSSID to template ram */ 523 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 524 tmp = (u32) (mac_bssid[i + 0]); 525 tmp |= (u32) (mac_bssid[i + 1]) << 8; 526 tmp |= (u32) (mac_bssid[i + 2]) << 16; 527 tmp |= (u32) (mac_bssid[i + 3]) << 24; 528 b43_ram_write(dev, 0x20 + i, tmp); 529 } 530} 531 532static void b43_upload_card_macaddress(struct b43_wldev *dev) 533{ 534 b43_write_mac_bssid_templates(dev); 535 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 536} 537 538static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 539{ 540 /* slot_time is in usec. */ 541 if (dev->phy.type != B43_PHYTYPE_G) 542 return; 543 b43_write16(dev, 0x684, 510 + slot_time); 544 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 545} 546 547static void b43_short_slot_timing_enable(struct b43_wldev *dev) 548{ 549 b43_set_slot_time(dev, 9); 550 dev->short_slot = 1; 551} 552 553static void b43_short_slot_timing_disable(struct b43_wldev *dev) 554{ 555 b43_set_slot_time(dev, 20); 556 dev->short_slot = 0; 557} 558 559/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable. 560 * Returns the _previously_ enabled IRQ mask. 561 */ 562static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask) 563{ 564 u32 old_mask; 565 566 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 567 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask); 568 569 return old_mask; 570} 571 572/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable. 573 * Returns the _previously_ enabled IRQ mask. 574 */ 575static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask) 576{ 577 u32 old_mask; 578 579 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 580 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask); 581 582 return old_mask; 583} 584 585/* Synchronize IRQ top- and bottom-half. 586 * IRQs must be masked before calling this. 587 * This must not be called with the irq_lock held. 588 */ 589static void b43_synchronize_irq(struct b43_wldev *dev) 590{ 591 synchronize_irq(dev->dev->irq); 592 tasklet_kill(&dev->isr_tasklet); 593} 594 595/* DummyTransmission function, as documented on 596 * http://bcm-specs.sipsolutions.net/DummyTransmission 597 */ 598void b43_dummy_transmission(struct b43_wldev *dev) 599{ 600 struct b43_phy *phy = &dev->phy; 601 unsigned int i, max_loop; 602 u16 value; 603 u32 buffer[5] = { 604 0x00000000, 605 0x00D40000, 606 0x00000000, 607 0x01000000, 608 0x00000000, 609 }; 610 611 switch (phy->type) { 612 case B43_PHYTYPE_A: 613 max_loop = 0x1E; 614 buffer[0] = 0x000201CC; 615 break; 616 case B43_PHYTYPE_B: 617 case B43_PHYTYPE_G: 618 max_loop = 0xFA; 619 buffer[0] = 0x000B846E; 620 break; 621 default: 622 B43_WARN_ON(1); 623 return; 624 } 625 626 for (i = 0; i < 5; i++) 627 b43_ram_write(dev, i * 4, buffer[i]); 628 629 /* Commit writes */ 630 b43_read32(dev, B43_MMIO_MACCTL); 631 632 b43_write16(dev, 0x0568, 0x0000); 633 b43_write16(dev, 0x07C0, 0x0000); 634 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0); 635 b43_write16(dev, 0x050C, value); 636 b43_write16(dev, 0x0508, 0x0000); 637 b43_write16(dev, 0x050A, 0x0000); 638 b43_write16(dev, 0x054C, 0x0000); 639 b43_write16(dev, 0x056A, 0x0014); 640 b43_write16(dev, 0x0568, 0x0826); 641 b43_write16(dev, 0x0500, 0x0000); 642 b43_write16(dev, 0x0502, 0x0030); 643 644 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 645 b43_radio_write16(dev, 0x0051, 0x0017); 646 for (i = 0x00; i < max_loop; i++) { 647 value = b43_read16(dev, 0x050E); 648 if (value & 0x0080) 649 break; 650 udelay(10); 651 } 652 for (i = 0x00; i < 0x0A; i++) { 653 value = b43_read16(dev, 0x050E); 654 if (value & 0x0400) 655 break; 656 udelay(10); 657 } 658 for (i = 0x00; i < 0x0A; i++) { 659 value = b43_read16(dev, 0x0690); 660 if (!(value & 0x0100)) 661 break; 662 udelay(10); 663 } 664 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 665 b43_radio_write16(dev, 0x0051, 0x0037); 666} 667 668static void key_write(struct b43_wldev *dev, 669 u8 index, u8 algorithm, const u8 * key) 670{ 671 unsigned int i; 672 u32 offset; 673 u16 value; 674 u16 kidx; 675 676 /* Key index/algo block */ 677 kidx = b43_kidx_to_fw(dev, index); 678 value = ((kidx << 4) | algorithm); 679 b43_shm_write16(dev, B43_SHM_SHARED, 680 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 681 682 /* Write the key to the Key Table Pointer offset */ 683 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 684 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 685 value = key[i]; 686 value |= (u16) (key[i + 1]) << 8; 687 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 688 } 689} 690 691static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr) 692{ 693 u32 addrtmp[2] = { 0, 0, }; 694 u8 per_sta_keys_start = 8; 695 696 if (b43_new_kidx_api(dev)) 697 per_sta_keys_start = 4; 698 699 B43_WARN_ON(index < per_sta_keys_start); 700 /* We have two default TX keys and possibly two default RX keys. 701 * Physical mac 0 is mapped to physical key 4 or 8, depending 702 * on the firmware version. 703 * So we must adjust the index here. 704 */ 705 index -= per_sta_keys_start; 706 707 if (addr) { 708 addrtmp[0] = addr[0]; 709 addrtmp[0] |= ((u32) (addr[1]) << 8); 710 addrtmp[0] |= ((u32) (addr[2]) << 16); 711 addrtmp[0] |= ((u32) (addr[3]) << 24); 712 addrtmp[1] = addr[4]; 713 addrtmp[1] |= ((u32) (addr[5]) << 8); 714 } 715 716 if (dev->dev->id.revision >= 5) { 717 /* Receive match transmitter address mechanism */ 718 b43_shm_write32(dev, B43_SHM_RCMTA, 719 (index * 2) + 0, addrtmp[0]); 720 b43_shm_write16(dev, B43_SHM_RCMTA, 721 (index * 2) + 1, addrtmp[1]); 722 } else { 723 /* RXE (Receive Engine) and 724 * PSM (Programmable State Machine) mechanism 725 */ 726 if (index < 8) { 727 /* TODO write to RCM 16, 19, 22 and 25 */ 728 } else { 729 b43_shm_write32(dev, B43_SHM_SHARED, 730 B43_SHM_SH_PSM + (index * 6) + 0, 731 addrtmp[0]); 732 b43_shm_write16(dev, B43_SHM_SHARED, 733 B43_SHM_SH_PSM + (index * 6) + 4, 734 addrtmp[1]); 735 } 736 } 737} 738 739static void do_key_write(struct b43_wldev *dev, 740 u8 index, u8 algorithm, 741 const u8 * key, size_t key_len, const u8 * mac_addr) 742{ 743 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 744 u8 per_sta_keys_start = 8; 745 746 if (b43_new_kidx_api(dev)) 747 per_sta_keys_start = 4; 748 749 B43_WARN_ON(index >= dev->max_nr_keys); 750 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 751 752 if (index >= per_sta_keys_start) 753 keymac_write(dev, index, NULL); /* First zero out mac. */ 754 if (key) 755 memcpy(buf, key, key_len); 756 key_write(dev, index, algorithm, buf); 757 if (index >= per_sta_keys_start) 758 keymac_write(dev, index, mac_addr); 759 760 dev->key[index].algorithm = algorithm; 761} 762 763static int b43_key_write(struct b43_wldev *dev, 764 int index, u8 algorithm, 765 const u8 * key, size_t key_len, 766 const u8 * mac_addr, 767 struct ieee80211_key_conf *keyconf) 768{ 769 int i; 770 int sta_keys_start; 771 772 if (key_len > B43_SEC_KEYSIZE) 773 return -EINVAL; 774 for (i = 0; i < dev->max_nr_keys; i++) { 775 /* Check that we don't already have this key. */ 776 B43_WARN_ON(dev->key[i].keyconf == keyconf); 777 } 778 if (index < 0) { 779 /* Either pairwise key or address is 00:00:00:00:00:00 780 * for transmit-only keys. Search the index. */ 781 if (b43_new_kidx_api(dev)) 782 sta_keys_start = 4; 783 else 784 sta_keys_start = 8; 785 for (i = sta_keys_start; i < dev->max_nr_keys; i++) { 786 if (!dev->key[i].keyconf) { 787 /* found empty */ 788 index = i; 789 break; 790 } 791 } 792 if (index < 0) { 793 b43err(dev->wl, "Out of hardware key memory\n"); 794 return -ENOSPC; 795 } 796 } else 797 B43_WARN_ON(index > 3); 798 799 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 800 if ((index <= 3) && !b43_new_kidx_api(dev)) { 801 /* Default RX key */ 802 B43_WARN_ON(mac_addr); 803 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 804 } 805 keyconf->hw_key_idx = index; 806 dev->key[index].keyconf = keyconf; 807 808 return 0; 809} 810 811static int b43_key_clear(struct b43_wldev *dev, int index) 812{ 813 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys))) 814 return -EINVAL; 815 do_key_write(dev, index, B43_SEC_ALGO_NONE, 816 NULL, B43_SEC_KEYSIZE, NULL); 817 if ((index <= 3) && !b43_new_kidx_api(dev)) { 818 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 819 NULL, B43_SEC_KEYSIZE, NULL); 820 } 821 dev->key[index].keyconf = NULL; 822 823 return 0; 824} 825 826static void b43_clear_keys(struct b43_wldev *dev) 827{ 828 int i; 829 830 for (i = 0; i < dev->max_nr_keys; i++) 831 b43_key_clear(dev, i); 832} 833 834void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 835{ 836 u32 macctl; 837 u16 ucstat; 838 bool hwps; 839 bool awake; 840 int i; 841 842 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 843 (ps_flags & B43_PS_DISABLED)); 844 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 845 846 if (ps_flags & B43_PS_ENABLED) { 847 hwps = 1; 848 } else if (ps_flags & B43_PS_DISABLED) { 849 hwps = 0; 850 } else { 851 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 852 // and thus is not an AP and we are associated, set bit 25 853 } 854 if (ps_flags & B43_PS_AWAKE) { 855 awake = 1; 856 } else if (ps_flags & B43_PS_ASLEEP) { 857 awake = 0; 858 } else { 859 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 860 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 861 // successful, set bit26 862 } 863 864/* FIXME: For now we force awake-on and hwps-off */ 865 hwps = 0; 866 awake = 1; 867 868 macctl = b43_read32(dev, B43_MMIO_MACCTL); 869 if (hwps) 870 macctl |= B43_MACCTL_HWPS; 871 else 872 macctl &= ~B43_MACCTL_HWPS; 873 if (awake) 874 macctl |= B43_MACCTL_AWAKE; 875 else 876 macctl &= ~B43_MACCTL_AWAKE; 877 b43_write32(dev, B43_MMIO_MACCTL, macctl); 878 /* Commit write */ 879 b43_read32(dev, B43_MMIO_MACCTL); 880 if (awake && dev->dev->id.revision >= 5) { 881 /* Wait for the microcode to wake up. */ 882 for (i = 0; i < 100; i++) { 883 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 884 B43_SHM_SH_UCODESTAT); 885 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 886 break; 887 udelay(10); 888 } 889 } 890} 891 892/* Turn the Analog ON/OFF */ 893static void b43_switch_analog(struct b43_wldev *dev, int on) 894{ 895 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); 896} 897 898void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 899{ 900 u32 tmslow; 901 u32 macctl; 902 903 flags |= B43_TMSLOW_PHYCLKEN; 904 flags |= B43_TMSLOW_PHYRESET; 905 ssb_device_enable(dev->dev, flags); 906 msleep(2); /* Wait for the PLL to turn on. */ 907 908 /* Now take the PHY out of Reset again */ 909 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 910 tmslow |= SSB_TMSLOW_FGC; 911 tmslow &= ~B43_TMSLOW_PHYRESET; 912 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 913 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 914 msleep(1); 915 tmslow &= ~SSB_TMSLOW_FGC; 916 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 917 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 918 msleep(1); 919 920 /* Turn Analog ON */ 921 b43_switch_analog(dev, 1); 922 923 macctl = b43_read32(dev, B43_MMIO_MACCTL); 924 macctl &= ~B43_MACCTL_GMODE; 925 if (flags & B43_TMSLOW_GMODE) 926 macctl |= B43_MACCTL_GMODE; 927 macctl |= B43_MACCTL_IHR_ENABLED; 928 b43_write32(dev, B43_MMIO_MACCTL, macctl); 929} 930 931static void handle_irq_transmit_status(struct b43_wldev *dev) 932{ 933 u32 v0, v1; 934 u16 tmp; 935 struct b43_txstatus stat; 936 937 while (1) { 938 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 939 if (!(v0 & 0x00000001)) 940 break; 941 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 942 943 stat.cookie = (v0 >> 16); 944 stat.seq = (v1 & 0x0000FFFF); 945 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 946 tmp = (v0 & 0x0000FFFF); 947 stat.frame_count = ((tmp & 0xF000) >> 12); 948 stat.rts_count = ((tmp & 0x0F00) >> 8); 949 stat.supp_reason = ((tmp & 0x001C) >> 2); 950 stat.pm_indicated = !!(tmp & 0x0080); 951 stat.intermediate = !!(tmp & 0x0040); 952 stat.for_ampdu = !!(tmp & 0x0020); 953 stat.acked = !!(tmp & 0x0002); 954 955 b43_handle_txstatus(dev, &stat); 956 } 957} 958 959static void drain_txstatus_queue(struct b43_wldev *dev) 960{ 961 u32 dummy; 962 963 if (dev->dev->id.revision < 5) 964 return; 965 /* Read all entries from the microcode TXstatus FIFO 966 * and throw them away. 967 */ 968 while (1) { 969 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 970 if (!(dummy & 0x00000001)) 971 break; 972 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 973 } 974} 975 976static u32 b43_jssi_read(struct b43_wldev *dev) 977{ 978 u32 val = 0; 979 980 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 981 val <<= 16; 982 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 983 984 return val; 985} 986 987static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 988{ 989 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 990 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 991} 992 993static void b43_generate_noise_sample(struct b43_wldev *dev) 994{ 995 b43_jssi_write(dev, 0x7F7F7F7F); 996 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, 997 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD) 998 | (1 << 4)); 999 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel); 1000} 1001 1002static void b43_calculate_link_quality(struct b43_wldev *dev) 1003{ 1004 /* Top half of Link Quality calculation. */ 1005 1006 if (dev->noisecalc.calculation_running) 1007 return; 1008 dev->noisecalc.channel_at_start = dev->phy.channel; 1009 dev->noisecalc.calculation_running = 1; 1010 dev->noisecalc.nr_samples = 0; 1011 1012 b43_generate_noise_sample(dev); 1013} 1014 1015static void handle_irq_noise(struct b43_wldev *dev) 1016{ 1017 struct b43_phy *phy = &dev->phy; 1018 u16 tmp; 1019 u8 noise[4]; 1020 u8 i, j; 1021 s32 average; 1022 1023 /* Bottom half of Link Quality calculation. */ 1024 1025 B43_WARN_ON(!dev->noisecalc.calculation_running); 1026 if (dev->noisecalc.channel_at_start != phy->channel) 1027 goto drop_calculation; 1028 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1029 if (noise[0] == 0x7F || noise[1] == 0x7F || 1030 noise[2] == 0x7F || noise[3] == 0x7F) 1031 goto generate_new; 1032 1033 /* Get the noise samples. */ 1034 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1035 i = dev->noisecalc.nr_samples; 1036 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1037 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1038 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1039 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1040 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1041 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1042 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1043 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1044 dev->noisecalc.nr_samples++; 1045 if (dev->noisecalc.nr_samples == 8) { 1046 /* Calculate the Link Quality by the noise samples. */ 1047 average = 0; 1048 for (i = 0; i < 8; i++) { 1049 for (j = 0; j < 4; j++) 1050 average += dev->noisecalc.samples[i][j]; 1051 } 1052 average /= (8 * 4); 1053 average *= 125; 1054 average += 64; 1055 average /= 128; 1056 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1057 tmp = (tmp / 128) & 0x1F; 1058 if (tmp >= 8) 1059 average += 2; 1060 else 1061 average -= 25; 1062 if (tmp == 8) 1063 average -= 72; 1064 else 1065 average -= 48; 1066 1067 dev->stats.link_noise = average; 1068 drop_calculation: 1069 dev->noisecalc.calculation_running = 0; 1070 return; 1071 } 1072 generate_new: 1073 b43_generate_noise_sample(dev); 1074} 1075 1076static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1077{ 1078 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) { 1079 ///TODO: PS TBTT 1080 } else { 1081 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1082 b43_power_saving_ctl_bits(dev, 0); 1083 } 1084 dev->reg124_set_0x4 = 0; 1085 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) 1086 dev->reg124_set_0x4 = 1; 1087} 1088 1089static void handle_irq_atim_end(struct b43_wldev *dev) 1090{ 1091 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ ) 1092 return; 1093 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, 1094 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD) 1095 | 0x4); 1096} 1097 1098static void handle_irq_pmq(struct b43_wldev *dev) 1099{ 1100 u32 tmp; 1101 1102 //TODO: AP mode. 1103 1104 while (1) { 1105 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1106 if (!(tmp & 0x00000008)) 1107 break; 1108 } 1109 /* 16bit write is odd, but correct. */ 1110 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1111} 1112 1113static void b43_write_template_common(struct b43_wldev *dev, 1114 const u8 * data, u16 size, 1115 u16 ram_offset, 1116 u16 shm_size_offset, u8 rate) 1117{ 1118 u32 i, tmp; 1119 struct b43_plcp_hdr4 plcp; 1120 1121 plcp.data = 0; 1122 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1123 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1124 ram_offset += sizeof(u32); 1125 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1126 * So leave the first two bytes of the next write blank. 1127 */ 1128 tmp = (u32) (data[0]) << 16; 1129 tmp |= (u32) (data[1]) << 24; 1130 b43_ram_write(dev, ram_offset, tmp); 1131 ram_offset += sizeof(u32); 1132 for (i = 2; i < size; i += sizeof(u32)) { 1133 tmp = (u32) (data[i + 0]); 1134 if (i + 1 < size) 1135 tmp |= (u32) (data[i + 1]) << 8; 1136 if (i + 2 < size) 1137 tmp |= (u32) (data[i + 2]) << 16; 1138 if (i + 3 < size) 1139 tmp |= (u32) (data[i + 3]) << 24; 1140 b43_ram_write(dev, ram_offset + i - 2, tmp); 1141 } 1142 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1143 size + sizeof(struct b43_plcp_hdr6)); 1144} 1145 1146static void b43_write_beacon_template(struct b43_wldev *dev, 1147 u16 ram_offset, 1148 u16 shm_size_offset, u8 rate) 1149{ 1150 int len; 1151 const u8 *data; 1152 1153 B43_WARN_ON(!dev->cached_beacon); 1154 len = min((size_t) dev->cached_beacon->len, 1155 0x200 - sizeof(struct b43_plcp_hdr6)); 1156 data = (const u8 *)(dev->cached_beacon->data); 1157 b43_write_template_common(dev, data, 1158 len, ram_offset, shm_size_offset, rate); 1159} 1160 1161static void b43_write_probe_resp_plcp(struct b43_wldev *dev, 1162 u16 shm_offset, u16 size, u8 rate) 1163{ 1164 struct b43_plcp_hdr4 plcp; 1165 u32 tmp; 1166 __le16 dur; 1167 1168 plcp.data = 0; 1169 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1170 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1171 dev->wl->if_id, size, 1172 B43_RATE_TO_BASE100KBPS(rate)); 1173 /* Write PLCP in two parts and timing for packet transfer */ 1174 tmp = le32_to_cpu(plcp.data); 1175 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF); 1176 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16); 1177 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur)); 1178} 1179 1180/* Instead of using custom probe response template, this function 1181 * just patches custom beacon template by: 1182 * 1) Changing packet type 1183 * 2) Patching duration field 1184 * 3) Stripping TIM 1185 */ 1186static u8 *b43_generate_probe_resp(struct b43_wldev *dev, 1187 u16 * dest_size, u8 rate) 1188{ 1189 const u8 *src_data; 1190 u8 *dest_data; 1191 u16 src_size, elem_size, src_pos, dest_pos; 1192 __le16 dur; 1193 struct ieee80211_hdr *hdr; 1194 1195 B43_WARN_ON(!dev->cached_beacon); 1196 src_size = dev->cached_beacon->len; 1197 src_data = (const u8 *)dev->cached_beacon->data; 1198 1199 if (unlikely(src_size < 0x24)) { 1200 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n"); 1201 return NULL; 1202 } 1203 1204 dest_data = kmalloc(src_size, GFP_ATOMIC); 1205 if (unlikely(!dest_data)) 1206 return NULL; 1207 1208 /* 0x24 is offset of first variable-len Information-Element 1209 * in beacon frame. 1210 */ 1211 memcpy(dest_data, src_data, 0x24); 1212 src_pos = dest_pos = 0x24; 1213 for (; src_pos < src_size - 2; src_pos += elem_size) { 1214 elem_size = src_data[src_pos + 1] + 2; 1215 if (src_data[src_pos] != 0x05) { /* TIM */ 1216 memcpy(dest_data + dest_pos, src_data + src_pos, 1217 elem_size); 1218 dest_pos += elem_size; 1219 } 1220 } 1221 *dest_size = dest_pos; 1222 hdr = (struct ieee80211_hdr *)dest_data; 1223 1224 /* Set the frame control. */ 1225 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | 1226 IEEE80211_STYPE_PROBE_RESP); 1227 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1228 dev->wl->if_id, *dest_size, 1229 B43_RATE_TO_BASE100KBPS(rate)); 1230 hdr->duration_id = dur; 1231 1232 return dest_data; 1233} 1234 1235static void b43_write_probe_resp_template(struct b43_wldev *dev, 1236 u16 ram_offset, 1237 u16 shm_size_offset, u8 rate) 1238{ 1239 u8 *probe_resp_data; 1240 u16 size; 1241 1242 B43_WARN_ON(!dev->cached_beacon); 1243 size = dev->cached_beacon->len; 1244 probe_resp_data = b43_generate_probe_resp(dev, &size, rate); 1245 if (unlikely(!probe_resp_data)) 1246 return; 1247 1248 /* Looks like PLCP headers plus packet timings are stored for 1249 * all possible basic rates 1250 */ 1251 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB); 1252 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB); 1253 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB); 1254 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB); 1255 1256 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6)); 1257 b43_write_template_common(dev, probe_resp_data, 1258 size, ram_offset, shm_size_offset, rate); 1259 kfree(probe_resp_data); 1260} 1261 1262static int b43_refresh_cached_beacon(struct b43_wldev *dev, 1263 struct sk_buff *beacon) 1264{ 1265 if (dev->cached_beacon) 1266 kfree_skb(dev->cached_beacon); 1267 dev->cached_beacon = beacon; 1268 1269 return 0; 1270} 1271 1272static void b43_update_templates(struct b43_wldev *dev) 1273{ 1274 u32 status; 1275 1276 B43_WARN_ON(!dev->cached_beacon); 1277 1278 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB); 1279 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB); 1280 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB); 1281 1282 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD); 1283 status |= 0x03; 1284 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1285} 1286 1287static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon) 1288{ 1289 int err; 1290 1291 err = b43_refresh_cached_beacon(dev, beacon); 1292 if (unlikely(err)) 1293 return; 1294 b43_update_templates(dev); 1295} 1296 1297static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len) 1298{ 1299 u32 tmp; 1300 u16 i, len; 1301 1302 len = min((u16) ssid_len, (u16) 0x100); 1303 for (i = 0; i < len; i += sizeof(u32)) { 1304 tmp = (u32) (ssid[i + 0]); 1305 if (i + 1 < len) 1306 tmp |= (u32) (ssid[i + 1]) << 8; 1307 if (i + 2 < len) 1308 tmp |= (u32) (ssid[i + 2]) << 16; 1309 if (i + 3 < len) 1310 tmp |= (u32) (ssid[i + 3]) << 24; 1311 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp); 1312 } 1313 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len); 1314} 1315 1316static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1317{ 1318 b43_time_lock(dev); 1319 if (dev->dev->id.revision >= 3) { 1320 b43_write32(dev, 0x188, (beacon_int << 16)); 1321 } else { 1322 b43_write16(dev, 0x606, (beacon_int >> 6)); 1323 b43_write16(dev, 0x610, beacon_int); 1324 } 1325 b43_time_unlock(dev); 1326} 1327 1328static void handle_irq_beacon(struct b43_wldev *dev) 1329{ 1330 u32 status; 1331 1332 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) 1333 return; 1334 1335 dev->irq_savedstate &= ~B43_IRQ_BEACON; 1336 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD); 1337 1338 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) { 1339 /* ACK beacon IRQ. */ 1340 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1341 dev->irq_savedstate |= B43_IRQ_BEACON; 1342 if (dev->cached_beacon) 1343 kfree_skb(dev->cached_beacon); 1344 dev->cached_beacon = NULL; 1345 return; 1346 } 1347 if (!(status & 0x1)) { 1348 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB); 1349 status |= 0x1; 1350 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1351 } 1352 if (!(status & 0x2)) { 1353 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB); 1354 status |= 0x2; 1355 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1356 } 1357} 1358 1359static void handle_irq_ucode_debug(struct b43_wldev *dev) 1360{ 1361 //TODO 1362} 1363 1364/* Interrupt handler bottom-half */ 1365static void b43_interrupt_tasklet(struct b43_wldev *dev) 1366{ 1367 u32 reason; 1368 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1369 u32 merged_dma_reason = 0; 1370 int i; 1371 unsigned long flags; 1372 1373 spin_lock_irqsave(&dev->wl->irq_lock, flags); 1374 1375 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED); 1376 1377 reason = dev->irq_reason; 1378 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1379 dma_reason[i] = dev->dma_reason[i]; 1380 merged_dma_reason |= dma_reason[i]; 1381 } 1382 1383 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1384 b43err(dev->wl, "MAC transmission error\n"); 1385 1386 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1387 b43err(dev->wl, "PHY transmission error\n"); 1388 rmb(); 1389 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1390 atomic_set(&dev->phy.txerr_cnt, 1391 B43_PHY_TX_BADNESS_LIMIT); 1392 b43err(dev->wl, "Too many PHY TX errors, " 1393 "restarting the controller\n"); 1394 b43_controller_restart(dev, "PHY TX errors"); 1395 } 1396 } 1397 1398 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1399 B43_DMAIRQ_NONFATALMASK))) { 1400 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1401 b43err(dev->wl, "Fatal DMA error: " 1402 "0x%08X, 0x%08X, 0x%08X, " 1403 "0x%08X, 0x%08X, 0x%08X\n", 1404 dma_reason[0], dma_reason[1], 1405 dma_reason[2], dma_reason[3], 1406 dma_reason[4], dma_reason[5]); 1407 b43_controller_restart(dev, "DMA error"); 1408 mmiowb(); 1409 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1410 return; 1411 } 1412 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1413 b43err(dev->wl, "DMA error: " 1414 "0x%08X, 0x%08X, 0x%08X, " 1415 "0x%08X, 0x%08X, 0x%08X\n", 1416 dma_reason[0], dma_reason[1], 1417 dma_reason[2], dma_reason[3], 1418 dma_reason[4], dma_reason[5]); 1419 } 1420 } 1421 1422 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1423 handle_irq_ucode_debug(dev); 1424 if (reason & B43_IRQ_TBTT_INDI) 1425 handle_irq_tbtt_indication(dev); 1426 if (reason & B43_IRQ_ATIM_END) 1427 handle_irq_atim_end(dev); 1428 if (reason & B43_IRQ_BEACON) 1429 handle_irq_beacon(dev); 1430 if (reason & B43_IRQ_PMQ) 1431 handle_irq_pmq(dev); 1432 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1433 ;/* TODO */ 1434 if (reason & B43_IRQ_NOISESAMPLE_OK) 1435 handle_irq_noise(dev); 1436 1437 /* Check the DMA reason registers for received data. */ 1438 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) 1439 b43_dma_rx(dev->dma.rx_ring0); 1440 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) 1441 b43_dma_rx(dev->dma.rx_ring3); 1442 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1443 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1444 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1445 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1446 1447 if (reason & B43_IRQ_TX_OK) 1448 handle_irq_transmit_status(dev); 1449 1450 b43_interrupt_enable(dev, dev->irq_savedstate); 1451 mmiowb(); 1452 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1453} 1454 1455static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason) 1456{ 1457 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1458 1459 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1460 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1461 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1462 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1463 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1464 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1465} 1466 1467/* Interrupt handler top-half */ 1468static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1469{ 1470 irqreturn_t ret = IRQ_NONE; 1471 struct b43_wldev *dev = dev_id; 1472 u32 reason; 1473 1474 if (!dev) 1475 return IRQ_NONE; 1476 1477 spin_lock(&dev->wl->irq_lock); 1478 1479 if (b43_status(dev) < B43_STAT_STARTED) 1480 goto out; 1481 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1482 if (reason == 0xffffffff) /* shared IRQ */ 1483 goto out; 1484 ret = IRQ_HANDLED; 1485 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 1486 if (!reason) 1487 goto out; 1488 1489 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1490 & 0x0001DC00; 1491 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1492 & 0x0000DC00; 1493 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1494 & 0x0000DC00; 1495 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1496 & 0x0001DC00; 1497 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1498 & 0x0000DC00; 1499 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1500 & 0x0000DC00; 1501 1502 b43_interrupt_ack(dev, reason); 1503 /* disable all IRQs. They are enabled again in the bottom half. */ 1504 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 1505 /* save the reason code and call our bottom half. */ 1506 dev->irq_reason = reason; 1507 tasklet_schedule(&dev->isr_tasklet); 1508 out: 1509 mmiowb(); 1510 spin_unlock(&dev->wl->irq_lock); 1511 1512 return ret; 1513} 1514 1515static void b43_release_firmware(struct b43_wldev *dev) 1516{ 1517 release_firmware(dev->fw.ucode); 1518 dev->fw.ucode = NULL; 1519 release_firmware(dev->fw.pcm); 1520 dev->fw.pcm = NULL; 1521 release_firmware(dev->fw.initvals); 1522 dev->fw.initvals = NULL; 1523 release_firmware(dev->fw.initvals_band); 1524 dev->fw.initvals_band = NULL; 1525} 1526 1527static void b43_print_fw_helptext(struct b43_wl *wl) 1528{ 1529 b43err(wl, "You must go to " 1530 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware " 1531 "and download the correct firmware (version 4).\n"); 1532} 1533 1534static int do_request_fw(struct b43_wldev *dev, 1535 const char *name, 1536 const struct firmware **fw) 1537{ 1538 char path[sizeof(modparam_fwpostfix) + 32]; 1539 struct b43_fw_header *hdr; 1540 u32 size; 1541 int err; 1542 1543 if (!name) 1544 return 0; 1545 1546 snprintf(path, ARRAY_SIZE(path), 1547 "b43%s/%s.fw", 1548 modparam_fwpostfix, name); 1549 err = request_firmware(fw, path, dev->dev->dev); 1550 if (err) { 1551 b43err(dev->wl, "Firmware file \"%s\" not found " 1552 "or load failed.\n", path); 1553 return err; 1554 } 1555 if ((*fw)->size < sizeof(struct b43_fw_header)) 1556 goto err_format; 1557 hdr = (struct b43_fw_header *)((*fw)->data); 1558 switch (hdr->type) { 1559 case B43_FW_TYPE_UCODE: 1560 case B43_FW_TYPE_PCM: 1561 size = be32_to_cpu(hdr->size); 1562 if (size != (*fw)->size - sizeof(struct b43_fw_header)) 1563 goto err_format; 1564 /* fallthrough */ 1565 case B43_FW_TYPE_IV: 1566 if (hdr->ver != 1) 1567 goto err_format; 1568 break; 1569 default: 1570 goto err_format; 1571 } 1572 1573 return err; 1574 1575err_format: 1576 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path); 1577 return -EPROTO; 1578} 1579 1580static int b43_request_firmware(struct b43_wldev *dev) 1581{ 1582 struct b43_firmware *fw = &dev->fw; 1583 const u8 rev = dev->dev->id.revision; 1584 const char *filename; 1585 u32 tmshigh; 1586 int err; 1587 1588 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 1589 if (!fw->ucode) { 1590 if ((rev >= 5) && (rev <= 10)) 1591 filename = "ucode5"; 1592 else if ((rev >= 11) && (rev <= 12)) 1593 filename = "ucode11"; 1594 else if (rev >= 13) 1595 filename = "ucode13"; 1596 else 1597 goto err_no_ucode; 1598 err = do_request_fw(dev, filename, &fw->ucode); 1599 if (err) 1600 goto err_load; 1601 } 1602 if (!fw->pcm) { 1603 if ((rev >= 5) && (rev <= 10)) 1604 filename = "pcm5"; 1605 else if (rev >= 11) 1606 filename = NULL; 1607 else 1608 goto err_no_pcm; 1609 err = do_request_fw(dev, filename, &fw->pcm); 1610 if (err) 1611 goto err_load; 1612 } 1613 if (!fw->initvals) { 1614 switch (dev->phy.type) { 1615 case B43_PHYTYPE_A: 1616 if ((rev >= 5) && (rev <= 10)) { 1617 if (tmshigh & B43_TMSHIGH_GPHY) 1618 filename = "a0g1initvals5"; 1619 else 1620 filename = "a0g0initvals5"; 1621 } else 1622 goto err_no_initvals; 1623 break; 1624 case B43_PHYTYPE_G: 1625 if ((rev >= 5) && (rev <= 10)) 1626 filename = "b0g0initvals5"; 1627 else if (rev >= 13) 1628 filename = "lp0initvals13"; 1629 else 1630 goto err_no_initvals; 1631 break; 1632 default: 1633 goto err_no_initvals; 1634 } 1635 err = do_request_fw(dev, filename, &fw->initvals); 1636 if (err) 1637 goto err_load; 1638 } 1639 if (!fw->initvals_band) { 1640 switch (dev->phy.type) { 1641 case B43_PHYTYPE_A: 1642 if ((rev >= 5) && (rev <= 10)) { 1643 if (tmshigh & B43_TMSHIGH_GPHY) 1644 filename = "a0g1bsinitvals5"; 1645 else 1646 filename = "a0g0bsinitvals5"; 1647 } else if (rev >= 11) 1648 filename = NULL; 1649 else 1650 goto err_no_initvals; 1651 break; 1652 case B43_PHYTYPE_G: 1653 if ((rev >= 5) && (rev <= 10)) 1654 filename = "b0g0bsinitvals5"; 1655 else if (rev >= 11) 1656 filename = NULL; 1657 else 1658 goto err_no_initvals; 1659 break; 1660 default: 1661 goto err_no_initvals; 1662 } 1663 err = do_request_fw(dev, filename, &fw->initvals_band); 1664 if (err) 1665 goto err_load; 1666 } 1667 1668 return 0; 1669 1670err_load: 1671 b43_print_fw_helptext(dev->wl); 1672 goto error; 1673 1674err_no_ucode: 1675 err = -ENODEV; 1676 b43err(dev->wl, "No microcode available for core rev %u\n", rev); 1677 goto error; 1678 1679err_no_pcm: 1680 err = -ENODEV; 1681 b43err(dev->wl, "No PCM available for core rev %u\n", rev); 1682 goto error; 1683 1684err_no_initvals: 1685 err = -ENODEV; 1686 b43err(dev->wl, "No Initial Values firmware file for PHY %u, " 1687 "core rev %u\n", dev->phy.type, rev); 1688 goto error; 1689 1690error: 1691 b43_release_firmware(dev); 1692 return err; 1693} 1694 1695static int b43_upload_microcode(struct b43_wldev *dev) 1696{ 1697 const size_t hdr_len = sizeof(struct b43_fw_header); 1698 const __be32 *data; 1699 unsigned int i, len; 1700 u16 fwrev, fwpatch, fwdate, fwtime; 1701 u32 tmp; 1702 int err = 0; 1703 1704 /* Upload Microcode. */ 1705 data = (__be32 *) (dev->fw.ucode->data + hdr_len); 1706 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32); 1707 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 1708 for (i = 0; i < len; i++) { 1709 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1710 udelay(10); 1711 } 1712 1713 if (dev->fw.pcm) { 1714 /* Upload PCM data. */ 1715 data = (__be32 *) (dev->fw.pcm->data + hdr_len); 1716 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32); 1717 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 1718 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 1719 /* No need for autoinc bit in SHM_HW */ 1720 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 1721 for (i = 0; i < len; i++) { 1722 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1723 udelay(10); 1724 } 1725 } 1726 1727 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 1728 b43_write32(dev, B43_MMIO_MACCTL, 1729 B43_MACCTL_PSM_RUN | 1730 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA); 1731 1732 /* Wait for the microcode to load and respond */ 1733 i = 0; 1734 while (1) { 1735 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1736 if (tmp == B43_IRQ_MAC_SUSPENDED) 1737 break; 1738 i++; 1739 if (i >= 50) { 1740 b43err(dev->wl, "Microcode not responding\n"); 1741 b43_print_fw_helptext(dev->wl); 1742 err = -ENODEV; 1743 goto out; 1744 } 1745 udelay(10); 1746 } 1747 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 1748 1749 /* Get and check the revisions. */ 1750 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 1751 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 1752 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 1753 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 1754 1755 if (fwrev <= 0x128) { 1756 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 1757 "binary drivers older than version 4.x is unsupported. " 1758 "You must upgrade your firmware files.\n"); 1759 b43_print_fw_helptext(dev->wl); 1760 b43_write32(dev, B43_MMIO_MACCTL, 0); 1761 err = -EOPNOTSUPP; 1762 goto out; 1763 } 1764 b43dbg(dev->wl, "Loading firmware version %u.%u " 1765 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 1766 fwrev, fwpatch, 1767 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 1768 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 1769 1770 dev->fw.rev = fwrev; 1771 dev->fw.patch = fwpatch; 1772 1773 out: 1774 return err; 1775} 1776 1777static int b43_write_initvals(struct b43_wldev *dev, 1778 const struct b43_iv *ivals, 1779 size_t count, 1780 size_t array_size) 1781{ 1782 const struct b43_iv *iv; 1783 u16 offset; 1784 size_t i; 1785 bool bit32; 1786 1787 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 1788 iv = ivals; 1789 for (i = 0; i < count; i++) { 1790 if (array_size < sizeof(iv->offset_size)) 1791 goto err_format; 1792 array_size -= sizeof(iv->offset_size); 1793 offset = be16_to_cpu(iv->offset_size); 1794 bit32 = !!(offset & B43_IV_32BIT); 1795 offset &= B43_IV_OFFSET_MASK; 1796 if (offset >= 0x1000) 1797 goto err_format; 1798 if (bit32) { 1799 u32 value; 1800 1801 if (array_size < sizeof(iv->data.d32)) 1802 goto err_format; 1803 array_size -= sizeof(iv->data.d32); 1804 1805 value = be32_to_cpu(get_unaligned(&iv->data.d32)); 1806 b43_write32(dev, offset, value); 1807 1808 iv = (const struct b43_iv *)((const uint8_t *)iv + 1809 sizeof(__be16) + 1810 sizeof(__be32)); 1811 } else { 1812 u16 value; 1813 1814 if (array_size < sizeof(iv->data.d16)) 1815 goto err_format; 1816 array_size -= sizeof(iv->data.d16); 1817 1818 value = be16_to_cpu(iv->data.d16); 1819 b43_write16(dev, offset, value); 1820 1821 iv = (const struct b43_iv *)((const uint8_t *)iv + 1822 sizeof(__be16) + 1823 sizeof(__be16)); 1824 } 1825 } 1826 if (array_size) 1827 goto err_format; 1828 1829 return 0; 1830 1831err_format: 1832 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 1833 b43_print_fw_helptext(dev->wl); 1834 1835 return -EPROTO; 1836} 1837 1838static int b43_upload_initvals(struct b43_wldev *dev) 1839{ 1840 const size_t hdr_len = sizeof(struct b43_fw_header); 1841 const struct b43_fw_header *hdr; 1842 struct b43_firmware *fw = &dev->fw; 1843 const struct b43_iv *ivals; 1844 size_t count; 1845 int err; 1846 1847 hdr = (const struct b43_fw_header *)(fw->initvals->data); 1848 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len); 1849 count = be32_to_cpu(hdr->size); 1850 err = b43_write_initvals(dev, ivals, count, 1851 fw->initvals->size - hdr_len); 1852 if (err) 1853 goto out; 1854 if (fw->initvals_band) { 1855 hdr = (const struct b43_fw_header *)(fw->initvals_band->data); 1856 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len); 1857 count = be32_to_cpu(hdr->size); 1858 err = b43_write_initvals(dev, ivals, count, 1859 fw->initvals_band->size - hdr_len); 1860 if (err) 1861 goto out; 1862 } 1863out: 1864 1865 return err; 1866} 1867 1868/* Initialize the GPIOs 1869 * http://bcm-specs.sipsolutions.net/GPIO 1870 */ 1871static int b43_gpio_init(struct b43_wldev *dev) 1872{ 1873 struct ssb_bus *bus = dev->dev->bus; 1874 struct ssb_device *gpiodev, *pcidev = NULL; 1875 u32 mask, set; 1876 1877 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 1878 & ~B43_MACCTL_GPOUTSMSK); 1879 1880 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 1881 | 0x000F); 1882 1883 mask = 0x0000001F; 1884 set = 0x0000000F; 1885 if (dev->dev->bus->chip_id == 0x4301) { 1886 mask |= 0x0060; 1887 set |= 0x0060; 1888 } 1889 if (0 /* FIXME: conditional unknown */ ) { 1890 b43_write16(dev, B43_MMIO_GPIO_MASK, 1891 b43_read16(dev, B43_MMIO_GPIO_MASK) 1892 | 0x0100); 1893 mask |= 0x0180; 1894 set |= 0x0180; 1895 } 1896 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) { 1897 b43_write16(dev, B43_MMIO_GPIO_MASK, 1898 b43_read16(dev, B43_MMIO_GPIO_MASK) 1899 | 0x0200); 1900 mask |= 0x0200; 1901 set |= 0x0200; 1902 } 1903 if (dev->dev->id.revision >= 2) 1904 mask |= 0x0010; /* FIXME: This is redundant. */ 1905 1906#ifdef CONFIG_SSB_DRIVER_PCICORE 1907 pcidev = bus->pcicore.dev; 1908#endif 1909 gpiodev = bus->chipco.dev ? : pcidev; 1910 if (!gpiodev) 1911 return 0; 1912 ssb_write32(gpiodev, B43_GPIO_CONTROL, 1913 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 1914 & mask) | set); 1915 1916 return 0; 1917} 1918 1919/* Turn off all GPIO stuff. Call this on module unload, for example. */ 1920static void b43_gpio_cleanup(struct b43_wldev *dev) 1921{ 1922 struct ssb_bus *bus = dev->dev->bus; 1923 struct ssb_device *gpiodev, *pcidev = NULL; 1924 1925#ifdef CONFIG_SSB_DRIVER_PCICORE 1926 pcidev = bus->pcicore.dev; 1927#endif 1928 gpiodev = bus->chipco.dev ? : pcidev; 1929 if (!gpiodev) 1930 return; 1931 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 1932} 1933 1934/* http://bcm-specs.sipsolutions.net/EnableMac */ 1935void b43_mac_enable(struct b43_wldev *dev) 1936{ 1937 dev->mac_suspended--; 1938 B43_WARN_ON(dev->mac_suspended < 0); 1939 B43_WARN_ON(irqs_disabled()); 1940 if (dev->mac_suspended == 0) { 1941 b43_write32(dev, B43_MMIO_MACCTL, 1942 b43_read32(dev, B43_MMIO_MACCTL) 1943 | B43_MACCTL_ENABLED); 1944 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 1945 B43_IRQ_MAC_SUSPENDED); 1946 /* Commit writes */ 1947 b43_read32(dev, B43_MMIO_MACCTL); 1948 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1949 b43_power_saving_ctl_bits(dev, 0); 1950 1951 /* Re-enable IRQs. */ 1952 spin_lock_irq(&dev->wl->irq_lock); 1953 b43_interrupt_enable(dev, dev->irq_savedstate); 1954 spin_unlock_irq(&dev->wl->irq_lock); 1955 } 1956} 1957 1958/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 1959void b43_mac_suspend(struct b43_wldev *dev) 1960{ 1961 int i; 1962 u32 tmp; 1963 1964 might_sleep(); 1965 B43_WARN_ON(irqs_disabled()); 1966 B43_WARN_ON(dev->mac_suspended < 0); 1967 1968 if (dev->mac_suspended == 0) { 1969 /* Mask IRQs before suspending MAC. Otherwise 1970 * the MAC stays busy and won't suspend. */ 1971 spin_lock_irq(&dev->wl->irq_lock); 1972 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL); 1973 spin_unlock_irq(&dev->wl->irq_lock); 1974 b43_synchronize_irq(dev); 1975 dev->irq_savedstate = tmp; 1976 1977 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 1978 b43_write32(dev, B43_MMIO_MACCTL, 1979 b43_read32(dev, B43_MMIO_MACCTL) 1980 & ~B43_MACCTL_ENABLED); 1981 /* force pci to flush the write */ 1982 b43_read32(dev, B43_MMIO_MACCTL); 1983 for (i = 40; i; i--) { 1984 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1985 if (tmp & B43_IRQ_MAC_SUSPENDED) 1986 goto out; 1987 msleep(1); 1988 } 1989 b43err(dev->wl, "MAC suspend failed\n"); 1990 } 1991out: 1992 dev->mac_suspended++; 1993} 1994 1995static void b43_adjust_opmode(struct b43_wldev *dev) 1996{ 1997 struct b43_wl *wl = dev->wl; 1998 u32 ctl; 1999 u16 cfp_pretbtt; 2000 2001 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2002 /* Reset status to STA infrastructure mode. */ 2003 ctl &= ~B43_MACCTL_AP; 2004 ctl &= ~B43_MACCTL_KEEP_CTL; 2005 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2006 ctl &= ~B43_MACCTL_KEEP_BAD; 2007 ctl &= ~B43_MACCTL_PROMISC; 2008 ctl &= ~B43_MACCTL_BEACPROMISC; 2009 ctl |= B43_MACCTL_INFRA; 2010 2011 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2012 ctl |= B43_MACCTL_AP; 2013 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) 2014 ctl &= ~B43_MACCTL_INFRA; 2015 2016 if (wl->filter_flags & FIF_CONTROL) 2017 ctl |= B43_MACCTL_KEEP_CTL; 2018 if (wl->filter_flags & FIF_FCSFAIL) 2019 ctl |= B43_MACCTL_KEEP_BAD; 2020 if (wl->filter_flags & FIF_PLCPFAIL) 2021 ctl |= B43_MACCTL_KEEP_BADPLCP; 2022 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2023 ctl |= B43_MACCTL_PROMISC; 2024 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2025 ctl |= B43_MACCTL_BEACPROMISC; 2026 2027 /* Workaround: On old hardware the HW-MAC-address-filter 2028 * doesn't work properly, so always run promisc in filter 2029 * it in software. */ 2030 if (dev->dev->id.revision <= 4) 2031 ctl |= B43_MACCTL_PROMISC; 2032 2033 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2034 2035 cfp_pretbtt = 2; 2036 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2037 if (dev->dev->bus->chip_id == 0x4306 && 2038 dev->dev->bus->chip_rev == 3) 2039 cfp_pretbtt = 100; 2040 else 2041 cfp_pretbtt = 50; 2042 } 2043 b43_write16(dev, 0x612, cfp_pretbtt); 2044} 2045 2046static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2047{ 2048 u16 offset; 2049 2050 if (is_ofdm) { 2051 offset = 0x480; 2052 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2053 } else { 2054 offset = 0x4C0; 2055 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2056 } 2057 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2058 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2059} 2060 2061static void b43_rate_memory_init(struct b43_wldev *dev) 2062{ 2063 switch (dev->phy.type) { 2064 case B43_PHYTYPE_A: 2065 case B43_PHYTYPE_G: 2066 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2067 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2068 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2069 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2070 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2071 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2072 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2073 if (dev->phy.type == B43_PHYTYPE_A) 2074 break; 2075 /* fallthrough */ 2076 case B43_PHYTYPE_B: 2077 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2078 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2079 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2080 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2081 break; 2082 default: 2083 B43_WARN_ON(1); 2084 } 2085} 2086 2087/* Set the TX-Antenna for management frames sent by firmware. */ 2088static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2089{ 2090 u16 ant = 0; 2091 u16 tmp; 2092 2093 switch (antenna) { 2094 case B43_ANTENNA0: 2095 ant |= B43_TX4_PHY_ANT0; 2096 break; 2097 case B43_ANTENNA1: 2098 ant |= B43_TX4_PHY_ANT1; 2099 break; 2100 case B43_ANTENNA_AUTO: 2101 ant |= B43_TX4_PHY_ANTLAST; 2102 break; 2103 default: 2104 B43_WARN_ON(1); 2105 } 2106 2107 /* FIXME We also need to set the other flags of the PHY control field somewhere. */ 2108 2109 /* For Beacons */ 2110 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 2111 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2112 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp); 2113 /* For ACK/CTS */ 2114 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2115 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2116 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2117 /* For Probe Resposes */ 2118 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2119 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2120 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2121} 2122 2123/* This is the opposite of b43_chip_init() */ 2124static void b43_chip_exit(struct b43_wldev *dev) 2125{ 2126 b43_radio_turn_off(dev, 1); 2127 b43_gpio_cleanup(dev); 2128 /* firmware is released later */ 2129} 2130 2131/* Initialize the chip 2132 * http://bcm-specs.sipsolutions.net/ChipInit 2133 */ 2134static int b43_chip_init(struct b43_wldev *dev) 2135{ 2136 struct b43_phy *phy = &dev->phy; 2137 int err, tmp; 2138 u32 value32; 2139 u16 value16; 2140 2141 b43_write32(dev, B43_MMIO_MACCTL, 2142 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED); 2143 2144 err = b43_request_firmware(dev); 2145 if (err) 2146 goto out; 2147 err = b43_upload_microcode(dev); 2148 if (err) 2149 goto out; /* firmware is released later */ 2150 2151 err = b43_gpio_init(dev); 2152 if (err) 2153 goto out; /* firmware is released later */ 2154 2155 err = b43_upload_initvals(dev); 2156 if (err) 2157 goto err_gpio_clean; 2158 b43_radio_turn_on(dev); 2159 2160 b43_write16(dev, 0x03E6, 0x0000); 2161 err = b43_phy_init(dev); 2162 if (err) 2163 goto err_radio_off; 2164 2165 /* Select initial Interference Mitigation. */ 2166 tmp = phy->interfmode; 2167 phy->interfmode = B43_INTERFMODE_NONE; 2168 b43_radio_set_interference_mitigation(dev, tmp); 2169 2170 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2171 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2172 2173 if (phy->type == B43_PHYTYPE_B) { 2174 value16 = b43_read16(dev, 0x005E); 2175 value16 |= 0x0004; 2176 b43_write16(dev, 0x005E, value16); 2177 } 2178 b43_write32(dev, 0x0100, 0x01000000); 2179 if (dev->dev->id.revision < 5) 2180 b43_write32(dev, 0x010C, 0x01000000); 2181 2182 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2183 & ~B43_MACCTL_INFRA); 2184 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2185 | B43_MACCTL_INFRA); 2186 2187 /* Probe Response Timeout value */ 2188 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2189 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2190 2191 /* Initially set the wireless operation mode. */ 2192 b43_adjust_opmode(dev); 2193 2194 if (dev->dev->id.revision < 3) { 2195 b43_write16(dev, 0x060E, 0x0000); 2196 b43_write16(dev, 0x0610, 0x8000); 2197 b43_write16(dev, 0x0604, 0x0000); 2198 b43_write16(dev, 0x0606, 0x0200); 2199 } else { 2200 b43_write32(dev, 0x0188, 0x80000000); 2201 b43_write32(dev, 0x018C, 0x02000000); 2202 } 2203 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2204 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2205 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2206 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2207 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2208 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2209 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2210 2211 value32 = ssb_read32(dev->dev, SSB_TMSLOW); 2212 value32 |= 0x00100000; 2213 ssb_write32(dev->dev, SSB_TMSLOW, value32); 2214 2215 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2216 dev->dev->bus->chipco.fast_pwrup_delay); 2217 2218 err = 0; 2219 b43dbg(dev->wl, "Chip initialized\n"); 2220out: 2221 return err; 2222 2223err_radio_off: 2224 b43_radio_turn_off(dev, 1); 2225err_gpio_clean: 2226 b43_gpio_cleanup(dev); 2227 return err; 2228} 2229 2230static void b43_periodic_every120sec(struct b43_wldev *dev) 2231{ 2232 struct b43_phy *phy = &dev->phy; 2233 2234 if (phy->type != B43_PHYTYPE_G || phy->rev < 2) 2235 return; 2236 2237 b43_mac_suspend(dev); 2238 b43_lo_g_measure(dev); 2239 b43_mac_enable(dev); 2240 if (b43_has_hardware_pctl(phy)) 2241 b43_lo_g_ctl_mark_all_unused(dev); 2242} 2243 2244static void b43_periodic_every60sec(struct b43_wldev *dev) 2245{ 2246 struct b43_phy *phy = &dev->phy; 2247 2248 if (!b43_has_hardware_pctl(phy)) 2249 b43_lo_g_ctl_mark_all_unused(dev); 2250 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) { 2251 b43_mac_suspend(dev); 2252 b43_calc_nrssi_slope(dev); 2253 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { 2254 u8 old_chan = phy->channel; 2255 2256 /* VCO Calibration */ 2257 if (old_chan >= 8) 2258 b43_radio_selectchannel(dev, 1, 0); 2259 else 2260 b43_radio_selectchannel(dev, 13, 0); 2261 b43_radio_selectchannel(dev, old_chan, 0); 2262 } 2263 b43_mac_enable(dev); 2264 } 2265} 2266 2267static void b43_periodic_every30sec(struct b43_wldev *dev) 2268{ 2269 /* Update device statistics. */ 2270 b43_calculate_link_quality(dev); 2271} 2272 2273static void b43_periodic_every15sec(struct b43_wldev *dev) 2274{ 2275 struct b43_phy *phy = &dev->phy; 2276 2277 if (phy->type == B43_PHYTYPE_G) { 2278 //TODO: update_aci_moving_average 2279 if (phy->aci_enable && phy->aci_wlan_automatic) { 2280 b43_mac_suspend(dev); 2281 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) { 2282 if (0 /*TODO: bunch of conditions */ ) { 2283 b43_radio_set_interference_mitigation 2284 (dev, B43_INTERFMODE_MANUALWLAN); 2285 } 2286 } else if (1 /*TODO*/) { 2287 /* 2288 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) { 2289 b43_radio_set_interference_mitigation(dev, 2290 B43_INTERFMODE_NONE); 2291 } 2292 */ 2293 } 2294 b43_mac_enable(dev); 2295 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN && 2296 phy->rev == 1) { 2297 //TODO: implement rev1 workaround 2298 } 2299 } 2300 b43_phy_xmitpower(dev); //FIXME: unless scanning? 2301 //TODO for APHY (temperature?) 2302 2303 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 2304 wmb(); 2305} 2306 2307static void do_periodic_work(struct b43_wldev *dev) 2308{ 2309 unsigned int state; 2310 2311 state = dev->periodic_state; 2312 if (state % 8 == 0) 2313 b43_periodic_every120sec(dev); 2314 if (state % 4 == 0) 2315 b43_periodic_every60sec(dev); 2316 if (state % 2 == 0) 2317 b43_periodic_every30sec(dev); 2318 b43_periodic_every15sec(dev); 2319} 2320 2321/* Periodic work locking policy: 2322 * The whole periodic work handler is protected by 2323 * wl->mutex. If another lock is needed somewhere in the 2324 * pwork callchain, it's aquired in-place, where it's needed. 2325 */ 2326static void b43_periodic_work_handler(struct work_struct *work) 2327{ 2328 struct b43_wldev *dev = container_of(work, struct b43_wldev, 2329 periodic_work.work); 2330 struct b43_wl *wl = dev->wl; 2331 unsigned long delay; 2332 2333 mutex_lock(&wl->mutex); 2334 2335 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 2336 goto out; 2337 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 2338 goto out_requeue; 2339 2340 do_periodic_work(dev); 2341 2342 dev->periodic_state++; 2343out_requeue: 2344 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 2345 delay = msecs_to_jiffies(50); 2346 else 2347 delay = round_jiffies_relative(HZ * 15); 2348 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay); 2349out: 2350 mutex_unlock(&wl->mutex); 2351} 2352 2353static void b43_periodic_tasks_setup(struct b43_wldev *dev) 2354{ 2355 struct delayed_work *work = &dev->periodic_work; 2356 2357 dev->periodic_state = 0; 2358 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 2359 queue_delayed_work(dev->wl->hw->workqueue, work, 0); 2360} 2361 2362/* Check if communication with the device works correctly. */ 2363static int b43_validate_chipaccess(struct b43_wldev *dev) 2364{ 2365 u32 v, backup; 2366 2367 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0); 2368 2369 /* Check for read/write and endianness problems. */ 2370 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 2371 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 2372 goto error; 2373 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 2374 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 2375 goto error; 2376 2377 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup); 2378 2379 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) { 2380 /* The 32bit register shadows the two 16bit registers 2381 * with update sideeffects. Validate this. */ 2382 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 2383 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 2384 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 2385 goto error; 2386 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 2387 goto error; 2388 } 2389 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 2390 2391 v = b43_read32(dev, B43_MMIO_MACCTL); 2392 v |= B43_MACCTL_GMODE; 2393 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 2394 goto error; 2395 2396 return 0; 2397error: 2398 b43err(dev->wl, "Failed to validate the chipaccess\n"); 2399 return -ENODEV; 2400} 2401 2402static void b43_security_init(struct b43_wldev *dev) 2403{ 2404 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20; 2405 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key)); 2406 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 2407 /* KTP is a word address, but we address SHM bytewise. 2408 * So multiply by two. 2409 */ 2410 dev->ktp *= 2; 2411 if (dev->dev->id.revision >= 5) { 2412 /* Number of RCMTA address slots */ 2413 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8); 2414 } 2415 b43_clear_keys(dev); 2416} 2417 2418static int b43_rng_read(struct hwrng *rng, u32 * data) 2419{ 2420 struct b43_wl *wl = (struct b43_wl *)rng->priv; 2421 unsigned long flags; 2422 2423 /* Don't take wl->mutex here, as it could deadlock with 2424 * hwrng internal locking. It's not needed to take 2425 * wl->mutex here, anyway. */ 2426 2427 spin_lock_irqsave(&wl->irq_lock, flags); 2428 *data = b43_read16(wl->current_dev, B43_MMIO_RNG); 2429 spin_unlock_irqrestore(&wl->irq_lock, flags); 2430 2431 return (sizeof(u16)); 2432} 2433 2434static void b43_rng_exit(struct b43_wl *wl) 2435{ 2436 if (wl->rng_initialized) 2437 hwrng_unregister(&wl->rng); 2438} 2439 2440static int b43_rng_init(struct b43_wl *wl) 2441{ 2442 int err; 2443 2444 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 2445 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 2446 wl->rng.name = wl->rng_name; 2447 wl->rng.data_read = b43_rng_read; 2448 wl->rng.priv = (unsigned long)wl; 2449 wl->rng_initialized = 1; 2450 err = hwrng_register(&wl->rng); 2451 if (err) { 2452 wl->rng_initialized = 0; 2453 b43err(wl, "Failed to register the random " 2454 "number generator (%d)\n", err); 2455 } 2456 2457 return err; 2458} 2459 2460static int b43_op_tx(struct ieee80211_hw *hw, 2461 struct sk_buff *skb, 2462 struct ieee80211_tx_control *ctl) 2463{ 2464 struct b43_wl *wl = hw_to_b43_wl(hw); 2465 struct b43_wldev *dev = wl->current_dev; 2466 int err = -ENODEV; 2467 2468 if (unlikely(!dev)) 2469 goto out; 2470 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2471 goto out; 2472 /* DMA-TX is done without a global lock. */ 2473 err = b43_dma_tx(dev, skb, ctl); 2474out: 2475 if (unlikely(err)) 2476 return NETDEV_TX_BUSY; 2477 return NETDEV_TX_OK; 2478} 2479 2480static int b43_op_conf_tx(struct ieee80211_hw *hw, 2481 int queue, 2482 const struct ieee80211_tx_queue_params *params) 2483{ 2484 return 0; 2485} 2486 2487static int b43_op_get_tx_stats(struct ieee80211_hw *hw, 2488 struct ieee80211_tx_queue_stats *stats) 2489{ 2490 struct b43_wl *wl = hw_to_b43_wl(hw); 2491 struct b43_wldev *dev = wl->current_dev; 2492 unsigned long flags; 2493 int err = -ENODEV; 2494 2495 if (!dev) 2496 goto out; 2497 spin_lock_irqsave(&wl->irq_lock, flags); 2498 if (likely(b43_status(dev) >= B43_STAT_STARTED)) { 2499 b43_dma_get_tx_stats(dev, stats); 2500 err = 0; 2501 } 2502 spin_unlock_irqrestore(&wl->irq_lock, flags); 2503out: 2504 return err; 2505} 2506 2507static int b43_op_get_stats(struct ieee80211_hw *hw, 2508 struct ieee80211_low_level_stats *stats) 2509{ 2510 struct b43_wl *wl = hw_to_b43_wl(hw); 2511 unsigned long flags; 2512 2513 spin_lock_irqsave(&wl->irq_lock, flags); 2514 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 2515 spin_unlock_irqrestore(&wl->irq_lock, flags); 2516 2517 return 0; 2518} 2519 2520static const char *phymode_to_string(unsigned int phymode) 2521{ 2522 switch (phymode) { 2523 case B43_PHYMODE_A: 2524 return "A"; 2525 case B43_PHYMODE_B: 2526 return "B"; 2527 case B43_PHYMODE_G: 2528 return "G"; 2529 default: 2530 B43_WARN_ON(1); 2531 } 2532 return ""; 2533} 2534 2535static int find_wldev_for_phymode(struct b43_wl *wl, 2536 unsigned int phymode, 2537 struct b43_wldev **dev, bool * gmode) 2538{ 2539 struct b43_wldev *d; 2540 2541 list_for_each_entry(d, &wl->devlist, list) { 2542 if (d->phy.possible_phymodes & phymode) { 2543 /* Ok, this device supports the PHY-mode. 2544 * Now figure out how the gmode bit has to be 2545 * set to support it. */ 2546 if (phymode == B43_PHYMODE_A) 2547 *gmode = 0; 2548 else 2549 *gmode = 1; 2550 *dev = d; 2551 2552 return 0; 2553 } 2554 } 2555 2556 return -ESRCH; 2557} 2558 2559static void b43_put_phy_into_reset(struct b43_wldev *dev) 2560{ 2561 struct ssb_device *sdev = dev->dev; 2562 u32 tmslow; 2563 2564 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2565 tmslow &= ~B43_TMSLOW_GMODE; 2566 tmslow |= B43_TMSLOW_PHYRESET; 2567 tmslow |= SSB_TMSLOW_FGC; 2568 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2569 msleep(1); 2570 2571 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2572 tmslow &= ~SSB_TMSLOW_FGC; 2573 tmslow |= B43_TMSLOW_PHYRESET; 2574 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2575 msleep(1); 2576} 2577 2578/* Expects wl->mutex locked */ 2579static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode) 2580{ 2581 struct b43_wldev *up_dev; 2582 struct b43_wldev *down_dev; 2583 int err; 2584 bool gmode = 0; 2585 int prev_status; 2586 2587 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode); 2588 if (err) { 2589 b43err(wl, "Could not find a device for %s-PHY mode\n", 2590 phymode_to_string(new_mode)); 2591 return err; 2592 } 2593 if ((up_dev == wl->current_dev) && 2594 (!!wl->current_dev->phy.gmode == !!gmode)) { 2595 /* This device is already running. */ 2596 return 0; 2597 } 2598 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n", 2599 phymode_to_string(new_mode)); 2600 down_dev = wl->current_dev; 2601 2602 prev_status = b43_status(down_dev); 2603 /* Shutdown the currently running core. */ 2604 if (prev_status >= B43_STAT_STARTED) 2605 b43_wireless_core_stop(down_dev); 2606 if (prev_status >= B43_STAT_INITIALIZED) 2607 b43_wireless_core_exit(down_dev); 2608 2609 if (down_dev != up_dev) { 2610 /* We switch to a different core, so we put PHY into 2611 * RESET on the old core. */ 2612 b43_put_phy_into_reset(down_dev); 2613 } 2614 2615 /* Now start the new core. */ 2616 up_dev->phy.gmode = gmode; 2617 if (prev_status >= B43_STAT_INITIALIZED) { 2618 err = b43_wireless_core_init(up_dev); 2619 if (err) { 2620 b43err(wl, "Fatal: Could not initialize device for " 2621 "newly selected %s-PHY mode\n", 2622 phymode_to_string(new_mode)); 2623 goto init_failure; 2624 } 2625 } 2626 if (prev_status >= B43_STAT_STARTED) { 2627 err = b43_wireless_core_start(up_dev); 2628 if (err) { 2629 b43err(wl, "Fatal: Coult not start device for " 2630 "newly selected %s-PHY mode\n", 2631 phymode_to_string(new_mode)); 2632 b43_wireless_core_exit(up_dev); 2633 goto init_failure; 2634 } 2635 } 2636 B43_WARN_ON(b43_status(up_dev) != prev_status); 2637 2638 wl->current_dev = up_dev; 2639 2640 return 0; 2641 init_failure: 2642 /* Whoops, failed to init the new core. No core is operating now. */ 2643 wl->current_dev = NULL; 2644 return err; 2645} 2646 2647/* Check if the use of the antenna that ieee80211 told us to 2648 * use is possible. This will fall back to DEFAULT. 2649 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 2650u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 2651 u8 antenna_nr) 2652{ 2653 u8 antenna_mask; 2654 2655 if (antenna_nr == 0) { 2656 /* Zero means "use default antenna". That's always OK. */ 2657 return 0; 2658 } 2659 2660 /* Get the mask of available antennas. */ 2661 if (dev->phy.gmode) 2662 antenna_mask = dev->dev->bus->sprom.ant_available_bg; 2663 else 2664 antenna_mask = dev->dev->bus->sprom.ant_available_a; 2665 2666 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 2667 /* This antenna is not available. Fall back to default. */ 2668 return 0; 2669 } 2670 2671 return antenna_nr; 2672} 2673 2674static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna) 2675{ 2676 antenna = b43_ieee80211_antenna_sanitize(dev, antenna); 2677 switch (antenna) { 2678 case 0: /* default/diversity */ 2679 return B43_ANTENNA_DEFAULT; 2680 case 1: /* Antenna 0 */ 2681 return B43_ANTENNA0; 2682 case 2: /* Antenna 1 */ 2683 return B43_ANTENNA1; 2684 default: 2685 return B43_ANTENNA_DEFAULT; 2686 } 2687} 2688 2689static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) 2690{ 2691 struct b43_wl *wl = hw_to_b43_wl(hw); 2692 struct b43_wldev *dev; 2693 struct b43_phy *phy; 2694 unsigned long flags; 2695 unsigned int new_phymode = 0xFFFF; 2696 int antenna; 2697 int err = 0; 2698 u32 savedirqs; 2699 2700 mutex_lock(&wl->mutex); 2701 2702 /* Switch the PHY mode (if necessary). */ 2703 switch (conf->phymode) { 2704 case MODE_IEEE80211A: 2705 new_phymode = B43_PHYMODE_A; 2706 break; 2707 case MODE_IEEE80211B: 2708 new_phymode = B43_PHYMODE_B; 2709 break; 2710 case MODE_IEEE80211G: 2711 new_phymode = B43_PHYMODE_G; 2712 break; 2713 default: 2714 B43_WARN_ON(1); 2715 } 2716 err = b43_switch_phymode(wl, new_phymode); 2717 if (err) 2718 goto out_unlock_mutex; 2719 dev = wl->current_dev; 2720 phy = &dev->phy; 2721 2722 /* Disable IRQs while reconfiguring the device. 2723 * This makes it possible to drop the spinlock throughout 2724 * the reconfiguration process. */ 2725 spin_lock_irqsave(&wl->irq_lock, flags); 2726 if (b43_status(dev) < B43_STAT_STARTED) { 2727 spin_unlock_irqrestore(&wl->irq_lock, flags); 2728 goto out_unlock_mutex; 2729 } 2730 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL); 2731 spin_unlock_irqrestore(&wl->irq_lock, flags); 2732 b43_synchronize_irq(dev); 2733 2734 /* Switch to the requested channel. 2735 * The firmware takes care of races with the TX handler. */ 2736 if (conf->channel_val != phy->channel) 2737 b43_radio_selectchannel(dev, conf->channel_val, 0); 2738 2739 /* Enable/Disable ShortSlot timing. */ 2740 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != 2741 dev->short_slot) { 2742 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2743 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) 2744 b43_short_slot_timing_enable(dev); 2745 else 2746 b43_short_slot_timing_disable(dev); 2747 } 2748 2749 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP); 2750 2751 /* Adjust the desired TX power level. */ 2752 if (conf->power_level != 0) { 2753 if (conf->power_level != phy->power_level) { 2754 phy->power_level = conf->power_level; 2755 b43_phy_xmitpower(dev); 2756 } 2757 } 2758 2759 /* Antennas for RX and management frame TX. */ 2760 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx); 2761 b43_mgmtframe_txantenna(dev, antenna); 2762 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx); 2763 b43_set_rx_antenna(dev, antenna); 2764 2765 /* Update templates for AP mode. */ 2766 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2767 b43_set_beacon_int(dev, conf->beacon_int); 2768 2769 if (!!conf->radio_enabled != phy->radio_on) { 2770 if (conf->radio_enabled) { 2771 b43_radio_turn_on(dev); 2772 b43info(dev->wl, "Radio turned on by software\n"); 2773 if (!dev->radio_hw_enable) { 2774 b43info(dev->wl, "The hardware RF-kill button " 2775 "still turns the radio physically off. " 2776 "Press the button to turn it on.\n"); 2777 } 2778 } else { 2779 b43_radio_turn_off(dev, 0); 2780 b43info(dev->wl, "Radio turned off by software\n"); 2781 } 2782 } 2783 2784 spin_lock_irqsave(&wl->irq_lock, flags); 2785 b43_interrupt_enable(dev, savedirqs); 2786 mmiowb(); 2787 spin_unlock_irqrestore(&wl->irq_lock, flags); 2788 out_unlock_mutex: 2789 mutex_unlock(&wl->mutex); 2790 2791 return err; 2792} 2793 2794static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 2795 const u8 *local_addr, const u8 *addr, 2796 struct ieee80211_key_conf *key) 2797{ 2798 struct b43_wl *wl = hw_to_b43_wl(hw); 2799 struct b43_wldev *dev; 2800 unsigned long flags; 2801 u8 algorithm; 2802 u8 index; 2803 int err; 2804 DECLARE_MAC_BUF(mac); 2805 2806 if (modparam_nohwcrypt) 2807 return -ENOSPC; /* User disabled HW-crypto */ 2808 2809 mutex_lock(&wl->mutex); 2810 spin_lock_irqsave(&wl->irq_lock, flags); 2811 2812 dev = wl->current_dev; 2813 err = -ENODEV; 2814 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 2815 goto out_unlock; 2816 2817 err = -EINVAL; 2818 switch (key->alg) { 2819 case ALG_WEP: 2820 if (key->keylen == 5) 2821 algorithm = B43_SEC_ALGO_WEP40; 2822 else 2823 algorithm = B43_SEC_ALGO_WEP104; 2824 break; 2825 case ALG_TKIP: 2826 algorithm = B43_SEC_ALGO_TKIP; 2827 break; 2828 case ALG_CCMP: 2829 algorithm = B43_SEC_ALGO_AES; 2830 break; 2831 default: 2832 B43_WARN_ON(1); 2833 goto out_unlock; 2834 } 2835 index = (u8) (key->keyidx); 2836 if (index > 3) 2837 goto out_unlock; 2838 2839 switch (cmd) { 2840 case SET_KEY: 2841 if (algorithm == B43_SEC_ALGO_TKIP) { 2842 /* FIXME: No TKIP hardware encryption for now. */ 2843 err = -EOPNOTSUPP; 2844 goto out_unlock; 2845 } 2846 2847 if (is_broadcast_ether_addr(addr)) { 2848 /* addr is FF:FF:FF:FF:FF:FF for default keys */ 2849 err = b43_key_write(dev, index, algorithm, 2850 key->key, key->keylen, NULL, key); 2851 } else { 2852 /* 2853 * either pairwise key or address is 00:00:00:00:00:00 2854 * for transmit-only keys 2855 */ 2856 err = b43_key_write(dev, -1, algorithm, 2857 key->key, key->keylen, addr, key); 2858 } 2859 if (err) 2860 goto out_unlock; 2861 2862 if (algorithm == B43_SEC_ALGO_WEP40 || 2863 algorithm == B43_SEC_ALGO_WEP104) { 2864 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 2865 } else { 2866 b43_hf_write(dev, 2867 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 2868 } 2869 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 2870 break; 2871 case DISABLE_KEY: { 2872 err = b43_key_clear(dev, key->hw_key_idx); 2873 if (err) 2874 goto out_unlock; 2875 break; 2876 } 2877 default: 2878 B43_WARN_ON(1); 2879 } 2880out_unlock: 2881 spin_unlock_irqrestore(&wl->irq_lock, flags); 2882 mutex_unlock(&wl->mutex); 2883 if (!err) { 2884 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 2885 "mac: %s\n", 2886 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 2887 print_mac(mac, addr)); 2888 } 2889 return err; 2890} 2891 2892static void b43_op_configure_filter(struct ieee80211_hw *hw, 2893 unsigned int changed, unsigned int *fflags, 2894 int mc_count, struct dev_addr_list *mc_list) 2895{ 2896 struct b43_wl *wl = hw_to_b43_wl(hw); 2897 struct b43_wldev *dev = wl->current_dev; 2898 unsigned long flags; 2899 2900 if (!dev) { 2901 *fflags = 0; 2902 return; 2903 } 2904 2905 spin_lock_irqsave(&wl->irq_lock, flags); 2906 *fflags &= FIF_PROMISC_IN_BSS | 2907 FIF_ALLMULTI | 2908 FIF_FCSFAIL | 2909 FIF_PLCPFAIL | 2910 FIF_CONTROL | 2911 FIF_OTHER_BSS | 2912 FIF_BCN_PRBRESP_PROMISC; 2913 2914 changed &= FIF_PROMISC_IN_BSS | 2915 FIF_ALLMULTI | 2916 FIF_FCSFAIL | 2917 FIF_PLCPFAIL | 2918 FIF_CONTROL | 2919 FIF_OTHER_BSS | 2920 FIF_BCN_PRBRESP_PROMISC; 2921 2922 wl->filter_flags = *fflags; 2923 2924 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 2925 b43_adjust_opmode(dev); 2926 spin_unlock_irqrestore(&wl->irq_lock, flags); 2927} 2928 2929static int b43_op_config_interface(struct ieee80211_hw *hw, 2930 int if_id, 2931 struct ieee80211_if_conf *conf) 2932{ 2933 struct b43_wl *wl = hw_to_b43_wl(hw); 2934 struct b43_wldev *dev = wl->current_dev; 2935 unsigned long flags; 2936 2937 if (!dev) 2938 return -ENODEV; 2939 mutex_lock(&wl->mutex); 2940 spin_lock_irqsave(&wl->irq_lock, flags); 2941 B43_WARN_ON(wl->if_id != if_id); 2942 if (conf->bssid) 2943 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 2944 else 2945 memset(wl->bssid, 0, ETH_ALEN); 2946 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 2947 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) { 2948 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); 2949 b43_set_ssid(dev, conf->ssid, conf->ssid_len); 2950 if (conf->beacon) 2951 b43_refresh_templates(dev, conf->beacon); 2952 } 2953 b43_write_mac_bssid_templates(dev); 2954 } 2955 spin_unlock_irqrestore(&wl->irq_lock, flags); 2956 mutex_unlock(&wl->mutex); 2957 2958 return 0; 2959} 2960 2961/* Locking: wl->mutex */ 2962static void b43_wireless_core_stop(struct b43_wldev *dev) 2963{ 2964 struct b43_wl *wl = dev->wl; 2965 unsigned long flags; 2966 2967 if (b43_status(dev) < B43_STAT_STARTED) 2968 return; 2969 2970 /* Disable and sync interrupts. We must do this before than 2971 * setting the status to INITIALIZED, as the interrupt handler 2972 * won't care about IRQs then. */ 2973 spin_lock_irqsave(&wl->irq_lock, flags); 2974 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 2975 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */ 2976 spin_unlock_irqrestore(&wl->irq_lock, flags); 2977 b43_synchronize_irq(dev); 2978 2979 b43_set_status(dev, B43_STAT_INITIALIZED); 2980 2981 mutex_unlock(&wl->mutex); 2982 /* Must unlock as it would otherwise deadlock. No races here. 2983 * Cancel the possibly running self-rearming periodic work. */ 2984 cancel_delayed_work_sync(&dev->periodic_work); 2985 mutex_lock(&wl->mutex); 2986 2987 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy. 2988 2989 b43_mac_suspend(dev); 2990 free_irq(dev->dev->irq, dev); 2991 b43dbg(wl, "Wireless interface stopped\n"); 2992} 2993 2994/* Locking: wl->mutex */ 2995static int b43_wireless_core_start(struct b43_wldev *dev) 2996{ 2997 int err; 2998 2999 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 3000 3001 drain_txstatus_queue(dev); 3002 err = request_irq(dev->dev->irq, b43_interrupt_handler, 3003 IRQF_SHARED, KBUILD_MODNAME, dev); 3004 if (err) { 3005 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); 3006 goto out; 3007 } 3008 3009 /* We are ready to run. */ 3010 b43_set_status(dev, B43_STAT_STARTED); 3011 3012 /* Start data flow (TX/RX). */ 3013 b43_mac_enable(dev); 3014 b43_interrupt_enable(dev, dev->irq_savedstate); 3015 ieee80211_start_queues(dev->wl->hw); 3016 3017 /* Start maintainance work */ 3018 b43_periodic_tasks_setup(dev); 3019 3020 b43dbg(dev->wl, "Wireless interface started\n"); 3021 out: 3022 return err; 3023} 3024 3025/* Get PHY and RADIO versioning numbers */ 3026static int b43_phy_versioning(struct b43_wldev *dev) 3027{ 3028 struct b43_phy *phy = &dev->phy; 3029 u32 tmp; 3030 u8 analog_type; 3031 u8 phy_type; 3032 u8 phy_rev; 3033 u16 radio_manuf; 3034 u16 radio_ver; 3035 u16 radio_rev; 3036 int unsupported = 0; 3037 3038 /* Get PHY versioning */ 3039 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 3040 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 3041 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 3042 phy_rev = (tmp & B43_PHYVER_VERSION); 3043 switch (phy_type) { 3044 case B43_PHYTYPE_A: 3045 if (phy_rev >= 4) 3046 unsupported = 1; 3047 break; 3048 case B43_PHYTYPE_B: 3049 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 3050 && phy_rev != 7) 3051 unsupported = 1; 3052 break; 3053 case B43_PHYTYPE_G: 3054 if (phy_rev > 9) 3055 unsupported = 1; 3056 break; 3057 default: 3058 unsupported = 1; 3059 }; 3060 if (unsupported) { 3061 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 3062 "(Analog %u, Type %u, Revision %u)\n", 3063 analog_type, phy_type, phy_rev); 3064 return -EOPNOTSUPP; 3065 } 3066 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 3067 analog_type, phy_type, phy_rev); 3068 3069 /* Get RADIO versioning */ 3070 if (dev->dev->bus->chip_id == 0x4317) { 3071 if (dev->dev->bus->chip_rev == 0) 3072 tmp = 0x3205017F; 3073 else if (dev->dev->bus->chip_rev == 1) 3074 tmp = 0x4205017F; 3075 else 3076 tmp = 0x5205017F; 3077 } else { 3078 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3079 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH); 3080 tmp <<= 16; 3081 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3082 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3083 } 3084 radio_manuf = (tmp & 0x00000FFF); 3085 radio_ver = (tmp & 0x0FFFF000) >> 12; 3086 radio_rev = (tmp & 0xF0000000) >> 28; 3087 switch (phy_type) { 3088 case B43_PHYTYPE_A: 3089 if (radio_ver != 0x2060) 3090 unsupported = 1; 3091 if (radio_rev != 1) 3092 unsupported = 1; 3093 if (radio_manuf != 0x17F) 3094 unsupported = 1; 3095 break; 3096 case B43_PHYTYPE_B: 3097 if ((radio_ver & 0xFFF0) != 0x2050) 3098 unsupported = 1; 3099 break; 3100 case B43_PHYTYPE_G: 3101 if (radio_ver != 0x2050) 3102 unsupported = 1; 3103 break; 3104 default: 3105 B43_WARN_ON(1); 3106 } 3107 if (unsupported) { 3108 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 3109 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 3110 radio_manuf, radio_ver, radio_rev); 3111 return -EOPNOTSUPP; 3112 } 3113 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 3114 radio_manuf, radio_ver, radio_rev); 3115 3116 phy->radio_manuf = radio_manuf; 3117 phy->radio_ver = radio_ver; 3118 phy->radio_rev = radio_rev; 3119 3120 phy->analog = analog_type; 3121 phy->type = phy_type; 3122 phy->rev = phy_rev; 3123 3124 return 0; 3125} 3126 3127static void setup_struct_phy_for_init(struct b43_wldev *dev, 3128 struct b43_phy *phy) 3129{ 3130 struct b43_txpower_lo_control *lo; 3131 int i; 3132 3133 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); 3134 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); 3135 3136 /* Flags */ 3137 phy->locked = 0; 3138 3139 phy->aci_enable = 0; 3140 phy->aci_wlan_automatic = 0; 3141 phy->aci_hw_rssi = 0; 3142 3143 phy->radio_off_context.valid = 0; 3144 3145 lo = phy->lo_control; 3146 if (lo) { 3147 memset(lo, 0, sizeof(*(phy->lo_control))); 3148 lo->rebuild = 1; 3149 lo->tx_bias = 0xFF; 3150 } 3151 phy->max_lb_gain = 0; 3152 phy->trsw_rx_gain = 0; 3153 phy->txpwr_offset = 0; 3154 3155 /* NRSSI */ 3156 phy->nrssislope = 0; 3157 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) 3158 phy->nrssi[i] = -1000; 3159 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) 3160 phy->nrssi_lt[i] = i; 3161 3162 phy->lofcal = 0xFFFF; 3163 phy->initval = 0xFFFF; 3164 3165 spin_lock_init(&phy->lock); 3166 phy->interfmode = B43_INTERFMODE_NONE; 3167 phy->channel = 0xFF; 3168 3169 phy->hardware_power_control = !!modparam_hwpctl; 3170 3171 /* PHY TX errors counter. */ 3172 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3173 3174 /* OFDM-table address caching. */ 3175 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN; 3176} 3177 3178static void setup_struct_wldev_for_init(struct b43_wldev *dev) 3179{ 3180 /* Flags */ 3181 dev->reg124_set_0x4 = 0; 3182 /* Assume the radio is enabled. If it's not enabled, the state will 3183 * immediately get fixed on the first periodic work run. */ 3184 dev->radio_hw_enable = 1; 3185 3186 /* Stats */ 3187 memset(&dev->stats, 0, sizeof(dev->stats)); 3188 3189 setup_struct_phy_for_init(dev, &dev->phy); 3190 3191 /* IRQ related flags */ 3192 dev->irq_reason = 0; 3193 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 3194 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE; 3195 3196 dev->mac_suspended = 1; 3197 3198 /* Noise calculation context */ 3199 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 3200} 3201 3202static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 3203{ 3204 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 3205 u32 hf; 3206 3207 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 3208 return; 3209 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 3210 return; 3211 3212 hf = b43_hf_read(dev); 3213 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 3214 hf |= B43_HF_BTCOEXALT; 3215 else 3216 hf |= B43_HF_BTCOEX; 3217 b43_hf_write(dev, hf); 3218 //TODO 3219} 3220 3221static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 3222{ //TODO 3223} 3224 3225static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 3226{ 3227#ifdef CONFIG_SSB_DRIVER_PCICORE 3228 struct ssb_bus *bus = dev->dev->bus; 3229 u32 tmp; 3230 3231 if (bus->pcicore.dev && 3232 bus->pcicore.dev->id.coreid == SSB_DEV_PCI && 3233 bus->pcicore.dev->id.revision <= 5) { 3234 /* IMCFGLO timeouts workaround. */ 3235 tmp = ssb_read32(dev->dev, SSB_IMCFGLO); 3236 tmp &= ~SSB_IMCFGLO_REQTO; 3237 tmp &= ~SSB_IMCFGLO_SERTO; 3238 switch (bus->bustype) { 3239 case SSB_BUSTYPE_PCI: 3240 case SSB_BUSTYPE_PCMCIA: 3241 tmp |= 0x32; 3242 break; 3243 case SSB_BUSTYPE_SSB: 3244 tmp |= 0x53; 3245 break; 3246 } 3247 ssb_write32(dev->dev, SSB_IMCFGLO, tmp); 3248 } 3249#endif /* CONFIG_SSB_DRIVER_PCICORE */ 3250} 3251 3252/* Write the short and long frame retry limit values. */ 3253static void b43_set_retry_limits(struct b43_wldev *dev, 3254 unsigned int short_retry, 3255 unsigned int long_retry) 3256{ 3257 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3258 * the chip-internal counter. */ 3259 short_retry = min(short_retry, (unsigned int)0xF); 3260 long_retry = min(long_retry, (unsigned int)0xF); 3261 3262 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3263 short_retry); 3264 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3265 long_retry); 3266} 3267 3268/* Shutdown a wireless core */ 3269/* Locking: wl->mutex */ 3270static void b43_wireless_core_exit(struct b43_wldev *dev) 3271{ 3272 struct b43_phy *phy = &dev->phy; 3273 3274 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED); 3275 if (b43_status(dev) != B43_STAT_INITIALIZED) 3276 return; 3277 b43_set_status(dev, B43_STAT_UNINIT); 3278 3279 b43_leds_exit(dev); 3280 b43_rng_exit(dev->wl); 3281 b43_dma_free(dev); 3282 b43_chip_exit(dev); 3283 b43_radio_turn_off(dev, 1); 3284 b43_switch_analog(dev, 0); 3285 if (phy->dyn_tssi_tbl) 3286 kfree(phy->tssi2dbm); 3287 kfree(phy->lo_control); 3288 phy->lo_control = NULL; 3289 ssb_device_disable(dev->dev, 0); 3290 ssb_bus_may_powerdown(dev->dev->bus); 3291} 3292 3293/* Initialize a wireless core */ 3294static int b43_wireless_core_init(struct b43_wldev *dev) 3295{ 3296 struct b43_wl *wl = dev->wl; 3297 struct ssb_bus *bus = dev->dev->bus; 3298 struct ssb_sprom *sprom = &bus->sprom; 3299 struct b43_phy *phy = &dev->phy; 3300 int err; 3301 u32 hf, tmp; 3302 3303 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3304 3305 err = ssb_bus_powerup(bus, 0); 3306 if (err) 3307 goto out; 3308 if (!ssb_device_is_enabled(dev->dev)) { 3309 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 3310 b43_wireless_core_reset(dev, tmp); 3311 } 3312 3313 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) { 3314 phy->lo_control = 3315 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL); 3316 if (!phy->lo_control) { 3317 err = -ENOMEM; 3318 goto err_busdown; 3319 } 3320 } 3321 setup_struct_wldev_for_init(dev); 3322 3323 err = b43_phy_init_tssi2dbm_table(dev); 3324 if (err) 3325 goto err_kfree_lo_control; 3326 3327 /* Enable IRQ routing to this device. */ 3328 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 3329 3330 b43_imcfglo_timeouts_workaround(dev); 3331 b43_bluetooth_coext_disable(dev); 3332 b43_phy_early_init(dev); 3333 err = b43_chip_init(dev); 3334 if (err) 3335 goto err_kfree_tssitbl; 3336 b43_shm_write16(dev, B43_SHM_SHARED, 3337 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 3338 hf = b43_hf_read(dev); 3339 if (phy->type == B43_PHYTYPE_G) { 3340 hf |= B43_HF_SYMW; 3341 if (phy->rev == 1) 3342 hf |= B43_HF_GDCW; 3343 if (sprom->boardflags_lo & B43_BFL_PACTRL) 3344 hf |= B43_HF_OFDMPABOOST; 3345 } else if (phy->type == B43_PHYTYPE_B) { 3346 hf |= B43_HF_SYMW; 3347 if (phy->rev >= 2 && phy->radio_ver == 0x2050) 3348 hf &= ~B43_HF_GDCW; 3349 } 3350 b43_hf_write(dev, hf); 3351 3352 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 3353 B43_DEFAULT_LONG_RETRY_LIMIT); 3354 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 3355 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 3356 3357 /* Disable sending probe responses from firmware. 3358 * Setting the MaxTime to one usec will always trigger 3359 * a timeout, so we never send any probe resp. 3360 * A timeout of zero is infinite. */ 3361 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 3362 3363 b43_rate_memory_init(dev); 3364 3365 /* Minimum Contention Window */ 3366 if (phy->type == B43_PHYTYPE_B) { 3367 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 3368 } else { 3369 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 3370 } 3371 /* Maximum Contention Window */ 3372 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 3373 3374 err = b43_dma_init(dev); 3375 if (err) 3376 goto err_chip_exit; 3377 b43_qos_init(dev); 3378 3379//FIXME 3380#if 1 3381 b43_write16(dev, 0x0612, 0x0050); 3382 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050); 3383 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4); 3384#endif 3385 3386 b43_bluetooth_coext_enable(dev); 3387 3388 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */ 3389 memset(wl->bssid, 0, ETH_ALEN); 3390 memset(wl->mac_addr, 0, ETH_ALEN); 3391 b43_upload_card_macaddress(dev); 3392 b43_security_init(dev); 3393 b43_rng_init(wl); 3394 3395 b43_set_status(dev, B43_STAT_INITIALIZED); 3396 3397 b43_leds_init(dev); 3398out: 3399 return err; 3400 3401 err_chip_exit: 3402 b43_chip_exit(dev); 3403 err_kfree_tssitbl: 3404 if (phy->dyn_tssi_tbl) 3405 kfree(phy->tssi2dbm); 3406 err_kfree_lo_control: 3407 kfree(phy->lo_control); 3408 phy->lo_control = NULL; 3409 err_busdown: 3410 ssb_bus_may_powerdown(bus); 3411 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3412 return err; 3413} 3414 3415static int b43_op_add_interface(struct ieee80211_hw *hw, 3416 struct ieee80211_if_init_conf *conf) 3417{ 3418 struct b43_wl *wl = hw_to_b43_wl(hw); 3419 struct b43_wldev *dev; 3420 unsigned long flags; 3421 int err = -EOPNOTSUPP; 3422 3423 /* TODO: allow WDS/AP devices to coexist */ 3424 3425 if (conf->type != IEEE80211_IF_TYPE_AP && 3426 conf->type != IEEE80211_IF_TYPE_STA && 3427 conf->type != IEEE80211_IF_TYPE_WDS && 3428 conf->type != IEEE80211_IF_TYPE_IBSS) 3429 return -EOPNOTSUPP; 3430 3431 mutex_lock(&wl->mutex); 3432 if (wl->operating) 3433 goto out_mutex_unlock; 3434 3435 b43dbg(wl, "Adding Interface type %d\n", conf->type); 3436 3437 dev = wl->current_dev; 3438 wl->operating = 1; 3439 wl->if_id = conf->if_id; 3440 wl->if_type = conf->type; 3441 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN); 3442 3443 spin_lock_irqsave(&wl->irq_lock, flags); 3444 b43_adjust_opmode(dev); 3445 b43_upload_card_macaddress(dev); 3446 spin_unlock_irqrestore(&wl->irq_lock, flags); 3447 3448 err = 0; 3449 out_mutex_unlock: 3450 mutex_unlock(&wl->mutex); 3451 3452 return err; 3453} 3454 3455static void b43_op_remove_interface(struct ieee80211_hw *hw, 3456 struct ieee80211_if_init_conf *conf) 3457{ 3458 struct b43_wl *wl = hw_to_b43_wl(hw); 3459 struct b43_wldev *dev = wl->current_dev; 3460 unsigned long flags; 3461 3462 b43dbg(wl, "Removing Interface type %d\n", conf->type); 3463 3464 mutex_lock(&wl->mutex); 3465 3466 B43_WARN_ON(!wl->operating); 3467 B43_WARN_ON(wl->if_id != conf->if_id); 3468 3469 wl->operating = 0; 3470 3471 spin_lock_irqsave(&wl->irq_lock, flags); 3472 b43_adjust_opmode(dev); 3473 memset(wl->mac_addr, 0, ETH_ALEN); 3474 b43_upload_card_macaddress(dev); 3475 spin_unlock_irqrestore(&wl->irq_lock, flags); 3476 3477 mutex_unlock(&wl->mutex); 3478} 3479 3480static int b43_op_start(struct ieee80211_hw *hw) 3481{ 3482 struct b43_wl *wl = hw_to_b43_wl(hw); 3483 struct b43_wldev *dev = wl->current_dev; 3484 int did_init = 0; 3485 int err = 0; 3486 3487 /* First register RFkill. 3488 * LEDs that are registered later depend on it. */ 3489 b43_rfkill_init(dev); 3490 3491 mutex_lock(&wl->mutex); 3492 3493 if (b43_status(dev) < B43_STAT_INITIALIZED) { 3494 err = b43_wireless_core_init(dev); 3495 if (err) 3496 goto out_mutex_unlock; 3497 did_init = 1; 3498 } 3499 3500 if (b43_status(dev) < B43_STAT_STARTED) { 3501 err = b43_wireless_core_start(dev); 3502 if (err) { 3503 if (did_init) 3504 b43_wireless_core_exit(dev); 3505 goto out_mutex_unlock; 3506 } 3507 } 3508 3509 out_mutex_unlock: 3510 mutex_unlock(&wl->mutex); 3511 3512 return err; 3513} 3514 3515static void b43_op_stop(struct ieee80211_hw *hw) 3516{ 3517 struct b43_wl *wl = hw_to_b43_wl(hw); 3518 struct b43_wldev *dev = wl->current_dev; 3519 3520 b43_rfkill_exit(dev); 3521 3522 mutex_lock(&wl->mutex); 3523 if (b43_status(dev) >= B43_STAT_STARTED) 3524 b43_wireless_core_stop(dev); 3525 b43_wireless_core_exit(dev); 3526 mutex_unlock(&wl->mutex); 3527} 3528 3529static int b43_op_set_retry_limit(struct ieee80211_hw *hw, 3530 u32 short_retry_limit, u32 long_retry_limit) 3531{ 3532 struct b43_wl *wl = hw_to_b43_wl(hw); 3533 struct b43_wldev *dev; 3534 int err = 0; 3535 3536 mutex_lock(&wl->mutex); 3537 dev = wl->current_dev; 3538 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) { 3539 err = -ENODEV; 3540 goto out_unlock; 3541 } 3542 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit); 3543out_unlock: 3544 mutex_unlock(&wl->mutex); 3545 3546 return err; 3547} 3548 3549static const struct ieee80211_ops b43_hw_ops = { 3550 .tx = b43_op_tx, 3551 .conf_tx = b43_op_conf_tx, 3552 .add_interface = b43_op_add_interface, 3553 .remove_interface = b43_op_remove_interface, 3554 .config = b43_op_config, 3555 .config_interface = b43_op_config_interface, 3556 .configure_filter = b43_op_configure_filter, 3557 .set_key = b43_op_set_key, 3558 .get_stats = b43_op_get_stats, 3559 .get_tx_stats = b43_op_get_tx_stats, 3560 .start = b43_op_start, 3561 .stop = b43_op_stop, 3562 .set_retry_limit = b43_op_set_retry_limit, 3563}; 3564 3565/* Hard-reset the chip. Do not call this directly. 3566 * Use b43_controller_restart() 3567 */ 3568static void b43_chip_reset(struct work_struct *work) 3569{ 3570 struct b43_wldev *dev = 3571 container_of(work, struct b43_wldev, restart_work); 3572 struct b43_wl *wl = dev->wl; 3573 int err = 0; 3574 int prev_status; 3575 3576 mutex_lock(&wl->mutex); 3577 3578 prev_status = b43_status(dev); 3579 /* Bring the device down... */ 3580 if (prev_status >= B43_STAT_STARTED) 3581 b43_wireless_core_stop(dev); 3582 if (prev_status >= B43_STAT_INITIALIZED) 3583 b43_wireless_core_exit(dev); 3584 3585 /* ...and up again. */ 3586 if (prev_status >= B43_STAT_INITIALIZED) { 3587 err = b43_wireless_core_init(dev); 3588 if (err) 3589 goto out; 3590 } 3591 if (prev_status >= B43_STAT_STARTED) { 3592 err = b43_wireless_core_start(dev); 3593 if (err) { 3594 b43_wireless_core_exit(dev); 3595 goto out; 3596 } 3597 } 3598 out: 3599 mutex_unlock(&wl->mutex); 3600 if (err) 3601 b43err(wl, "Controller restart FAILED\n"); 3602 else 3603 b43info(wl, "Controller restarted\n"); 3604} 3605 3606static int b43_setup_modes(struct b43_wldev *dev, 3607 int have_aphy, int have_bphy, int have_gphy) 3608{ 3609 struct ieee80211_hw *hw = dev->wl->hw; 3610 struct ieee80211_hw_mode *mode; 3611 struct b43_phy *phy = &dev->phy; 3612 int cnt = 0; 3613 int err; 3614 3615/*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */ 3616 have_aphy = 0; 3617 3618 phy->possible_phymodes = 0; 3619 for (; 1; cnt++) { 3620 if (have_aphy) { 3621 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3622 mode = &phy->hwmodes[cnt]; 3623 3624 mode->mode = MODE_IEEE80211A; 3625 mode->num_channels = b43_a_chantable_size; 3626 mode->channels = b43_a_chantable; 3627 mode->num_rates = b43_a_ratetable_size; 3628 mode->rates = b43_a_ratetable; 3629 err = ieee80211_register_hwmode(hw, mode); 3630 if (err) 3631 return err; 3632 3633 phy->possible_phymodes |= B43_PHYMODE_A; 3634 have_aphy = 0; 3635 continue; 3636 } 3637 if (have_bphy) { 3638 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3639 mode = &phy->hwmodes[cnt]; 3640 3641 mode->mode = MODE_IEEE80211B; 3642 mode->num_channels = b43_bg_chantable_size; 3643 mode->channels = b43_bg_chantable; 3644 mode->num_rates = b43_b_ratetable_size; 3645 mode->rates = b43_b_ratetable; 3646 err = ieee80211_register_hwmode(hw, mode); 3647 if (err) 3648 return err; 3649 3650 phy->possible_phymodes |= B43_PHYMODE_B; 3651 have_bphy = 0; 3652 continue; 3653 } 3654 if (have_gphy) { 3655 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3656 mode = &phy->hwmodes[cnt]; 3657 3658 mode->mode = MODE_IEEE80211G; 3659 mode->num_channels = b43_bg_chantable_size; 3660 mode->channels = b43_bg_chantable; 3661 mode->num_rates = b43_g_ratetable_size; 3662 mode->rates = b43_g_ratetable; 3663 err = ieee80211_register_hwmode(hw, mode); 3664 if (err) 3665 return err; 3666 3667 phy->possible_phymodes |= B43_PHYMODE_G; 3668 have_gphy = 0; 3669 continue; 3670 } 3671 break; 3672 } 3673 3674 return 0; 3675} 3676 3677static void b43_wireless_core_detach(struct b43_wldev *dev) 3678{ 3679 /* We release firmware that late to not be required to re-request 3680 * is all the time when we reinit the core. */ 3681 b43_release_firmware(dev); 3682} 3683 3684static int b43_wireless_core_attach(struct b43_wldev *dev) 3685{ 3686 struct b43_wl *wl = dev->wl; 3687 struct ssb_bus *bus = dev->dev->bus; 3688 struct pci_dev *pdev = bus->host_pci; 3689 int err; 3690 int have_aphy = 0, have_bphy = 0, have_gphy = 0; 3691 u32 tmp; 3692 3693 /* Do NOT do any device initialization here. 3694 * Do it in wireless_core_init() instead. 3695 * This function is for gathering basic information about the HW, only. 3696 * Also some structs may be set up here. But most likely you want to have 3697 * that in core_init(), too. 3698 */ 3699 3700 err = ssb_bus_powerup(bus, 0); 3701 if (err) { 3702 b43err(wl, "Bus powerup failed\n"); 3703 goto out; 3704 } 3705 /* Get the PHY type. */ 3706 if (dev->dev->id.revision >= 5) { 3707 u32 tmshigh; 3708 3709 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 3710 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY); 3711 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY); 3712 if (!have_aphy && !have_gphy) 3713 have_bphy = 1; 3714 } else if (dev->dev->id.revision == 4) { 3715 have_gphy = 1; 3716 have_aphy = 1; 3717 } else 3718 have_bphy = 1; 3719 3720 dev->phy.gmode = (have_gphy || have_bphy); 3721 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3722 b43_wireless_core_reset(dev, tmp); 3723 3724 err = b43_phy_versioning(dev); 3725 if (err) 3726 goto err_powerdown; 3727 /* Check if this device supports multiband. */ 3728 if (!pdev || 3729 (pdev->device != 0x4312 && 3730 pdev->device != 0x4319 && pdev->device != 0x4324)) { 3731 /* No multiband support. */ 3732 have_aphy = 0; 3733 have_bphy = 0; 3734 have_gphy = 0; 3735 switch (dev->phy.type) { 3736 case B43_PHYTYPE_A: 3737 have_aphy = 1; 3738 break; 3739 case B43_PHYTYPE_B: 3740 have_bphy = 1; 3741 break; 3742 case B43_PHYTYPE_G: 3743 have_gphy = 1; 3744 break; 3745 default: 3746 B43_WARN_ON(1); 3747 } 3748 } 3749 dev->phy.gmode = (have_gphy || have_bphy); 3750 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3751 b43_wireless_core_reset(dev, tmp); 3752 3753 err = b43_validate_chipaccess(dev); 3754 if (err) 3755 goto err_powerdown; 3756 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy); 3757 if (err) 3758 goto err_powerdown; 3759 3760 /* Now set some default "current_dev" */ 3761 if (!wl->current_dev) 3762 wl->current_dev = dev; 3763 INIT_WORK(&dev->restart_work, b43_chip_reset); 3764 3765 b43_radio_turn_off(dev, 1); 3766 b43_switch_analog(dev, 0); 3767 ssb_device_disable(dev->dev, 0); 3768 ssb_bus_may_powerdown(bus); 3769 3770out: 3771 return err; 3772 3773err_powerdown: 3774 ssb_bus_may_powerdown(bus); 3775 return err; 3776} 3777 3778static void b43_one_core_detach(struct ssb_device *dev) 3779{ 3780 struct b43_wldev *wldev; 3781 struct b43_wl *wl; 3782 3783 wldev = ssb_get_drvdata(dev); 3784 wl = wldev->wl; 3785 cancel_work_sync(&wldev->restart_work); 3786 b43_debugfs_remove_device(wldev); 3787 b43_wireless_core_detach(wldev); 3788 list_del(&wldev->list); 3789 wl->nr_devs--; 3790 ssb_set_drvdata(dev, NULL); 3791 kfree(wldev); 3792} 3793 3794static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 3795{ 3796 struct b43_wldev *wldev; 3797 struct pci_dev *pdev; 3798 int err = -ENOMEM; 3799 3800 if (!list_empty(&wl->devlist)) { 3801 /* We are not the first core on this chip. */ 3802 pdev = dev->bus->host_pci; 3803 /* Only special chips support more than one wireless 3804 * core, although some of the other chips have more than 3805 * one wireless core as well. Check for this and 3806 * bail out early. 3807 */ 3808 if (!pdev || 3809 ((pdev->device != 0x4321) && 3810 (pdev->device != 0x4313) && (pdev->device != 0x431A))) { 3811 b43dbg(wl, "Ignoring unconnected 802.11 core\n"); 3812 return -ENODEV; 3813 } 3814 } 3815 3816 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 3817 if (!wldev) 3818 goto out; 3819 3820 wldev->dev = dev; 3821 wldev->wl = wl; 3822 b43_set_status(wldev, B43_STAT_UNINIT); 3823 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 3824 tasklet_init(&wldev->isr_tasklet, 3825 (void (*)(unsigned long))b43_interrupt_tasklet, 3826 (unsigned long)wldev); 3827 INIT_LIST_HEAD(&wldev->list); 3828 3829 err = b43_wireless_core_attach(wldev); 3830 if (err) 3831 goto err_kfree_wldev; 3832 3833 list_add(&wldev->list, &wl->devlist); 3834 wl->nr_devs++; 3835 ssb_set_drvdata(dev, wldev); 3836 b43_debugfs_add_device(wldev); 3837 3838 out: 3839 return err; 3840 3841 err_kfree_wldev: 3842 kfree(wldev); 3843 return err; 3844} 3845 3846static void b43_sprom_fixup(struct ssb_bus *bus) 3847{ 3848 /* boardflags workarounds */ 3849 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 3850 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 3851 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 3852 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3853 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 3854 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 3855} 3856 3857static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 3858{ 3859 struct ieee80211_hw *hw = wl->hw; 3860 3861 ssb_set_devtypedata(dev, NULL); 3862 ieee80211_free_hw(hw); 3863} 3864 3865static int b43_wireless_init(struct ssb_device *dev) 3866{ 3867 struct ssb_sprom *sprom = &dev->bus->sprom; 3868 struct ieee80211_hw *hw; 3869 struct b43_wl *wl; 3870 int err = -ENOMEM; 3871 3872 b43_sprom_fixup(dev->bus); 3873 3874 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 3875 if (!hw) { 3876 b43err(NULL, "Could not allocate ieee80211 device\n"); 3877 goto out; 3878 } 3879 3880 /* fill hw info */ 3881 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 3882 IEEE80211_HW_RX_INCLUDES_FCS; 3883 hw->max_signal = 100; 3884 hw->max_rssi = -110; 3885 hw->max_noise = -110; 3886 hw->queues = 1; /* FIXME: hardware has more queues */ 3887 SET_IEEE80211_DEV(hw, dev->dev); 3888 if (is_valid_ether_addr(sprom->et1mac)) 3889 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 3890 else 3891 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 3892 3893 /* Get and initialize struct b43_wl */ 3894 wl = hw_to_b43_wl(hw); 3895 memset(wl, 0, sizeof(*wl)); 3896 wl->hw = hw; 3897 spin_lock_init(&wl->irq_lock); 3898 spin_lock_init(&wl->leds_lock); 3899 mutex_init(&wl->mutex); 3900 INIT_LIST_HEAD(&wl->devlist); 3901 3902 ssb_set_devtypedata(dev, wl); 3903 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id); 3904 err = 0; 3905 out: 3906 return err; 3907} 3908 3909static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id) 3910{ 3911 struct b43_wl *wl; 3912 int err; 3913 int first = 0; 3914 3915 wl = ssb_get_devtypedata(dev); 3916 if (!wl) { 3917 /* Probing the first core. Must setup common struct b43_wl */ 3918 first = 1; 3919 err = b43_wireless_init(dev); 3920 if (err) 3921 goto out; 3922 wl = ssb_get_devtypedata(dev); 3923 B43_WARN_ON(!wl); 3924 } 3925 err = b43_one_core_attach(dev, wl); 3926 if (err) 3927 goto err_wireless_exit; 3928 3929 if (first) { 3930 err = ieee80211_register_hw(wl->hw); 3931 if (err) 3932 goto err_one_core_detach; 3933 } 3934 3935 out: 3936 return err; 3937 3938 err_one_core_detach: 3939 b43_one_core_detach(dev); 3940 err_wireless_exit: 3941 if (first) 3942 b43_wireless_exit(dev, wl); 3943 return err; 3944} 3945 3946static void b43_remove(struct ssb_device *dev) 3947{ 3948 struct b43_wl *wl = ssb_get_devtypedata(dev); 3949 struct b43_wldev *wldev = ssb_get_drvdata(dev); 3950 3951 B43_WARN_ON(!wl); 3952 if (wl->current_dev == wldev) 3953 ieee80211_unregister_hw(wl->hw); 3954 3955 b43_one_core_detach(dev); 3956 3957 if (list_empty(&wl->devlist)) { 3958 /* Last core on the chip unregistered. 3959 * We can destroy common struct b43_wl. 3960 */ 3961 b43_wireless_exit(dev, wl); 3962 } 3963} 3964 3965/* Perform a hardware reset. This can be called from any context. */ 3966void b43_controller_restart(struct b43_wldev *dev, const char *reason) 3967{ 3968 /* Must avoid requeueing, if we are in shutdown. */ 3969 if (b43_status(dev) < B43_STAT_INITIALIZED) 3970 return; 3971 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 3972 queue_work(dev->wl->hw->workqueue, &dev->restart_work); 3973} 3974 3975#ifdef CONFIG_PM 3976 3977static int b43_suspend(struct ssb_device *dev, pm_message_t state) 3978{ 3979 struct b43_wldev *wldev = ssb_get_drvdata(dev); 3980 struct b43_wl *wl = wldev->wl; 3981 3982 b43dbg(wl, "Suspending...\n"); 3983 3984 mutex_lock(&wl->mutex); 3985 wldev->suspend_init_status = b43_status(wldev); 3986 if (wldev->suspend_init_status >= B43_STAT_STARTED) 3987 b43_wireless_core_stop(wldev); 3988 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) 3989 b43_wireless_core_exit(wldev); 3990 mutex_unlock(&wl->mutex); 3991 3992 b43dbg(wl, "Device suspended.\n"); 3993 3994 return 0; 3995} 3996 3997static int b43_resume(struct ssb_device *dev) 3998{ 3999 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4000 struct b43_wl *wl = wldev->wl; 4001 int err = 0; 4002 4003 b43dbg(wl, "Resuming...\n"); 4004 4005 mutex_lock(&wl->mutex); 4006 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) { 4007 err = b43_wireless_core_init(wldev); 4008 if (err) { 4009 b43err(wl, "Resume failed at core init\n"); 4010 goto out; 4011 } 4012 } 4013 if (wldev->suspend_init_status >= B43_STAT_STARTED) { 4014 err = b43_wireless_core_start(wldev); 4015 if (err) { 4016 b43_wireless_core_exit(wldev); 4017 b43err(wl, "Resume failed at core start\n"); 4018 goto out; 4019 } 4020 } 4021 mutex_unlock(&wl->mutex); 4022 4023 b43dbg(wl, "Device resumed.\n"); 4024 out: 4025 return err; 4026} 4027 4028#else /* CONFIG_PM */ 4029# define b43_suspend NULL 4030# define b43_resume NULL 4031#endif /* CONFIG_PM */ 4032 4033static struct ssb_driver b43_ssb_driver = { 4034 .name = KBUILD_MODNAME, 4035 .id_table = b43_ssb_tbl, 4036 .probe = b43_probe, 4037 .remove = b43_remove, 4038 .suspend = b43_suspend, 4039 .resume = b43_resume, 4040}; 4041 4042static int __init b43_init(void) 4043{ 4044 int err; 4045 4046 b43_debugfs_init(); 4047 err = b43_pcmcia_init(); 4048 if (err) 4049 goto err_dfs_exit; 4050 err = ssb_driver_register(&b43_ssb_driver); 4051 if (err) 4052 goto err_pcmcia_exit; 4053 4054 return err; 4055 4056err_pcmcia_exit: 4057 b43_pcmcia_exit(); 4058err_dfs_exit: 4059 b43_debugfs_exit(); 4060 return err; 4061} 4062 4063static void __exit b43_exit(void) 4064{ 4065 ssb_driver_unregister(&b43_ssb_driver); 4066 b43_pcmcia_exit(); 4067 b43_debugfs_exit(); 4068} 4069 4070module_init(b43_init) 4071module_exit(b43_exit) 4072