main.c revision 05155c83d13b983ac2c5691575fd471543df31fe
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net> 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 Some parts of the code in this file are derived from the ipw2200 12 driver Copyright(c) 2003 - 2004 Intel Corporation. 13 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; either version 2 of the License, or 17 (at your option) any later version. 18 19 This program is distributed in the hope that it will be useful, 20 but WITHOUT ANY WARRANTY; without even the implied warranty of 21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 GNU General Public License for more details. 23 24 You should have received a copy of the GNU General Public License 25 along with this program; see the file COPYING. If not, write to 26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 27 Boston, MA 02110-1301, USA. 28 29*/ 30 31#include <linux/delay.h> 32#include <linux/init.h> 33#include <linux/moduleparam.h> 34#include <linux/if_arp.h> 35#include <linux/etherdevice.h> 36#include <linux/version.h> 37#include <linux/firmware.h> 38#include <linux/wireless.h> 39#include <linux/workqueue.h> 40#include <linux/skbuff.h> 41#include <linux/dma-mapping.h> 42#include <asm/unaligned.h> 43 44#include "b43.h" 45#include "main.h" 46#include "debugfs.h" 47#include "phy.h" 48#include "dma.h" 49#include "pio.h" 50#include "sysfs.h" 51#include "xmit.h" 52#include "sysfs.h" 53#include "lo.h" 54#include "pcmcia.h" 55 56MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 57MODULE_AUTHOR("Martin Langer"); 58MODULE_AUTHOR("Stefano Brivio"); 59MODULE_AUTHOR("Michael Buesch"); 60MODULE_LICENSE("GPL"); 61 62extern char *nvram_get(char *name); 63 64#if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO) 65static int modparam_pio; 66module_param_named(pio, modparam_pio, int, 0444); 67MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode"); 68#elif defined(CONFIG_B43_DMA) 69# define modparam_pio 0 70#elif defined(CONFIG_B43_PIO) 71# define modparam_pio 1 72#endif 73 74static int modparam_bad_frames_preempt; 75module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 76MODULE_PARM_DESC(bad_frames_preempt, 77 "enable(1) / disable(0) Bad Frames Preemption"); 78 79static int modparam_short_retry = B43_DEFAULT_SHORT_RETRY_LIMIT; 80module_param_named(short_retry, modparam_short_retry, int, 0444); 81MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)"); 82 83static int modparam_long_retry = B43_DEFAULT_LONG_RETRY_LIMIT; 84module_param_named(long_retry, modparam_long_retry, int, 0444); 85MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)"); 86 87static int modparam_noleds; 88module_param_named(noleds, modparam_noleds, int, 0444); 89MODULE_PARM_DESC(noleds, "Turn off all LED activity"); 90 91static char modparam_fwpostfix[16]; 92module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 93MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 94 95static int modparam_mon_keep_bad; 96module_param_named(mon_keep_bad, modparam_mon_keep_bad, int, 0444); 97MODULE_PARM_DESC(mon_keep_bad, "Keep bad frames in monitor mode"); 98 99static int modparam_mon_keep_badplcp; 100module_param_named(mon_keep_badplcp, modparam_mon_keep_bad, int, 0444); 101MODULE_PARM_DESC(mon_keep_badplcp, "Keep frames with bad PLCP in monitor mode"); 102 103static int modparam_hwpctl; 104module_param_named(hwpctl, modparam_hwpctl, int, 0444); 105MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 106 107static int modparam_nohwcrypt; 108module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 109MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 110 111static const struct ssb_device_id b43_ssb_tbl[] = { 112 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 113 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 114 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 115 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 116 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 117 SSB_DEVTABLE_END 118}; 119 120MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 121 122/* Channel and ratetables are shared for all devices. 123 * They can't be const, because ieee80211 puts some precalculated 124 * data in there. This data is the same for all devices, so we don't 125 * get concurrency issues */ 126#define RATETAB_ENT(_rateid, _flags) \ 127 { \ 128 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \ 129 .val = (_rateid), \ 130 .val2 = (_rateid), \ 131 .flags = (_flags), \ 132 } 133static struct ieee80211_rate __b43_ratetable[] = { 134 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK), 135 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2), 136 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2), 137 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2), 138 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM), 139 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM), 140 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM), 141 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM), 142 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM), 143 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM), 144 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM), 145 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM), 146}; 147 148#define b43_a_ratetable (__b43_ratetable + 4) 149#define b43_a_ratetable_size 8 150#define b43_b_ratetable (__b43_ratetable + 0) 151#define b43_b_ratetable_size 4 152#define b43_g_ratetable (__b43_ratetable + 0) 153#define b43_g_ratetable_size 12 154 155#define CHANTAB_ENT(_chanid, _freq) \ 156 { \ 157 .chan = (_chanid), \ 158 .freq = (_freq), \ 159 .val = (_chanid), \ 160 .flag = IEEE80211_CHAN_W_SCAN | \ 161 IEEE80211_CHAN_W_ACTIVE_SCAN | \ 162 IEEE80211_CHAN_W_IBSS, \ 163 .power_level = 0xFF, \ 164 .antenna_max = 0xFF, \ 165 } 166static struct ieee80211_channel b43_bg_chantable[] = { 167 CHANTAB_ENT(1, 2412), 168 CHANTAB_ENT(2, 2417), 169 CHANTAB_ENT(3, 2422), 170 CHANTAB_ENT(4, 2427), 171 CHANTAB_ENT(5, 2432), 172 CHANTAB_ENT(6, 2437), 173 CHANTAB_ENT(7, 2442), 174 CHANTAB_ENT(8, 2447), 175 CHANTAB_ENT(9, 2452), 176 CHANTAB_ENT(10, 2457), 177 CHANTAB_ENT(11, 2462), 178 CHANTAB_ENT(12, 2467), 179 CHANTAB_ENT(13, 2472), 180 CHANTAB_ENT(14, 2484), 181}; 182 183#define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable) 184static struct ieee80211_channel b43_a_chantable[] = { 185 CHANTAB_ENT(36, 5180), 186 CHANTAB_ENT(40, 5200), 187 CHANTAB_ENT(44, 5220), 188 CHANTAB_ENT(48, 5240), 189 CHANTAB_ENT(52, 5260), 190 CHANTAB_ENT(56, 5280), 191 CHANTAB_ENT(60, 5300), 192 CHANTAB_ENT(64, 5320), 193 CHANTAB_ENT(149, 5745), 194 CHANTAB_ENT(153, 5765), 195 CHANTAB_ENT(157, 5785), 196 CHANTAB_ENT(161, 5805), 197 CHANTAB_ENT(165, 5825), 198}; 199 200#define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable) 201 202static void b43_wireless_core_exit(struct b43_wldev *dev); 203static int b43_wireless_core_init(struct b43_wldev *dev); 204static void b43_wireless_core_stop(struct b43_wldev *dev); 205static int b43_wireless_core_start(struct b43_wldev *dev); 206 207static int b43_ratelimit(struct b43_wl *wl) 208{ 209 if (!wl || !wl->current_dev) 210 return 1; 211 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 212 return 1; 213 /* We are up and running. 214 * Ratelimit the messages to avoid DoS over the net. */ 215 return net_ratelimit(); 216} 217 218void b43info(struct b43_wl *wl, const char *fmt, ...) 219{ 220 va_list args; 221 222 if (!b43_ratelimit(wl)) 223 return; 224 va_start(args, fmt); 225 printk(KERN_INFO "b43-%s: ", 226 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 227 vprintk(fmt, args); 228 va_end(args); 229} 230 231void b43err(struct b43_wl *wl, const char *fmt, ...) 232{ 233 va_list args; 234 235 if (!b43_ratelimit(wl)) 236 return; 237 va_start(args, fmt); 238 printk(KERN_ERR "b43-%s ERROR: ", 239 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 240 vprintk(fmt, args); 241 va_end(args); 242} 243 244void b43warn(struct b43_wl *wl, const char *fmt, ...) 245{ 246 va_list args; 247 248 if (!b43_ratelimit(wl)) 249 return; 250 va_start(args, fmt); 251 printk(KERN_WARNING "b43-%s warning: ", 252 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 253 vprintk(fmt, args); 254 va_end(args); 255} 256 257#if B43_DEBUG 258void b43dbg(struct b43_wl *wl, const char *fmt, ...) 259{ 260 va_list args; 261 262 va_start(args, fmt); 263 printk(KERN_DEBUG "b43-%s debug: ", 264 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 265 vprintk(fmt, args); 266 va_end(args); 267} 268#endif /* DEBUG */ 269 270static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 271{ 272 u32 macctl; 273 274 B43_WARN_ON(offset % 4 != 0); 275 276 macctl = b43_read32(dev, B43_MMIO_MACCTL); 277 if (macctl & B43_MACCTL_BE) 278 val = swab32(val); 279 280 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 281 mmiowb(); 282 b43_write32(dev, B43_MMIO_RAM_DATA, val); 283} 284 285static inline 286 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset) 287{ 288 u32 control; 289 290 /* "offset" is the WORD offset. */ 291 292 control = routing; 293 control <<= 16; 294 control |= offset; 295 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 296} 297 298u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 299{ 300 u32 ret; 301 302 if (routing == B43_SHM_SHARED) { 303 B43_WARN_ON(offset & 0x0001); 304 if (offset & 0x0003) { 305 /* Unaligned access */ 306 b43_shm_control_word(dev, routing, offset >> 2); 307 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 308 ret <<= 16; 309 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 310 ret |= b43_read16(dev, B43_MMIO_SHM_DATA); 311 312 return ret; 313 } 314 offset >>= 2; 315 } 316 b43_shm_control_word(dev, routing, offset); 317 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 318 319 return ret; 320} 321 322u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset) 323{ 324 u16 ret; 325 326 if (routing == B43_SHM_SHARED) { 327 B43_WARN_ON(offset & 0x0001); 328 if (offset & 0x0003) { 329 /* Unaligned access */ 330 b43_shm_control_word(dev, routing, offset >> 2); 331 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 332 333 return ret; 334 } 335 offset >>= 2; 336 } 337 b43_shm_control_word(dev, routing, offset); 338 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 339 340 return ret; 341} 342 343void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 344{ 345 if (routing == B43_SHM_SHARED) { 346 B43_WARN_ON(offset & 0x0001); 347 if (offset & 0x0003) { 348 /* Unaligned access */ 349 b43_shm_control_word(dev, routing, offset >> 2); 350 mmiowb(); 351 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 352 (value >> 16) & 0xffff); 353 mmiowb(); 354 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 355 mmiowb(); 356 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff); 357 return; 358 } 359 offset >>= 2; 360 } 361 b43_shm_control_word(dev, routing, offset); 362 mmiowb(); 363 b43_write32(dev, B43_MMIO_SHM_DATA, value); 364} 365 366void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 367{ 368 if (routing == B43_SHM_SHARED) { 369 B43_WARN_ON(offset & 0x0001); 370 if (offset & 0x0003) { 371 /* Unaligned access */ 372 b43_shm_control_word(dev, routing, offset >> 2); 373 mmiowb(); 374 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 375 return; 376 } 377 offset >>= 2; 378 } 379 b43_shm_control_word(dev, routing, offset); 380 mmiowb(); 381 b43_write16(dev, B43_MMIO_SHM_DATA, value); 382} 383 384/* Read HostFlags */ 385u32 b43_hf_read(struct b43_wldev * dev) 386{ 387 u32 ret; 388 389 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 390 ret <<= 16; 391 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 392 393 return ret; 394} 395 396/* Write HostFlags */ 397void b43_hf_write(struct b43_wldev *dev, u32 value) 398{ 399 b43_shm_write16(dev, B43_SHM_SHARED, 400 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF)); 401 b43_shm_write16(dev, B43_SHM_SHARED, 402 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16)); 403} 404 405void b43_tsf_read(struct b43_wldev *dev, u64 * tsf) 406{ 407 /* We need to be careful. As we read the TSF from multiple 408 * registers, we should take care of register overflows. 409 * In theory, the whole tsf read process should be atomic. 410 * We try to be atomic here, by restaring the read process, 411 * if any of the high registers changed (overflew). 412 */ 413 if (dev->dev->id.revision >= 3) { 414 u32 low, high, high2; 415 416 do { 417 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 418 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 419 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 420 } while (unlikely(high != high2)); 421 422 *tsf = high; 423 *tsf <<= 32; 424 *tsf |= low; 425 } else { 426 u64 tmp; 427 u16 v0, v1, v2, v3; 428 u16 test1, test2, test3; 429 430 do { 431 v3 = b43_read16(dev, B43_MMIO_TSF_3); 432 v2 = b43_read16(dev, B43_MMIO_TSF_2); 433 v1 = b43_read16(dev, B43_MMIO_TSF_1); 434 v0 = b43_read16(dev, B43_MMIO_TSF_0); 435 436 test3 = b43_read16(dev, B43_MMIO_TSF_3); 437 test2 = b43_read16(dev, B43_MMIO_TSF_2); 438 test1 = b43_read16(dev, B43_MMIO_TSF_1); 439 } while (v3 != test3 || v2 != test2 || v1 != test1); 440 441 *tsf = v3; 442 *tsf <<= 48; 443 tmp = v2; 444 tmp <<= 32; 445 *tsf |= tmp; 446 tmp = v1; 447 tmp <<= 16; 448 *tsf |= tmp; 449 *tsf |= v0; 450 } 451} 452 453static void b43_time_lock(struct b43_wldev *dev) 454{ 455 u32 macctl; 456 457 macctl = b43_read32(dev, B43_MMIO_MACCTL); 458 macctl |= B43_MACCTL_TBTTHOLD; 459 b43_write32(dev, B43_MMIO_MACCTL, macctl); 460 /* Commit the write */ 461 b43_read32(dev, B43_MMIO_MACCTL); 462} 463 464static void b43_time_unlock(struct b43_wldev *dev) 465{ 466 u32 macctl; 467 468 macctl = b43_read32(dev, B43_MMIO_MACCTL); 469 macctl &= ~B43_MACCTL_TBTTHOLD; 470 b43_write32(dev, B43_MMIO_MACCTL, macctl); 471 /* Commit the write */ 472 b43_read32(dev, B43_MMIO_MACCTL); 473} 474 475static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 476{ 477 /* Be careful with the in-progress timer. 478 * First zero out the low register, so we have a full 479 * register-overflow duration to complete the operation. 480 */ 481 if (dev->dev->id.revision >= 3) { 482 u32 lo = (tsf & 0x00000000FFFFFFFFULL); 483 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32; 484 485 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0); 486 mmiowb(); 487 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi); 488 mmiowb(); 489 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo); 490 } else { 491 u16 v0 = (tsf & 0x000000000000FFFFULL); 492 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16; 493 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32; 494 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; 495 496 b43_write16(dev, B43_MMIO_TSF_0, 0); 497 mmiowb(); 498 b43_write16(dev, B43_MMIO_TSF_3, v3); 499 mmiowb(); 500 b43_write16(dev, B43_MMIO_TSF_2, v2); 501 mmiowb(); 502 b43_write16(dev, B43_MMIO_TSF_1, v1); 503 mmiowb(); 504 b43_write16(dev, B43_MMIO_TSF_0, v0); 505 } 506} 507 508void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 509{ 510 b43_time_lock(dev); 511 b43_tsf_write_locked(dev, tsf); 512 b43_time_unlock(dev); 513} 514 515static 516void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac) 517{ 518 static const u8 zero_addr[ETH_ALEN] = { 0 }; 519 u16 data; 520 521 if (!mac) 522 mac = zero_addr; 523 524 offset |= 0x0020; 525 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 526 527 data = mac[0]; 528 data |= mac[1] << 8; 529 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 530 data = mac[2]; 531 data |= mac[3] << 8; 532 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 533 data = mac[4]; 534 data |= mac[5] << 8; 535 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 536} 537 538static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 539{ 540 const u8 *mac; 541 const u8 *bssid; 542 u8 mac_bssid[ETH_ALEN * 2]; 543 int i; 544 u32 tmp; 545 546 bssid = dev->wl->bssid; 547 mac = dev->wl->mac_addr; 548 549 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 550 551 memcpy(mac_bssid, mac, ETH_ALEN); 552 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 553 554 /* Write our MAC address and BSSID to template ram */ 555 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 556 tmp = (u32) (mac_bssid[i + 0]); 557 tmp |= (u32) (mac_bssid[i + 1]) << 8; 558 tmp |= (u32) (mac_bssid[i + 2]) << 16; 559 tmp |= (u32) (mac_bssid[i + 3]) << 24; 560 b43_ram_write(dev, 0x20 + i, tmp); 561 } 562} 563 564static void b43_upload_card_macaddress(struct b43_wldev *dev, 565 const u8 * mac_addr) 566{ 567 if (mac_addr) 568 memcpy(dev->wl->mac_addr, mac_addr, ETH_ALEN); 569 else 570 memset(dev->wl->mac_addr, 0, ETH_ALEN); 571 b43_write_mac_bssid_templates(dev); 572 b43_macfilter_set(dev, B43_MACFILTER_SELF, mac_addr); 573} 574 575static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 576{ 577 /* slot_time is in usec. */ 578 if (dev->phy.type != B43_PHYTYPE_G) 579 return; 580 b43_write16(dev, 0x684, 510 + slot_time); 581 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 582} 583 584static void b43_short_slot_timing_enable(struct b43_wldev *dev) 585{ 586 b43_set_slot_time(dev, 9); 587 dev->short_slot = 1; 588} 589 590static void b43_short_slot_timing_disable(struct b43_wldev *dev) 591{ 592 b43_set_slot_time(dev, 20); 593 dev->short_slot = 0; 594} 595 596/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable. 597 * Returns the _previously_ enabled IRQ mask. 598 */ 599static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask) 600{ 601 u32 old_mask; 602 603 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 604 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask); 605 606 return old_mask; 607} 608 609/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable. 610 * Returns the _previously_ enabled IRQ mask. 611 */ 612static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask) 613{ 614 u32 old_mask; 615 616 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 617 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask); 618 619 return old_mask; 620} 621 622/* Synchronize IRQ top- and bottom-half. 623 * IRQs must be masked before calling this. 624 * This must not be called with the irq_lock held. 625 */ 626static void b43_synchronize_irq(struct b43_wldev *dev) 627{ 628 synchronize_irq(dev->dev->irq); 629 tasklet_kill(&dev->isr_tasklet); 630} 631 632/* DummyTransmission function, as documented on 633 * http://bcm-specs.sipsolutions.net/DummyTransmission 634 */ 635void b43_dummy_transmission(struct b43_wldev *dev) 636{ 637 struct b43_phy *phy = &dev->phy; 638 unsigned int i, max_loop; 639 u16 value; 640 u32 buffer[5] = { 641 0x00000000, 642 0x00D40000, 643 0x00000000, 644 0x01000000, 645 0x00000000, 646 }; 647 648 switch (phy->type) { 649 case B43_PHYTYPE_A: 650 max_loop = 0x1E; 651 buffer[0] = 0x000201CC; 652 break; 653 case B43_PHYTYPE_B: 654 case B43_PHYTYPE_G: 655 max_loop = 0xFA; 656 buffer[0] = 0x000B846E; 657 break; 658 default: 659 B43_WARN_ON(1); 660 return; 661 } 662 663 for (i = 0; i < 5; i++) 664 b43_ram_write(dev, i * 4, buffer[i]); 665 666 /* Commit writes */ 667 b43_read32(dev, B43_MMIO_MACCTL); 668 669 b43_write16(dev, 0x0568, 0x0000); 670 b43_write16(dev, 0x07C0, 0x0000); 671 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0); 672 b43_write16(dev, 0x050C, value); 673 b43_write16(dev, 0x0508, 0x0000); 674 b43_write16(dev, 0x050A, 0x0000); 675 b43_write16(dev, 0x054C, 0x0000); 676 b43_write16(dev, 0x056A, 0x0014); 677 b43_write16(dev, 0x0568, 0x0826); 678 b43_write16(dev, 0x0500, 0x0000); 679 b43_write16(dev, 0x0502, 0x0030); 680 681 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 682 b43_radio_write16(dev, 0x0051, 0x0017); 683 for (i = 0x00; i < max_loop; i++) { 684 value = b43_read16(dev, 0x050E); 685 if (value & 0x0080) 686 break; 687 udelay(10); 688 } 689 for (i = 0x00; i < 0x0A; i++) { 690 value = b43_read16(dev, 0x050E); 691 if (value & 0x0400) 692 break; 693 udelay(10); 694 } 695 for (i = 0x00; i < 0x0A; i++) { 696 value = b43_read16(dev, 0x0690); 697 if (!(value & 0x0100)) 698 break; 699 udelay(10); 700 } 701 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 702 b43_radio_write16(dev, 0x0051, 0x0037); 703} 704 705static void key_write(struct b43_wldev *dev, 706 u8 index, u8 algorithm, const u8 * key) 707{ 708 unsigned int i; 709 u32 offset; 710 u16 value; 711 u16 kidx; 712 713 /* Key index/algo block */ 714 kidx = b43_kidx_to_fw(dev, index); 715 value = ((kidx << 4) | algorithm); 716 b43_shm_write16(dev, B43_SHM_SHARED, 717 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 718 719 /* Write the key to the Key Table Pointer offset */ 720 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 721 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 722 value = key[i]; 723 value |= (u16) (key[i + 1]) << 8; 724 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 725 } 726} 727 728static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr) 729{ 730 u32 addrtmp[2] = { 0, 0, }; 731 u8 per_sta_keys_start = 8; 732 733 if (b43_new_kidx_api(dev)) 734 per_sta_keys_start = 4; 735 736 B43_WARN_ON(index < per_sta_keys_start); 737 /* We have two default TX keys and possibly two default RX keys. 738 * Physical mac 0 is mapped to physical key 4 or 8, depending 739 * on the firmware version. 740 * So we must adjust the index here. 741 */ 742 index -= per_sta_keys_start; 743 744 if (addr) { 745 addrtmp[0] = addr[0]; 746 addrtmp[0] |= ((u32) (addr[1]) << 8); 747 addrtmp[0] |= ((u32) (addr[2]) << 16); 748 addrtmp[0] |= ((u32) (addr[3]) << 24); 749 addrtmp[1] = addr[4]; 750 addrtmp[1] |= ((u32) (addr[5]) << 8); 751 } 752 753 if (dev->dev->id.revision >= 5) { 754 /* Receive match transmitter address mechanism */ 755 b43_shm_write32(dev, B43_SHM_RCMTA, 756 (index * 2) + 0, addrtmp[0]); 757 b43_shm_write16(dev, B43_SHM_RCMTA, 758 (index * 2) + 1, addrtmp[1]); 759 } else { 760 /* RXE (Receive Engine) and 761 * PSM (Programmable State Machine) mechanism 762 */ 763 if (index < 8) { 764 /* TODO write to RCM 16, 19, 22 and 25 */ 765 } else { 766 b43_shm_write32(dev, B43_SHM_SHARED, 767 B43_SHM_SH_PSM + (index * 6) + 0, 768 addrtmp[0]); 769 b43_shm_write16(dev, B43_SHM_SHARED, 770 B43_SHM_SH_PSM + (index * 6) + 4, 771 addrtmp[1]); 772 } 773 } 774} 775 776static void do_key_write(struct b43_wldev *dev, 777 u8 index, u8 algorithm, 778 const u8 * key, size_t key_len, const u8 * mac_addr) 779{ 780 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 781 u8 per_sta_keys_start = 8; 782 783 if (b43_new_kidx_api(dev)) 784 per_sta_keys_start = 4; 785 786 B43_WARN_ON(index >= dev->max_nr_keys); 787 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 788 789 if (index >= per_sta_keys_start) 790 keymac_write(dev, index, NULL); /* First zero out mac. */ 791 if (key) 792 memcpy(buf, key, key_len); 793 key_write(dev, index, algorithm, buf); 794 if (index >= per_sta_keys_start) 795 keymac_write(dev, index, mac_addr); 796 797 dev->key[index].algorithm = algorithm; 798} 799 800static int b43_key_write(struct b43_wldev *dev, 801 int index, u8 algorithm, 802 const u8 * key, size_t key_len, 803 const u8 * mac_addr, 804 struct ieee80211_key_conf *keyconf) 805{ 806 int i; 807 int sta_keys_start; 808 809 if (key_len > B43_SEC_KEYSIZE) 810 return -EINVAL; 811 for (i = 0; i < dev->max_nr_keys; i++) { 812 /* Check that we don't already have this key. */ 813 B43_WARN_ON(dev->key[i].keyconf == keyconf); 814 } 815 if (index < 0) { 816 /* Either pairwise key or address is 00:00:00:00:00:00 817 * for transmit-only keys. Search the index. */ 818 if (b43_new_kidx_api(dev)) 819 sta_keys_start = 4; 820 else 821 sta_keys_start = 8; 822 for (i = sta_keys_start; i < dev->max_nr_keys; i++) { 823 if (!dev->key[i].keyconf) { 824 /* found empty */ 825 index = i; 826 break; 827 } 828 } 829 if (index < 0) { 830 b43err(dev->wl, "Out of hardware key memory\n"); 831 return -ENOSPC; 832 } 833 } else 834 B43_WARN_ON(index > 3); 835 836 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 837 if ((index <= 3) && !b43_new_kidx_api(dev)) { 838 /* Default RX key */ 839 B43_WARN_ON(mac_addr); 840 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 841 } 842 keyconf->hw_key_idx = index; 843 dev->key[index].keyconf = keyconf; 844 845 return 0; 846} 847 848static int b43_key_clear(struct b43_wldev *dev, int index) 849{ 850 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys))) 851 return -EINVAL; 852 do_key_write(dev, index, B43_SEC_ALGO_NONE, 853 NULL, B43_SEC_KEYSIZE, NULL); 854 if ((index <= 3) && !b43_new_kidx_api(dev)) { 855 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 856 NULL, B43_SEC_KEYSIZE, NULL); 857 } 858 dev->key[index].keyconf = NULL; 859 860 return 0; 861} 862 863static void b43_clear_keys(struct b43_wldev *dev) 864{ 865 int i; 866 867 for (i = 0; i < dev->max_nr_keys; i++) 868 b43_key_clear(dev, i); 869} 870 871void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 872{ 873 u32 macctl; 874 u16 ucstat; 875 bool hwps; 876 bool awake; 877 int i; 878 879 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 880 (ps_flags & B43_PS_DISABLED)); 881 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 882 883 if (ps_flags & B43_PS_ENABLED) { 884 hwps = 1; 885 } else if (ps_flags & B43_PS_DISABLED) { 886 hwps = 0; 887 } else { 888 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 889 // and thus is not an AP and we are associated, set bit 25 890 } 891 if (ps_flags & B43_PS_AWAKE) { 892 awake = 1; 893 } else if (ps_flags & B43_PS_ASLEEP) { 894 awake = 0; 895 } else { 896 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 897 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 898 // successful, set bit26 899 } 900 901/* FIXME: For now we force awake-on and hwps-off */ 902 hwps = 0; 903 awake = 1; 904 905 macctl = b43_read32(dev, B43_MMIO_MACCTL); 906 if (hwps) 907 macctl |= B43_MACCTL_HWPS; 908 else 909 macctl &= ~B43_MACCTL_HWPS; 910 if (awake) 911 macctl |= B43_MACCTL_AWAKE; 912 else 913 macctl &= ~B43_MACCTL_AWAKE; 914 b43_write32(dev, B43_MMIO_MACCTL, macctl); 915 /* Commit write */ 916 b43_read32(dev, B43_MMIO_MACCTL); 917 if (awake && dev->dev->id.revision >= 5) { 918 /* Wait for the microcode to wake up. */ 919 for (i = 0; i < 100; i++) { 920 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 921 B43_SHM_SH_UCODESTAT); 922 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 923 break; 924 udelay(10); 925 } 926 } 927} 928 929/* Turn the Analog ON/OFF */ 930static void b43_switch_analog(struct b43_wldev *dev, int on) 931{ 932 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); 933} 934 935void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 936{ 937 u32 tmslow; 938 u32 macctl; 939 940 flags |= B43_TMSLOW_PHYCLKEN; 941 flags |= B43_TMSLOW_PHYRESET; 942 ssb_device_enable(dev->dev, flags); 943 msleep(2); /* Wait for the PLL to turn on. */ 944 945 /* Now take the PHY out of Reset again */ 946 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 947 tmslow |= SSB_TMSLOW_FGC; 948 tmslow &= ~B43_TMSLOW_PHYRESET; 949 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 950 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 951 msleep(1); 952 tmslow &= ~SSB_TMSLOW_FGC; 953 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 954 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 955 msleep(1); 956 957 /* Turn Analog ON */ 958 b43_switch_analog(dev, 1); 959 960 macctl = b43_read32(dev, B43_MMIO_MACCTL); 961 macctl &= ~B43_MACCTL_GMODE; 962 if (flags & B43_TMSLOW_GMODE) 963 macctl |= B43_MACCTL_GMODE; 964 macctl |= B43_MACCTL_IHR_ENABLED; 965 b43_write32(dev, B43_MMIO_MACCTL, macctl); 966} 967 968static void handle_irq_transmit_status(struct b43_wldev *dev) 969{ 970 u32 v0, v1; 971 u16 tmp; 972 struct b43_txstatus stat; 973 974 while (1) { 975 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 976 if (!(v0 & 0x00000001)) 977 break; 978 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 979 980 stat.cookie = (v0 >> 16); 981 stat.seq = (v1 & 0x0000FFFF); 982 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 983 tmp = (v0 & 0x0000FFFF); 984 stat.frame_count = ((tmp & 0xF000) >> 12); 985 stat.rts_count = ((tmp & 0x0F00) >> 8); 986 stat.supp_reason = ((tmp & 0x001C) >> 2); 987 stat.pm_indicated = !!(tmp & 0x0080); 988 stat.intermediate = !!(tmp & 0x0040); 989 stat.for_ampdu = !!(tmp & 0x0020); 990 stat.acked = !!(tmp & 0x0002); 991 992 b43_handle_txstatus(dev, &stat); 993 } 994} 995 996static void drain_txstatus_queue(struct b43_wldev *dev) 997{ 998 u32 dummy; 999 1000 if (dev->dev->id.revision < 5) 1001 return; 1002 /* Read all entries from the microcode TXstatus FIFO 1003 * and throw them away. 1004 */ 1005 while (1) { 1006 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1007 if (!(dummy & 0x00000001)) 1008 break; 1009 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1010 } 1011} 1012 1013static u32 b43_jssi_read(struct b43_wldev *dev) 1014{ 1015 u32 val = 0; 1016 1017 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 1018 val <<= 16; 1019 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1020 1021 return val; 1022} 1023 1024static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1025{ 1026 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1027 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1028} 1029 1030static void b43_generate_noise_sample(struct b43_wldev *dev) 1031{ 1032 b43_jssi_write(dev, 0x7F7F7F7F); 1033 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, 1034 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD) 1035 | (1 << 4)); 1036 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel); 1037} 1038 1039static void b43_calculate_link_quality(struct b43_wldev *dev) 1040{ 1041 /* Top half of Link Quality calculation. */ 1042 1043 if (dev->noisecalc.calculation_running) 1044 return; 1045 dev->noisecalc.channel_at_start = dev->phy.channel; 1046 dev->noisecalc.calculation_running = 1; 1047 dev->noisecalc.nr_samples = 0; 1048 1049 b43_generate_noise_sample(dev); 1050} 1051 1052static void handle_irq_noise(struct b43_wldev *dev) 1053{ 1054 struct b43_phy *phy = &dev->phy; 1055 u16 tmp; 1056 u8 noise[4]; 1057 u8 i, j; 1058 s32 average; 1059 1060 /* Bottom half of Link Quality calculation. */ 1061 1062 B43_WARN_ON(!dev->noisecalc.calculation_running); 1063 if (dev->noisecalc.channel_at_start != phy->channel) 1064 goto drop_calculation; 1065 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1066 if (noise[0] == 0x7F || noise[1] == 0x7F || 1067 noise[2] == 0x7F || noise[3] == 0x7F) 1068 goto generate_new; 1069 1070 /* Get the noise samples. */ 1071 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1072 i = dev->noisecalc.nr_samples; 1073 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1074 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1075 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1076 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1077 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1078 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1079 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1080 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1081 dev->noisecalc.nr_samples++; 1082 if (dev->noisecalc.nr_samples == 8) { 1083 /* Calculate the Link Quality by the noise samples. */ 1084 average = 0; 1085 for (i = 0; i < 8; i++) { 1086 for (j = 0; j < 4; j++) 1087 average += dev->noisecalc.samples[i][j]; 1088 } 1089 average /= (8 * 4); 1090 average *= 125; 1091 average += 64; 1092 average /= 128; 1093 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1094 tmp = (tmp / 128) & 0x1F; 1095 if (tmp >= 8) 1096 average += 2; 1097 else 1098 average -= 25; 1099 if (tmp == 8) 1100 average -= 72; 1101 else 1102 average -= 48; 1103 1104 dev->stats.link_noise = average; 1105 drop_calculation: 1106 dev->noisecalc.calculation_running = 0; 1107 return; 1108 } 1109 generate_new: 1110 b43_generate_noise_sample(dev); 1111} 1112 1113static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1114{ 1115 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) { 1116 ///TODO: PS TBTT 1117 } else { 1118 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1119 b43_power_saving_ctl_bits(dev, 0); 1120 } 1121 dev->reg124_set_0x4 = 0; 1122 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) 1123 dev->reg124_set_0x4 = 1; 1124} 1125 1126static void handle_irq_atim_end(struct b43_wldev *dev) 1127{ 1128 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ ) 1129 return; 1130 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, 1131 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD) 1132 | 0x4); 1133} 1134 1135static void handle_irq_pmq(struct b43_wldev *dev) 1136{ 1137 u32 tmp; 1138 1139 //TODO: AP mode. 1140 1141 while (1) { 1142 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1143 if (!(tmp & 0x00000008)) 1144 break; 1145 } 1146 /* 16bit write is odd, but correct. */ 1147 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1148} 1149 1150static void b43_write_template_common(struct b43_wldev *dev, 1151 const u8 * data, u16 size, 1152 u16 ram_offset, 1153 u16 shm_size_offset, u8 rate) 1154{ 1155 u32 i, tmp; 1156 struct b43_plcp_hdr4 plcp; 1157 1158 plcp.data = 0; 1159 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1160 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1161 ram_offset += sizeof(u32); 1162 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1163 * So leave the first two bytes of the next write blank. 1164 */ 1165 tmp = (u32) (data[0]) << 16; 1166 tmp |= (u32) (data[1]) << 24; 1167 b43_ram_write(dev, ram_offset, tmp); 1168 ram_offset += sizeof(u32); 1169 for (i = 2; i < size; i += sizeof(u32)) { 1170 tmp = (u32) (data[i + 0]); 1171 if (i + 1 < size) 1172 tmp |= (u32) (data[i + 1]) << 8; 1173 if (i + 2 < size) 1174 tmp |= (u32) (data[i + 2]) << 16; 1175 if (i + 3 < size) 1176 tmp |= (u32) (data[i + 3]) << 24; 1177 b43_ram_write(dev, ram_offset + i - 2, tmp); 1178 } 1179 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1180 size + sizeof(struct b43_plcp_hdr6)); 1181} 1182 1183static void b43_write_beacon_template(struct b43_wldev *dev, 1184 u16 ram_offset, 1185 u16 shm_size_offset, u8 rate) 1186{ 1187 int len; 1188 const u8 *data; 1189 1190 B43_WARN_ON(!dev->cached_beacon); 1191 len = min((size_t) dev->cached_beacon->len, 1192 0x200 - sizeof(struct b43_plcp_hdr6)); 1193 data = (const u8 *)(dev->cached_beacon->data); 1194 b43_write_template_common(dev, data, 1195 len, ram_offset, shm_size_offset, rate); 1196} 1197 1198static void b43_write_probe_resp_plcp(struct b43_wldev *dev, 1199 u16 shm_offset, u16 size, u8 rate) 1200{ 1201 struct b43_plcp_hdr4 plcp; 1202 u32 tmp; 1203 __le16 dur; 1204 1205 plcp.data = 0; 1206 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1207 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1208 dev->wl->if_id, size, 1209 B43_RATE_TO_BASE100KBPS(rate)); 1210 /* Write PLCP in two parts and timing for packet transfer */ 1211 tmp = le32_to_cpu(plcp.data); 1212 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF); 1213 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16); 1214 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur)); 1215} 1216 1217/* Instead of using custom probe response template, this function 1218 * just patches custom beacon template by: 1219 * 1) Changing packet type 1220 * 2) Patching duration field 1221 * 3) Stripping TIM 1222 */ 1223static u8 *b43_generate_probe_resp(struct b43_wldev *dev, 1224 u16 * dest_size, u8 rate) 1225{ 1226 const u8 *src_data; 1227 u8 *dest_data; 1228 u16 src_size, elem_size, src_pos, dest_pos; 1229 __le16 dur; 1230 struct ieee80211_hdr *hdr; 1231 1232 B43_WARN_ON(!dev->cached_beacon); 1233 src_size = dev->cached_beacon->len; 1234 src_data = (const u8 *)dev->cached_beacon->data; 1235 1236 if (unlikely(src_size < 0x24)) { 1237 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n"); 1238 return NULL; 1239 } 1240 1241 dest_data = kmalloc(src_size, GFP_ATOMIC); 1242 if (unlikely(!dest_data)) 1243 return NULL; 1244 1245 /* 0x24 is offset of first variable-len Information-Element 1246 * in beacon frame. 1247 */ 1248 memcpy(dest_data, src_data, 0x24); 1249 src_pos = dest_pos = 0x24; 1250 for (; src_pos < src_size - 2; src_pos += elem_size) { 1251 elem_size = src_data[src_pos + 1] + 2; 1252 if (src_data[src_pos] != 0x05) { /* TIM */ 1253 memcpy(dest_data + dest_pos, src_data + src_pos, 1254 elem_size); 1255 dest_pos += elem_size; 1256 } 1257 } 1258 *dest_size = dest_pos; 1259 hdr = (struct ieee80211_hdr *)dest_data; 1260 1261 /* Set the frame control. */ 1262 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | 1263 IEEE80211_STYPE_PROBE_RESP); 1264 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1265 dev->wl->if_id, *dest_size, 1266 B43_RATE_TO_BASE100KBPS(rate)); 1267 hdr->duration_id = dur; 1268 1269 return dest_data; 1270} 1271 1272static void b43_write_probe_resp_template(struct b43_wldev *dev, 1273 u16 ram_offset, 1274 u16 shm_size_offset, u8 rate) 1275{ 1276 u8 *probe_resp_data; 1277 u16 size; 1278 1279 B43_WARN_ON(!dev->cached_beacon); 1280 size = dev->cached_beacon->len; 1281 probe_resp_data = b43_generate_probe_resp(dev, &size, rate); 1282 if (unlikely(!probe_resp_data)) 1283 return; 1284 1285 /* Looks like PLCP headers plus packet timings are stored for 1286 * all possible basic rates 1287 */ 1288 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB); 1289 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB); 1290 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB); 1291 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB); 1292 1293 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6)); 1294 b43_write_template_common(dev, probe_resp_data, 1295 size, ram_offset, shm_size_offset, rate); 1296 kfree(probe_resp_data); 1297} 1298 1299static int b43_refresh_cached_beacon(struct b43_wldev *dev, 1300 struct sk_buff *beacon) 1301{ 1302 if (dev->cached_beacon) 1303 kfree_skb(dev->cached_beacon); 1304 dev->cached_beacon = beacon; 1305 1306 return 0; 1307} 1308 1309static void b43_update_templates(struct b43_wldev *dev) 1310{ 1311 u32 status; 1312 1313 B43_WARN_ON(!dev->cached_beacon); 1314 1315 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB); 1316 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB); 1317 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB); 1318 1319 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD); 1320 status |= 0x03; 1321 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1322} 1323 1324static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon) 1325{ 1326 int err; 1327 1328 err = b43_refresh_cached_beacon(dev, beacon); 1329 if (unlikely(err)) 1330 return; 1331 b43_update_templates(dev); 1332} 1333 1334static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len) 1335{ 1336 u32 tmp; 1337 u16 i, len; 1338 1339 len = min((u16) ssid_len, (u16) 0x100); 1340 for (i = 0; i < len; i += sizeof(u32)) { 1341 tmp = (u32) (ssid[i + 0]); 1342 if (i + 1 < len) 1343 tmp |= (u32) (ssid[i + 1]) << 8; 1344 if (i + 2 < len) 1345 tmp |= (u32) (ssid[i + 2]) << 16; 1346 if (i + 3 < len) 1347 tmp |= (u32) (ssid[i + 3]) << 24; 1348 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp); 1349 } 1350 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len); 1351} 1352 1353static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1354{ 1355 b43_time_lock(dev); 1356 if (dev->dev->id.revision >= 3) { 1357 b43_write32(dev, 0x188, (beacon_int << 16)); 1358 } else { 1359 b43_write16(dev, 0x606, (beacon_int >> 6)); 1360 b43_write16(dev, 0x610, beacon_int); 1361 } 1362 b43_time_unlock(dev); 1363} 1364 1365static void handle_irq_beacon(struct b43_wldev *dev) 1366{ 1367 u32 status; 1368 1369 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) 1370 return; 1371 1372 dev->irq_savedstate &= ~B43_IRQ_BEACON; 1373 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD); 1374 1375 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) { 1376 /* ACK beacon IRQ. */ 1377 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1378 dev->irq_savedstate |= B43_IRQ_BEACON; 1379 if (dev->cached_beacon) 1380 kfree_skb(dev->cached_beacon); 1381 dev->cached_beacon = NULL; 1382 return; 1383 } 1384 if (!(status & 0x1)) { 1385 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB); 1386 status |= 0x1; 1387 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1388 } 1389 if (!(status & 0x2)) { 1390 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB); 1391 status |= 0x2; 1392 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1393 } 1394} 1395 1396static void handle_irq_ucode_debug(struct b43_wldev *dev) 1397{ 1398 //TODO 1399} 1400 1401/* Interrupt handler bottom-half */ 1402static void b43_interrupt_tasklet(struct b43_wldev *dev) 1403{ 1404 u32 reason; 1405 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1406 u32 merged_dma_reason = 0; 1407 int i, activity = 0; 1408 unsigned long flags; 1409 1410 spin_lock_irqsave(&dev->wl->irq_lock, flags); 1411 1412 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED); 1413 1414 reason = dev->irq_reason; 1415 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1416 dma_reason[i] = dev->dma_reason[i]; 1417 merged_dma_reason |= dma_reason[i]; 1418 } 1419 1420 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1421 b43err(dev->wl, "MAC transmission error\n"); 1422 1423 if (unlikely(reason & B43_IRQ_PHY_TXERR)) 1424 b43err(dev->wl, "PHY transmission error\n"); 1425 1426 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1427 B43_DMAIRQ_NONFATALMASK))) { 1428 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1429 b43err(dev->wl, "Fatal DMA error: " 1430 "0x%08X, 0x%08X, 0x%08X, " 1431 "0x%08X, 0x%08X, 0x%08X\n", 1432 dma_reason[0], dma_reason[1], 1433 dma_reason[2], dma_reason[3], 1434 dma_reason[4], dma_reason[5]); 1435 b43_controller_restart(dev, "DMA error"); 1436 mmiowb(); 1437 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1438 return; 1439 } 1440 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1441 b43err(dev->wl, "DMA error: " 1442 "0x%08X, 0x%08X, 0x%08X, " 1443 "0x%08X, 0x%08X, 0x%08X\n", 1444 dma_reason[0], dma_reason[1], 1445 dma_reason[2], dma_reason[3], 1446 dma_reason[4], dma_reason[5]); 1447 } 1448 } 1449 1450 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1451 handle_irq_ucode_debug(dev); 1452 if (reason & B43_IRQ_TBTT_INDI) 1453 handle_irq_tbtt_indication(dev); 1454 if (reason & B43_IRQ_ATIM_END) 1455 handle_irq_atim_end(dev); 1456 if (reason & B43_IRQ_BEACON) 1457 handle_irq_beacon(dev); 1458 if (reason & B43_IRQ_PMQ) 1459 handle_irq_pmq(dev); 1460 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) ; 1461 /*TODO*/ if (reason & B43_IRQ_NOISESAMPLE_OK) 1462 handle_irq_noise(dev); 1463 1464 /* Check the DMA reason registers for received data. */ 1465 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 1466 if (b43_using_pio(dev)) 1467 b43_pio_rx(dev->pio.queue0); 1468 else 1469 b43_dma_rx(dev->dma.rx_ring0); 1470 /* We intentionally don't set "activity" to 1, here. */ 1471 } 1472 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1473 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1474 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) { 1475 if (b43_using_pio(dev)) 1476 b43_pio_rx(dev->pio.queue3); 1477 else 1478 b43_dma_rx(dev->dma.rx_ring3); 1479 activity = 1; 1480 } 1481 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1482 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1483 1484 if (reason & B43_IRQ_TX_OK) { 1485 handle_irq_transmit_status(dev); 1486 activity = 1; 1487 //TODO: In AP mode, this also causes sending of powersave responses. 1488 } 1489 1490 if (!modparam_noleds) 1491 b43_leds_update(dev, activity); 1492 b43_interrupt_enable(dev, dev->irq_savedstate); 1493 mmiowb(); 1494 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1495} 1496 1497static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx) 1498{ 1499 u16 rxctl; 1500 1501 rxctl = b43_read16(dev, base + B43_PIO_RXCTL); 1502 if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE) 1503 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE; 1504 else 1505 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE; 1506} 1507 1508static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason) 1509{ 1510 if (b43_using_pio(dev) && 1511 (dev->dev->id.revision < 3) && 1512 (!(reason & B43_IRQ_PIO_WORKAROUND))) { 1513 /* Apply a PIO specific workaround to the dma_reasons */ 1514 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0); 1515 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1); 1516 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2); 1517 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3); 1518 } 1519 1520 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1521 1522 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1523 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1524 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1525 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1526 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1527 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1528} 1529 1530/* Interrupt handler top-half */ 1531static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1532{ 1533 irqreturn_t ret = IRQ_NONE; 1534 struct b43_wldev *dev = dev_id; 1535 u32 reason; 1536 1537 if (!dev) 1538 return IRQ_NONE; 1539 1540 spin_lock(&dev->wl->irq_lock); 1541 1542 if (b43_status(dev) < B43_STAT_STARTED) 1543 goto out; 1544 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1545 if (reason == 0xffffffff) /* shared IRQ */ 1546 goto out; 1547 ret = IRQ_HANDLED; 1548 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 1549 if (!reason) 1550 goto out; 1551 1552 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1553 & 0x0001DC00; 1554 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1555 & 0x0000DC00; 1556 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1557 & 0x0000DC00; 1558 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1559 & 0x0001DC00; 1560 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1561 & 0x0000DC00; 1562 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1563 & 0x0000DC00; 1564 1565 b43_interrupt_ack(dev, reason); 1566 /* disable all IRQs. They are enabled again in the bottom half. */ 1567 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 1568 /* save the reason code and call our bottom half. */ 1569 dev->irq_reason = reason; 1570 tasklet_schedule(&dev->isr_tasklet); 1571 out: 1572 mmiowb(); 1573 spin_unlock(&dev->wl->irq_lock); 1574 1575 return ret; 1576} 1577 1578static void b43_release_firmware(struct b43_wldev *dev) 1579{ 1580 release_firmware(dev->fw.ucode); 1581 dev->fw.ucode = NULL; 1582 release_firmware(dev->fw.pcm); 1583 dev->fw.pcm = NULL; 1584 release_firmware(dev->fw.initvals); 1585 dev->fw.initvals = NULL; 1586 release_firmware(dev->fw.initvals_band); 1587 dev->fw.initvals_band = NULL; 1588} 1589 1590static void b43_print_fw_helptext(struct b43_wl *wl) 1591{ 1592 b43err(wl, "You must go to " 1593 "http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware " 1594 "and download the correct firmware (version 4).\n"); 1595} 1596 1597static int do_request_fw(struct b43_wldev *dev, 1598 const char *name, 1599 const struct firmware **fw) 1600{ 1601 char path[sizeof(modparam_fwpostfix) + 32]; 1602 struct b43_fw_header *hdr; 1603 u32 size; 1604 int err; 1605 1606 if (!name) 1607 return 0; 1608 1609 snprintf(path, ARRAY_SIZE(path), 1610 "b43%s/%s.fw", 1611 modparam_fwpostfix, name); 1612 err = request_firmware(fw, path, dev->dev->dev); 1613 if (err) { 1614 b43err(dev->wl, "Firmware file \"%s\" not found " 1615 "or load failed.\n", path); 1616 return err; 1617 } 1618 if ((*fw)->size < sizeof(struct b43_fw_header)) 1619 goto err_format; 1620 hdr = (struct b43_fw_header *)((*fw)->data); 1621 switch (hdr->type) { 1622 case B43_FW_TYPE_UCODE: 1623 case B43_FW_TYPE_PCM: 1624 size = be32_to_cpu(hdr->size); 1625 if (size != (*fw)->size - sizeof(struct b43_fw_header)) 1626 goto err_format; 1627 /* fallthrough */ 1628 case B43_FW_TYPE_IV: 1629 if (hdr->ver != 1) 1630 goto err_format; 1631 break; 1632 default: 1633 goto err_format; 1634 } 1635 1636 return err; 1637 1638err_format: 1639 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path); 1640 return -EPROTO; 1641} 1642 1643static int b43_request_firmware(struct b43_wldev *dev) 1644{ 1645 struct b43_firmware *fw = &dev->fw; 1646 const u8 rev = dev->dev->id.revision; 1647 const char *filename; 1648 u32 tmshigh; 1649 int err; 1650 1651 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 1652 if (!fw->ucode) { 1653 if ((rev >= 5) && (rev <= 10)) 1654 filename = "ucode5"; 1655 else if ((rev >= 11) && (rev <= 12)) 1656 filename = "ucode11"; 1657 else if (rev >= 13) 1658 filename = "ucode13"; 1659 else 1660 goto err_no_ucode; 1661 err = do_request_fw(dev, filename, &fw->ucode); 1662 if (err) 1663 goto err_load; 1664 } 1665 if (!fw->pcm) { 1666 if ((rev >= 5) && (rev <= 10)) 1667 filename = "pcm5"; 1668 else if (rev >= 11) 1669 filename = NULL; 1670 else 1671 goto err_no_pcm; 1672 err = do_request_fw(dev, filename, &fw->pcm); 1673 if (err) 1674 goto err_load; 1675 } 1676 if (!fw->initvals) { 1677 switch (dev->phy.type) { 1678 case B43_PHYTYPE_A: 1679 if ((rev >= 5) && (rev <= 10)) { 1680 if (tmshigh & B43_TMSHIGH_GPHY) 1681 filename = "a0g1initvals5"; 1682 else 1683 filename = "a0g0initvals5"; 1684 } else 1685 goto err_no_initvals; 1686 break; 1687 case B43_PHYTYPE_G: 1688 if ((rev >= 5) && (rev <= 10)) 1689 filename = "b0g0initvals5"; 1690 else if (rev >= 13) 1691 filename = "lp0initvals13"; 1692 else 1693 goto err_no_initvals; 1694 break; 1695 default: 1696 goto err_no_initvals; 1697 } 1698 err = do_request_fw(dev, filename, &fw->initvals); 1699 if (err) 1700 goto err_load; 1701 } 1702 if (!fw->initvals_band) { 1703 switch (dev->phy.type) { 1704 case B43_PHYTYPE_A: 1705 if ((rev >= 5) && (rev <= 10)) { 1706 if (tmshigh & B43_TMSHIGH_GPHY) 1707 filename = "a0g1bsinitvals5"; 1708 else 1709 filename = "a0g0bsinitvals5"; 1710 } else if (rev >= 11) 1711 filename = NULL; 1712 else 1713 goto err_no_initvals; 1714 break; 1715 case B43_PHYTYPE_G: 1716 if ((rev >= 5) && (rev <= 10)) 1717 filename = "b0g0bsinitvals5"; 1718 else if (rev >= 11) 1719 filename = NULL; 1720 else 1721 goto err_no_initvals; 1722 break; 1723 default: 1724 goto err_no_initvals; 1725 } 1726 err = do_request_fw(dev, filename, &fw->initvals_band); 1727 if (err) 1728 goto err_load; 1729 } 1730 1731 return 0; 1732 1733err_load: 1734 b43_print_fw_helptext(dev->wl); 1735 goto error; 1736 1737err_no_ucode: 1738 err = -ENODEV; 1739 b43err(dev->wl, "No microcode available for core rev %u\n", rev); 1740 goto error; 1741 1742err_no_pcm: 1743 err = -ENODEV; 1744 b43err(dev->wl, "No PCM available for core rev %u\n", rev); 1745 goto error; 1746 1747err_no_initvals: 1748 err = -ENODEV; 1749 b43err(dev->wl, "No Initial Values firmware file for PHY %u, " 1750 "core rev %u\n", dev->phy.type, rev); 1751 goto error; 1752 1753error: 1754 b43_release_firmware(dev); 1755 return err; 1756} 1757 1758static int b43_upload_microcode(struct b43_wldev *dev) 1759{ 1760 const size_t hdr_len = sizeof(struct b43_fw_header); 1761 const __be32 *data; 1762 unsigned int i, len; 1763 u16 fwrev, fwpatch, fwdate, fwtime; 1764 u32 tmp; 1765 int err = 0; 1766 1767 /* Upload Microcode. */ 1768 data = (__be32 *) (dev->fw.ucode->data + hdr_len); 1769 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32); 1770 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 1771 for (i = 0; i < len; i++) { 1772 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1773 udelay(10); 1774 } 1775 1776 if (dev->fw.pcm) { 1777 /* Upload PCM data. */ 1778 data = (__be32 *) (dev->fw.pcm->data + hdr_len); 1779 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32); 1780 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 1781 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 1782 /* No need for autoinc bit in SHM_HW */ 1783 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 1784 for (i = 0; i < len; i++) { 1785 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1786 udelay(10); 1787 } 1788 } 1789 1790 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 1791 b43_write32(dev, B43_MMIO_MACCTL, 1792 B43_MACCTL_PSM_RUN | 1793 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA); 1794 1795 /* Wait for the microcode to load and respond */ 1796 i = 0; 1797 while (1) { 1798 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1799 if (tmp == B43_IRQ_MAC_SUSPENDED) 1800 break; 1801 i++; 1802 if (i >= 50) { 1803 b43err(dev->wl, "Microcode not responding\n"); 1804 b43_print_fw_helptext(dev->wl); 1805 err = -ENODEV; 1806 goto out; 1807 } 1808 udelay(10); 1809 } 1810 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 1811 1812 /* Get and check the revisions. */ 1813 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 1814 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 1815 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 1816 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 1817 1818 if (fwrev <= 0x128) { 1819 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 1820 "binary drivers older than version 4.x is unsupported. " 1821 "You must upgrade your firmware files.\n"); 1822 b43_print_fw_helptext(dev->wl); 1823 b43_write32(dev, B43_MMIO_MACCTL, 0); 1824 err = -EOPNOTSUPP; 1825 goto out; 1826 } 1827 b43dbg(dev->wl, "Loading firmware version %u.%u " 1828 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 1829 fwrev, fwpatch, 1830 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 1831 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 1832 1833 dev->fw.rev = fwrev; 1834 dev->fw.patch = fwpatch; 1835 1836 out: 1837 return err; 1838} 1839 1840static int b43_write_initvals(struct b43_wldev *dev, 1841 const struct b43_iv *ivals, 1842 size_t count, 1843 size_t array_size) 1844{ 1845 const struct b43_iv *iv; 1846 u16 offset; 1847 size_t i; 1848 bool bit32; 1849 1850 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 1851 iv = ivals; 1852 for (i = 0; i < count; i++) { 1853 if (array_size < sizeof(iv->offset_size)) 1854 goto err_format; 1855 array_size -= sizeof(iv->offset_size); 1856 offset = be16_to_cpu(iv->offset_size); 1857 bit32 = !!(offset & B43_IV_32BIT); 1858 offset &= B43_IV_OFFSET_MASK; 1859 if (offset >= 0x1000) 1860 goto err_format; 1861 if (bit32) { 1862 u32 value; 1863 1864 if (array_size < sizeof(iv->data.d32)) 1865 goto err_format; 1866 array_size -= sizeof(iv->data.d32); 1867 1868 value = be32_to_cpu(get_unaligned(&iv->data.d32)); 1869 b43_write32(dev, offset, value); 1870 1871 iv = (const struct b43_iv *)((const uint8_t *)iv + 1872 sizeof(__be16) + 1873 sizeof(__be32)); 1874 } else { 1875 u16 value; 1876 1877 if (array_size < sizeof(iv->data.d16)) 1878 goto err_format; 1879 array_size -= sizeof(iv->data.d16); 1880 1881 value = be16_to_cpu(iv->data.d16); 1882 b43_write16(dev, offset, value); 1883 1884 iv = (const struct b43_iv *)((const uint8_t *)iv + 1885 sizeof(__be16) + 1886 sizeof(__be16)); 1887 } 1888 } 1889 if (array_size) 1890 goto err_format; 1891 1892 return 0; 1893 1894err_format: 1895 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 1896 b43_print_fw_helptext(dev->wl); 1897 1898 return -EPROTO; 1899} 1900 1901static int b43_upload_initvals(struct b43_wldev *dev) 1902{ 1903 const size_t hdr_len = sizeof(struct b43_fw_header); 1904 const struct b43_fw_header *hdr; 1905 struct b43_firmware *fw = &dev->fw; 1906 const struct b43_iv *ivals; 1907 size_t count; 1908 int err; 1909 1910 hdr = (const struct b43_fw_header *)(fw->initvals->data); 1911 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len); 1912 count = be32_to_cpu(hdr->size); 1913 err = b43_write_initvals(dev, ivals, count, 1914 fw->initvals->size - hdr_len); 1915 if (err) 1916 goto out; 1917 if (fw->initvals_band) { 1918 hdr = (const struct b43_fw_header *)(fw->initvals_band->data); 1919 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len); 1920 count = be32_to_cpu(hdr->size); 1921 err = b43_write_initvals(dev, ivals, count, 1922 fw->initvals_band->size - hdr_len); 1923 if (err) 1924 goto out; 1925 } 1926out: 1927 1928 return err; 1929} 1930 1931/* Initialize the GPIOs 1932 * http://bcm-specs.sipsolutions.net/GPIO 1933 */ 1934static int b43_gpio_init(struct b43_wldev *dev) 1935{ 1936 struct ssb_bus *bus = dev->dev->bus; 1937 struct ssb_device *gpiodev, *pcidev = NULL; 1938 u32 mask, set; 1939 1940 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 1941 & ~B43_MACCTL_GPOUTSMSK); 1942 1943 b43_leds_switch_all(dev, 0); 1944 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 1945 | 0x000F); 1946 1947 mask = 0x0000001F; 1948 set = 0x0000000F; 1949 if (dev->dev->bus->chip_id == 0x4301) { 1950 mask |= 0x0060; 1951 set |= 0x0060; 1952 } 1953 if (0 /* FIXME: conditional unknown */ ) { 1954 b43_write16(dev, B43_MMIO_GPIO_MASK, 1955 b43_read16(dev, B43_MMIO_GPIO_MASK) 1956 | 0x0100); 1957 mask |= 0x0180; 1958 set |= 0x0180; 1959 } 1960 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) { 1961 b43_write16(dev, B43_MMIO_GPIO_MASK, 1962 b43_read16(dev, B43_MMIO_GPIO_MASK) 1963 | 0x0200); 1964 mask |= 0x0200; 1965 set |= 0x0200; 1966 } 1967 if (dev->dev->id.revision >= 2) 1968 mask |= 0x0010; /* FIXME: This is redundant. */ 1969 1970#ifdef CONFIG_SSB_DRIVER_PCICORE 1971 pcidev = bus->pcicore.dev; 1972#endif 1973 gpiodev = bus->chipco.dev ? : pcidev; 1974 if (!gpiodev) 1975 return 0; 1976 ssb_write32(gpiodev, B43_GPIO_CONTROL, 1977 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 1978 & mask) | set); 1979 1980 return 0; 1981} 1982 1983/* Turn off all GPIO stuff. Call this on module unload, for example. */ 1984static void b43_gpio_cleanup(struct b43_wldev *dev) 1985{ 1986 struct ssb_bus *bus = dev->dev->bus; 1987 struct ssb_device *gpiodev, *pcidev = NULL; 1988 1989#ifdef CONFIG_SSB_DRIVER_PCICORE 1990 pcidev = bus->pcicore.dev; 1991#endif 1992 gpiodev = bus->chipco.dev ? : pcidev; 1993 if (!gpiodev) 1994 return; 1995 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 1996} 1997 1998/* http://bcm-specs.sipsolutions.net/EnableMac */ 1999void b43_mac_enable(struct b43_wldev *dev) 2000{ 2001 dev->mac_suspended--; 2002 B43_WARN_ON(dev->mac_suspended < 0); 2003 if (dev->mac_suspended == 0) { 2004 b43_write32(dev, B43_MMIO_MACCTL, 2005 b43_read32(dev, B43_MMIO_MACCTL) 2006 | B43_MACCTL_ENABLED); 2007 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2008 B43_IRQ_MAC_SUSPENDED); 2009 /* Commit writes */ 2010 b43_read32(dev, B43_MMIO_MACCTL); 2011 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2012 b43_power_saving_ctl_bits(dev, 0); 2013 } 2014} 2015 2016/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2017void b43_mac_suspend(struct b43_wldev *dev) 2018{ 2019 int i; 2020 u32 tmp; 2021 2022 B43_WARN_ON(dev->mac_suspended < 0); 2023 if (dev->mac_suspended == 0) { 2024 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2025 b43_write32(dev, B43_MMIO_MACCTL, 2026 b43_read32(dev, B43_MMIO_MACCTL) 2027 & ~B43_MACCTL_ENABLED); 2028 /* force pci to flush the write */ 2029 b43_read32(dev, B43_MMIO_MACCTL); 2030 for (i = 10000; i; i--) { 2031 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2032 if (tmp & B43_IRQ_MAC_SUSPENDED) 2033 goto out; 2034 udelay(1); 2035 } 2036 b43err(dev->wl, "MAC suspend failed\n"); 2037 } 2038 out: 2039 dev->mac_suspended++; 2040} 2041 2042static void b43_adjust_opmode(struct b43_wldev *dev) 2043{ 2044 struct b43_wl *wl = dev->wl; 2045 u32 ctl; 2046 u16 cfp_pretbtt; 2047 2048 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2049 /* Reset status to STA infrastructure mode. */ 2050 ctl &= ~B43_MACCTL_AP; 2051 ctl &= ~B43_MACCTL_KEEP_CTL; 2052 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2053 ctl &= ~B43_MACCTL_KEEP_BAD; 2054 ctl &= ~B43_MACCTL_PROMISC; 2055 ctl |= B43_MACCTL_INFRA; 2056 2057 if (wl->operating) { 2058 switch (wl->if_type) { 2059 case IEEE80211_IF_TYPE_AP: 2060 ctl |= B43_MACCTL_AP; 2061 break; 2062 case IEEE80211_IF_TYPE_IBSS: 2063 ctl &= ~B43_MACCTL_INFRA; 2064 break; 2065 case IEEE80211_IF_TYPE_STA: 2066 case IEEE80211_IF_TYPE_MNTR: 2067 case IEEE80211_IF_TYPE_WDS: 2068 break; 2069 default: 2070 B43_WARN_ON(1); 2071 } 2072 } 2073 if (wl->monitor) { 2074 ctl |= B43_MACCTL_KEEP_CTL; 2075 if (modparam_mon_keep_bad) 2076 ctl |= B43_MACCTL_KEEP_BAD; 2077 if (modparam_mon_keep_badplcp) 2078 ctl |= B43_MACCTL_KEEP_BADPLCP; 2079 } 2080 if (wl->promisc) 2081 ctl |= B43_MACCTL_PROMISC; 2082 /* Workaround: On old hardware the HW-MAC-address-filter 2083 * doesn't work properly, so always run promisc in filter 2084 * it in software. */ 2085 if (dev->dev->id.revision <= 4) 2086 ctl |= B43_MACCTL_PROMISC; 2087 2088 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2089 2090 cfp_pretbtt = 2; 2091 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2092 if (dev->dev->bus->chip_id == 0x4306 && 2093 dev->dev->bus->chip_rev == 3) 2094 cfp_pretbtt = 100; 2095 else 2096 cfp_pretbtt = 50; 2097 } 2098 b43_write16(dev, 0x612, cfp_pretbtt); 2099} 2100 2101static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2102{ 2103 u16 offset; 2104 2105 if (is_ofdm) { 2106 offset = 0x480; 2107 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2108 } else { 2109 offset = 0x4C0; 2110 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2111 } 2112 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2113 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2114} 2115 2116static void b43_rate_memory_init(struct b43_wldev *dev) 2117{ 2118 switch (dev->phy.type) { 2119 case B43_PHYTYPE_A: 2120 case B43_PHYTYPE_G: 2121 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2122 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2123 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2124 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2125 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2126 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2127 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2128 if (dev->phy.type == B43_PHYTYPE_A) 2129 break; 2130 /* fallthrough */ 2131 case B43_PHYTYPE_B: 2132 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2133 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2134 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2135 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2136 break; 2137 default: 2138 B43_WARN_ON(1); 2139 } 2140} 2141 2142/* Set the TX-Antenna for management frames sent by firmware. */ 2143static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2144{ 2145 u16 ant = 0; 2146 u16 tmp; 2147 2148 switch (antenna) { 2149 case B43_ANTENNA0: 2150 ant |= B43_TX4_PHY_ANT0; 2151 break; 2152 case B43_ANTENNA1: 2153 ant |= B43_TX4_PHY_ANT1; 2154 break; 2155 case B43_ANTENNA_AUTO: 2156 ant |= B43_TX4_PHY_ANTLAST; 2157 break; 2158 default: 2159 B43_WARN_ON(1); 2160 } 2161 2162 /* FIXME We also need to set the other flags of the PHY control field somewhere. */ 2163 2164 /* For Beacons */ 2165 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 2166 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2167 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp); 2168 /* For ACK/CTS */ 2169 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2170 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2171 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2172 /* For Probe Resposes */ 2173 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2174 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2175 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2176} 2177 2178/* Returns TRUE, if the radio is enabled in hardware. */ 2179static bool b43_is_hw_radio_enabled(struct b43_wldev *dev) 2180{ 2181 if (dev->phy.rev >= 3) { 2182 if (!(b43_read32(dev, B43_MMIO_RADIO_HWENABLED_HI) 2183 & B43_MMIO_RADIO_HWENABLED_HI_MASK)) 2184 return 1; 2185 } else { 2186 if (b43_read16(dev, B43_MMIO_RADIO_HWENABLED_LO) 2187 & B43_MMIO_RADIO_HWENABLED_LO_MASK) 2188 return 1; 2189 } 2190 return 0; 2191} 2192 2193/* This is the opposite of b43_chip_init() */ 2194static void b43_chip_exit(struct b43_wldev *dev) 2195{ 2196 b43_radio_turn_off(dev); 2197 if (!modparam_noleds) 2198 b43_leds_exit(dev); 2199 b43_gpio_cleanup(dev); 2200 /* firmware is released later */ 2201} 2202 2203/* Initialize the chip 2204 * http://bcm-specs.sipsolutions.net/ChipInit 2205 */ 2206static int b43_chip_init(struct b43_wldev *dev) 2207{ 2208 struct b43_phy *phy = &dev->phy; 2209 int err, tmp; 2210 u32 value32; 2211 u16 value16; 2212 2213 b43_write32(dev, B43_MMIO_MACCTL, 2214 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED); 2215 2216 err = b43_request_firmware(dev); 2217 if (err) 2218 goto out; 2219 err = b43_upload_microcode(dev); 2220 if (err) 2221 goto out; /* firmware is released later */ 2222 2223 err = b43_gpio_init(dev); 2224 if (err) 2225 goto out; /* firmware is released later */ 2226 err = b43_upload_initvals(dev); 2227 if (err) 2228 goto err_gpio_cleanup; 2229 b43_radio_turn_on(dev); 2230 dev->radio_hw_enable = b43_is_hw_radio_enabled(dev); 2231 b43dbg(dev->wl, "Radio %s by hardware\n", 2232 dev->radio_hw_enable ? "enabled" : "disabled"); 2233 2234 b43_write16(dev, 0x03E6, 0x0000); 2235 err = b43_phy_init(dev); 2236 if (err) 2237 goto err_radio_off; 2238 2239 /* Select initial Interference Mitigation. */ 2240 tmp = phy->interfmode; 2241 phy->interfmode = B43_INTERFMODE_NONE; 2242 b43_radio_set_interference_mitigation(dev, tmp); 2243 2244 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2245 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2246 2247 if (phy->type == B43_PHYTYPE_B) { 2248 value16 = b43_read16(dev, 0x005E); 2249 value16 |= 0x0004; 2250 b43_write16(dev, 0x005E, value16); 2251 } 2252 b43_write32(dev, 0x0100, 0x01000000); 2253 if (dev->dev->id.revision < 5) 2254 b43_write32(dev, 0x010C, 0x01000000); 2255 2256 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2257 & ~B43_MACCTL_INFRA); 2258 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2259 | B43_MACCTL_INFRA); 2260 /* Let beacons come through */ 2261 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2262 | B43_MACCTL_BEACPROMISC); 2263 2264 if (b43_using_pio(dev)) { 2265 b43_write32(dev, 0x0210, 0x00000100); 2266 b43_write32(dev, 0x0230, 0x00000100); 2267 b43_write32(dev, 0x0250, 0x00000100); 2268 b43_write32(dev, 0x0270, 0x00000100); 2269 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000); 2270 } 2271 2272 /* Probe Response Timeout value */ 2273 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2274 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2275 2276 /* Initially set the wireless operation mode. */ 2277 b43_adjust_opmode(dev); 2278 2279 if (dev->dev->id.revision < 3) { 2280 b43_write16(dev, 0x060E, 0x0000); 2281 b43_write16(dev, 0x0610, 0x8000); 2282 b43_write16(dev, 0x0604, 0x0000); 2283 b43_write16(dev, 0x0606, 0x0200); 2284 } else { 2285 b43_write32(dev, 0x0188, 0x80000000); 2286 b43_write32(dev, 0x018C, 0x02000000); 2287 } 2288 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2289 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2290 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2291 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2292 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2293 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2294 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2295 2296 value32 = ssb_read32(dev->dev, SSB_TMSLOW); 2297 value32 |= 0x00100000; 2298 ssb_write32(dev->dev, SSB_TMSLOW, value32); 2299 2300 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2301 dev->dev->bus->chipco.fast_pwrup_delay); 2302 2303 err = 0; 2304 b43dbg(dev->wl, "Chip initialized\n"); 2305 out: 2306 return err; 2307 2308 err_radio_off: 2309 b43_radio_turn_off(dev); 2310 err_gpio_cleanup: 2311 b43_gpio_cleanup(dev); 2312 goto out; 2313} 2314 2315static void b43_periodic_every120sec(struct b43_wldev *dev) 2316{ 2317 struct b43_phy *phy = &dev->phy; 2318 2319 if (phy->type != B43_PHYTYPE_G || phy->rev < 2) 2320 return; 2321 2322 b43_mac_suspend(dev); 2323 b43_lo_g_measure(dev); 2324 b43_mac_enable(dev); 2325 if (b43_has_hardware_pctl(phy)) 2326 b43_lo_g_ctl_mark_all_unused(dev); 2327} 2328 2329static void b43_periodic_every60sec(struct b43_wldev *dev) 2330{ 2331 struct b43_phy *phy = &dev->phy; 2332 2333 if (!b43_has_hardware_pctl(phy)) 2334 b43_lo_g_ctl_mark_all_unused(dev); 2335 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) { 2336 b43_mac_suspend(dev); 2337 b43_calc_nrssi_slope(dev); 2338 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { 2339 u8 old_chan = phy->channel; 2340 2341 /* VCO Calibration */ 2342 if (old_chan >= 8) 2343 b43_radio_selectchannel(dev, 1, 0); 2344 else 2345 b43_radio_selectchannel(dev, 13, 0); 2346 b43_radio_selectchannel(dev, old_chan, 0); 2347 } 2348 b43_mac_enable(dev); 2349 } 2350} 2351 2352static void b43_periodic_every30sec(struct b43_wldev *dev) 2353{ 2354 /* Update device statistics. */ 2355 b43_calculate_link_quality(dev); 2356} 2357 2358static void b43_periodic_every15sec(struct b43_wldev *dev) 2359{ 2360 struct b43_phy *phy = &dev->phy; 2361 2362 if (phy->type == B43_PHYTYPE_G) { 2363 //TODO: update_aci_moving_average 2364 if (phy->aci_enable && phy->aci_wlan_automatic) { 2365 b43_mac_suspend(dev); 2366 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) { 2367 if (0 /*TODO: bunch of conditions */ ) { 2368 b43_radio_set_interference_mitigation 2369 (dev, B43_INTERFMODE_MANUALWLAN); 2370 } 2371 } else if (1 /*TODO*/) { 2372 /* 2373 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) { 2374 b43_radio_set_interference_mitigation(dev, 2375 B43_INTERFMODE_NONE); 2376 } 2377 */ 2378 } 2379 b43_mac_enable(dev); 2380 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN && 2381 phy->rev == 1) { 2382 //TODO: implement rev1 workaround 2383 } 2384 } 2385 b43_phy_xmitpower(dev); //FIXME: unless scanning? 2386 //TODO for APHY (temperature?) 2387} 2388 2389static void b43_periodic_every1sec(struct b43_wldev *dev) 2390{ 2391 bool radio_hw_enable; 2392 2393 /* check if radio hardware enabled status changed */ 2394 radio_hw_enable = b43_is_hw_radio_enabled(dev); 2395 if (unlikely(dev->radio_hw_enable != radio_hw_enable)) { 2396 dev->radio_hw_enable = radio_hw_enable; 2397 b43info(dev->wl, "Radio hardware status changed to %s\n", 2398 radio_hw_enable ? "ENABLED" : "DISABLED"); 2399 b43_leds_update(dev, 0); 2400 } 2401} 2402 2403static void do_periodic_work(struct b43_wldev *dev) 2404{ 2405 unsigned int state; 2406 2407 state = dev->periodic_state; 2408 if (state % 120 == 0) 2409 b43_periodic_every120sec(dev); 2410 if (state % 60 == 0) 2411 b43_periodic_every60sec(dev); 2412 if (state % 30 == 0) 2413 b43_periodic_every30sec(dev); 2414 if (state % 15 == 0) 2415 b43_periodic_every15sec(dev); 2416 b43_periodic_every1sec(dev); 2417} 2418 2419/* Estimate a "Badness" value based on the periodic work 2420 * state-machine state. "Badness" is worse (bigger), if the 2421 * periodic work will take longer. 2422 */ 2423static int estimate_periodic_work_badness(unsigned int state) 2424{ 2425 int badness = 0; 2426 2427 if (state % 120 == 0) /* every 120 sec */ 2428 badness += 10; 2429 if (state % 60 == 0) /* every 60 sec */ 2430 badness += 5; 2431 if (state % 30 == 0) /* every 30 sec */ 2432 badness += 1; 2433 if (state % 15 == 0) /* every 15 sec */ 2434 badness += 1; 2435 2436#define BADNESS_LIMIT 4 2437 return badness; 2438} 2439 2440static void b43_periodic_work_handler(struct work_struct *work) 2441{ 2442 struct b43_wldev *dev = 2443 container_of(work, struct b43_wldev, periodic_work.work); 2444 unsigned long flags, delay; 2445 u32 savedirqs = 0; 2446 int badness; 2447 2448 mutex_lock(&dev->wl->mutex); 2449 2450 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 2451 goto out; 2452 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 2453 goto out_requeue; 2454 2455 badness = estimate_periodic_work_badness(dev->periodic_state); 2456 if (badness > BADNESS_LIMIT) { 2457 spin_lock_irqsave(&dev->wl->irq_lock, flags); 2458 /* Suspend TX as we don't want to transmit packets while 2459 * we recalibrate the hardware. */ 2460 b43_tx_suspend(dev); 2461 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL); 2462 /* Periodic work will take a long time, so we want it to 2463 * be preemtible and release the spinlock. */ 2464 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 2465 b43_synchronize_irq(dev); 2466 2467 do_periodic_work(dev); 2468 2469 spin_lock_irqsave(&dev->wl->irq_lock, flags); 2470 b43_interrupt_enable(dev, savedirqs); 2471 b43_tx_resume(dev); 2472 mmiowb(); 2473 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 2474 } else { 2475 /* Take the global driver lock. This will lock any operation. */ 2476 spin_lock_irqsave(&dev->wl->irq_lock, flags); 2477 2478 do_periodic_work(dev); 2479 2480 mmiowb(); 2481 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 2482 } 2483 dev->periodic_state++; 2484 out_requeue: 2485 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 2486 delay = msecs_to_jiffies(50); 2487 else 2488 delay = round_jiffies(HZ); 2489 queue_delayed_work(dev->wl->hw->workqueue, &dev->periodic_work, delay); 2490 out: 2491 mutex_unlock(&dev->wl->mutex); 2492} 2493 2494static void b43_periodic_tasks_setup(struct b43_wldev *dev) 2495{ 2496 struct delayed_work *work = &dev->periodic_work; 2497 2498 dev->periodic_state = 0; 2499 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 2500 queue_delayed_work(dev->wl->hw->workqueue, work, 0); 2501} 2502 2503/* Validate access to the chip (SHM) */ 2504static int b43_validate_chipaccess(struct b43_wldev *dev) 2505{ 2506 u32 value; 2507 u32 shm_backup; 2508 2509 shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0); 2510 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 2511 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 2512 goto error; 2513 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 2514 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 2515 goto error; 2516 b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup); 2517 2518 value = b43_read32(dev, B43_MMIO_MACCTL); 2519 if ((value | B43_MACCTL_GMODE) != 2520 (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 2521 goto error; 2522 2523 value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2524 if (value) 2525 goto error; 2526 2527 return 0; 2528 error: 2529 b43err(dev->wl, "Failed to validate the chipaccess\n"); 2530 return -ENODEV; 2531} 2532 2533static void b43_security_init(struct b43_wldev *dev) 2534{ 2535 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20; 2536 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key)); 2537 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 2538 /* KTP is a word address, but we address SHM bytewise. 2539 * So multiply by two. 2540 */ 2541 dev->ktp *= 2; 2542 if (dev->dev->id.revision >= 5) { 2543 /* Number of RCMTA address slots */ 2544 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8); 2545 } 2546 b43_clear_keys(dev); 2547} 2548 2549static int b43_rng_read(struct hwrng *rng, u32 * data) 2550{ 2551 struct b43_wl *wl = (struct b43_wl *)rng->priv; 2552 unsigned long flags; 2553 2554 /* Don't take wl->mutex here, as it could deadlock with 2555 * hwrng internal locking. It's not needed to take 2556 * wl->mutex here, anyway. */ 2557 2558 spin_lock_irqsave(&wl->irq_lock, flags); 2559 *data = b43_read16(wl->current_dev, B43_MMIO_RNG); 2560 spin_unlock_irqrestore(&wl->irq_lock, flags); 2561 2562 return (sizeof(u16)); 2563} 2564 2565static void b43_rng_exit(struct b43_wl *wl) 2566{ 2567 if (wl->rng_initialized) 2568 hwrng_unregister(&wl->rng); 2569} 2570 2571static int b43_rng_init(struct b43_wl *wl) 2572{ 2573 int err; 2574 2575 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 2576 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 2577 wl->rng.name = wl->rng_name; 2578 wl->rng.data_read = b43_rng_read; 2579 wl->rng.priv = (unsigned long)wl; 2580 wl->rng_initialized = 1; 2581 err = hwrng_register(&wl->rng); 2582 if (err) { 2583 wl->rng_initialized = 0; 2584 b43err(wl, "Failed to register the random " 2585 "number generator (%d)\n", err); 2586 } 2587 2588 return err; 2589} 2590 2591static int b43_tx(struct ieee80211_hw *hw, 2592 struct sk_buff *skb, struct ieee80211_tx_control *ctl) 2593{ 2594 struct b43_wl *wl = hw_to_b43_wl(hw); 2595 struct b43_wldev *dev = wl->current_dev; 2596 int err = -ENODEV; 2597 unsigned long flags; 2598 2599 if (unlikely(!dev)) 2600 goto out; 2601 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2602 goto out; 2603 /* DMA-TX is done without a global lock. */ 2604 if (b43_using_pio(dev)) { 2605 spin_lock_irqsave(&wl->irq_lock, flags); 2606 err = b43_pio_tx(dev, skb, ctl); 2607 spin_unlock_irqrestore(&wl->irq_lock, flags); 2608 } else 2609 err = b43_dma_tx(dev, skb, ctl); 2610 out: 2611 if (unlikely(err)) 2612 return NETDEV_TX_BUSY; 2613 return NETDEV_TX_OK; 2614} 2615 2616static int b43_conf_tx(struct ieee80211_hw *hw, 2617 int queue, 2618 const struct ieee80211_tx_queue_params *params) 2619{ 2620 return 0; 2621} 2622 2623static int b43_get_tx_stats(struct ieee80211_hw *hw, 2624 struct ieee80211_tx_queue_stats *stats) 2625{ 2626 struct b43_wl *wl = hw_to_b43_wl(hw); 2627 struct b43_wldev *dev = wl->current_dev; 2628 unsigned long flags; 2629 int err = -ENODEV; 2630 2631 if (!dev) 2632 goto out; 2633 spin_lock_irqsave(&wl->irq_lock, flags); 2634 if (likely(b43_status(dev) >= B43_STAT_STARTED)) { 2635 if (b43_using_pio(dev)) 2636 b43_pio_get_tx_stats(dev, stats); 2637 else 2638 b43_dma_get_tx_stats(dev, stats); 2639 err = 0; 2640 } 2641 spin_unlock_irqrestore(&wl->irq_lock, flags); 2642 out: 2643 return err; 2644} 2645 2646static int b43_get_stats(struct ieee80211_hw *hw, 2647 struct ieee80211_low_level_stats *stats) 2648{ 2649 struct b43_wl *wl = hw_to_b43_wl(hw); 2650 unsigned long flags; 2651 2652 spin_lock_irqsave(&wl->irq_lock, flags); 2653 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 2654 spin_unlock_irqrestore(&wl->irq_lock, flags); 2655 2656 return 0; 2657} 2658 2659static const char *phymode_to_string(unsigned int phymode) 2660{ 2661 switch (phymode) { 2662 case B43_PHYMODE_A: 2663 return "A"; 2664 case B43_PHYMODE_B: 2665 return "B"; 2666 case B43_PHYMODE_G: 2667 return "G"; 2668 default: 2669 B43_WARN_ON(1); 2670 } 2671 return ""; 2672} 2673 2674static int find_wldev_for_phymode(struct b43_wl *wl, 2675 unsigned int phymode, 2676 struct b43_wldev **dev, bool * gmode) 2677{ 2678 struct b43_wldev *d; 2679 2680 list_for_each_entry(d, &wl->devlist, list) { 2681 if (d->phy.possible_phymodes & phymode) { 2682 /* Ok, this device supports the PHY-mode. 2683 * Now figure out how the gmode bit has to be 2684 * set to support it. */ 2685 if (phymode == B43_PHYMODE_A) 2686 *gmode = 0; 2687 else 2688 *gmode = 1; 2689 *dev = d; 2690 2691 return 0; 2692 } 2693 } 2694 2695 return -ESRCH; 2696} 2697 2698static void b43_put_phy_into_reset(struct b43_wldev *dev) 2699{ 2700 struct ssb_device *sdev = dev->dev; 2701 u32 tmslow; 2702 2703 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2704 tmslow &= ~B43_TMSLOW_GMODE; 2705 tmslow |= B43_TMSLOW_PHYRESET; 2706 tmslow |= SSB_TMSLOW_FGC; 2707 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2708 msleep(1); 2709 2710 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2711 tmslow &= ~SSB_TMSLOW_FGC; 2712 tmslow |= B43_TMSLOW_PHYRESET; 2713 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2714 msleep(1); 2715} 2716 2717/* Expects wl->mutex locked */ 2718static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode) 2719{ 2720 struct b43_wldev *up_dev; 2721 struct b43_wldev *down_dev; 2722 int err; 2723 bool gmode = 0; 2724 int prev_status; 2725 2726 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode); 2727 if (err) { 2728 b43err(wl, "Could not find a device for %s-PHY mode\n", 2729 phymode_to_string(new_mode)); 2730 return err; 2731 } 2732 if ((up_dev == wl->current_dev) && 2733 (!!wl->current_dev->phy.gmode == !!gmode)) { 2734 /* This device is already running. */ 2735 return 0; 2736 } 2737 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n", 2738 phymode_to_string(new_mode)); 2739 down_dev = wl->current_dev; 2740 2741 prev_status = b43_status(down_dev); 2742 /* Shutdown the currently running core. */ 2743 if (prev_status >= B43_STAT_STARTED) 2744 b43_wireless_core_stop(down_dev); 2745 if (prev_status >= B43_STAT_INITIALIZED) 2746 b43_wireless_core_exit(down_dev); 2747 2748 if (down_dev != up_dev) { 2749 /* We switch to a different core, so we put PHY into 2750 * RESET on the old core. */ 2751 b43_put_phy_into_reset(down_dev); 2752 } 2753 2754 /* Now start the new core. */ 2755 up_dev->phy.gmode = gmode; 2756 if (prev_status >= B43_STAT_INITIALIZED) { 2757 err = b43_wireless_core_init(up_dev); 2758 if (err) { 2759 b43err(wl, "Fatal: Could not initialize device for " 2760 "newly selected %s-PHY mode\n", 2761 phymode_to_string(new_mode)); 2762 goto init_failure; 2763 } 2764 } 2765 if (prev_status >= B43_STAT_STARTED) { 2766 err = b43_wireless_core_start(up_dev); 2767 if (err) { 2768 b43err(wl, "Fatal: Coult not start device for " 2769 "newly selected %s-PHY mode\n", 2770 phymode_to_string(new_mode)); 2771 b43_wireless_core_exit(up_dev); 2772 goto init_failure; 2773 } 2774 } 2775 B43_WARN_ON(b43_status(up_dev) != prev_status); 2776 2777 wl->current_dev = up_dev; 2778 2779 return 0; 2780 init_failure: 2781 /* Whoops, failed to init the new core. No core is operating now. */ 2782 wl->current_dev = NULL; 2783 return err; 2784} 2785 2786static int b43_antenna_from_ieee80211(u8 antenna) 2787{ 2788 switch (antenna) { 2789 case 0: /* default/diversity */ 2790 return B43_ANTENNA_DEFAULT; 2791 case 1: /* Antenna 0 */ 2792 return B43_ANTENNA0; 2793 case 2: /* Antenna 1 */ 2794 return B43_ANTENNA1; 2795 default: 2796 return B43_ANTENNA_DEFAULT; 2797 } 2798} 2799 2800static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) 2801{ 2802 struct b43_wl *wl = hw_to_b43_wl(hw); 2803 struct b43_wldev *dev; 2804 struct b43_phy *phy; 2805 unsigned long flags; 2806 unsigned int new_phymode = 0xFFFF; 2807 int antenna_tx; 2808 int antenna_rx; 2809 int err = 0; 2810 u32 savedirqs; 2811 2812 antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx); 2813 antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx); 2814 2815 mutex_lock(&wl->mutex); 2816 2817 /* Switch the PHY mode (if necessary). */ 2818 switch (conf->phymode) { 2819 case MODE_IEEE80211A: 2820 new_phymode = B43_PHYMODE_A; 2821 break; 2822 case MODE_IEEE80211B: 2823 new_phymode = B43_PHYMODE_B; 2824 break; 2825 case MODE_IEEE80211G: 2826 new_phymode = B43_PHYMODE_G; 2827 break; 2828 default: 2829 B43_WARN_ON(1); 2830 } 2831 err = b43_switch_phymode(wl, new_phymode); 2832 if (err) 2833 goto out_unlock_mutex; 2834 dev = wl->current_dev; 2835 phy = &dev->phy; 2836 2837 /* Disable IRQs while reconfiguring the device. 2838 * This makes it possible to drop the spinlock throughout 2839 * the reconfiguration process. */ 2840 spin_lock_irqsave(&wl->irq_lock, flags); 2841 if (b43_status(dev) < B43_STAT_STARTED) { 2842 spin_unlock_irqrestore(&wl->irq_lock, flags); 2843 goto out_unlock_mutex; 2844 } 2845 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL); 2846 spin_unlock_irqrestore(&wl->irq_lock, flags); 2847 b43_synchronize_irq(dev); 2848 2849 /* Switch to the requested channel. 2850 * The firmware takes care of races with the TX handler. */ 2851 if (conf->channel_val != phy->channel) 2852 b43_radio_selectchannel(dev, conf->channel_val, 0); 2853 2854 /* Enable/Disable ShortSlot timing. */ 2855 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != 2856 dev->short_slot) { 2857 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2858 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) 2859 b43_short_slot_timing_enable(dev); 2860 else 2861 b43_short_slot_timing_disable(dev); 2862 } 2863 2864 /* Adjust the desired TX power level. */ 2865 if (conf->power_level != 0) { 2866 if (conf->power_level != phy->power_level) { 2867 phy->power_level = conf->power_level; 2868 b43_phy_xmitpower(dev); 2869 } 2870 } 2871 2872 /* Antennas for RX and management frame TX. */ 2873 b43_mgmtframe_txantenna(dev, antenna_tx); 2874 b43_set_rx_antenna(dev, antenna_rx); 2875 2876 /* Update templates for AP mode. */ 2877 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2878 b43_set_beacon_int(dev, conf->beacon_int); 2879 2880 spin_lock_irqsave(&wl->irq_lock, flags); 2881 b43_interrupt_enable(dev, savedirqs); 2882 mmiowb(); 2883 spin_unlock_irqrestore(&wl->irq_lock, flags); 2884 out_unlock_mutex: 2885 mutex_unlock(&wl->mutex); 2886 2887 return err; 2888} 2889 2890static int b43_dev_set_key(struct ieee80211_hw *hw, 2891 set_key_cmd cmd, const u8 *local_addr, 2892 const u8 *addr, struct ieee80211_key_conf *key) 2893{ 2894 struct b43_wl *wl = hw_to_b43_wl(hw); 2895 struct b43_wldev *dev = wl->current_dev; 2896 unsigned long flags; 2897 u8 algorithm; 2898 u8 index; 2899 int err = -EINVAL; 2900 DECLARE_MAC_BUF(mac); 2901 2902 if (modparam_nohwcrypt) 2903 return -ENOSPC; /* User disabled HW-crypto */ 2904 2905 if (!dev) 2906 return -ENODEV; 2907 switch (key->alg) { 2908 case ALG_NONE: 2909 algorithm = B43_SEC_ALGO_NONE; 2910 break; 2911 case ALG_WEP: 2912 if (key->keylen == 5) 2913 algorithm = B43_SEC_ALGO_WEP40; 2914 else 2915 algorithm = B43_SEC_ALGO_WEP104; 2916 break; 2917 case ALG_TKIP: 2918 algorithm = B43_SEC_ALGO_TKIP; 2919 break; 2920 case ALG_CCMP: 2921 algorithm = B43_SEC_ALGO_AES; 2922 break; 2923 default: 2924 B43_WARN_ON(1); 2925 goto out; 2926 } 2927 2928 index = (u8) (key->keyidx); 2929 if (index > 3) 2930 goto out; 2931 2932 mutex_lock(&wl->mutex); 2933 spin_lock_irqsave(&wl->irq_lock, flags); 2934 2935 if (b43_status(dev) < B43_STAT_INITIALIZED) { 2936 err = -ENODEV; 2937 goto out_unlock; 2938 } 2939 2940 switch (cmd) { 2941 case SET_KEY: 2942 if (algorithm == B43_SEC_ALGO_TKIP) { 2943 /* FIXME: No TKIP hardware encryption for now. */ 2944 err = -EOPNOTSUPP; 2945 goto out_unlock; 2946 } 2947 2948 if (is_broadcast_ether_addr(addr)) { 2949 /* addr is FF:FF:FF:FF:FF:FF for default keys */ 2950 err = b43_key_write(dev, index, algorithm, 2951 key->key, key->keylen, NULL, key); 2952 } else { 2953 /* 2954 * either pairwise key or address is 00:00:00:00:00:00 2955 * for transmit-only keys 2956 */ 2957 err = b43_key_write(dev, -1, algorithm, 2958 key->key, key->keylen, addr, key); 2959 } 2960 if (err) 2961 goto out_unlock; 2962 2963 if (algorithm == B43_SEC_ALGO_WEP40 || 2964 algorithm == B43_SEC_ALGO_WEP104) { 2965 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 2966 } else { 2967 b43_hf_write(dev, 2968 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 2969 } 2970 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 2971 break; 2972 case DISABLE_KEY: { 2973 err = b43_key_clear(dev, key->hw_key_idx); 2974 if (err) 2975 goto out_unlock; 2976 break; 2977 } 2978 default: 2979 B43_WARN_ON(1); 2980 } 2981out_unlock: 2982 spin_unlock_irqrestore(&wl->irq_lock, flags); 2983 mutex_unlock(&wl->mutex); 2984out: 2985 if (!err) { 2986 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 2987 "mac: %s\n", 2988 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 2989 print_mac(mac, addr)); 2990 } 2991 return err; 2992} 2993 2994static void b43_set_multicast_list(struct ieee80211_hw *hw, 2995 unsigned short netflags, int mc_count) 2996{ 2997 struct b43_wl *wl = hw_to_b43_wl(hw); 2998 struct b43_wldev *dev = wl->current_dev; 2999 unsigned long flags; 3000 3001 if (!dev) 3002 return; 3003 spin_lock_irqsave(&wl->irq_lock, flags); 3004 if (wl->promisc != !!(netflags & IFF_PROMISC)) { 3005 wl->promisc = !!(netflags & IFF_PROMISC); 3006 if (b43_status(dev) >= B43_STAT_INITIALIZED) 3007 b43_adjust_opmode(dev); 3008 } 3009 spin_unlock_irqrestore(&wl->irq_lock, flags); 3010} 3011 3012static int b43_config_interface(struct ieee80211_hw *hw, 3013 int if_id, struct ieee80211_if_conf *conf) 3014{ 3015 struct b43_wl *wl = hw_to_b43_wl(hw); 3016 struct b43_wldev *dev = wl->current_dev; 3017 unsigned long flags; 3018 3019 if (!dev) 3020 return -ENODEV; 3021 mutex_lock(&wl->mutex); 3022 spin_lock_irqsave(&wl->irq_lock, flags); 3023 if (conf->type != IEEE80211_IF_TYPE_MNTR) { 3024 B43_WARN_ON(wl->if_id != if_id); 3025 if (conf->bssid) 3026 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3027 else 3028 memset(wl->bssid, 0, ETH_ALEN); 3029 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3030 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) { 3031 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); 3032 b43_set_ssid(dev, conf->ssid, conf->ssid_len); 3033 if (conf->beacon) 3034 b43_refresh_templates(dev, conf->beacon); 3035 } 3036 b43_write_mac_bssid_templates(dev); 3037 } 3038 } 3039 spin_unlock_irqrestore(&wl->irq_lock, flags); 3040 mutex_unlock(&wl->mutex); 3041 3042 return 0; 3043} 3044 3045/* Locking: wl->mutex */ 3046static void b43_wireless_core_stop(struct b43_wldev *dev) 3047{ 3048 struct b43_wl *wl = dev->wl; 3049 unsigned long flags; 3050 3051 if (b43_status(dev) < B43_STAT_STARTED) 3052 return; 3053 b43_set_status(dev, B43_STAT_INITIALIZED); 3054 3055 mutex_unlock(&wl->mutex); 3056 /* Must unlock as it would otherwise deadlock. No races here. 3057 * Cancel the possibly running self-rearming periodic work. */ 3058 cancel_delayed_work_sync(&dev->periodic_work); 3059 mutex_lock(&wl->mutex); 3060 3061 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy. 3062 3063 /* Disable and sync interrupts. */ 3064 spin_lock_irqsave(&wl->irq_lock, flags); 3065 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 3066 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */ 3067 spin_unlock_irqrestore(&wl->irq_lock, flags); 3068 b43_synchronize_irq(dev); 3069 3070 b43_mac_suspend(dev); 3071 free_irq(dev->dev->irq, dev); 3072 b43dbg(wl, "Wireless interface stopped\n"); 3073} 3074 3075/* Locking: wl->mutex */ 3076static int b43_wireless_core_start(struct b43_wldev *dev) 3077{ 3078 int err; 3079 3080 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 3081 3082 drain_txstatus_queue(dev); 3083 err = request_irq(dev->dev->irq, b43_interrupt_handler, 3084 IRQF_SHARED, KBUILD_MODNAME, dev); 3085 if (err) { 3086 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); 3087 goto out; 3088 } 3089 3090 /* We are ready to run. */ 3091 b43_set_status(dev, B43_STAT_STARTED); 3092 3093 /* Start data flow (TX/RX). */ 3094 b43_mac_enable(dev); 3095 b43_interrupt_enable(dev, dev->irq_savedstate); 3096 ieee80211_start_queues(dev->wl->hw); 3097 3098 /* Start maintainance work */ 3099 b43_periodic_tasks_setup(dev); 3100 3101 b43dbg(dev->wl, "Wireless interface started\n"); 3102 out: 3103 return err; 3104} 3105 3106/* Get PHY and RADIO versioning numbers */ 3107static int b43_phy_versioning(struct b43_wldev *dev) 3108{ 3109 struct b43_phy *phy = &dev->phy; 3110 u32 tmp; 3111 u8 analog_type; 3112 u8 phy_type; 3113 u8 phy_rev; 3114 u16 radio_manuf; 3115 u16 radio_ver; 3116 u16 radio_rev; 3117 int unsupported = 0; 3118 3119 /* Get PHY versioning */ 3120 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 3121 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 3122 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 3123 phy_rev = (tmp & B43_PHYVER_VERSION); 3124 switch (phy_type) { 3125 case B43_PHYTYPE_A: 3126 if (phy_rev >= 4) 3127 unsupported = 1; 3128 break; 3129 case B43_PHYTYPE_B: 3130 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 3131 && phy_rev != 7) 3132 unsupported = 1; 3133 break; 3134 case B43_PHYTYPE_G: 3135 if (phy_rev > 8) 3136 unsupported = 1; 3137 break; 3138 default: 3139 unsupported = 1; 3140 }; 3141 if (unsupported) { 3142 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 3143 "(Analog %u, Type %u, Revision %u)\n", 3144 analog_type, phy_type, phy_rev); 3145 return -EOPNOTSUPP; 3146 } 3147 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 3148 analog_type, phy_type, phy_rev); 3149 3150 /* Get RADIO versioning */ 3151 if (dev->dev->bus->chip_id == 0x4317) { 3152 if (dev->dev->bus->chip_rev == 0) 3153 tmp = 0x3205017F; 3154 else if (dev->dev->bus->chip_rev == 1) 3155 tmp = 0x4205017F; 3156 else 3157 tmp = 0x5205017F; 3158 } else { 3159 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3160 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH); 3161 tmp <<= 16; 3162 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3163 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3164 } 3165 radio_manuf = (tmp & 0x00000FFF); 3166 radio_ver = (tmp & 0x0FFFF000) >> 12; 3167 radio_rev = (tmp & 0xF0000000) >> 28; 3168 switch (phy_type) { 3169 case B43_PHYTYPE_A: 3170 if (radio_ver != 0x2060) 3171 unsupported = 1; 3172 if (radio_rev != 1) 3173 unsupported = 1; 3174 if (radio_manuf != 0x17F) 3175 unsupported = 1; 3176 break; 3177 case B43_PHYTYPE_B: 3178 if ((radio_ver & 0xFFF0) != 0x2050) 3179 unsupported = 1; 3180 break; 3181 case B43_PHYTYPE_G: 3182 if (radio_ver != 0x2050) 3183 unsupported = 1; 3184 break; 3185 default: 3186 B43_WARN_ON(1); 3187 } 3188 if (unsupported) { 3189 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 3190 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 3191 radio_manuf, radio_ver, radio_rev); 3192 return -EOPNOTSUPP; 3193 } 3194 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 3195 radio_manuf, radio_ver, radio_rev); 3196 3197 phy->radio_manuf = radio_manuf; 3198 phy->radio_ver = radio_ver; 3199 phy->radio_rev = radio_rev; 3200 3201 phy->analog = analog_type; 3202 phy->type = phy_type; 3203 phy->rev = phy_rev; 3204 3205 return 0; 3206} 3207 3208static void setup_struct_phy_for_init(struct b43_wldev *dev, 3209 struct b43_phy *phy) 3210{ 3211 struct b43_txpower_lo_control *lo; 3212 int i; 3213 3214 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); 3215 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); 3216 3217 /* Flags */ 3218 phy->locked = 0; 3219 3220 phy->aci_enable = 0; 3221 phy->aci_wlan_automatic = 0; 3222 phy->aci_hw_rssi = 0; 3223 3224 lo = phy->lo_control; 3225 if (lo) { 3226 memset(lo, 0, sizeof(*(phy->lo_control))); 3227 lo->rebuild = 1; 3228 lo->tx_bias = 0xFF; 3229 } 3230 phy->max_lb_gain = 0; 3231 phy->trsw_rx_gain = 0; 3232 phy->txpwr_offset = 0; 3233 3234 /* NRSSI */ 3235 phy->nrssislope = 0; 3236 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) 3237 phy->nrssi[i] = -1000; 3238 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) 3239 phy->nrssi_lt[i] = i; 3240 3241 phy->lofcal = 0xFFFF; 3242 phy->initval = 0xFFFF; 3243 3244 spin_lock_init(&phy->lock); 3245 phy->interfmode = B43_INTERFMODE_NONE; 3246 phy->channel = 0xFF; 3247 3248 phy->hardware_power_control = !!modparam_hwpctl; 3249} 3250 3251static void setup_struct_wldev_for_init(struct b43_wldev *dev) 3252{ 3253 /* Flags */ 3254 dev->reg124_set_0x4 = 0; 3255 3256 /* Stats */ 3257 memset(&dev->stats, 0, sizeof(dev->stats)); 3258 3259 setup_struct_phy_for_init(dev, &dev->phy); 3260 3261 /* IRQ related flags */ 3262 dev->irq_reason = 0; 3263 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 3264 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE; 3265 3266 dev->mac_suspended = 1; 3267 3268 /* Noise calculation context */ 3269 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 3270} 3271 3272static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 3273{ 3274 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 3275 u32 hf; 3276 3277 if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST)) 3278 return; 3279 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 3280 return; 3281 3282 hf = b43_hf_read(dev); 3283 if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD) 3284 hf |= B43_HF_BTCOEXALT; 3285 else 3286 hf |= B43_HF_BTCOEX; 3287 b43_hf_write(dev, hf); 3288 //TODO 3289} 3290 3291static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 3292{ //TODO 3293} 3294 3295static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 3296{ 3297#ifdef CONFIG_SSB_DRIVER_PCICORE 3298 struct ssb_bus *bus = dev->dev->bus; 3299 u32 tmp; 3300 3301 if (bus->pcicore.dev && 3302 bus->pcicore.dev->id.coreid == SSB_DEV_PCI && 3303 bus->pcicore.dev->id.revision <= 5) { 3304 /* IMCFGLO timeouts workaround. */ 3305 tmp = ssb_read32(dev->dev, SSB_IMCFGLO); 3306 tmp &= ~SSB_IMCFGLO_REQTO; 3307 tmp &= ~SSB_IMCFGLO_SERTO; 3308 switch (bus->bustype) { 3309 case SSB_BUSTYPE_PCI: 3310 case SSB_BUSTYPE_PCMCIA: 3311 tmp |= 0x32; 3312 break; 3313 case SSB_BUSTYPE_SSB: 3314 tmp |= 0x53; 3315 break; 3316 } 3317 ssb_write32(dev->dev, SSB_IMCFGLO, tmp); 3318 } 3319#endif /* CONFIG_SSB_DRIVER_PCICORE */ 3320} 3321 3322/* Shutdown a wireless core */ 3323/* Locking: wl->mutex */ 3324static void b43_wireless_core_exit(struct b43_wldev *dev) 3325{ 3326 struct b43_phy *phy = &dev->phy; 3327 3328 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED); 3329 if (b43_status(dev) != B43_STAT_INITIALIZED) 3330 return; 3331 b43_set_status(dev, B43_STAT_UNINIT); 3332 3333 b43_rng_exit(dev->wl); 3334 b43_pio_free(dev); 3335 b43_dma_free(dev); 3336 b43_chip_exit(dev); 3337 b43_radio_turn_off(dev); 3338 b43_switch_analog(dev, 0); 3339 if (phy->dyn_tssi_tbl) 3340 kfree(phy->tssi2dbm); 3341 kfree(phy->lo_control); 3342 phy->lo_control = NULL; 3343 ssb_device_disable(dev->dev, 0); 3344 ssb_bus_may_powerdown(dev->dev->bus); 3345} 3346 3347/* Initialize a wireless core */ 3348static int b43_wireless_core_init(struct b43_wldev *dev) 3349{ 3350 struct b43_wl *wl = dev->wl; 3351 struct ssb_bus *bus = dev->dev->bus; 3352 struct ssb_sprom *sprom = &bus->sprom; 3353 struct b43_phy *phy = &dev->phy; 3354 int err; 3355 u32 hf, tmp; 3356 3357 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3358 3359 err = ssb_bus_powerup(bus, 0); 3360 if (err) 3361 goto out; 3362 if (!ssb_device_is_enabled(dev->dev)) { 3363 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 3364 b43_wireless_core_reset(dev, tmp); 3365 } 3366 3367 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) { 3368 phy->lo_control = 3369 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL); 3370 if (!phy->lo_control) { 3371 err = -ENOMEM; 3372 goto err_busdown; 3373 } 3374 } 3375 setup_struct_wldev_for_init(dev); 3376 3377 err = b43_phy_init_tssi2dbm_table(dev); 3378 if (err) 3379 goto err_kfree_lo_control; 3380 3381 /* Enable IRQ routing to this device. */ 3382 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 3383 3384 b43_imcfglo_timeouts_workaround(dev); 3385 b43_bluetooth_coext_disable(dev); 3386 b43_phy_early_init(dev); 3387 err = b43_chip_init(dev); 3388 if (err) 3389 goto err_kfree_tssitbl; 3390 b43_shm_write16(dev, B43_SHM_SHARED, 3391 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 3392 hf = b43_hf_read(dev); 3393 if (phy->type == B43_PHYTYPE_G) { 3394 hf |= B43_HF_SYMW; 3395 if (phy->rev == 1) 3396 hf |= B43_HF_GDCW; 3397 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL) 3398 hf |= B43_HF_OFDMPABOOST; 3399 } else if (phy->type == B43_PHYTYPE_B) { 3400 hf |= B43_HF_SYMW; 3401 if (phy->rev >= 2 && phy->radio_ver == 0x2050) 3402 hf &= ~B43_HF_GDCW; 3403 } 3404 b43_hf_write(dev, hf); 3405 3406 /* Short/Long Retry Limit. 3407 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing 3408 * the chip-internal counter. 3409 */ 3410 tmp = limit_value(modparam_short_retry, 0, 0xF); 3411 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, tmp); 3412 tmp = limit_value(modparam_long_retry, 0, 0xF); 3413 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, tmp); 3414 3415 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 3416 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 3417 3418 /* Disable sending probe responses from firmware. 3419 * Setting the MaxTime to one usec will always trigger 3420 * a timeout, so we never send any probe resp. 3421 * A timeout of zero is infinite. */ 3422 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 3423 3424 b43_rate_memory_init(dev); 3425 3426 /* Minimum Contention Window */ 3427 if (phy->type == B43_PHYTYPE_B) { 3428 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 3429 } else { 3430 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 3431 } 3432 /* Maximum Contention Window */ 3433 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 3434 3435 do { 3436 if (b43_using_pio(dev)) { 3437 err = b43_pio_init(dev); 3438 } else { 3439 err = b43_dma_init(dev); 3440 if (!err) 3441 b43_qos_init(dev); 3442 } 3443 } while (err == -EAGAIN); 3444 if (err) 3445 goto err_chip_exit; 3446 3447//FIXME 3448#if 1 3449 b43_write16(dev, 0x0612, 0x0050); 3450 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050); 3451 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4); 3452#endif 3453 3454 b43_bluetooth_coext_enable(dev); 3455 3456 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */ 3457 memset(wl->bssid, 0, ETH_ALEN); 3458 b43_upload_card_macaddress(dev, NULL); 3459 b43_security_init(dev); 3460 b43_rng_init(wl); 3461 3462 b43_set_status(dev, B43_STAT_INITIALIZED); 3463 3464 out: 3465 return err; 3466 3467 err_chip_exit: 3468 b43_chip_exit(dev); 3469 err_kfree_tssitbl: 3470 if (phy->dyn_tssi_tbl) 3471 kfree(phy->tssi2dbm); 3472 err_kfree_lo_control: 3473 kfree(phy->lo_control); 3474 phy->lo_control = NULL; 3475 err_busdown: 3476 ssb_bus_may_powerdown(bus); 3477 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3478 return err; 3479} 3480 3481static int b43_add_interface(struct ieee80211_hw *hw, 3482 struct ieee80211_if_init_conf *conf) 3483{ 3484 struct b43_wl *wl = hw_to_b43_wl(hw); 3485 struct b43_wldev *dev; 3486 unsigned long flags; 3487 int err = -EOPNOTSUPP; 3488 int did_init = 0; 3489 3490 mutex_lock(&wl->mutex); 3491 if ((conf->type != IEEE80211_IF_TYPE_MNTR) && wl->operating) 3492 goto out_mutex_unlock; 3493 3494 b43dbg(wl, "Adding Interface type %d\n", conf->type); 3495 3496 dev = wl->current_dev; 3497 if (b43_status(dev) < B43_STAT_INITIALIZED) { 3498 err = b43_wireless_core_init(dev); 3499 if (err) 3500 goto out_mutex_unlock; 3501 did_init = 1; 3502 } 3503 if (b43_status(dev) < B43_STAT_STARTED) { 3504 err = b43_wireless_core_start(dev); 3505 if (err) { 3506 if (did_init) 3507 b43_wireless_core_exit(dev); 3508 goto out_mutex_unlock; 3509 } 3510 } 3511 3512 spin_lock_irqsave(&wl->irq_lock, flags); 3513 switch (conf->type) { 3514 case IEEE80211_IF_TYPE_MNTR: 3515 wl->monitor++; 3516 break; 3517 default: 3518 wl->operating = 1; 3519 wl->if_id = conf->if_id; 3520 wl->if_type = conf->type; 3521 b43_upload_card_macaddress(dev, conf->mac_addr); 3522 } 3523 b43_adjust_opmode(dev); 3524 spin_unlock_irqrestore(&wl->irq_lock, flags); 3525 3526 err = 0; 3527 out_mutex_unlock: 3528 mutex_unlock(&wl->mutex); 3529 3530 return err; 3531} 3532 3533static void b43_remove_interface(struct ieee80211_hw *hw, 3534 struct ieee80211_if_init_conf *conf) 3535{ 3536 struct b43_wl *wl = hw_to_b43_wl(hw); 3537 struct b43_wldev *dev; 3538 unsigned long flags; 3539 3540 b43dbg(wl, "Removing Interface type %d\n", conf->type); 3541 3542 mutex_lock(&wl->mutex); 3543 if (conf->type == IEEE80211_IF_TYPE_MNTR) { 3544 wl->monitor--; 3545 B43_WARN_ON(wl->monitor < 0); 3546 } else { 3547 B43_WARN_ON(!wl->operating); 3548 wl->operating = 0; 3549 } 3550 3551 dev = wl->current_dev; 3552 if (!wl->operating && wl->monitor == 0) { 3553 /* No interface left. */ 3554 if (b43_status(dev) >= B43_STAT_STARTED) 3555 b43_wireless_core_stop(dev); 3556 b43_wireless_core_exit(dev); 3557 } else { 3558 /* Just monitor interfaces left. */ 3559 spin_lock_irqsave(&wl->irq_lock, flags); 3560 b43_adjust_opmode(dev); 3561 if (!wl->operating) 3562 b43_upload_card_macaddress(dev, NULL); 3563 spin_unlock_irqrestore(&wl->irq_lock, flags); 3564 } 3565 mutex_unlock(&wl->mutex); 3566} 3567 3568static const struct ieee80211_ops b43_hw_ops = { 3569 .tx = b43_tx, 3570 .conf_tx = b43_conf_tx, 3571 .add_interface = b43_add_interface, 3572 .remove_interface = b43_remove_interface, 3573 .config = b43_dev_config, 3574 .config_interface = b43_config_interface, 3575 .set_multicast_list = b43_set_multicast_list, 3576 .set_key = b43_dev_set_key, 3577 .get_stats = b43_get_stats, 3578 .get_tx_stats = b43_get_tx_stats, 3579}; 3580 3581/* Hard-reset the chip. Do not call this directly. 3582 * Use b43_controller_restart() 3583 */ 3584static void b43_chip_reset(struct work_struct *work) 3585{ 3586 struct b43_wldev *dev = 3587 container_of(work, struct b43_wldev, restart_work); 3588 struct b43_wl *wl = dev->wl; 3589 int err = 0; 3590 int prev_status; 3591 3592 mutex_lock(&wl->mutex); 3593 3594 prev_status = b43_status(dev); 3595 /* Bring the device down... */ 3596 if (prev_status >= B43_STAT_STARTED) 3597 b43_wireless_core_stop(dev); 3598 if (prev_status >= B43_STAT_INITIALIZED) 3599 b43_wireless_core_exit(dev); 3600 3601 /* ...and up again. */ 3602 if (prev_status >= B43_STAT_INITIALIZED) { 3603 err = b43_wireless_core_init(dev); 3604 if (err) 3605 goto out; 3606 } 3607 if (prev_status >= B43_STAT_STARTED) { 3608 err = b43_wireless_core_start(dev); 3609 if (err) { 3610 b43_wireless_core_exit(dev); 3611 goto out; 3612 } 3613 } 3614 out: 3615 mutex_unlock(&wl->mutex); 3616 if (err) 3617 b43err(wl, "Controller restart FAILED\n"); 3618 else 3619 b43info(wl, "Controller restarted\n"); 3620} 3621 3622static int b43_setup_modes(struct b43_wldev *dev, 3623 int have_aphy, int have_bphy, int have_gphy) 3624{ 3625 struct ieee80211_hw *hw = dev->wl->hw; 3626 struct ieee80211_hw_mode *mode; 3627 struct b43_phy *phy = &dev->phy; 3628 int cnt = 0; 3629 int err; 3630 3631/*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */ 3632 have_aphy = 0; 3633 3634 phy->possible_phymodes = 0; 3635 for (; 1; cnt++) { 3636 if (have_aphy) { 3637 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3638 mode = &phy->hwmodes[cnt]; 3639 3640 mode->mode = MODE_IEEE80211A; 3641 mode->num_channels = b43_a_chantable_size; 3642 mode->channels = b43_a_chantable; 3643 mode->num_rates = b43_a_ratetable_size; 3644 mode->rates = b43_a_ratetable; 3645 err = ieee80211_register_hwmode(hw, mode); 3646 if (err) 3647 return err; 3648 3649 phy->possible_phymodes |= B43_PHYMODE_A; 3650 have_aphy = 0; 3651 continue; 3652 } 3653 if (have_bphy) { 3654 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3655 mode = &phy->hwmodes[cnt]; 3656 3657 mode->mode = MODE_IEEE80211B; 3658 mode->num_channels = b43_bg_chantable_size; 3659 mode->channels = b43_bg_chantable; 3660 mode->num_rates = b43_b_ratetable_size; 3661 mode->rates = b43_b_ratetable; 3662 err = ieee80211_register_hwmode(hw, mode); 3663 if (err) 3664 return err; 3665 3666 phy->possible_phymodes |= B43_PHYMODE_B; 3667 have_bphy = 0; 3668 continue; 3669 } 3670 if (have_gphy) { 3671 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3672 mode = &phy->hwmodes[cnt]; 3673 3674 mode->mode = MODE_IEEE80211G; 3675 mode->num_channels = b43_bg_chantable_size; 3676 mode->channels = b43_bg_chantable; 3677 mode->num_rates = b43_g_ratetable_size; 3678 mode->rates = b43_g_ratetable; 3679 err = ieee80211_register_hwmode(hw, mode); 3680 if (err) 3681 return err; 3682 3683 phy->possible_phymodes |= B43_PHYMODE_G; 3684 have_gphy = 0; 3685 continue; 3686 } 3687 break; 3688 } 3689 3690 return 0; 3691} 3692 3693static void b43_wireless_core_detach(struct b43_wldev *dev) 3694{ 3695 /* We release firmware that late to not be required to re-request 3696 * is all the time when we reinit the core. */ 3697 b43_release_firmware(dev); 3698} 3699 3700static int b43_wireless_core_attach(struct b43_wldev *dev) 3701{ 3702 struct b43_wl *wl = dev->wl; 3703 struct ssb_bus *bus = dev->dev->bus; 3704 struct pci_dev *pdev = bus->host_pci; 3705 int err; 3706 int have_aphy = 0, have_bphy = 0, have_gphy = 0; 3707 u32 tmp; 3708 3709 /* Do NOT do any device initialization here. 3710 * Do it in wireless_core_init() instead. 3711 * This function is for gathering basic information about the HW, only. 3712 * Also some structs may be set up here. But most likely you want to have 3713 * that in core_init(), too. 3714 */ 3715 3716 err = ssb_bus_powerup(bus, 0); 3717 if (err) { 3718 b43err(wl, "Bus powerup failed\n"); 3719 goto out; 3720 } 3721 /* Get the PHY type. */ 3722 if (dev->dev->id.revision >= 5) { 3723 u32 tmshigh; 3724 3725 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 3726 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY); 3727 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY); 3728 if (!have_aphy && !have_gphy) 3729 have_bphy = 1; 3730 } else if (dev->dev->id.revision == 4) { 3731 have_gphy = 1; 3732 have_aphy = 1; 3733 } else 3734 have_bphy = 1; 3735 3736 /* Initialize LEDs structs. */ 3737 err = b43_leds_init(dev); 3738 if (err) 3739 goto err_powerdown; 3740 3741 dev->phy.gmode = (have_gphy || have_bphy); 3742 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3743 b43_wireless_core_reset(dev, tmp); 3744 3745 err = b43_phy_versioning(dev); 3746 if (err) 3747 goto err_leds_exit; 3748 /* Check if this device supports multiband. */ 3749 if (!pdev || 3750 (pdev->device != 0x4312 && 3751 pdev->device != 0x4319 && pdev->device != 0x4324)) { 3752 /* No multiband support. */ 3753 have_aphy = 0; 3754 have_bphy = 0; 3755 have_gphy = 0; 3756 switch (dev->phy.type) { 3757 case B43_PHYTYPE_A: 3758 have_aphy = 1; 3759 break; 3760 case B43_PHYTYPE_B: 3761 have_bphy = 1; 3762 break; 3763 case B43_PHYTYPE_G: 3764 have_gphy = 1; 3765 break; 3766 default: 3767 B43_WARN_ON(1); 3768 } 3769 } 3770 dev->phy.gmode = (have_gphy || have_bphy); 3771 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3772 b43_wireless_core_reset(dev, tmp); 3773 3774 err = b43_validate_chipaccess(dev); 3775 if (err) 3776 goto err_leds_exit; 3777 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy); 3778 if (err) 3779 goto err_leds_exit; 3780 3781 /* Now set some default "current_dev" */ 3782 if (!wl->current_dev) 3783 wl->current_dev = dev; 3784 INIT_WORK(&dev->restart_work, b43_chip_reset); 3785 3786 b43_radio_turn_off(dev); 3787 b43_switch_analog(dev, 0); 3788 ssb_device_disable(dev->dev, 0); 3789 ssb_bus_may_powerdown(bus); 3790 3791out: 3792 return err; 3793 3794err_leds_exit: 3795 b43_leds_exit(dev); 3796err_powerdown: 3797 ssb_bus_may_powerdown(bus); 3798 return err; 3799} 3800 3801static void b43_one_core_detach(struct ssb_device *dev) 3802{ 3803 struct b43_wldev *wldev; 3804 struct b43_wl *wl; 3805 3806 wldev = ssb_get_drvdata(dev); 3807 wl = wldev->wl; 3808 cancel_work_sync(&wldev->restart_work); 3809 b43_debugfs_remove_device(wldev); 3810 b43_wireless_core_detach(wldev); 3811 list_del(&wldev->list); 3812 wl->nr_devs--; 3813 ssb_set_drvdata(dev, NULL); 3814 kfree(wldev); 3815} 3816 3817static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 3818{ 3819 struct b43_wldev *wldev; 3820 struct pci_dev *pdev; 3821 int err = -ENOMEM; 3822 3823 if (!list_empty(&wl->devlist)) { 3824 /* We are not the first core on this chip. */ 3825 pdev = dev->bus->host_pci; 3826 /* Only special chips support more than one wireless 3827 * core, although some of the other chips have more than 3828 * one wireless core as well. Check for this and 3829 * bail out early. 3830 */ 3831 if (!pdev || 3832 ((pdev->device != 0x4321) && 3833 (pdev->device != 0x4313) && (pdev->device != 0x431A))) { 3834 b43dbg(wl, "Ignoring unconnected 802.11 core\n"); 3835 return -ENODEV; 3836 } 3837 } 3838 3839 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 3840 if (!wldev) 3841 goto out; 3842 3843 wldev->dev = dev; 3844 wldev->wl = wl; 3845 b43_set_status(wldev, B43_STAT_UNINIT); 3846 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 3847 tasklet_init(&wldev->isr_tasklet, 3848 (void (*)(unsigned long))b43_interrupt_tasklet, 3849 (unsigned long)wldev); 3850 if (modparam_pio) 3851 wldev->__using_pio = 1; 3852 INIT_LIST_HEAD(&wldev->list); 3853 3854 err = b43_wireless_core_attach(wldev); 3855 if (err) 3856 goto err_kfree_wldev; 3857 3858 list_add(&wldev->list, &wl->devlist); 3859 wl->nr_devs++; 3860 ssb_set_drvdata(dev, wldev); 3861 b43_debugfs_add_device(wldev); 3862 3863 out: 3864 return err; 3865 3866 err_kfree_wldev: 3867 kfree(wldev); 3868 return err; 3869} 3870 3871static void b43_sprom_fixup(struct ssb_bus *bus) 3872{ 3873 /* boardflags workarounds */ 3874 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 3875 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 3876 bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST; 3877 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3878 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 3879 bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL; 3880 3881 /* Handle case when gain is not set in sprom */ 3882 if (bus->sprom.r1.antenna_gain_a == 0xFF) 3883 bus->sprom.r1.antenna_gain_a = 2; 3884 if (bus->sprom.r1.antenna_gain_bg == 0xFF) 3885 bus->sprom.r1.antenna_gain_bg = 2; 3886 3887 /* Convert Antennagain values to Q5.2 */ 3888 bus->sprom.r1.antenna_gain_a <<= 2; 3889 bus->sprom.r1.antenna_gain_bg <<= 2; 3890} 3891 3892static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 3893{ 3894 struct ieee80211_hw *hw = wl->hw; 3895 3896 ssb_set_devtypedata(dev, NULL); 3897 ieee80211_free_hw(hw); 3898} 3899 3900static int b43_wireless_init(struct ssb_device *dev) 3901{ 3902 struct ssb_sprom *sprom = &dev->bus->sprom; 3903 struct ieee80211_hw *hw; 3904 struct b43_wl *wl; 3905 int err = -ENOMEM; 3906 3907 b43_sprom_fixup(dev->bus); 3908 3909 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 3910 if (!hw) { 3911 b43err(NULL, "Could not allocate ieee80211 device\n"); 3912 goto out; 3913 } 3914 3915 /* fill hw info */ 3916 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 3917 IEEE80211_HW_MONITOR_DURING_OPER; 3918 hw->max_signal = 100; 3919 hw->max_rssi = -110; 3920 hw->max_noise = -110; 3921 hw->queues = 1; /* FIXME: hardware has more queues */ 3922 SET_IEEE80211_DEV(hw, dev->dev); 3923 if (is_valid_ether_addr(sprom->r1.et1mac)) 3924 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac); 3925 else 3926 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac); 3927 3928 /* Get and initialize struct b43_wl */ 3929 wl = hw_to_b43_wl(hw); 3930 memset(wl, 0, sizeof(*wl)); 3931 wl->hw = hw; 3932 spin_lock_init(&wl->irq_lock); 3933 spin_lock_init(&wl->leds_lock); 3934 mutex_init(&wl->mutex); 3935 INIT_LIST_HEAD(&wl->devlist); 3936 3937 ssb_set_devtypedata(dev, wl); 3938 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id); 3939 err = 0; 3940 out: 3941 return err; 3942} 3943 3944static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id) 3945{ 3946 struct b43_wl *wl; 3947 int err; 3948 int first = 0; 3949 3950 wl = ssb_get_devtypedata(dev); 3951 if (!wl) { 3952 /* Probing the first core. Must setup common struct b43_wl */ 3953 first = 1; 3954 err = b43_wireless_init(dev); 3955 if (err) 3956 goto out; 3957 wl = ssb_get_devtypedata(dev); 3958 B43_WARN_ON(!wl); 3959 } 3960 err = b43_one_core_attach(dev, wl); 3961 if (err) 3962 goto err_wireless_exit; 3963 3964 if (first) { 3965 err = ieee80211_register_hw(wl->hw); 3966 if (err) 3967 goto err_one_core_detach; 3968 } 3969 3970 out: 3971 return err; 3972 3973 err_one_core_detach: 3974 b43_one_core_detach(dev); 3975 err_wireless_exit: 3976 if (first) 3977 b43_wireless_exit(dev, wl); 3978 return err; 3979} 3980 3981static void b43_remove(struct ssb_device *dev) 3982{ 3983 struct b43_wl *wl = ssb_get_devtypedata(dev); 3984 struct b43_wldev *wldev = ssb_get_drvdata(dev); 3985 3986 B43_WARN_ON(!wl); 3987 if (wl->current_dev == wldev) 3988 ieee80211_unregister_hw(wl->hw); 3989 3990 b43_one_core_detach(dev); 3991 3992 if (list_empty(&wl->devlist)) { 3993 /* Last core on the chip unregistered. 3994 * We can destroy common struct b43_wl. 3995 */ 3996 b43_wireless_exit(dev, wl); 3997 } 3998} 3999 4000/* Perform a hardware reset. This can be called from any context. */ 4001void b43_controller_restart(struct b43_wldev *dev, const char *reason) 4002{ 4003 /* Must avoid requeueing, if we are in shutdown. */ 4004 if (b43_status(dev) < B43_STAT_INITIALIZED) 4005 return; 4006 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 4007 queue_work(dev->wl->hw->workqueue, &dev->restart_work); 4008} 4009 4010#ifdef CONFIG_PM 4011 4012static int b43_suspend(struct ssb_device *dev, pm_message_t state) 4013{ 4014 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4015 struct b43_wl *wl = wldev->wl; 4016 4017 b43dbg(wl, "Suspending...\n"); 4018 4019 mutex_lock(&wl->mutex); 4020 wldev->suspend_init_status = b43_status(wldev); 4021 if (wldev->suspend_init_status >= B43_STAT_STARTED) 4022 b43_wireless_core_stop(wldev); 4023 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) 4024 b43_wireless_core_exit(wldev); 4025 mutex_unlock(&wl->mutex); 4026 4027 b43dbg(wl, "Device suspended.\n"); 4028 4029 return 0; 4030} 4031 4032static int b43_resume(struct ssb_device *dev) 4033{ 4034 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4035 struct b43_wl *wl = wldev->wl; 4036 int err = 0; 4037 4038 b43dbg(wl, "Resuming...\n"); 4039 4040 mutex_lock(&wl->mutex); 4041 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) { 4042 err = b43_wireless_core_init(wldev); 4043 if (err) { 4044 b43err(wl, "Resume failed at core init\n"); 4045 goto out; 4046 } 4047 } 4048 if (wldev->suspend_init_status >= B43_STAT_STARTED) { 4049 err = b43_wireless_core_start(wldev); 4050 if (err) { 4051 b43_wireless_core_exit(wldev); 4052 b43err(wl, "Resume failed at core start\n"); 4053 goto out; 4054 } 4055 } 4056 mutex_unlock(&wl->mutex); 4057 4058 b43dbg(wl, "Device resumed.\n"); 4059 out: 4060 return err; 4061} 4062 4063#else /* CONFIG_PM */ 4064# define b43_suspend NULL 4065# define b43_resume NULL 4066#endif /* CONFIG_PM */ 4067 4068static struct ssb_driver b43_ssb_driver = { 4069 .name = KBUILD_MODNAME, 4070 .id_table = b43_ssb_tbl, 4071 .probe = b43_probe, 4072 .remove = b43_remove, 4073 .suspend = b43_suspend, 4074 .resume = b43_resume, 4075}; 4076 4077static int __init b43_init(void) 4078{ 4079 int err; 4080 4081 b43_debugfs_init(); 4082 err = b43_pcmcia_init(); 4083 if (err) 4084 goto err_dfs_exit; 4085 err = ssb_driver_register(&b43_ssb_driver); 4086 if (err) 4087 goto err_pcmcia_exit; 4088 4089 return err; 4090 4091err_pcmcia_exit: 4092 b43_pcmcia_exit(); 4093err_dfs_exit: 4094 b43_debugfs_exit(); 4095 return err; 4096} 4097 4098static void __exit b43_exit(void) 4099{ 4100 ssb_driver_unregister(&b43_ssb_driver); 4101 b43_pcmcia_exit(); 4102 b43_debugfs_exit(); 4103} 4104 4105module_init(b43_init) 4106module_exit(b43_exit) 4107