main.c revision 4da909e7b572b561d8150f9d41b04bcfff386222
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 SDIO support 12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> 13 14 Some parts of the code in this file are derived from the ipw2200 15 driver Copyright(c) 2003 - 2004 Intel Corporation. 16 17 This program is free software; you can redistribute it and/or modify 18 it under the terms of the GNU General Public License as published by 19 the Free Software Foundation; either version 2 of the License, or 20 (at your option) any later version. 21 22 This program is distributed in the hope that it will be useful, 23 but WITHOUT ANY WARRANTY; without even the implied warranty of 24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 GNU General Public License for more details. 26 27 You should have received a copy of the GNU General Public License 28 along with this program; see the file COPYING. If not, write to 29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 30 Boston, MA 02110-1301, USA. 31 32*/ 33 34#include <linux/delay.h> 35#include <linux/init.h> 36#include <linux/moduleparam.h> 37#include <linux/if_arp.h> 38#include <linux/etherdevice.h> 39#include <linux/firmware.h> 40#include <linux/wireless.h> 41#include <linux/workqueue.h> 42#include <linux/skbuff.h> 43#include <linux/io.h> 44#include <linux/dma-mapping.h> 45#include <linux/slab.h> 46#include <asm/unaligned.h> 47 48#include "b43.h" 49#include "main.h" 50#include "debugfs.h" 51#include "phy_common.h" 52#include "phy_g.h" 53#include "phy_n.h" 54#include "dma.h" 55#include "pio.h" 56#include "sysfs.h" 57#include "xmit.h" 58#include "lo.h" 59#include "pcmcia.h" 60#include "sdio.h" 61#include <linux/mmc/sdio_func.h> 62 63MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 64MODULE_AUTHOR("Martin Langer"); 65MODULE_AUTHOR("Stefano Brivio"); 66MODULE_AUTHOR("Michael Buesch"); 67MODULE_AUTHOR("Gábor Stefanik"); 68MODULE_LICENSE("GPL"); 69 70MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID); 71MODULE_FIRMWARE("b43/ucode11.fw"); 72MODULE_FIRMWARE("b43/ucode13.fw"); 73MODULE_FIRMWARE("b43/ucode14.fw"); 74MODULE_FIRMWARE("b43/ucode15.fw"); 75MODULE_FIRMWARE("b43/ucode16_mimo.fw"); 76MODULE_FIRMWARE("b43/ucode5.fw"); 77MODULE_FIRMWARE("b43/ucode9.fw"); 78 79static int modparam_bad_frames_preempt; 80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 81MODULE_PARM_DESC(bad_frames_preempt, 82 "enable(1) / disable(0) Bad Frames Preemption"); 83 84static char modparam_fwpostfix[16]; 85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 87 88static int modparam_hwpctl; 89module_param_named(hwpctl, modparam_hwpctl, int, 0444); 90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 91 92static int modparam_nohwcrypt; 93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 95 96static int modparam_hwtkip; 97module_param_named(hwtkip, modparam_hwtkip, int, 0444); 98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip."); 99 100static int modparam_qos = 1; 101module_param_named(qos, modparam_qos, int, 0444); 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); 103 104static int modparam_btcoex = 1; 105module_param_named(btcoex, modparam_btcoex, int, 0444); 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)"); 107 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT; 109module_param_named(verbose, b43_modparam_verbose, int, 0644); 110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug"); 111 112static int b43_modparam_pio = B43_PIO_DEFAULT; 113module_param_named(pio, b43_modparam_pio, int, 0644); 114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO"); 115 116static const struct ssb_device_id b43_ssb_tbl[] = { 117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 119 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 123 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12), 124 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 125 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15), 126 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), 127 SSB_DEVTABLE_END 128}; 129 130MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 131 132/* Channel and ratetables are shared for all devices. 133 * They can't be const, because ieee80211 puts some precalculated 134 * data in there. This data is the same for all devices, so we don't 135 * get concurrency issues */ 136#define RATETAB_ENT(_rateid, _flags) \ 137 { \ 138 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ 139 .hw_value = (_rateid), \ 140 .flags = (_flags), \ 141 } 142 143/* 144 * NOTE: When changing this, sync with xmit.c's 145 * b43_plcp_get_bitrate_idx_* functions! 146 */ 147static struct ieee80211_rate __b43_ratetable[] = { 148 RATETAB_ENT(B43_CCK_RATE_1MB, 0), 149 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), 150 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), 151 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), 152 RATETAB_ENT(B43_OFDM_RATE_6MB, 0), 153 RATETAB_ENT(B43_OFDM_RATE_9MB, 0), 154 RATETAB_ENT(B43_OFDM_RATE_12MB, 0), 155 RATETAB_ENT(B43_OFDM_RATE_18MB, 0), 156 RATETAB_ENT(B43_OFDM_RATE_24MB, 0), 157 RATETAB_ENT(B43_OFDM_RATE_36MB, 0), 158 RATETAB_ENT(B43_OFDM_RATE_48MB, 0), 159 RATETAB_ENT(B43_OFDM_RATE_54MB, 0), 160}; 161 162#define b43_a_ratetable (__b43_ratetable + 4) 163#define b43_a_ratetable_size 8 164#define b43_b_ratetable (__b43_ratetable + 0) 165#define b43_b_ratetable_size 4 166#define b43_g_ratetable (__b43_ratetable + 0) 167#define b43_g_ratetable_size 12 168 169#define CHAN4G(_channel, _freq, _flags) { \ 170 .band = IEEE80211_BAND_2GHZ, \ 171 .center_freq = (_freq), \ 172 .hw_value = (_channel), \ 173 .flags = (_flags), \ 174 .max_antenna_gain = 0, \ 175 .max_power = 30, \ 176} 177static struct ieee80211_channel b43_2ghz_chantable[] = { 178 CHAN4G(1, 2412, 0), 179 CHAN4G(2, 2417, 0), 180 CHAN4G(3, 2422, 0), 181 CHAN4G(4, 2427, 0), 182 CHAN4G(5, 2432, 0), 183 CHAN4G(6, 2437, 0), 184 CHAN4G(7, 2442, 0), 185 CHAN4G(8, 2447, 0), 186 CHAN4G(9, 2452, 0), 187 CHAN4G(10, 2457, 0), 188 CHAN4G(11, 2462, 0), 189 CHAN4G(12, 2467, 0), 190 CHAN4G(13, 2472, 0), 191 CHAN4G(14, 2484, 0), 192}; 193#undef CHAN4G 194 195#define CHAN5G(_channel, _flags) { \ 196 .band = IEEE80211_BAND_5GHZ, \ 197 .center_freq = 5000 + (5 * (_channel)), \ 198 .hw_value = (_channel), \ 199 .flags = (_flags), \ 200 .max_antenna_gain = 0, \ 201 .max_power = 30, \ 202} 203static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { 204 CHAN5G(32, 0), CHAN5G(34, 0), 205 CHAN5G(36, 0), CHAN5G(38, 0), 206 CHAN5G(40, 0), CHAN5G(42, 0), 207 CHAN5G(44, 0), CHAN5G(46, 0), 208 CHAN5G(48, 0), CHAN5G(50, 0), 209 CHAN5G(52, 0), CHAN5G(54, 0), 210 CHAN5G(56, 0), CHAN5G(58, 0), 211 CHAN5G(60, 0), CHAN5G(62, 0), 212 CHAN5G(64, 0), CHAN5G(66, 0), 213 CHAN5G(68, 0), CHAN5G(70, 0), 214 CHAN5G(72, 0), CHAN5G(74, 0), 215 CHAN5G(76, 0), CHAN5G(78, 0), 216 CHAN5G(80, 0), CHAN5G(82, 0), 217 CHAN5G(84, 0), CHAN5G(86, 0), 218 CHAN5G(88, 0), CHAN5G(90, 0), 219 CHAN5G(92, 0), CHAN5G(94, 0), 220 CHAN5G(96, 0), CHAN5G(98, 0), 221 CHAN5G(100, 0), CHAN5G(102, 0), 222 CHAN5G(104, 0), CHAN5G(106, 0), 223 CHAN5G(108, 0), CHAN5G(110, 0), 224 CHAN5G(112, 0), CHAN5G(114, 0), 225 CHAN5G(116, 0), CHAN5G(118, 0), 226 CHAN5G(120, 0), CHAN5G(122, 0), 227 CHAN5G(124, 0), CHAN5G(126, 0), 228 CHAN5G(128, 0), CHAN5G(130, 0), 229 CHAN5G(132, 0), CHAN5G(134, 0), 230 CHAN5G(136, 0), CHAN5G(138, 0), 231 CHAN5G(140, 0), CHAN5G(142, 0), 232 CHAN5G(144, 0), CHAN5G(145, 0), 233 CHAN5G(146, 0), CHAN5G(147, 0), 234 CHAN5G(148, 0), CHAN5G(149, 0), 235 CHAN5G(150, 0), CHAN5G(151, 0), 236 CHAN5G(152, 0), CHAN5G(153, 0), 237 CHAN5G(154, 0), CHAN5G(155, 0), 238 CHAN5G(156, 0), CHAN5G(157, 0), 239 CHAN5G(158, 0), CHAN5G(159, 0), 240 CHAN5G(160, 0), CHAN5G(161, 0), 241 CHAN5G(162, 0), CHAN5G(163, 0), 242 CHAN5G(164, 0), CHAN5G(165, 0), 243 CHAN5G(166, 0), CHAN5G(168, 0), 244 CHAN5G(170, 0), CHAN5G(172, 0), 245 CHAN5G(174, 0), CHAN5G(176, 0), 246 CHAN5G(178, 0), CHAN5G(180, 0), 247 CHAN5G(182, 0), CHAN5G(184, 0), 248 CHAN5G(186, 0), CHAN5G(188, 0), 249 CHAN5G(190, 0), CHAN5G(192, 0), 250 CHAN5G(194, 0), CHAN5G(196, 0), 251 CHAN5G(198, 0), CHAN5G(200, 0), 252 CHAN5G(202, 0), CHAN5G(204, 0), 253 CHAN5G(206, 0), CHAN5G(208, 0), 254 CHAN5G(210, 0), CHAN5G(212, 0), 255 CHAN5G(214, 0), CHAN5G(216, 0), 256 CHAN5G(218, 0), CHAN5G(220, 0), 257 CHAN5G(222, 0), CHAN5G(224, 0), 258 CHAN5G(226, 0), CHAN5G(228, 0), 259}; 260 261static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { 262 CHAN5G(34, 0), CHAN5G(36, 0), 263 CHAN5G(38, 0), CHAN5G(40, 0), 264 CHAN5G(42, 0), CHAN5G(44, 0), 265 CHAN5G(46, 0), CHAN5G(48, 0), 266 CHAN5G(52, 0), CHAN5G(56, 0), 267 CHAN5G(60, 0), CHAN5G(64, 0), 268 CHAN5G(100, 0), CHAN5G(104, 0), 269 CHAN5G(108, 0), CHAN5G(112, 0), 270 CHAN5G(116, 0), CHAN5G(120, 0), 271 CHAN5G(124, 0), CHAN5G(128, 0), 272 CHAN5G(132, 0), CHAN5G(136, 0), 273 CHAN5G(140, 0), CHAN5G(149, 0), 274 CHAN5G(153, 0), CHAN5G(157, 0), 275 CHAN5G(161, 0), CHAN5G(165, 0), 276 CHAN5G(184, 0), CHAN5G(188, 0), 277 CHAN5G(192, 0), CHAN5G(196, 0), 278 CHAN5G(200, 0), CHAN5G(204, 0), 279 CHAN5G(208, 0), CHAN5G(212, 0), 280 CHAN5G(216, 0), 281}; 282#undef CHAN5G 283 284static struct ieee80211_supported_band b43_band_5GHz_nphy = { 285 .band = IEEE80211_BAND_5GHZ, 286 .channels = b43_5ghz_nphy_chantable, 287 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), 288 .bitrates = b43_a_ratetable, 289 .n_bitrates = b43_a_ratetable_size, 290}; 291 292static struct ieee80211_supported_band b43_band_5GHz_aphy = { 293 .band = IEEE80211_BAND_5GHZ, 294 .channels = b43_5ghz_aphy_chantable, 295 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), 296 .bitrates = b43_a_ratetable, 297 .n_bitrates = b43_a_ratetable_size, 298}; 299 300static struct ieee80211_supported_band b43_band_2GHz = { 301 .band = IEEE80211_BAND_2GHZ, 302 .channels = b43_2ghz_chantable, 303 .n_channels = ARRAY_SIZE(b43_2ghz_chantable), 304 .bitrates = b43_g_ratetable, 305 .n_bitrates = b43_g_ratetable_size, 306}; 307 308static void b43_wireless_core_exit(struct b43_wldev *dev); 309static int b43_wireless_core_init(struct b43_wldev *dev); 310static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev); 311static int b43_wireless_core_start(struct b43_wldev *dev); 312 313static int b43_ratelimit(struct b43_wl *wl) 314{ 315 if (!wl || !wl->current_dev) 316 return 1; 317 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 318 return 1; 319 /* We are up and running. 320 * Ratelimit the messages to avoid DoS over the net. */ 321 return net_ratelimit(); 322} 323 324void b43info(struct b43_wl *wl, const char *fmt, ...) 325{ 326 struct va_format vaf; 327 va_list args; 328 329 if (b43_modparam_verbose < B43_VERBOSITY_INFO) 330 return; 331 if (!b43_ratelimit(wl)) 332 return; 333 334 va_start(args, fmt); 335 336 vaf.fmt = fmt; 337 vaf.va = &args; 338 339 printk(KERN_INFO "b43-%s: %pV", 340 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 341 342 va_end(args); 343} 344 345void b43err(struct b43_wl *wl, const char *fmt, ...) 346{ 347 struct va_format vaf; 348 va_list args; 349 350 if (b43_modparam_verbose < B43_VERBOSITY_ERROR) 351 return; 352 if (!b43_ratelimit(wl)) 353 return; 354 355 va_start(args, fmt); 356 357 vaf.fmt = fmt; 358 vaf.va = &args; 359 360 printk(KERN_ERR "b43-%s ERROR: %pV", 361 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 362 363 va_end(args); 364} 365 366void b43warn(struct b43_wl *wl, const char *fmt, ...) 367{ 368 struct va_format vaf; 369 va_list args; 370 371 if (b43_modparam_verbose < B43_VERBOSITY_WARN) 372 return; 373 if (!b43_ratelimit(wl)) 374 return; 375 376 va_start(args, fmt); 377 378 vaf.fmt = fmt; 379 vaf.va = &args; 380 381 printk(KERN_WARNING "b43-%s warning: %pV", 382 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 383 384 va_end(args); 385} 386 387void b43dbg(struct b43_wl *wl, const char *fmt, ...) 388{ 389 struct va_format vaf; 390 va_list args; 391 392 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 393 return; 394 395 va_start(args, fmt); 396 397 vaf.fmt = fmt; 398 vaf.va = &args; 399 400 printk(KERN_DEBUG "b43-%s debug: %pV", 401 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 402 403 va_end(args); 404} 405 406static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 407{ 408 u32 macctl; 409 410 B43_WARN_ON(offset % 4 != 0); 411 412 macctl = b43_read32(dev, B43_MMIO_MACCTL); 413 if (macctl & B43_MACCTL_BE) 414 val = swab32(val); 415 416 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 417 mmiowb(); 418 b43_write32(dev, B43_MMIO_RAM_DATA, val); 419} 420 421static inline void b43_shm_control_word(struct b43_wldev *dev, 422 u16 routing, u16 offset) 423{ 424 u32 control; 425 426 /* "offset" is the WORD offset. */ 427 control = routing; 428 control <<= 16; 429 control |= offset; 430 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 431} 432 433u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 434{ 435 u32 ret; 436 437 if (routing == B43_SHM_SHARED) { 438 B43_WARN_ON(offset & 0x0001); 439 if (offset & 0x0003) { 440 /* Unaligned access */ 441 b43_shm_control_word(dev, routing, offset >> 2); 442 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 443 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 444 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16; 445 446 goto out; 447 } 448 offset >>= 2; 449 } 450 b43_shm_control_word(dev, routing, offset); 451 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 452out: 453 return ret; 454} 455 456u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset) 457{ 458 u16 ret; 459 460 if (routing == B43_SHM_SHARED) { 461 B43_WARN_ON(offset & 0x0001); 462 if (offset & 0x0003) { 463 /* Unaligned access */ 464 b43_shm_control_word(dev, routing, offset >> 2); 465 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 466 467 goto out; 468 } 469 offset >>= 2; 470 } 471 b43_shm_control_word(dev, routing, offset); 472 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 473out: 474 return ret; 475} 476 477void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 478{ 479 if (routing == B43_SHM_SHARED) { 480 B43_WARN_ON(offset & 0x0001); 481 if (offset & 0x0003) { 482 /* Unaligned access */ 483 b43_shm_control_word(dev, routing, offset >> 2); 484 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 485 value & 0xFFFF); 486 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 487 b43_write16(dev, B43_MMIO_SHM_DATA, 488 (value >> 16) & 0xFFFF); 489 return; 490 } 491 offset >>= 2; 492 } 493 b43_shm_control_word(dev, routing, offset); 494 b43_write32(dev, B43_MMIO_SHM_DATA, value); 495} 496 497void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 498{ 499 if (routing == B43_SHM_SHARED) { 500 B43_WARN_ON(offset & 0x0001); 501 if (offset & 0x0003) { 502 /* Unaligned access */ 503 b43_shm_control_word(dev, routing, offset >> 2); 504 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 505 return; 506 } 507 offset >>= 2; 508 } 509 b43_shm_control_word(dev, routing, offset); 510 b43_write16(dev, B43_MMIO_SHM_DATA, value); 511} 512 513/* Read HostFlags */ 514u64 b43_hf_read(struct b43_wldev *dev) 515{ 516 u64 ret; 517 518 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 519 ret <<= 16; 520 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI); 521 ret <<= 16; 522 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 523 524 return ret; 525} 526 527/* Write HostFlags */ 528void b43_hf_write(struct b43_wldev *dev, u64 value) 529{ 530 u16 lo, mi, hi; 531 532 lo = (value & 0x00000000FFFFULL); 533 mi = (value & 0x0000FFFF0000ULL) >> 16; 534 hi = (value & 0xFFFF00000000ULL) >> 32; 535 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo); 536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi); 537 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi); 538} 539 540/* Read the firmware capabilities bitmask (Opensource firmware only) */ 541static u16 b43_fwcapa_read(struct b43_wldev *dev) 542{ 543 B43_WARN_ON(!dev->fw.opensource); 544 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA); 545} 546 547void b43_tsf_read(struct b43_wldev *dev, u64 *tsf) 548{ 549 u32 low, high; 550 551 B43_WARN_ON(dev->dev->core_rev < 3); 552 553 /* The hardware guarantees us an atomic read, if we 554 * read the low register first. */ 555 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 556 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 557 558 *tsf = high; 559 *tsf <<= 32; 560 *tsf |= low; 561} 562 563static void b43_time_lock(struct b43_wldev *dev) 564{ 565 u32 macctl; 566 567 macctl = b43_read32(dev, B43_MMIO_MACCTL); 568 macctl |= B43_MACCTL_TBTTHOLD; 569 b43_write32(dev, B43_MMIO_MACCTL, macctl); 570 /* Commit the write */ 571 b43_read32(dev, B43_MMIO_MACCTL); 572} 573 574static void b43_time_unlock(struct b43_wldev *dev) 575{ 576 u32 macctl; 577 578 macctl = b43_read32(dev, B43_MMIO_MACCTL); 579 macctl &= ~B43_MACCTL_TBTTHOLD; 580 b43_write32(dev, B43_MMIO_MACCTL, macctl); 581 /* Commit the write */ 582 b43_read32(dev, B43_MMIO_MACCTL); 583} 584 585static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 586{ 587 u32 low, high; 588 589 B43_WARN_ON(dev->dev->core_rev < 3); 590 591 low = tsf; 592 high = (tsf >> 32); 593 /* The hardware guarantees us an atomic write, if we 594 * write the low register first. */ 595 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low); 596 mmiowb(); 597 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high); 598 mmiowb(); 599} 600 601void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 602{ 603 b43_time_lock(dev); 604 b43_tsf_write_locked(dev, tsf); 605 b43_time_unlock(dev); 606} 607 608static 609void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac) 610{ 611 static const u8 zero_addr[ETH_ALEN] = { 0 }; 612 u16 data; 613 614 if (!mac) 615 mac = zero_addr; 616 617 offset |= 0x0020; 618 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 619 620 data = mac[0]; 621 data |= mac[1] << 8; 622 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 623 data = mac[2]; 624 data |= mac[3] << 8; 625 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 626 data = mac[4]; 627 data |= mac[5] << 8; 628 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 629} 630 631static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 632{ 633 const u8 *mac; 634 const u8 *bssid; 635 u8 mac_bssid[ETH_ALEN * 2]; 636 int i; 637 u32 tmp; 638 639 bssid = dev->wl->bssid; 640 mac = dev->wl->mac_addr; 641 642 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 643 644 memcpy(mac_bssid, mac, ETH_ALEN); 645 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 646 647 /* Write our MAC address and BSSID to template ram */ 648 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 649 tmp = (u32) (mac_bssid[i + 0]); 650 tmp |= (u32) (mac_bssid[i + 1]) << 8; 651 tmp |= (u32) (mac_bssid[i + 2]) << 16; 652 tmp |= (u32) (mac_bssid[i + 3]) << 24; 653 b43_ram_write(dev, 0x20 + i, tmp); 654 } 655} 656 657static void b43_upload_card_macaddress(struct b43_wldev *dev) 658{ 659 b43_write_mac_bssid_templates(dev); 660 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 661} 662 663static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 664{ 665 /* slot_time is in usec. */ 666 /* This test used to exit for all but a G PHY. */ 667 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 668 return; 669 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time); 670 /* Shared memory location 0x0010 is the slot time and should be 671 * set to slot_time; however, this register is initially 0 and changing 672 * the value adversely affects the transmit rate for BCM4311 673 * devices. Until this behavior is unterstood, delete this step 674 * 675 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 676 */ 677} 678 679static void b43_short_slot_timing_enable(struct b43_wldev *dev) 680{ 681 b43_set_slot_time(dev, 9); 682} 683 684static void b43_short_slot_timing_disable(struct b43_wldev *dev) 685{ 686 b43_set_slot_time(dev, 20); 687} 688 689/* DummyTransmission function, as documented on 690 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission 691 */ 692void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) 693{ 694 struct b43_phy *phy = &dev->phy; 695 unsigned int i, max_loop; 696 u16 value; 697 u32 buffer[5] = { 698 0x00000000, 699 0x00D40000, 700 0x00000000, 701 0x01000000, 702 0x00000000, 703 }; 704 705 if (ofdm) { 706 max_loop = 0x1E; 707 buffer[0] = 0x000201CC; 708 } else { 709 max_loop = 0xFA; 710 buffer[0] = 0x000B846E; 711 } 712 713 for (i = 0; i < 5; i++) 714 b43_ram_write(dev, i * 4, buffer[i]); 715 716 b43_write16(dev, 0x0568, 0x0000); 717 if (dev->dev->core_rev < 11) 718 b43_write16(dev, 0x07C0, 0x0000); 719 else 720 b43_write16(dev, 0x07C0, 0x0100); 721 value = (ofdm ? 0x41 : 0x40); 722 b43_write16(dev, 0x050C, value); 723 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP)) 724 b43_write16(dev, 0x0514, 0x1A02); 725 b43_write16(dev, 0x0508, 0x0000); 726 b43_write16(dev, 0x050A, 0x0000); 727 b43_write16(dev, 0x054C, 0x0000); 728 b43_write16(dev, 0x056A, 0x0014); 729 b43_write16(dev, 0x0568, 0x0826); 730 b43_write16(dev, 0x0500, 0x0000); 731 if (!pa_on && (phy->type == B43_PHYTYPE_N)) { 732 //SPEC TODO 733 } 734 735 switch (phy->type) { 736 case B43_PHYTYPE_N: 737 b43_write16(dev, 0x0502, 0x00D0); 738 break; 739 case B43_PHYTYPE_LP: 740 b43_write16(dev, 0x0502, 0x0050); 741 break; 742 default: 743 b43_write16(dev, 0x0502, 0x0030); 744 } 745 746 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 747 b43_radio_write16(dev, 0x0051, 0x0017); 748 for (i = 0x00; i < max_loop; i++) { 749 value = b43_read16(dev, 0x050E); 750 if (value & 0x0080) 751 break; 752 udelay(10); 753 } 754 for (i = 0x00; i < 0x0A; i++) { 755 value = b43_read16(dev, 0x050E); 756 if (value & 0x0400) 757 break; 758 udelay(10); 759 } 760 for (i = 0x00; i < 0x19; i++) { 761 value = b43_read16(dev, 0x0690); 762 if (!(value & 0x0100)) 763 break; 764 udelay(10); 765 } 766 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 767 b43_radio_write16(dev, 0x0051, 0x0037); 768} 769 770static void key_write(struct b43_wldev *dev, 771 u8 index, u8 algorithm, const u8 *key) 772{ 773 unsigned int i; 774 u32 offset; 775 u16 value; 776 u16 kidx; 777 778 /* Key index/algo block */ 779 kidx = b43_kidx_to_fw(dev, index); 780 value = ((kidx << 4) | algorithm); 781 b43_shm_write16(dev, B43_SHM_SHARED, 782 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 783 784 /* Write the key to the Key Table Pointer offset */ 785 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 786 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 787 value = key[i]; 788 value |= (u16) (key[i + 1]) << 8; 789 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 790 } 791} 792 793static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr) 794{ 795 u32 addrtmp[2] = { 0, 0, }; 796 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 797 798 if (b43_new_kidx_api(dev)) 799 pairwise_keys_start = B43_NR_GROUP_KEYS; 800 801 B43_WARN_ON(index < pairwise_keys_start); 802 /* We have four default TX keys and possibly four default RX keys. 803 * Physical mac 0 is mapped to physical key 4 or 8, depending 804 * on the firmware version. 805 * So we must adjust the index here. 806 */ 807 index -= pairwise_keys_start; 808 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 809 810 if (addr) { 811 addrtmp[0] = addr[0]; 812 addrtmp[0] |= ((u32) (addr[1]) << 8); 813 addrtmp[0] |= ((u32) (addr[2]) << 16); 814 addrtmp[0] |= ((u32) (addr[3]) << 24); 815 addrtmp[1] = addr[4]; 816 addrtmp[1] |= ((u32) (addr[5]) << 8); 817 } 818 819 /* Receive match transmitter address (RCMTA) mechanism */ 820 b43_shm_write32(dev, B43_SHM_RCMTA, 821 (index * 2) + 0, addrtmp[0]); 822 b43_shm_write16(dev, B43_SHM_RCMTA, 823 (index * 2) + 1, addrtmp[1]); 824} 825 826/* The ucode will use phase1 key with TEK key to decrypt rx packets. 827 * When a packet is received, the iv32 is checked. 828 * - if it doesn't the packet is returned without modification (and software 829 * decryption can be done). That's what happen when iv16 wrap. 830 * - if it does, the rc4 key is computed, and decryption is tried. 831 * Either it will success and B43_RX_MAC_DEC is returned, 832 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned 833 * and the packet is not usable (it got modified by the ucode). 834 * So in order to never have B43_RX_MAC_DECERR, we should provide 835 * a iv32 and phase1key that match. Because we drop packets in case of 836 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all 837 * packets will be lost without higher layer knowing (ie no resync possible 838 * until next wrap). 839 * 840 * NOTE : this should support 50 key like RCMTA because 841 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50 842 */ 843static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32, 844 u16 *phase1key) 845{ 846 unsigned int i; 847 u32 offset; 848 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 849 850 if (!modparam_hwtkip) 851 return; 852 853 if (b43_new_kidx_api(dev)) 854 pairwise_keys_start = B43_NR_GROUP_KEYS; 855 856 B43_WARN_ON(index < pairwise_keys_start); 857 /* We have four default TX keys and possibly four default RX keys. 858 * Physical mac 0 is mapped to physical key 4 or 8, depending 859 * on the firmware version. 860 * So we must adjust the index here. 861 */ 862 index -= pairwise_keys_start; 863 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 864 865 if (b43_debug(dev, B43_DBG_KEYS)) { 866 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", 867 index, iv32); 868 } 869 /* Write the key to the RX tkip shared mem */ 870 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4); 871 for (i = 0; i < 10; i += 2) { 872 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, 873 phase1key ? phase1key[i / 2] : 0); 874 } 875 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32); 876 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16); 877} 878 879static void b43_op_update_tkip_key(struct ieee80211_hw *hw, 880 struct ieee80211_vif *vif, 881 struct ieee80211_key_conf *keyconf, 882 struct ieee80211_sta *sta, 883 u32 iv32, u16 *phase1key) 884{ 885 struct b43_wl *wl = hw_to_b43_wl(hw); 886 struct b43_wldev *dev; 887 int index = keyconf->hw_key_idx; 888 889 if (B43_WARN_ON(!modparam_hwtkip)) 890 return; 891 892 /* This is only called from the RX path through mac80211, where 893 * our mutex is already locked. */ 894 B43_WARN_ON(!mutex_is_locked(&wl->mutex)); 895 dev = wl->current_dev; 896 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED); 897 898 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */ 899 900 rx_tkip_phase1_write(dev, index, iv32, phase1key); 901 /* only pairwise TKIP keys are supported right now */ 902 if (WARN_ON(!sta)) 903 return; 904 keymac_write(dev, index, sta->addr); 905} 906 907static void do_key_write(struct b43_wldev *dev, 908 u8 index, u8 algorithm, 909 const u8 *key, size_t key_len, const u8 *mac_addr) 910{ 911 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 912 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 913 914 if (b43_new_kidx_api(dev)) 915 pairwise_keys_start = B43_NR_GROUP_KEYS; 916 917 B43_WARN_ON(index >= ARRAY_SIZE(dev->key)); 918 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 919 920 if (index >= pairwise_keys_start) 921 keymac_write(dev, index, NULL); /* First zero out mac. */ 922 if (algorithm == B43_SEC_ALGO_TKIP) { 923 /* 924 * We should provide an initial iv32, phase1key pair. 925 * We could start with iv32=0 and compute the corresponding 926 * phase1key, but this means calling ieee80211_get_tkip_key 927 * with a fake skb (or export other tkip function). 928 * Because we are lazy we hope iv32 won't start with 929 * 0xffffffff and let's b43_op_update_tkip_key provide a 930 * correct pair. 931 */ 932 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); 933 } else if (index >= pairwise_keys_start) /* clear it */ 934 rx_tkip_phase1_write(dev, index, 0, NULL); 935 if (key) 936 memcpy(buf, key, key_len); 937 key_write(dev, index, algorithm, buf); 938 if (index >= pairwise_keys_start) 939 keymac_write(dev, index, mac_addr); 940 941 dev->key[index].algorithm = algorithm; 942} 943 944static int b43_key_write(struct b43_wldev *dev, 945 int index, u8 algorithm, 946 const u8 *key, size_t key_len, 947 const u8 *mac_addr, 948 struct ieee80211_key_conf *keyconf) 949{ 950 int i; 951 int pairwise_keys_start; 952 953 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block: 954 * - Temporal Encryption Key (128 bits) 955 * - Temporal Authenticator Tx MIC Key (64 bits) 956 * - Temporal Authenticator Rx MIC Key (64 bits) 957 * 958 * Hardware only store TEK 959 */ 960 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32) 961 key_len = 16; 962 if (key_len > B43_SEC_KEYSIZE) 963 return -EINVAL; 964 for (i = 0; i < ARRAY_SIZE(dev->key); i++) { 965 /* Check that we don't already have this key. */ 966 B43_WARN_ON(dev->key[i].keyconf == keyconf); 967 } 968 if (index < 0) { 969 /* Pairwise key. Get an empty slot for the key. */ 970 if (b43_new_kidx_api(dev)) 971 pairwise_keys_start = B43_NR_GROUP_KEYS; 972 else 973 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 974 for (i = pairwise_keys_start; 975 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS; 976 i++) { 977 B43_WARN_ON(i >= ARRAY_SIZE(dev->key)); 978 if (!dev->key[i].keyconf) { 979 /* found empty */ 980 index = i; 981 break; 982 } 983 } 984 if (index < 0) { 985 b43warn(dev->wl, "Out of hardware key memory\n"); 986 return -ENOSPC; 987 } 988 } else 989 B43_WARN_ON(index > 3); 990 991 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 992 if ((index <= 3) && !b43_new_kidx_api(dev)) { 993 /* Default RX key */ 994 B43_WARN_ON(mac_addr); 995 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 996 } 997 keyconf->hw_key_idx = index; 998 dev->key[index].keyconf = keyconf; 999 1000 return 0; 1001} 1002 1003static int b43_key_clear(struct b43_wldev *dev, int index) 1004{ 1005 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) 1006 return -EINVAL; 1007 do_key_write(dev, index, B43_SEC_ALGO_NONE, 1008 NULL, B43_SEC_KEYSIZE, NULL); 1009 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1010 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 1011 NULL, B43_SEC_KEYSIZE, NULL); 1012 } 1013 dev->key[index].keyconf = NULL; 1014 1015 return 0; 1016} 1017 1018static void b43_clear_keys(struct b43_wldev *dev) 1019{ 1020 int i, count; 1021 1022 if (b43_new_kidx_api(dev)) 1023 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1024 else 1025 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1026 for (i = 0; i < count; i++) 1027 b43_key_clear(dev, i); 1028} 1029 1030static void b43_dump_keymemory(struct b43_wldev *dev) 1031{ 1032 unsigned int i, index, count, offset, pairwise_keys_start; 1033 u8 mac[ETH_ALEN]; 1034 u16 algo; 1035 u32 rcmta0; 1036 u16 rcmta1; 1037 u64 hf; 1038 struct b43_key *key; 1039 1040 if (!b43_debug(dev, B43_DBG_KEYS)) 1041 return; 1042 1043 hf = b43_hf_read(dev); 1044 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n", 1045 !!(hf & B43_HF_USEDEFKEYS)); 1046 if (b43_new_kidx_api(dev)) { 1047 pairwise_keys_start = B43_NR_GROUP_KEYS; 1048 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1049 } else { 1050 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 1051 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1052 } 1053 for (index = 0; index < count; index++) { 1054 key = &(dev->key[index]); 1055 printk(KERN_DEBUG "Key slot %02u: %s", 1056 index, (key->keyconf == NULL) ? " " : "*"); 1057 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 1058 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 1059 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1060 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1061 } 1062 1063 algo = b43_shm_read16(dev, B43_SHM_SHARED, 1064 B43_SHM_SH_KEYIDXBLOCK + (index * 2)); 1065 printk(" Algo: %04X/%02X", algo, key->algorithm); 1066 1067 if (index >= pairwise_keys_start) { 1068 if (key->algorithm == B43_SEC_ALGO_TKIP) { 1069 printk(" TKIP: "); 1070 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4); 1071 for (i = 0; i < 14; i += 2) { 1072 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1073 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1074 } 1075 } 1076 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA, 1077 ((index - pairwise_keys_start) * 2) + 0); 1078 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA, 1079 ((index - pairwise_keys_start) * 2) + 1); 1080 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); 1081 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1); 1082 printk(" MAC: %pM", mac); 1083 } else 1084 printk(" DEFAULT KEY"); 1085 printk("\n"); 1086 } 1087} 1088 1089void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 1090{ 1091 u32 macctl; 1092 u16 ucstat; 1093 bool hwps; 1094 bool awake; 1095 int i; 1096 1097 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 1098 (ps_flags & B43_PS_DISABLED)); 1099 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 1100 1101 if (ps_flags & B43_PS_ENABLED) { 1102 hwps = 1; 1103 } else if (ps_flags & B43_PS_DISABLED) { 1104 hwps = 0; 1105 } else { 1106 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 1107 // and thus is not an AP and we are associated, set bit 25 1108 } 1109 if (ps_flags & B43_PS_AWAKE) { 1110 awake = 1; 1111 } else if (ps_flags & B43_PS_ASLEEP) { 1112 awake = 0; 1113 } else { 1114 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 1115 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 1116 // successful, set bit26 1117 } 1118 1119/* FIXME: For now we force awake-on and hwps-off */ 1120 hwps = 0; 1121 awake = 1; 1122 1123 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1124 if (hwps) 1125 macctl |= B43_MACCTL_HWPS; 1126 else 1127 macctl &= ~B43_MACCTL_HWPS; 1128 if (awake) 1129 macctl |= B43_MACCTL_AWAKE; 1130 else 1131 macctl &= ~B43_MACCTL_AWAKE; 1132 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1133 /* Commit write */ 1134 b43_read32(dev, B43_MMIO_MACCTL); 1135 if (awake && dev->dev->core_rev >= 5) { 1136 /* Wait for the microcode to wake up. */ 1137 for (i = 0; i < 100; i++) { 1138 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 1139 B43_SHM_SH_UCODESTAT); 1140 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 1141 break; 1142 udelay(10); 1143 } 1144 } 1145} 1146 1147static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1148{ 1149 struct ssb_device *sdev = dev->dev->sdev; 1150 u32 tmslow; 1151 u32 flags = 0; 1152 1153 if (gmode) 1154 flags |= B43_TMSLOW_GMODE; 1155 flags |= B43_TMSLOW_PHYCLKEN; 1156 flags |= B43_TMSLOW_PHYRESET; 1157 if (dev->phy.type == B43_PHYTYPE_N) 1158 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */ 1159 b43_device_enable(dev, flags); 1160 msleep(2); /* Wait for the PLL to turn on. */ 1161 1162 /* Now take the PHY out of Reset again */ 1163 tmslow = ssb_read32(sdev, SSB_TMSLOW); 1164 tmslow |= SSB_TMSLOW_FGC; 1165 tmslow &= ~B43_TMSLOW_PHYRESET; 1166 ssb_write32(sdev, SSB_TMSLOW, tmslow); 1167 ssb_read32(sdev, SSB_TMSLOW); /* flush */ 1168 msleep(1); 1169 tmslow &= ~SSB_TMSLOW_FGC; 1170 ssb_write32(sdev, SSB_TMSLOW, tmslow); 1171 ssb_read32(sdev, SSB_TMSLOW); /* flush */ 1172 msleep(1); 1173} 1174 1175void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1176{ 1177 u32 macctl; 1178 1179 b43_ssb_wireless_core_reset(dev, gmode); 1180 1181 /* Turn Analog ON, but only if we already know the PHY-type. 1182 * This protects against very early setup where we don't know the 1183 * PHY-type, yet. wireless_core_reset will be called once again later, 1184 * when we know the PHY-type. */ 1185 if (dev->phy.ops) 1186 dev->phy.ops->switch_analog(dev, 1); 1187 1188 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1189 macctl &= ~B43_MACCTL_GMODE; 1190 if (gmode) 1191 macctl |= B43_MACCTL_GMODE; 1192 macctl |= B43_MACCTL_IHR_ENABLED; 1193 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1194} 1195 1196static void handle_irq_transmit_status(struct b43_wldev *dev) 1197{ 1198 u32 v0, v1; 1199 u16 tmp; 1200 struct b43_txstatus stat; 1201 1202 while (1) { 1203 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1204 if (!(v0 & 0x00000001)) 1205 break; 1206 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1207 1208 stat.cookie = (v0 >> 16); 1209 stat.seq = (v1 & 0x0000FFFF); 1210 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 1211 tmp = (v0 & 0x0000FFFF); 1212 stat.frame_count = ((tmp & 0xF000) >> 12); 1213 stat.rts_count = ((tmp & 0x0F00) >> 8); 1214 stat.supp_reason = ((tmp & 0x001C) >> 2); 1215 stat.pm_indicated = !!(tmp & 0x0080); 1216 stat.intermediate = !!(tmp & 0x0040); 1217 stat.for_ampdu = !!(tmp & 0x0020); 1218 stat.acked = !!(tmp & 0x0002); 1219 1220 b43_handle_txstatus(dev, &stat); 1221 } 1222} 1223 1224static void drain_txstatus_queue(struct b43_wldev *dev) 1225{ 1226 u32 dummy; 1227 1228 if (dev->dev->core_rev < 5) 1229 return; 1230 /* Read all entries from the microcode TXstatus FIFO 1231 * and throw them away. 1232 */ 1233 while (1) { 1234 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1235 if (!(dummy & 0x00000001)) 1236 break; 1237 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1238 } 1239} 1240 1241static u32 b43_jssi_read(struct b43_wldev *dev) 1242{ 1243 u32 val = 0; 1244 1245 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 1246 val <<= 16; 1247 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1248 1249 return val; 1250} 1251 1252static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1253{ 1254 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1255 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1256} 1257 1258static void b43_generate_noise_sample(struct b43_wldev *dev) 1259{ 1260 b43_jssi_write(dev, 0x7F7F7F7F); 1261 b43_write32(dev, B43_MMIO_MACCMD, 1262 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1263} 1264 1265static void b43_calculate_link_quality(struct b43_wldev *dev) 1266{ 1267 /* Top half of Link Quality calculation. */ 1268 1269 if (dev->phy.type != B43_PHYTYPE_G) 1270 return; 1271 if (dev->noisecalc.calculation_running) 1272 return; 1273 dev->noisecalc.calculation_running = 1; 1274 dev->noisecalc.nr_samples = 0; 1275 1276 b43_generate_noise_sample(dev); 1277} 1278 1279static void handle_irq_noise(struct b43_wldev *dev) 1280{ 1281 struct b43_phy_g *phy = dev->phy.g; 1282 u16 tmp; 1283 u8 noise[4]; 1284 u8 i, j; 1285 s32 average; 1286 1287 /* Bottom half of Link Quality calculation. */ 1288 1289 if (dev->phy.type != B43_PHYTYPE_G) 1290 return; 1291 1292 /* Possible race condition: It might be possible that the user 1293 * changed to a different channel in the meantime since we 1294 * started the calculation. We ignore that fact, since it's 1295 * not really that much of a problem. The background noise is 1296 * an estimation only anyway. Slightly wrong results will get damped 1297 * by the averaging of the 8 sample rounds. Additionally the 1298 * value is shortlived. So it will be replaced by the next noise 1299 * calculation round soon. */ 1300 1301 B43_WARN_ON(!dev->noisecalc.calculation_running); 1302 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1303 if (noise[0] == 0x7F || noise[1] == 0x7F || 1304 noise[2] == 0x7F || noise[3] == 0x7F) 1305 goto generate_new; 1306 1307 /* Get the noise samples. */ 1308 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1309 i = dev->noisecalc.nr_samples; 1310 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1311 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1312 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1313 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1314 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1315 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1316 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1317 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1318 dev->noisecalc.nr_samples++; 1319 if (dev->noisecalc.nr_samples == 8) { 1320 /* Calculate the Link Quality by the noise samples. */ 1321 average = 0; 1322 for (i = 0; i < 8; i++) { 1323 for (j = 0; j < 4; j++) 1324 average += dev->noisecalc.samples[i][j]; 1325 } 1326 average /= (8 * 4); 1327 average *= 125; 1328 average += 64; 1329 average /= 128; 1330 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1331 tmp = (tmp / 128) & 0x1F; 1332 if (tmp >= 8) 1333 average += 2; 1334 else 1335 average -= 25; 1336 if (tmp == 8) 1337 average -= 72; 1338 else 1339 average -= 48; 1340 1341 dev->stats.link_noise = average; 1342 dev->noisecalc.calculation_running = 0; 1343 return; 1344 } 1345generate_new: 1346 b43_generate_noise_sample(dev); 1347} 1348 1349static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1350{ 1351 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) { 1352 ///TODO: PS TBTT 1353 } else { 1354 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1355 b43_power_saving_ctl_bits(dev, 0); 1356 } 1357 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 1358 dev->dfq_valid = 1; 1359} 1360 1361static void handle_irq_atim_end(struct b43_wldev *dev) 1362{ 1363 if (dev->dfq_valid) { 1364 b43_write32(dev, B43_MMIO_MACCMD, 1365 b43_read32(dev, B43_MMIO_MACCMD) 1366 | B43_MACCMD_DFQ_VALID); 1367 dev->dfq_valid = 0; 1368 } 1369} 1370 1371static void handle_irq_pmq(struct b43_wldev *dev) 1372{ 1373 u32 tmp; 1374 1375 //TODO: AP mode. 1376 1377 while (1) { 1378 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1379 if (!(tmp & 0x00000008)) 1380 break; 1381 } 1382 /* 16bit write is odd, but correct. */ 1383 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1384} 1385 1386static void b43_write_template_common(struct b43_wldev *dev, 1387 const u8 *data, u16 size, 1388 u16 ram_offset, 1389 u16 shm_size_offset, u8 rate) 1390{ 1391 u32 i, tmp; 1392 struct b43_plcp_hdr4 plcp; 1393 1394 plcp.data = 0; 1395 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1396 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1397 ram_offset += sizeof(u32); 1398 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1399 * So leave the first two bytes of the next write blank. 1400 */ 1401 tmp = (u32) (data[0]) << 16; 1402 tmp |= (u32) (data[1]) << 24; 1403 b43_ram_write(dev, ram_offset, tmp); 1404 ram_offset += sizeof(u32); 1405 for (i = 2; i < size; i += sizeof(u32)) { 1406 tmp = (u32) (data[i + 0]); 1407 if (i + 1 < size) 1408 tmp |= (u32) (data[i + 1]) << 8; 1409 if (i + 2 < size) 1410 tmp |= (u32) (data[i + 2]) << 16; 1411 if (i + 3 < size) 1412 tmp |= (u32) (data[i + 3]) << 24; 1413 b43_ram_write(dev, ram_offset + i - 2, tmp); 1414 } 1415 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1416 size + sizeof(struct b43_plcp_hdr6)); 1417} 1418 1419/* Check if the use of the antenna that ieee80211 told us to 1420 * use is possible. This will fall back to DEFAULT. 1421 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 1422u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 1423 u8 antenna_nr) 1424{ 1425 u8 antenna_mask; 1426 1427 if (antenna_nr == 0) { 1428 /* Zero means "use default antenna". That's always OK. */ 1429 return 0; 1430 } 1431 1432 /* Get the mask of available antennas. */ 1433 if (dev->phy.gmode) 1434 antenna_mask = dev->dev->bus_sprom->ant_available_bg; 1435 else 1436 antenna_mask = dev->dev->bus_sprom->ant_available_a; 1437 1438 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 1439 /* This antenna is not available. Fall back to default. */ 1440 return 0; 1441 } 1442 1443 return antenna_nr; 1444} 1445 1446/* Convert a b43 antenna number value to the PHY TX control value. */ 1447static u16 b43_antenna_to_phyctl(int antenna) 1448{ 1449 switch (antenna) { 1450 case B43_ANTENNA0: 1451 return B43_TXH_PHY_ANT0; 1452 case B43_ANTENNA1: 1453 return B43_TXH_PHY_ANT1; 1454 case B43_ANTENNA2: 1455 return B43_TXH_PHY_ANT2; 1456 case B43_ANTENNA3: 1457 return B43_TXH_PHY_ANT3; 1458 case B43_ANTENNA_AUTO0: 1459 case B43_ANTENNA_AUTO1: 1460 return B43_TXH_PHY_ANT01AUTO; 1461 } 1462 B43_WARN_ON(1); 1463 return 0; 1464} 1465 1466static void b43_write_beacon_template(struct b43_wldev *dev, 1467 u16 ram_offset, 1468 u16 shm_size_offset) 1469{ 1470 unsigned int i, len, variable_len; 1471 const struct ieee80211_mgmt *bcn; 1472 const u8 *ie; 1473 bool tim_found = 0; 1474 unsigned int rate; 1475 u16 ctl; 1476 int antenna; 1477 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon); 1478 1479 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1480 len = min((size_t) dev->wl->current_beacon->len, 1481 0x200 - sizeof(struct b43_plcp_hdr6)); 1482 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; 1483 1484 b43_write_template_common(dev, (const u8 *)bcn, 1485 len, ram_offset, shm_size_offset, rate); 1486 1487 /* Write the PHY TX control parameters. */ 1488 antenna = B43_ANTENNA_DEFAULT; 1489 antenna = b43_antenna_to_phyctl(antenna); 1490 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 1491 /* We can't send beacons with short preamble. Would get PHY errors. */ 1492 ctl &= ~B43_TXH_PHY_SHORTPRMBL; 1493 ctl &= ~B43_TXH_PHY_ANT; 1494 ctl &= ~B43_TXH_PHY_ENC; 1495 ctl |= antenna; 1496 if (b43_is_cck_rate(rate)) 1497 ctl |= B43_TXH_PHY_ENC_CCK; 1498 else 1499 ctl |= B43_TXH_PHY_ENC_OFDM; 1500 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 1501 1502 /* Find the position of the TIM and the DTIM_period value 1503 * and write them to SHM. */ 1504 ie = bcn->u.beacon.variable; 1505 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1506 for (i = 0; i < variable_len - 2; ) { 1507 uint8_t ie_id, ie_len; 1508 1509 ie_id = ie[i]; 1510 ie_len = ie[i + 1]; 1511 if (ie_id == 5) { 1512 u16 tim_position; 1513 u16 dtim_period; 1514 /* This is the TIM Information Element */ 1515 1516 /* Check whether the ie_len is in the beacon data range. */ 1517 if (variable_len < ie_len + 2 + i) 1518 break; 1519 /* A valid TIM is at least 4 bytes long. */ 1520 if (ie_len < 4) 1521 break; 1522 tim_found = 1; 1523 1524 tim_position = sizeof(struct b43_plcp_hdr6); 1525 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1526 tim_position += i; 1527 1528 dtim_period = ie[i + 3]; 1529 1530 b43_shm_write16(dev, B43_SHM_SHARED, 1531 B43_SHM_SH_TIMBPOS, tim_position); 1532 b43_shm_write16(dev, B43_SHM_SHARED, 1533 B43_SHM_SH_DTIMPER, dtim_period); 1534 break; 1535 } 1536 i += ie_len + 2; 1537 } 1538 if (!tim_found) { 1539 /* 1540 * If ucode wants to modify TIM do it behind the beacon, this 1541 * will happen, for example, when doing mesh networking. 1542 */ 1543 b43_shm_write16(dev, B43_SHM_SHARED, 1544 B43_SHM_SH_TIMBPOS, 1545 len + sizeof(struct b43_plcp_hdr6)); 1546 b43_shm_write16(dev, B43_SHM_SHARED, 1547 B43_SHM_SH_DTIMPER, 0); 1548 } 1549 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); 1550} 1551 1552static void b43_upload_beacon0(struct b43_wldev *dev) 1553{ 1554 struct b43_wl *wl = dev->wl; 1555 1556 if (wl->beacon0_uploaded) 1557 return; 1558 b43_write_beacon_template(dev, 0x68, 0x18); 1559 wl->beacon0_uploaded = 1; 1560} 1561 1562static void b43_upload_beacon1(struct b43_wldev *dev) 1563{ 1564 struct b43_wl *wl = dev->wl; 1565 1566 if (wl->beacon1_uploaded) 1567 return; 1568 b43_write_beacon_template(dev, 0x468, 0x1A); 1569 wl->beacon1_uploaded = 1; 1570} 1571 1572static void handle_irq_beacon(struct b43_wldev *dev) 1573{ 1574 struct b43_wl *wl = dev->wl; 1575 u32 cmd, beacon0_valid, beacon1_valid; 1576 1577 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && 1578 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 1579 return; 1580 1581 /* This is the bottom half of the asynchronous beacon update. */ 1582 1583 /* Ignore interrupt in the future. */ 1584 dev->irq_mask &= ~B43_IRQ_BEACON; 1585 1586 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1587 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); 1588 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); 1589 1590 /* Schedule interrupt manually, if busy. */ 1591 if (beacon0_valid && beacon1_valid) { 1592 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1593 dev->irq_mask |= B43_IRQ_BEACON; 1594 return; 1595 } 1596 1597 if (unlikely(wl->beacon_templates_virgin)) { 1598 /* We never uploaded a beacon before. 1599 * Upload both templates now, but only mark one valid. */ 1600 wl->beacon_templates_virgin = 0; 1601 b43_upload_beacon0(dev); 1602 b43_upload_beacon1(dev); 1603 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1604 cmd |= B43_MACCMD_BEACON0_VALID; 1605 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1606 } else { 1607 if (!beacon0_valid) { 1608 b43_upload_beacon0(dev); 1609 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1610 cmd |= B43_MACCMD_BEACON0_VALID; 1611 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1612 } else if (!beacon1_valid) { 1613 b43_upload_beacon1(dev); 1614 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1615 cmd |= B43_MACCMD_BEACON1_VALID; 1616 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1617 } 1618 } 1619} 1620 1621static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev) 1622{ 1623 u32 old_irq_mask = dev->irq_mask; 1624 1625 /* update beacon right away or defer to irq */ 1626 handle_irq_beacon(dev); 1627 if (old_irq_mask != dev->irq_mask) { 1628 /* The handler updated the IRQ mask. */ 1629 B43_WARN_ON(!dev->irq_mask); 1630 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) { 1631 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1632 } else { 1633 /* Device interrupts are currently disabled. That means 1634 * we just ran the hardirq handler and scheduled the 1635 * IRQ thread. The thread will write the IRQ mask when 1636 * it finished, so there's nothing to do here. Writing 1637 * the mask _here_ would incorrectly re-enable IRQs. */ 1638 } 1639 } 1640} 1641 1642static void b43_beacon_update_trigger_work(struct work_struct *work) 1643{ 1644 struct b43_wl *wl = container_of(work, struct b43_wl, 1645 beacon_update_trigger); 1646 struct b43_wldev *dev; 1647 1648 mutex_lock(&wl->mutex); 1649 dev = wl->current_dev; 1650 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { 1651 if (b43_bus_host_is_sdio(dev->dev)) { 1652 /* wl->mutex is enough. */ 1653 b43_do_beacon_update_trigger_work(dev); 1654 mmiowb(); 1655 } else { 1656 spin_lock_irq(&wl->hardirq_lock); 1657 b43_do_beacon_update_trigger_work(dev); 1658 mmiowb(); 1659 spin_unlock_irq(&wl->hardirq_lock); 1660 } 1661 } 1662 mutex_unlock(&wl->mutex); 1663} 1664 1665/* Asynchronously update the packet templates in template RAM. 1666 * Locking: Requires wl->mutex to be locked. */ 1667static void b43_update_templates(struct b43_wl *wl) 1668{ 1669 struct sk_buff *beacon; 1670 1671 /* This is the top half of the ansynchronous beacon update. 1672 * The bottom half is the beacon IRQ. 1673 * Beacon update must be asynchronous to avoid sending an 1674 * invalid beacon. This can happen for example, if the firmware 1675 * transmits a beacon while we are updating it. */ 1676 1677 /* We could modify the existing beacon and set the aid bit in 1678 * the TIM field, but that would probably require resizing and 1679 * moving of data within the beacon template. 1680 * Simply request a new beacon and let mac80211 do the hard work. */ 1681 beacon = ieee80211_beacon_get(wl->hw, wl->vif); 1682 if (unlikely(!beacon)) 1683 return; 1684 1685 if (wl->current_beacon) 1686 dev_kfree_skb_any(wl->current_beacon); 1687 wl->current_beacon = beacon; 1688 wl->beacon0_uploaded = 0; 1689 wl->beacon1_uploaded = 0; 1690 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); 1691} 1692 1693static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1694{ 1695 b43_time_lock(dev); 1696 if (dev->dev->core_rev >= 3) { 1697 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); 1698 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); 1699 } else { 1700 b43_write16(dev, 0x606, (beacon_int >> 6)); 1701 b43_write16(dev, 0x610, beacon_int); 1702 } 1703 b43_time_unlock(dev); 1704 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1705} 1706 1707static void b43_handle_firmware_panic(struct b43_wldev *dev) 1708{ 1709 u16 reason; 1710 1711 /* Read the register that contains the reason code for the panic. */ 1712 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG); 1713 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason); 1714 1715 switch (reason) { 1716 default: 1717 b43dbg(dev->wl, "The panic reason is unknown.\n"); 1718 /* fallthrough */ 1719 case B43_FWPANIC_DIE: 1720 /* Do not restart the controller or firmware. 1721 * The device is nonfunctional from now on. 1722 * Restarting would result in this panic to trigger again, 1723 * so we avoid that recursion. */ 1724 break; 1725 case B43_FWPANIC_RESTART: 1726 b43_controller_restart(dev, "Microcode panic"); 1727 break; 1728 } 1729} 1730 1731static void handle_irq_ucode_debug(struct b43_wldev *dev) 1732{ 1733 unsigned int i, cnt; 1734 u16 reason, marker_id, marker_line; 1735 __le16 *buf; 1736 1737 /* The proprietary firmware doesn't have this IRQ. */ 1738 if (!dev->fw.opensource) 1739 return; 1740 1741 /* Read the register that contains the reason code for this IRQ. */ 1742 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG); 1743 1744 switch (reason) { 1745 case B43_DEBUGIRQ_PANIC: 1746 b43_handle_firmware_panic(dev); 1747 break; 1748 case B43_DEBUGIRQ_DUMP_SHM: 1749 if (!B43_DEBUG) 1750 break; /* Only with driver debugging enabled. */ 1751 buf = kmalloc(4096, GFP_ATOMIC); 1752 if (!buf) { 1753 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n"); 1754 goto out; 1755 } 1756 for (i = 0; i < 4096; i += 2) { 1757 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i); 1758 buf[i / 2] = cpu_to_le16(tmp); 1759 } 1760 b43info(dev->wl, "Shared memory dump:\n"); 1761 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 1762 16, 2, buf, 4096, 1); 1763 kfree(buf); 1764 break; 1765 case B43_DEBUGIRQ_DUMP_REGS: 1766 if (!B43_DEBUG) 1767 break; /* Only with driver debugging enabled. */ 1768 b43info(dev->wl, "Microcode register dump:\n"); 1769 for (i = 0, cnt = 0; i < 64; i++) { 1770 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i); 1771 if (cnt == 0) 1772 printk(KERN_INFO); 1773 printk("r%02u: 0x%04X ", i, tmp); 1774 cnt++; 1775 if (cnt == 6) { 1776 printk("\n"); 1777 cnt = 0; 1778 } 1779 } 1780 printk("\n"); 1781 break; 1782 case B43_DEBUGIRQ_MARKER: 1783 if (!B43_DEBUG) 1784 break; /* Only with driver debugging enabled. */ 1785 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH, 1786 B43_MARKER_ID_REG); 1787 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH, 1788 B43_MARKER_LINE_REG); 1789 b43info(dev->wl, "The firmware just executed the MARKER(%u) " 1790 "at line number %u\n", 1791 marker_id, marker_line); 1792 break; 1793 default: 1794 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n", 1795 reason); 1796 } 1797out: 1798 /* Acknowledge the debug-IRQ, so the firmware can continue. */ 1799 b43_shm_write16(dev, B43_SHM_SCRATCH, 1800 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK); 1801} 1802 1803static void b43_do_interrupt_thread(struct b43_wldev *dev) 1804{ 1805 u32 reason; 1806 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1807 u32 merged_dma_reason = 0; 1808 int i; 1809 1810 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 1811 return; 1812 1813 reason = dev->irq_reason; 1814 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1815 dma_reason[i] = dev->dma_reason[i]; 1816 merged_dma_reason |= dma_reason[i]; 1817 } 1818 1819 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1820 b43err(dev->wl, "MAC transmission error\n"); 1821 1822 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1823 b43err(dev->wl, "PHY transmission error\n"); 1824 rmb(); 1825 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1826 atomic_set(&dev->phy.txerr_cnt, 1827 B43_PHY_TX_BADNESS_LIMIT); 1828 b43err(dev->wl, "Too many PHY TX errors, " 1829 "restarting the controller\n"); 1830 b43_controller_restart(dev, "PHY TX errors"); 1831 } 1832 } 1833 1834 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1835 B43_DMAIRQ_NONFATALMASK))) { 1836 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1837 b43err(dev->wl, "Fatal DMA error: " 1838 "0x%08X, 0x%08X, 0x%08X, " 1839 "0x%08X, 0x%08X, 0x%08X\n", 1840 dma_reason[0], dma_reason[1], 1841 dma_reason[2], dma_reason[3], 1842 dma_reason[4], dma_reason[5]); 1843 b43err(dev->wl, "This device does not support DMA " 1844 "on your system. It will now be switched to PIO.\n"); 1845 /* Fall back to PIO transfers if we get fatal DMA errors! */ 1846 dev->use_pio = 1; 1847 b43_controller_restart(dev, "DMA error"); 1848 return; 1849 } 1850 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1851 b43err(dev->wl, "DMA error: " 1852 "0x%08X, 0x%08X, 0x%08X, " 1853 "0x%08X, 0x%08X, 0x%08X\n", 1854 dma_reason[0], dma_reason[1], 1855 dma_reason[2], dma_reason[3], 1856 dma_reason[4], dma_reason[5]); 1857 } 1858 } 1859 1860 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1861 handle_irq_ucode_debug(dev); 1862 if (reason & B43_IRQ_TBTT_INDI) 1863 handle_irq_tbtt_indication(dev); 1864 if (reason & B43_IRQ_ATIM_END) 1865 handle_irq_atim_end(dev); 1866 if (reason & B43_IRQ_BEACON) 1867 handle_irq_beacon(dev); 1868 if (reason & B43_IRQ_PMQ) 1869 handle_irq_pmq(dev); 1870 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1871 ;/* TODO */ 1872 if (reason & B43_IRQ_NOISESAMPLE_OK) 1873 handle_irq_noise(dev); 1874 1875 /* Check the DMA reason registers for received data. */ 1876 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 1877 if (b43_using_pio_transfers(dev)) 1878 b43_pio_rx(dev->pio.rx_queue); 1879 else 1880 b43_dma_rx(dev->dma.rx_ring); 1881 } 1882 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1883 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1884 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); 1885 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1886 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1887 1888 if (reason & B43_IRQ_TX_OK) 1889 handle_irq_transmit_status(dev); 1890 1891 /* Re-enable interrupts on the device by restoring the current interrupt mask. */ 1892 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1893 1894#if B43_DEBUG 1895 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 1896 dev->irq_count++; 1897 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 1898 if (reason & (1 << i)) 1899 dev->irq_bit_count[i]++; 1900 } 1901 } 1902#endif 1903} 1904 1905/* Interrupt thread handler. Handles device interrupts in thread context. */ 1906static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id) 1907{ 1908 struct b43_wldev *dev = dev_id; 1909 1910 mutex_lock(&dev->wl->mutex); 1911 b43_do_interrupt_thread(dev); 1912 mmiowb(); 1913 mutex_unlock(&dev->wl->mutex); 1914 1915 return IRQ_HANDLED; 1916} 1917 1918static irqreturn_t b43_do_interrupt(struct b43_wldev *dev) 1919{ 1920 u32 reason; 1921 1922 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses. 1923 * On SDIO, this runs under wl->mutex. */ 1924 1925 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1926 if (reason == 0xffffffff) /* shared IRQ */ 1927 return IRQ_NONE; 1928 reason &= dev->irq_mask; 1929 if (!reason) 1930 return IRQ_HANDLED; 1931 1932 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1933 & 0x0001DC00; 1934 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1935 & 0x0000DC00; 1936 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1937 & 0x0000DC00; 1938 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1939 & 0x0001DC00; 1940 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1941 & 0x0000DC00; 1942/* Unused ring 1943 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1944 & 0x0000DC00; 1945*/ 1946 1947 /* ACK the interrupt. */ 1948 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1949 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1950 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1951 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1952 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1953 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1954/* Unused ring 1955 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1956*/ 1957 1958 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */ 1959 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 1960 /* Save the reason bitmasks for the IRQ thread handler. */ 1961 dev->irq_reason = reason; 1962 1963 return IRQ_WAKE_THREAD; 1964} 1965 1966/* Interrupt handler top-half. This runs with interrupts disabled. */ 1967static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1968{ 1969 struct b43_wldev *dev = dev_id; 1970 irqreturn_t ret; 1971 1972 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 1973 return IRQ_NONE; 1974 1975 spin_lock(&dev->wl->hardirq_lock); 1976 ret = b43_do_interrupt(dev); 1977 mmiowb(); 1978 spin_unlock(&dev->wl->hardirq_lock); 1979 1980 return ret; 1981} 1982 1983/* SDIO interrupt handler. This runs in process context. */ 1984static void b43_sdio_interrupt_handler(struct b43_wldev *dev) 1985{ 1986 struct b43_wl *wl = dev->wl; 1987 irqreturn_t ret; 1988 1989 mutex_lock(&wl->mutex); 1990 1991 ret = b43_do_interrupt(dev); 1992 if (ret == IRQ_WAKE_THREAD) 1993 b43_do_interrupt_thread(dev); 1994 1995 mutex_unlock(&wl->mutex); 1996} 1997 1998void b43_do_release_fw(struct b43_firmware_file *fw) 1999{ 2000 release_firmware(fw->data); 2001 fw->data = NULL; 2002 fw->filename = NULL; 2003} 2004 2005static void b43_release_firmware(struct b43_wldev *dev) 2006{ 2007 b43_do_release_fw(&dev->fw.ucode); 2008 b43_do_release_fw(&dev->fw.pcm); 2009 b43_do_release_fw(&dev->fw.initvals); 2010 b43_do_release_fw(&dev->fw.initvals_band); 2011} 2012 2013static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 2014{ 2015 const char text[] = 2016 "You must go to " \ 2017 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \ 2018 "and download the correct firmware for this driver version. " \ 2019 "Please carefully read all instructions on this website.\n"; 2020 2021 if (error) 2022 b43err(wl, text); 2023 else 2024 b43warn(wl, text); 2025} 2026 2027int b43_do_request_fw(struct b43_request_fw_context *ctx, 2028 const char *name, 2029 struct b43_firmware_file *fw) 2030{ 2031 const struct firmware *blob; 2032 struct b43_fw_header *hdr; 2033 u32 size; 2034 int err; 2035 2036 if (!name) { 2037 /* Don't fetch anything. Free possibly cached firmware. */ 2038 /* FIXME: We should probably keep it anyway, to save some headache 2039 * on suspend/resume with multiband devices. */ 2040 b43_do_release_fw(fw); 2041 return 0; 2042 } 2043 if (fw->filename) { 2044 if ((fw->type == ctx->req_type) && 2045 (strcmp(fw->filename, name) == 0)) 2046 return 0; /* Already have this fw. */ 2047 /* Free the cached firmware first. */ 2048 /* FIXME: We should probably do this later after we successfully 2049 * got the new fw. This could reduce headache with multiband devices. 2050 * We could also redesign this to cache the firmware for all possible 2051 * bands all the time. */ 2052 b43_do_release_fw(fw); 2053 } 2054 2055 switch (ctx->req_type) { 2056 case B43_FWTYPE_PROPRIETARY: 2057 snprintf(ctx->fwname, sizeof(ctx->fwname), 2058 "b43%s/%s.fw", 2059 modparam_fwpostfix, name); 2060 break; 2061 case B43_FWTYPE_OPENSOURCE: 2062 snprintf(ctx->fwname, sizeof(ctx->fwname), 2063 "b43-open%s/%s.fw", 2064 modparam_fwpostfix, name); 2065 break; 2066 default: 2067 B43_WARN_ON(1); 2068 return -ENOSYS; 2069 } 2070 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev); 2071 if (err == -ENOENT) { 2072 snprintf(ctx->errors[ctx->req_type], 2073 sizeof(ctx->errors[ctx->req_type]), 2074 "Firmware file \"%s\" not found\n", ctx->fwname); 2075 return err; 2076 } else if (err) { 2077 snprintf(ctx->errors[ctx->req_type], 2078 sizeof(ctx->errors[ctx->req_type]), 2079 "Firmware file \"%s\" request failed (err=%d)\n", 2080 ctx->fwname, err); 2081 return err; 2082 } 2083 if (blob->size < sizeof(struct b43_fw_header)) 2084 goto err_format; 2085 hdr = (struct b43_fw_header *)(blob->data); 2086 switch (hdr->type) { 2087 case B43_FW_TYPE_UCODE: 2088 case B43_FW_TYPE_PCM: 2089 size = be32_to_cpu(hdr->size); 2090 if (size != blob->size - sizeof(struct b43_fw_header)) 2091 goto err_format; 2092 /* fallthrough */ 2093 case B43_FW_TYPE_IV: 2094 if (hdr->ver != 1) 2095 goto err_format; 2096 break; 2097 default: 2098 goto err_format; 2099 } 2100 2101 fw->data = blob; 2102 fw->filename = name; 2103 fw->type = ctx->req_type; 2104 2105 return 0; 2106 2107err_format: 2108 snprintf(ctx->errors[ctx->req_type], 2109 sizeof(ctx->errors[ctx->req_type]), 2110 "Firmware file \"%s\" format error.\n", ctx->fwname); 2111 release_firmware(blob); 2112 2113 return -EPROTO; 2114} 2115 2116static int b43_try_request_fw(struct b43_request_fw_context *ctx) 2117{ 2118 struct b43_wldev *dev = ctx->dev; 2119 struct b43_firmware *fw = &ctx->dev->fw; 2120 const u8 rev = ctx->dev->dev->core_rev; 2121 const char *filename; 2122 u32 tmshigh; 2123 int err; 2124 2125 /* Get microcode */ 2126 if ((rev >= 5) && (rev <= 10)) 2127 filename = "ucode5"; 2128 else if ((rev >= 11) && (rev <= 12)) 2129 filename = "ucode11"; 2130 else if (rev == 13) 2131 filename = "ucode13"; 2132 else if (rev == 14) 2133 filename = "ucode14"; 2134 else if (rev == 15) 2135 filename = "ucode15"; 2136 else if ((rev >= 16) && (rev <= 20)) 2137 filename = "ucode16_mimo"; 2138 else 2139 goto err_no_ucode; 2140 err = b43_do_request_fw(ctx, filename, &fw->ucode); 2141 if (err) 2142 goto err_load; 2143 2144 /* Get PCM code */ 2145 if ((rev >= 5) && (rev <= 10)) 2146 filename = "pcm5"; 2147 else if (rev >= 11) 2148 filename = NULL; 2149 else 2150 goto err_no_pcm; 2151 fw->pcm_request_failed = 0; 2152 err = b43_do_request_fw(ctx, filename, &fw->pcm); 2153 if (err == -ENOENT) { 2154 /* We did not find a PCM file? Not fatal, but 2155 * core rev <= 10 must do without hwcrypto then. */ 2156 fw->pcm_request_failed = 1; 2157 } else if (err) 2158 goto err_load; 2159 2160 /* Get initvals */ 2161 switch (dev->phy.type) { 2162 case B43_PHYTYPE_A: 2163 if ((rev >= 5) && (rev <= 10)) { 2164 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 2165 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2166 filename = "a0g1initvals5"; 2167 else 2168 filename = "a0g0initvals5"; 2169 } else 2170 goto err_no_initvals; 2171 break; 2172 case B43_PHYTYPE_G: 2173 if ((rev >= 5) && (rev <= 10)) 2174 filename = "b0g0initvals5"; 2175 else if (rev >= 13) 2176 filename = "b0g0initvals13"; 2177 else 2178 goto err_no_initvals; 2179 break; 2180 case B43_PHYTYPE_N: 2181 if (rev >= 16) 2182 filename = "n0initvals16"; 2183 else if ((rev >= 11) && (rev <= 12)) 2184 filename = "n0initvals11"; 2185 else 2186 goto err_no_initvals; 2187 break; 2188 case B43_PHYTYPE_LP: 2189 if (rev == 13) 2190 filename = "lp0initvals13"; 2191 else if (rev == 14) 2192 filename = "lp0initvals14"; 2193 else if (rev >= 15) 2194 filename = "lp0initvals15"; 2195 else 2196 goto err_no_initvals; 2197 break; 2198 default: 2199 goto err_no_initvals; 2200 } 2201 err = b43_do_request_fw(ctx, filename, &fw->initvals); 2202 if (err) 2203 goto err_load; 2204 2205 /* Get bandswitch initvals */ 2206 switch (dev->phy.type) { 2207 case B43_PHYTYPE_A: 2208 if ((rev >= 5) && (rev <= 10)) { 2209 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 2210 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2211 filename = "a0g1bsinitvals5"; 2212 else 2213 filename = "a0g0bsinitvals5"; 2214 } else if (rev >= 11) 2215 filename = NULL; 2216 else 2217 goto err_no_initvals; 2218 break; 2219 case B43_PHYTYPE_G: 2220 if ((rev >= 5) && (rev <= 10)) 2221 filename = "b0g0bsinitvals5"; 2222 else if (rev >= 11) 2223 filename = NULL; 2224 else 2225 goto err_no_initvals; 2226 break; 2227 case B43_PHYTYPE_N: 2228 if (rev >= 16) 2229 filename = "n0bsinitvals16"; 2230 else if ((rev >= 11) && (rev <= 12)) 2231 filename = "n0bsinitvals11"; 2232 else 2233 goto err_no_initvals; 2234 break; 2235 case B43_PHYTYPE_LP: 2236 if (rev == 13) 2237 filename = "lp0bsinitvals13"; 2238 else if (rev == 14) 2239 filename = "lp0bsinitvals14"; 2240 else if (rev >= 15) 2241 filename = "lp0bsinitvals15"; 2242 else 2243 goto err_no_initvals; 2244 break; 2245 default: 2246 goto err_no_initvals; 2247 } 2248 err = b43_do_request_fw(ctx, filename, &fw->initvals_band); 2249 if (err) 2250 goto err_load; 2251 2252 return 0; 2253 2254err_no_ucode: 2255 err = ctx->fatal_failure = -EOPNOTSUPP; 2256 b43err(dev->wl, "The driver does not know which firmware (ucode) " 2257 "is required for your device (wl-core rev %u)\n", rev); 2258 goto error; 2259 2260err_no_pcm: 2261 err = ctx->fatal_failure = -EOPNOTSUPP; 2262 b43err(dev->wl, "The driver does not know which firmware (PCM) " 2263 "is required for your device (wl-core rev %u)\n", rev); 2264 goto error; 2265 2266err_no_initvals: 2267 err = ctx->fatal_failure = -EOPNOTSUPP; 2268 b43err(dev->wl, "The driver does not know which firmware (initvals) " 2269 "is required for your device (wl-core rev %u)\n", rev); 2270 goto error; 2271 2272err_load: 2273 /* We failed to load this firmware image. The error message 2274 * already is in ctx->errors. Return and let our caller decide 2275 * what to do. */ 2276 goto error; 2277 2278error: 2279 b43_release_firmware(dev); 2280 return err; 2281} 2282 2283static int b43_request_firmware(struct b43_wldev *dev) 2284{ 2285 struct b43_request_fw_context *ctx; 2286 unsigned int i; 2287 int err; 2288 const char *errmsg; 2289 2290 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2291 if (!ctx) 2292 return -ENOMEM; 2293 ctx->dev = dev; 2294 2295 ctx->req_type = B43_FWTYPE_PROPRIETARY; 2296 err = b43_try_request_fw(ctx); 2297 if (!err) 2298 goto out; /* Successfully loaded it. */ 2299 err = ctx->fatal_failure; 2300 if (err) 2301 goto out; 2302 2303 ctx->req_type = B43_FWTYPE_OPENSOURCE; 2304 err = b43_try_request_fw(ctx); 2305 if (!err) 2306 goto out; /* Successfully loaded it. */ 2307 err = ctx->fatal_failure; 2308 if (err) 2309 goto out; 2310 2311 /* Could not find a usable firmware. Print the errors. */ 2312 for (i = 0; i < B43_NR_FWTYPES; i++) { 2313 errmsg = ctx->errors[i]; 2314 if (strlen(errmsg)) 2315 b43err(dev->wl, errmsg); 2316 } 2317 b43_print_fw_helptext(dev->wl, 1); 2318 err = -ENOENT; 2319 2320out: 2321 kfree(ctx); 2322 return err; 2323} 2324 2325static int b43_upload_microcode(struct b43_wldev *dev) 2326{ 2327 struct wiphy *wiphy = dev->wl->hw->wiphy; 2328 const size_t hdr_len = sizeof(struct b43_fw_header); 2329 const __be32 *data; 2330 unsigned int i, len; 2331 u16 fwrev, fwpatch, fwdate, fwtime; 2332 u32 tmp, macctl; 2333 int err = 0; 2334 2335 /* Jump the microcode PSM to offset 0 */ 2336 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2337 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); 2338 macctl |= B43_MACCTL_PSM_JMP0; 2339 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2340 /* Zero out all microcode PSM registers and shared memory. */ 2341 for (i = 0; i < 64; i++) 2342 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); 2343 for (i = 0; i < 4096; i += 2) 2344 b43_shm_write16(dev, B43_SHM_SHARED, i, 0); 2345 2346 /* Upload Microcode. */ 2347 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); 2348 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); 2349 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 2350 for (i = 0; i < len; i++) { 2351 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2352 udelay(10); 2353 } 2354 2355 if (dev->fw.pcm.data) { 2356 /* Upload PCM data. */ 2357 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); 2358 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); 2359 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 2360 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 2361 /* No need for autoinc bit in SHM_HW */ 2362 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 2363 for (i = 0; i < len; i++) { 2364 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2365 udelay(10); 2366 } 2367 } 2368 2369 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 2370 2371 /* Start the microcode PSM */ 2372 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2373 macctl &= ~B43_MACCTL_PSM_JMP0; 2374 macctl |= B43_MACCTL_PSM_RUN; 2375 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2376 2377 /* Wait for the microcode to load and respond */ 2378 i = 0; 2379 while (1) { 2380 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2381 if (tmp == B43_IRQ_MAC_SUSPENDED) 2382 break; 2383 i++; 2384 if (i >= 20) { 2385 b43err(dev->wl, "Microcode not responding\n"); 2386 b43_print_fw_helptext(dev->wl, 1); 2387 err = -ENODEV; 2388 goto error; 2389 } 2390 msleep(50); 2391 } 2392 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 2393 2394 /* Get and check the revisions. */ 2395 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 2396 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 2397 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 2398 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 2399 2400 if (fwrev <= 0x128) { 2401 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 2402 "binary drivers older than version 4.x is unsupported. " 2403 "You must upgrade your firmware files.\n"); 2404 b43_print_fw_helptext(dev->wl, 1); 2405 err = -EOPNOTSUPP; 2406 goto error; 2407 } 2408 dev->fw.rev = fwrev; 2409 dev->fw.patch = fwpatch; 2410 dev->fw.opensource = (fwdate == 0xFFFF); 2411 2412 /* Default to use-all-queues. */ 2413 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues; 2414 dev->qos_enabled = !!modparam_qos; 2415 /* Default to firmware/hardware crypto acceleration. */ 2416 dev->hwcrypto_enabled = 1; 2417 2418 if (dev->fw.opensource) { 2419 u16 fwcapa; 2420 2421 /* Patchlevel info is encoded in the "time" field. */ 2422 dev->fw.patch = fwtime; 2423 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n", 2424 dev->fw.rev, dev->fw.patch); 2425 2426 fwcapa = b43_fwcapa_read(dev); 2427 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) { 2428 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n"); 2429 /* Disable hardware crypto and fall back to software crypto. */ 2430 dev->hwcrypto_enabled = 0; 2431 } 2432 if (!(fwcapa & B43_FWCAPA_QOS)) { 2433 b43info(dev->wl, "QoS not supported by firmware\n"); 2434 /* Disable QoS. Tweak hw->queues to 1. It will be restored before 2435 * ieee80211_unregister to make sure the networking core can 2436 * properly free possible resources. */ 2437 dev->wl->hw->queues = 1; 2438 dev->qos_enabled = 0; 2439 } 2440 } else { 2441 b43info(dev->wl, "Loading firmware version %u.%u " 2442 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 2443 fwrev, fwpatch, 2444 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 2445 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 2446 if (dev->fw.pcm_request_failed) { 2447 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. " 2448 "Hardware accelerated cryptography is disabled.\n"); 2449 b43_print_fw_helptext(dev->wl, 0); 2450 } 2451 } 2452 2453 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", 2454 dev->fw.rev, dev->fw.patch); 2455 wiphy->hw_version = dev->dev->core_id; 2456 2457 if (b43_is_old_txhdr_format(dev)) { 2458 /* We're over the deadline, but we keep support for old fw 2459 * until it turns out to be in major conflict with something new. */ 2460 b43warn(dev->wl, "You are using an old firmware image. " 2461 "Support for old firmware will be removed soon " 2462 "(official deadline was July 2008).\n"); 2463 b43_print_fw_helptext(dev->wl, 0); 2464 } 2465 2466 return 0; 2467 2468error: 2469 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2470 macctl &= ~B43_MACCTL_PSM_RUN; 2471 macctl |= B43_MACCTL_PSM_JMP0; 2472 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2473 2474 return err; 2475} 2476 2477static int b43_write_initvals(struct b43_wldev *dev, 2478 const struct b43_iv *ivals, 2479 size_t count, 2480 size_t array_size) 2481{ 2482 const struct b43_iv *iv; 2483 u16 offset; 2484 size_t i; 2485 bool bit32; 2486 2487 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 2488 iv = ivals; 2489 for (i = 0; i < count; i++) { 2490 if (array_size < sizeof(iv->offset_size)) 2491 goto err_format; 2492 array_size -= sizeof(iv->offset_size); 2493 offset = be16_to_cpu(iv->offset_size); 2494 bit32 = !!(offset & B43_IV_32BIT); 2495 offset &= B43_IV_OFFSET_MASK; 2496 if (offset >= 0x1000) 2497 goto err_format; 2498 if (bit32) { 2499 u32 value; 2500 2501 if (array_size < sizeof(iv->data.d32)) 2502 goto err_format; 2503 array_size -= sizeof(iv->data.d32); 2504 2505 value = get_unaligned_be32(&iv->data.d32); 2506 b43_write32(dev, offset, value); 2507 2508 iv = (const struct b43_iv *)((const uint8_t *)iv + 2509 sizeof(__be16) + 2510 sizeof(__be32)); 2511 } else { 2512 u16 value; 2513 2514 if (array_size < sizeof(iv->data.d16)) 2515 goto err_format; 2516 array_size -= sizeof(iv->data.d16); 2517 2518 value = be16_to_cpu(iv->data.d16); 2519 b43_write16(dev, offset, value); 2520 2521 iv = (const struct b43_iv *)((const uint8_t *)iv + 2522 sizeof(__be16) + 2523 sizeof(__be16)); 2524 } 2525 } 2526 if (array_size) 2527 goto err_format; 2528 2529 return 0; 2530 2531err_format: 2532 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 2533 b43_print_fw_helptext(dev->wl, 1); 2534 2535 return -EPROTO; 2536} 2537 2538static int b43_upload_initvals(struct b43_wldev *dev) 2539{ 2540 const size_t hdr_len = sizeof(struct b43_fw_header); 2541 const struct b43_fw_header *hdr; 2542 struct b43_firmware *fw = &dev->fw; 2543 const struct b43_iv *ivals; 2544 size_t count; 2545 int err; 2546 2547 hdr = (const struct b43_fw_header *)(fw->initvals.data->data); 2548 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); 2549 count = be32_to_cpu(hdr->size); 2550 err = b43_write_initvals(dev, ivals, count, 2551 fw->initvals.data->size - hdr_len); 2552 if (err) 2553 goto out; 2554 if (fw->initvals_band.data) { 2555 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); 2556 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); 2557 count = be32_to_cpu(hdr->size); 2558 err = b43_write_initvals(dev, ivals, count, 2559 fw->initvals_band.data->size - hdr_len); 2560 if (err) 2561 goto out; 2562 } 2563out: 2564 2565 return err; 2566} 2567 2568/* Initialize the GPIOs 2569 * http://bcm-specs.sipsolutions.net/GPIO 2570 */ 2571static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev) 2572{ 2573 struct ssb_bus *bus = dev->dev->sdev->bus; 2574 2575#ifdef CONFIG_SSB_DRIVER_PCICORE 2576 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev); 2577#else 2578 return bus->chipco.dev; 2579#endif 2580} 2581 2582static int b43_gpio_init(struct b43_wldev *dev) 2583{ 2584 struct ssb_device *gpiodev; 2585 u32 mask, set; 2586 2587 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2588 & ~B43_MACCTL_GPOUTSMSK); 2589 2590 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 2591 | 0x000F); 2592 2593 mask = 0x0000001F; 2594 set = 0x0000000F; 2595 if (dev->dev->chip_id == 0x4301) { 2596 mask |= 0x0060; 2597 set |= 0x0060; 2598 } 2599 if (0 /* FIXME: conditional unknown */ ) { 2600 b43_write16(dev, B43_MMIO_GPIO_MASK, 2601 b43_read16(dev, B43_MMIO_GPIO_MASK) 2602 | 0x0100); 2603 mask |= 0x0180; 2604 set |= 0x0180; 2605 } 2606 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) { 2607 b43_write16(dev, B43_MMIO_GPIO_MASK, 2608 b43_read16(dev, B43_MMIO_GPIO_MASK) 2609 | 0x0200); 2610 mask |= 0x0200; 2611 set |= 0x0200; 2612 } 2613 if (dev->dev->core_rev >= 2) 2614 mask |= 0x0010; /* FIXME: This is redundant. */ 2615 2616 gpiodev = b43_ssb_gpio_dev(dev); 2617 if (gpiodev) 2618 ssb_write32(gpiodev, B43_GPIO_CONTROL, 2619 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2620 & mask) | set); 2621 2622 return 0; 2623} 2624 2625/* Turn off all GPIO stuff. Call this on module unload, for example. */ 2626static void b43_gpio_cleanup(struct b43_wldev *dev) 2627{ 2628 struct ssb_device *gpiodev; 2629 2630 gpiodev = b43_ssb_gpio_dev(dev); 2631 if (gpiodev) 2632 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2633} 2634 2635/* http://bcm-specs.sipsolutions.net/EnableMac */ 2636void b43_mac_enable(struct b43_wldev *dev) 2637{ 2638 if (b43_debug(dev, B43_DBG_FIRMWARE)) { 2639 u16 fwstate; 2640 2641 fwstate = b43_shm_read16(dev, B43_SHM_SHARED, 2642 B43_SHM_SH_UCODESTAT); 2643 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) && 2644 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) { 2645 b43err(dev->wl, "b43_mac_enable(): The firmware " 2646 "should be suspended, but current state is %u\n", 2647 fwstate); 2648 } 2649 } 2650 2651 dev->mac_suspended--; 2652 B43_WARN_ON(dev->mac_suspended < 0); 2653 if (dev->mac_suspended == 0) { 2654 b43_write32(dev, B43_MMIO_MACCTL, 2655 b43_read32(dev, B43_MMIO_MACCTL) 2656 | B43_MACCTL_ENABLED); 2657 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2658 B43_IRQ_MAC_SUSPENDED); 2659 /* Commit writes */ 2660 b43_read32(dev, B43_MMIO_MACCTL); 2661 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2662 b43_power_saving_ctl_bits(dev, 0); 2663 } 2664} 2665 2666/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2667void b43_mac_suspend(struct b43_wldev *dev) 2668{ 2669 int i; 2670 u32 tmp; 2671 2672 might_sleep(); 2673 B43_WARN_ON(dev->mac_suspended < 0); 2674 2675 if (dev->mac_suspended == 0) { 2676 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2677 b43_write32(dev, B43_MMIO_MACCTL, 2678 b43_read32(dev, B43_MMIO_MACCTL) 2679 & ~B43_MACCTL_ENABLED); 2680 /* force pci to flush the write */ 2681 b43_read32(dev, B43_MMIO_MACCTL); 2682 for (i = 35; i; i--) { 2683 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2684 if (tmp & B43_IRQ_MAC_SUSPENDED) 2685 goto out; 2686 udelay(10); 2687 } 2688 /* Hm, it seems this will take some time. Use msleep(). */ 2689 for (i = 40; i; i--) { 2690 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2691 if (tmp & B43_IRQ_MAC_SUSPENDED) 2692 goto out; 2693 msleep(1); 2694 } 2695 b43err(dev->wl, "MAC suspend failed\n"); 2696 } 2697out: 2698 dev->mac_suspended++; 2699} 2700 2701/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 2702void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on) 2703{ 2704 u32 tmslow = ssb_read32(dev->sdev, SSB_TMSLOW); 2705 if (on) 2706 tmslow |= B43_TMSLOW_MACPHYCLKEN; 2707 else 2708 tmslow &= ~B43_TMSLOW_MACPHYCLKEN; 2709 ssb_write32(dev->sdev, SSB_TMSLOW, tmslow); 2710} 2711 2712static void b43_adjust_opmode(struct b43_wldev *dev) 2713{ 2714 struct b43_wl *wl = dev->wl; 2715 u32 ctl; 2716 u16 cfp_pretbtt; 2717 2718 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2719 /* Reset status to STA infrastructure mode. */ 2720 ctl &= ~B43_MACCTL_AP; 2721 ctl &= ~B43_MACCTL_KEEP_CTL; 2722 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2723 ctl &= ~B43_MACCTL_KEEP_BAD; 2724 ctl &= ~B43_MACCTL_PROMISC; 2725 ctl &= ~B43_MACCTL_BEACPROMISC; 2726 ctl |= B43_MACCTL_INFRA; 2727 2728 if (b43_is_mode(wl, NL80211_IFTYPE_AP) || 2729 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 2730 ctl |= B43_MACCTL_AP; 2731 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 2732 ctl &= ~B43_MACCTL_INFRA; 2733 2734 if (wl->filter_flags & FIF_CONTROL) 2735 ctl |= B43_MACCTL_KEEP_CTL; 2736 if (wl->filter_flags & FIF_FCSFAIL) 2737 ctl |= B43_MACCTL_KEEP_BAD; 2738 if (wl->filter_flags & FIF_PLCPFAIL) 2739 ctl |= B43_MACCTL_KEEP_BADPLCP; 2740 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2741 ctl |= B43_MACCTL_PROMISC; 2742 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2743 ctl |= B43_MACCTL_BEACPROMISC; 2744 2745 /* Workaround: On old hardware the HW-MAC-address-filter 2746 * doesn't work properly, so always run promisc in filter 2747 * it in software. */ 2748 if (dev->dev->core_rev <= 4) 2749 ctl |= B43_MACCTL_PROMISC; 2750 2751 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2752 2753 cfp_pretbtt = 2; 2754 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2755 if (dev->dev->chip_id == 0x4306 && 2756 dev->dev->chip_rev == 3) 2757 cfp_pretbtt = 100; 2758 else 2759 cfp_pretbtt = 50; 2760 } 2761 b43_write16(dev, 0x612, cfp_pretbtt); 2762 2763 /* FIXME: We don't currently implement the PMQ mechanism, 2764 * so always disable it. If we want to implement PMQ, 2765 * we need to enable it here (clear DISCPMQ) in AP mode. 2766 */ 2767 if (0 /* ctl & B43_MACCTL_AP */) { 2768 b43_write32(dev, B43_MMIO_MACCTL, 2769 b43_read32(dev, B43_MMIO_MACCTL) 2770 & ~B43_MACCTL_DISCPMQ); 2771 } else { 2772 b43_write32(dev, B43_MMIO_MACCTL, 2773 b43_read32(dev, B43_MMIO_MACCTL) 2774 | B43_MACCTL_DISCPMQ); 2775 } 2776} 2777 2778static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2779{ 2780 u16 offset; 2781 2782 if (is_ofdm) { 2783 offset = 0x480; 2784 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2785 } else { 2786 offset = 0x4C0; 2787 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2788 } 2789 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2790 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2791} 2792 2793static void b43_rate_memory_init(struct b43_wldev *dev) 2794{ 2795 switch (dev->phy.type) { 2796 case B43_PHYTYPE_A: 2797 case B43_PHYTYPE_G: 2798 case B43_PHYTYPE_N: 2799 case B43_PHYTYPE_LP: 2800 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2801 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2802 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2803 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2804 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2805 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2806 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2807 if (dev->phy.type == B43_PHYTYPE_A) 2808 break; 2809 /* fallthrough */ 2810 case B43_PHYTYPE_B: 2811 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2812 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2813 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2814 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2815 break; 2816 default: 2817 B43_WARN_ON(1); 2818 } 2819} 2820 2821/* Set the default values for the PHY TX Control Words. */ 2822static void b43_set_phytxctl_defaults(struct b43_wldev *dev) 2823{ 2824 u16 ctl = 0; 2825 2826 ctl |= B43_TXH_PHY_ENC_CCK; 2827 ctl |= B43_TXH_PHY_ANT01AUTO; 2828 ctl |= B43_TXH_PHY_TXPWR; 2829 2830 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 2831 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); 2832 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); 2833} 2834 2835/* Set the TX-Antenna for management frames sent by firmware. */ 2836static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2837{ 2838 u16 ant; 2839 u16 tmp; 2840 2841 ant = b43_antenna_to_phyctl(antenna); 2842 2843 /* For ACK/CTS */ 2844 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2845 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2846 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2847 /* For Probe Resposes */ 2848 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2849 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2850 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2851} 2852 2853/* This is the opposite of b43_chip_init() */ 2854static void b43_chip_exit(struct b43_wldev *dev) 2855{ 2856 b43_phy_exit(dev); 2857 b43_gpio_cleanup(dev); 2858 /* firmware is released later */ 2859} 2860 2861/* Initialize the chip 2862 * http://bcm-specs.sipsolutions.net/ChipInit 2863 */ 2864static int b43_chip_init(struct b43_wldev *dev) 2865{ 2866 struct b43_phy *phy = &dev->phy; 2867 int err; 2868 u32 macctl; 2869 u16 value16; 2870 2871 /* Initialize the MAC control */ 2872 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; 2873 if (dev->phy.gmode) 2874 macctl |= B43_MACCTL_GMODE; 2875 macctl |= B43_MACCTL_INFRA; 2876 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2877 2878 err = b43_request_firmware(dev); 2879 if (err) 2880 goto out; 2881 err = b43_upload_microcode(dev); 2882 if (err) 2883 goto out; /* firmware is released later */ 2884 2885 err = b43_gpio_init(dev); 2886 if (err) 2887 goto out; /* firmware is released later */ 2888 2889 err = b43_upload_initvals(dev); 2890 if (err) 2891 goto err_gpio_clean; 2892 2893 /* Turn the Analog on and initialize the PHY. */ 2894 phy->ops->switch_analog(dev, 1); 2895 err = b43_phy_init(dev); 2896 if (err) 2897 goto err_gpio_clean; 2898 2899 /* Disable Interference Mitigation. */ 2900 if (phy->ops->interf_mitigation) 2901 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); 2902 2903 /* Select the antennae */ 2904 if (phy->ops->set_rx_antenna) 2905 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2906 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2907 2908 if (phy->type == B43_PHYTYPE_B) { 2909 value16 = b43_read16(dev, 0x005E); 2910 value16 |= 0x0004; 2911 b43_write16(dev, 0x005E, value16); 2912 } 2913 b43_write32(dev, 0x0100, 0x01000000); 2914 if (dev->dev->core_rev < 5) 2915 b43_write32(dev, 0x010C, 0x01000000); 2916 2917 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2918 & ~B43_MACCTL_INFRA); 2919 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2920 | B43_MACCTL_INFRA); 2921 2922 /* Probe Response Timeout value */ 2923 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2924 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2925 2926 /* Initially set the wireless operation mode. */ 2927 b43_adjust_opmode(dev); 2928 2929 if (dev->dev->core_rev < 3) { 2930 b43_write16(dev, 0x060E, 0x0000); 2931 b43_write16(dev, 0x0610, 0x8000); 2932 b43_write16(dev, 0x0604, 0x0000); 2933 b43_write16(dev, 0x0606, 0x0200); 2934 } else { 2935 b43_write32(dev, 0x0188, 0x80000000); 2936 b43_write32(dev, 0x018C, 0x02000000); 2937 } 2938 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2939 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2940 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2941 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2942 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2943 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2944 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2945 2946 b43_mac_phy_clock_set(dev, true); 2947 2948 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2949 dev->sdev->bus->chipco.fast_pwrup_delay); 2950 2951 err = 0; 2952 b43dbg(dev->wl, "Chip initialized\n"); 2953out: 2954 return err; 2955 2956err_gpio_clean: 2957 b43_gpio_cleanup(dev); 2958 return err; 2959} 2960 2961static void b43_periodic_every60sec(struct b43_wldev *dev) 2962{ 2963 const struct b43_phy_operations *ops = dev->phy.ops; 2964 2965 if (ops->pwork_60sec) 2966 ops->pwork_60sec(dev); 2967 2968 /* Force check the TX power emission now. */ 2969 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME); 2970} 2971 2972static void b43_periodic_every30sec(struct b43_wldev *dev) 2973{ 2974 /* Update device statistics. */ 2975 b43_calculate_link_quality(dev); 2976} 2977 2978static void b43_periodic_every15sec(struct b43_wldev *dev) 2979{ 2980 struct b43_phy *phy = &dev->phy; 2981 u16 wdr; 2982 2983 if (dev->fw.opensource) { 2984 /* Check if the firmware is still alive. 2985 * It will reset the watchdog counter to 0 in its idle loop. */ 2986 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG); 2987 if (unlikely(wdr)) { 2988 b43err(dev->wl, "Firmware watchdog: The firmware died!\n"); 2989 b43_controller_restart(dev, "Firmware watchdog"); 2990 return; 2991 } else { 2992 b43_shm_write16(dev, B43_SHM_SCRATCH, 2993 B43_WATCHDOG_REG, 1); 2994 } 2995 } 2996 2997 if (phy->ops->pwork_15sec) 2998 phy->ops->pwork_15sec(dev); 2999 3000 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3001 wmb(); 3002 3003#if B43_DEBUG 3004 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 3005 unsigned int i; 3006 3007 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n", 3008 dev->irq_count / 15, 3009 dev->tx_count / 15, 3010 dev->rx_count / 15); 3011 dev->irq_count = 0; 3012 dev->tx_count = 0; 3013 dev->rx_count = 0; 3014 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 3015 if (dev->irq_bit_count[i]) { 3016 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", 3017 dev->irq_bit_count[i] / 15, i, (1 << i)); 3018 dev->irq_bit_count[i] = 0; 3019 } 3020 } 3021 } 3022#endif 3023} 3024 3025static void do_periodic_work(struct b43_wldev *dev) 3026{ 3027 unsigned int state; 3028 3029 state = dev->periodic_state; 3030 if (state % 4 == 0) 3031 b43_periodic_every60sec(dev); 3032 if (state % 2 == 0) 3033 b43_periodic_every30sec(dev); 3034 b43_periodic_every15sec(dev); 3035} 3036 3037/* Periodic work locking policy: 3038 * The whole periodic work handler is protected by 3039 * wl->mutex. If another lock is needed somewhere in the 3040 * pwork callchain, it's acquired in-place, where it's needed. 3041 */ 3042static void b43_periodic_work_handler(struct work_struct *work) 3043{ 3044 struct b43_wldev *dev = container_of(work, struct b43_wldev, 3045 periodic_work.work); 3046 struct b43_wl *wl = dev->wl; 3047 unsigned long delay; 3048 3049 mutex_lock(&wl->mutex); 3050 3051 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 3052 goto out; 3053 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 3054 goto out_requeue; 3055 3056 do_periodic_work(dev); 3057 3058 dev->periodic_state++; 3059out_requeue: 3060 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 3061 delay = msecs_to_jiffies(50); 3062 else 3063 delay = round_jiffies_relative(HZ * 15); 3064 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); 3065out: 3066 mutex_unlock(&wl->mutex); 3067} 3068 3069static void b43_periodic_tasks_setup(struct b43_wldev *dev) 3070{ 3071 struct delayed_work *work = &dev->periodic_work; 3072 3073 dev->periodic_state = 0; 3074 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 3075 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); 3076} 3077 3078/* Check if communication with the device works correctly. */ 3079static int b43_validate_chipaccess(struct b43_wldev *dev) 3080{ 3081 u32 v, backup0, backup4; 3082 3083 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); 3084 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4); 3085 3086 /* Check for read/write and endianness problems. */ 3087 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 3088 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 3089 goto error; 3090 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 3091 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 3092 goto error; 3093 3094 /* Check if unaligned 32bit SHM_SHARED access works properly. 3095 * However, don't bail out on failure, because it's noncritical. */ 3096 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); 3097 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); 3098 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); 3099 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); 3100 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) 3101 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n"); 3102 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); 3103 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || 3104 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || 3105 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || 3106 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) 3107 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n"); 3108 3109 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); 3110 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); 3111 3112 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) { 3113 /* The 32bit register shadows the two 16bit registers 3114 * with update sideeffects. Validate this. */ 3115 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 3116 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 3117 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 3118 goto error; 3119 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 3120 goto error; 3121 } 3122 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 3123 3124 v = b43_read32(dev, B43_MMIO_MACCTL); 3125 v |= B43_MACCTL_GMODE; 3126 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 3127 goto error; 3128 3129 return 0; 3130error: 3131 b43err(dev->wl, "Failed to validate the chipaccess\n"); 3132 return -ENODEV; 3133} 3134 3135static void b43_security_init(struct b43_wldev *dev) 3136{ 3137 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 3138 /* KTP is a word address, but we address SHM bytewise. 3139 * So multiply by two. 3140 */ 3141 dev->ktp *= 2; 3142 /* Number of RCMTA address slots */ 3143 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS); 3144 /* Clear the key memory. */ 3145 b43_clear_keys(dev); 3146} 3147 3148#ifdef CONFIG_B43_HWRNG 3149static int b43_rng_read(struct hwrng *rng, u32 *data) 3150{ 3151 struct b43_wl *wl = (struct b43_wl *)rng->priv; 3152 struct b43_wldev *dev; 3153 int count = -ENODEV; 3154 3155 mutex_lock(&wl->mutex); 3156 dev = wl->current_dev; 3157 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) { 3158 *data = b43_read16(dev, B43_MMIO_RNG); 3159 count = sizeof(u16); 3160 } 3161 mutex_unlock(&wl->mutex); 3162 3163 return count; 3164} 3165#endif /* CONFIG_B43_HWRNG */ 3166 3167static void b43_rng_exit(struct b43_wl *wl) 3168{ 3169#ifdef CONFIG_B43_HWRNG 3170 if (wl->rng_initialized) 3171 hwrng_unregister(&wl->rng); 3172#endif /* CONFIG_B43_HWRNG */ 3173} 3174 3175static int b43_rng_init(struct b43_wl *wl) 3176{ 3177 int err = 0; 3178 3179#ifdef CONFIG_B43_HWRNG 3180 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 3181 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 3182 wl->rng.name = wl->rng_name; 3183 wl->rng.data_read = b43_rng_read; 3184 wl->rng.priv = (unsigned long)wl; 3185 wl->rng_initialized = 1; 3186 err = hwrng_register(&wl->rng); 3187 if (err) { 3188 wl->rng_initialized = 0; 3189 b43err(wl, "Failed to register the random " 3190 "number generator (%d)\n", err); 3191 } 3192#endif /* CONFIG_B43_HWRNG */ 3193 3194 return err; 3195} 3196 3197static void b43_tx_work(struct work_struct *work) 3198{ 3199 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work); 3200 struct b43_wldev *dev; 3201 struct sk_buff *skb; 3202 int err = 0; 3203 3204 mutex_lock(&wl->mutex); 3205 dev = wl->current_dev; 3206 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) { 3207 mutex_unlock(&wl->mutex); 3208 return; 3209 } 3210 3211 while (skb_queue_len(&wl->tx_queue)) { 3212 skb = skb_dequeue(&wl->tx_queue); 3213 3214 if (b43_using_pio_transfers(dev)) 3215 err = b43_pio_tx(dev, skb); 3216 else 3217 err = b43_dma_tx(dev, skb); 3218 if (unlikely(err)) 3219 dev_kfree_skb(skb); /* Drop it */ 3220 } 3221 3222#if B43_DEBUG 3223 dev->tx_count++; 3224#endif 3225 mutex_unlock(&wl->mutex); 3226} 3227 3228static void b43_op_tx(struct ieee80211_hw *hw, 3229 struct sk_buff *skb) 3230{ 3231 struct b43_wl *wl = hw_to_b43_wl(hw); 3232 3233 if (unlikely(skb->len < 2 + 2 + 6)) { 3234 /* Too short, this can't be a valid frame. */ 3235 dev_kfree_skb_any(skb); 3236 return; 3237 } 3238 B43_WARN_ON(skb_shinfo(skb)->nr_frags); 3239 3240 skb_queue_tail(&wl->tx_queue, skb); 3241 ieee80211_queue_work(wl->hw, &wl->tx_work); 3242} 3243 3244static void b43_qos_params_upload(struct b43_wldev *dev, 3245 const struct ieee80211_tx_queue_params *p, 3246 u16 shm_offset) 3247{ 3248 u16 params[B43_NR_QOSPARAMS]; 3249 int bslots, tmp; 3250 unsigned int i; 3251 3252 if (!dev->qos_enabled) 3253 return; 3254 3255 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min; 3256 3257 memset(¶ms, 0, sizeof(params)); 3258 3259 params[B43_QOSPARAM_TXOP] = p->txop * 32; 3260 params[B43_QOSPARAM_CWMIN] = p->cw_min; 3261 params[B43_QOSPARAM_CWMAX] = p->cw_max; 3262 params[B43_QOSPARAM_CWCUR] = p->cw_min; 3263 params[B43_QOSPARAM_AIFS] = p->aifs; 3264 params[B43_QOSPARAM_BSLOTS] = bslots; 3265 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs; 3266 3267 for (i = 0; i < ARRAY_SIZE(params); i++) { 3268 if (i == B43_QOSPARAM_STATUS) { 3269 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 3270 shm_offset + (i * 2)); 3271 /* Mark the parameters as updated. */ 3272 tmp |= 0x100; 3273 b43_shm_write16(dev, B43_SHM_SHARED, 3274 shm_offset + (i * 2), 3275 tmp); 3276 } else { 3277 b43_shm_write16(dev, B43_SHM_SHARED, 3278 shm_offset + (i * 2), 3279 params[i]); 3280 } 3281 } 3282} 3283 3284/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */ 3285static const u16 b43_qos_shm_offsets[] = { 3286 /* [mac80211-queue-nr] = SHM_OFFSET, */ 3287 [0] = B43_QOS_VOICE, 3288 [1] = B43_QOS_VIDEO, 3289 [2] = B43_QOS_BESTEFFORT, 3290 [3] = B43_QOS_BACKGROUND, 3291}; 3292 3293/* Update all QOS parameters in hardware. */ 3294static void b43_qos_upload_all(struct b43_wldev *dev) 3295{ 3296 struct b43_wl *wl = dev->wl; 3297 struct b43_qos_params *params; 3298 unsigned int i; 3299 3300 if (!dev->qos_enabled) 3301 return; 3302 3303 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3304 ARRAY_SIZE(wl->qos_params)); 3305 3306 b43_mac_suspend(dev); 3307 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3308 params = &(wl->qos_params[i]); 3309 b43_qos_params_upload(dev, &(params->p), 3310 b43_qos_shm_offsets[i]); 3311 } 3312 b43_mac_enable(dev); 3313} 3314 3315static void b43_qos_clear(struct b43_wl *wl) 3316{ 3317 struct b43_qos_params *params; 3318 unsigned int i; 3319 3320 /* Initialize QoS parameters to sane defaults. */ 3321 3322 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3323 ARRAY_SIZE(wl->qos_params)); 3324 3325 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3326 params = &(wl->qos_params[i]); 3327 3328 switch (b43_qos_shm_offsets[i]) { 3329 case B43_QOS_VOICE: 3330 params->p.txop = 0; 3331 params->p.aifs = 2; 3332 params->p.cw_min = 0x0001; 3333 params->p.cw_max = 0x0001; 3334 break; 3335 case B43_QOS_VIDEO: 3336 params->p.txop = 0; 3337 params->p.aifs = 2; 3338 params->p.cw_min = 0x0001; 3339 params->p.cw_max = 0x0001; 3340 break; 3341 case B43_QOS_BESTEFFORT: 3342 params->p.txop = 0; 3343 params->p.aifs = 3; 3344 params->p.cw_min = 0x0001; 3345 params->p.cw_max = 0x03FF; 3346 break; 3347 case B43_QOS_BACKGROUND: 3348 params->p.txop = 0; 3349 params->p.aifs = 7; 3350 params->p.cw_min = 0x0001; 3351 params->p.cw_max = 0x03FF; 3352 break; 3353 default: 3354 B43_WARN_ON(1); 3355 } 3356 } 3357} 3358 3359/* Initialize the core's QOS capabilities */ 3360static void b43_qos_init(struct b43_wldev *dev) 3361{ 3362 if (!dev->qos_enabled) { 3363 /* Disable QOS support. */ 3364 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF); 3365 b43_write16(dev, B43_MMIO_IFSCTL, 3366 b43_read16(dev, B43_MMIO_IFSCTL) 3367 & ~B43_MMIO_IFSCTL_USE_EDCF); 3368 b43dbg(dev->wl, "QoS disabled\n"); 3369 return; 3370 } 3371 3372 /* Upload the current QOS parameters. */ 3373 b43_qos_upload_all(dev); 3374 3375 /* Enable QOS support. */ 3376 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); 3377 b43_write16(dev, B43_MMIO_IFSCTL, 3378 b43_read16(dev, B43_MMIO_IFSCTL) 3379 | B43_MMIO_IFSCTL_USE_EDCF); 3380 b43dbg(dev->wl, "QoS enabled\n"); 3381} 3382 3383static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue, 3384 const struct ieee80211_tx_queue_params *params) 3385{ 3386 struct b43_wl *wl = hw_to_b43_wl(hw); 3387 struct b43_wldev *dev; 3388 unsigned int queue = (unsigned int)_queue; 3389 int err = -ENODEV; 3390 3391 if (queue >= ARRAY_SIZE(wl->qos_params)) { 3392 /* Queue not available or don't support setting 3393 * params on this queue. Return success to not 3394 * confuse mac80211. */ 3395 return 0; 3396 } 3397 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3398 ARRAY_SIZE(wl->qos_params)); 3399 3400 mutex_lock(&wl->mutex); 3401 dev = wl->current_dev; 3402 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) 3403 goto out_unlock; 3404 3405 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params)); 3406 b43_mac_suspend(dev); 3407 b43_qos_params_upload(dev, &(wl->qos_params[queue].p), 3408 b43_qos_shm_offsets[queue]); 3409 b43_mac_enable(dev); 3410 err = 0; 3411 3412out_unlock: 3413 mutex_unlock(&wl->mutex); 3414 3415 return err; 3416} 3417 3418static int b43_op_get_stats(struct ieee80211_hw *hw, 3419 struct ieee80211_low_level_stats *stats) 3420{ 3421 struct b43_wl *wl = hw_to_b43_wl(hw); 3422 3423 mutex_lock(&wl->mutex); 3424 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 3425 mutex_unlock(&wl->mutex); 3426 3427 return 0; 3428} 3429 3430static u64 b43_op_get_tsf(struct ieee80211_hw *hw) 3431{ 3432 struct b43_wl *wl = hw_to_b43_wl(hw); 3433 struct b43_wldev *dev; 3434 u64 tsf; 3435 3436 mutex_lock(&wl->mutex); 3437 dev = wl->current_dev; 3438 3439 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3440 b43_tsf_read(dev, &tsf); 3441 else 3442 tsf = 0; 3443 3444 mutex_unlock(&wl->mutex); 3445 3446 return tsf; 3447} 3448 3449static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3450{ 3451 struct b43_wl *wl = hw_to_b43_wl(hw); 3452 struct b43_wldev *dev; 3453 3454 mutex_lock(&wl->mutex); 3455 dev = wl->current_dev; 3456 3457 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3458 b43_tsf_write(dev, tsf); 3459 3460 mutex_unlock(&wl->mutex); 3461} 3462 3463static void b43_put_phy_into_reset(struct b43_wldev *dev) 3464{ 3465 struct ssb_device *sdev = dev->sdev; 3466 u32 tmslow; 3467 3468 tmslow = ssb_read32(sdev, SSB_TMSLOW); 3469 tmslow &= ~B43_TMSLOW_GMODE; 3470 tmslow |= B43_TMSLOW_PHYRESET; 3471 tmslow |= SSB_TMSLOW_FGC; 3472 ssb_write32(sdev, SSB_TMSLOW, tmslow); 3473 msleep(1); 3474 3475 tmslow = ssb_read32(sdev, SSB_TMSLOW); 3476 tmslow &= ~SSB_TMSLOW_FGC; 3477 tmslow |= B43_TMSLOW_PHYRESET; 3478 ssb_write32(sdev, SSB_TMSLOW, tmslow); 3479 msleep(1); 3480} 3481 3482static const char *band_to_string(enum ieee80211_band band) 3483{ 3484 switch (band) { 3485 case IEEE80211_BAND_5GHZ: 3486 return "5"; 3487 case IEEE80211_BAND_2GHZ: 3488 return "2.4"; 3489 default: 3490 break; 3491 } 3492 B43_WARN_ON(1); 3493 return ""; 3494} 3495 3496/* Expects wl->mutex locked */ 3497static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan) 3498{ 3499 struct b43_wldev *up_dev = NULL; 3500 struct b43_wldev *down_dev; 3501 struct b43_wldev *d; 3502 int err; 3503 bool uninitialized_var(gmode); 3504 int prev_status; 3505 3506 /* Find a device and PHY which supports the band. */ 3507 list_for_each_entry(d, &wl->devlist, list) { 3508 switch (chan->band) { 3509 case IEEE80211_BAND_5GHZ: 3510 if (d->phy.supports_5ghz) { 3511 up_dev = d; 3512 gmode = 0; 3513 } 3514 break; 3515 case IEEE80211_BAND_2GHZ: 3516 if (d->phy.supports_2ghz) { 3517 up_dev = d; 3518 gmode = 1; 3519 } 3520 break; 3521 default: 3522 B43_WARN_ON(1); 3523 return -EINVAL; 3524 } 3525 if (up_dev) 3526 break; 3527 } 3528 if (!up_dev) { 3529 b43err(wl, "Could not find a device for %s-GHz band operation\n", 3530 band_to_string(chan->band)); 3531 return -ENODEV; 3532 } 3533 if ((up_dev == wl->current_dev) && 3534 (!!wl->current_dev->phy.gmode == !!gmode)) { 3535 /* This device is already running. */ 3536 return 0; 3537 } 3538 b43dbg(wl, "Switching to %s-GHz band\n", 3539 band_to_string(chan->band)); 3540 down_dev = wl->current_dev; 3541 3542 prev_status = b43_status(down_dev); 3543 /* Shutdown the currently running core. */ 3544 if (prev_status >= B43_STAT_STARTED) 3545 down_dev = b43_wireless_core_stop(down_dev); 3546 if (prev_status >= B43_STAT_INITIALIZED) 3547 b43_wireless_core_exit(down_dev); 3548 3549 if (down_dev != up_dev) { 3550 /* We switch to a different core, so we put PHY into 3551 * RESET on the old core. */ 3552 b43_put_phy_into_reset(down_dev); 3553 } 3554 3555 /* Now start the new core. */ 3556 up_dev->phy.gmode = gmode; 3557 if (prev_status >= B43_STAT_INITIALIZED) { 3558 err = b43_wireless_core_init(up_dev); 3559 if (err) { 3560 b43err(wl, "Fatal: Could not initialize device for " 3561 "selected %s-GHz band\n", 3562 band_to_string(chan->band)); 3563 goto init_failure; 3564 } 3565 } 3566 if (prev_status >= B43_STAT_STARTED) { 3567 err = b43_wireless_core_start(up_dev); 3568 if (err) { 3569 b43err(wl, "Fatal: Coult not start device for " 3570 "selected %s-GHz band\n", 3571 band_to_string(chan->band)); 3572 b43_wireless_core_exit(up_dev); 3573 goto init_failure; 3574 } 3575 } 3576 B43_WARN_ON(b43_status(up_dev) != prev_status); 3577 3578 wl->current_dev = up_dev; 3579 3580 return 0; 3581init_failure: 3582 /* Whoops, failed to init the new core. No core is operating now. */ 3583 wl->current_dev = NULL; 3584 return err; 3585} 3586 3587/* Write the short and long frame retry limit values. */ 3588static void b43_set_retry_limits(struct b43_wldev *dev, 3589 unsigned int short_retry, 3590 unsigned int long_retry) 3591{ 3592 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3593 * the chip-internal counter. */ 3594 short_retry = min(short_retry, (unsigned int)0xF); 3595 long_retry = min(long_retry, (unsigned int)0xF); 3596 3597 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3598 short_retry); 3599 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3600 long_retry); 3601} 3602 3603static int b43_op_config(struct ieee80211_hw *hw, u32 changed) 3604{ 3605 struct b43_wl *wl = hw_to_b43_wl(hw); 3606 struct b43_wldev *dev; 3607 struct b43_phy *phy; 3608 struct ieee80211_conf *conf = &hw->conf; 3609 int antenna; 3610 int err = 0; 3611 3612 mutex_lock(&wl->mutex); 3613 3614 /* Switch the band (if necessary). This might change the active core. */ 3615 err = b43_switch_band(wl, conf->channel); 3616 if (err) 3617 goto out_unlock_mutex; 3618 dev = wl->current_dev; 3619 phy = &dev->phy; 3620 3621 if (conf_is_ht(conf)) 3622 phy->is_40mhz = 3623 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf)); 3624 else 3625 phy->is_40mhz = false; 3626 3627 b43_mac_suspend(dev); 3628 3629 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 3630 b43_set_retry_limits(dev, conf->short_frame_max_tx_count, 3631 conf->long_frame_max_tx_count); 3632 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; 3633 if (!changed) 3634 goto out_mac_enable; 3635 3636 /* Switch to the requested channel. 3637 * The firmware takes care of races with the TX handler. */ 3638 if (conf->channel->hw_value != phy->channel) 3639 b43_switch_channel(dev, conf->channel->hw_value); 3640 3641 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 3642 3643 /* Adjust the desired TX power level. */ 3644 if (conf->power_level != 0) { 3645 if (conf->power_level != phy->desired_txpower) { 3646 phy->desired_txpower = conf->power_level; 3647 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME | 3648 B43_TXPWR_IGNORE_TSSI); 3649 } 3650 } 3651 3652 /* Antennas for RX and management frame TX. */ 3653 antenna = B43_ANTENNA_DEFAULT; 3654 b43_mgmtframe_txantenna(dev, antenna); 3655 antenna = B43_ANTENNA_DEFAULT; 3656 if (phy->ops->set_rx_antenna) 3657 phy->ops->set_rx_antenna(dev, antenna); 3658 3659 if (wl->radio_enabled != phy->radio_on) { 3660 if (wl->radio_enabled) { 3661 b43_software_rfkill(dev, false); 3662 b43info(dev->wl, "Radio turned on by software\n"); 3663 if (!dev->radio_hw_enable) { 3664 b43info(dev->wl, "The hardware RF-kill button " 3665 "still turns the radio physically off. " 3666 "Press the button to turn it on.\n"); 3667 } 3668 } else { 3669 b43_software_rfkill(dev, true); 3670 b43info(dev->wl, "Radio turned off by software\n"); 3671 } 3672 } 3673 3674out_mac_enable: 3675 b43_mac_enable(dev); 3676out_unlock_mutex: 3677 mutex_unlock(&wl->mutex); 3678 3679 return err; 3680} 3681 3682static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates) 3683{ 3684 struct ieee80211_supported_band *sband = 3685 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)]; 3686 struct ieee80211_rate *rate; 3687 int i; 3688 u16 basic, direct, offset, basic_offset, rateptr; 3689 3690 for (i = 0; i < sband->n_bitrates; i++) { 3691 rate = &sband->bitrates[i]; 3692 3693 if (b43_is_cck_rate(rate->hw_value)) { 3694 direct = B43_SHM_SH_CCKDIRECT; 3695 basic = B43_SHM_SH_CCKBASIC; 3696 offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3697 offset &= 0xF; 3698 } else { 3699 direct = B43_SHM_SH_OFDMDIRECT; 3700 basic = B43_SHM_SH_OFDMBASIC; 3701 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3702 offset &= 0xF; 3703 } 3704 3705 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); 3706 3707 if (b43_is_cck_rate(rate->hw_value)) { 3708 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3709 basic_offset &= 0xF; 3710 } else { 3711 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3712 basic_offset &= 0xF; 3713 } 3714 3715 /* 3716 * Get the pointer that we need to point to 3717 * from the direct map 3718 */ 3719 rateptr = b43_shm_read16(dev, B43_SHM_SHARED, 3720 direct + 2 * basic_offset); 3721 /* and write it to the basic map */ 3722 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset, 3723 rateptr); 3724 } 3725} 3726 3727static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 3728 struct ieee80211_vif *vif, 3729 struct ieee80211_bss_conf *conf, 3730 u32 changed) 3731{ 3732 struct b43_wl *wl = hw_to_b43_wl(hw); 3733 struct b43_wldev *dev; 3734 3735 mutex_lock(&wl->mutex); 3736 3737 dev = wl->current_dev; 3738 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3739 goto out_unlock_mutex; 3740 3741 B43_WARN_ON(wl->vif != vif); 3742 3743 if (changed & BSS_CHANGED_BSSID) { 3744 if (conf->bssid) 3745 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3746 else 3747 memset(wl->bssid, 0, ETH_ALEN); 3748 } 3749 3750 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3751 if (changed & BSS_CHANGED_BEACON && 3752 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3753 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3754 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3755 b43_update_templates(wl); 3756 3757 if (changed & BSS_CHANGED_BSSID) 3758 b43_write_mac_bssid_templates(dev); 3759 } 3760 3761 b43_mac_suspend(dev); 3762 3763 /* Update templates for AP/mesh mode. */ 3764 if (changed & BSS_CHANGED_BEACON_INT && 3765 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3766 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3767 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3768 b43_set_beacon_int(dev, conf->beacon_int); 3769 3770 if (changed & BSS_CHANGED_BASIC_RATES) 3771 b43_update_basic_rates(dev, conf->basic_rates); 3772 3773 if (changed & BSS_CHANGED_ERP_SLOT) { 3774 if (conf->use_short_slot) 3775 b43_short_slot_timing_enable(dev); 3776 else 3777 b43_short_slot_timing_disable(dev); 3778 } 3779 3780 b43_mac_enable(dev); 3781out_unlock_mutex: 3782 mutex_unlock(&wl->mutex); 3783} 3784 3785static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3786 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3787 struct ieee80211_key_conf *key) 3788{ 3789 struct b43_wl *wl = hw_to_b43_wl(hw); 3790 struct b43_wldev *dev; 3791 u8 algorithm; 3792 u8 index; 3793 int err; 3794 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3795 3796 if (modparam_nohwcrypt) 3797 return -ENOSPC; /* User disabled HW-crypto */ 3798 3799 mutex_lock(&wl->mutex); 3800 3801 dev = wl->current_dev; 3802 err = -ENODEV; 3803 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 3804 goto out_unlock; 3805 3806 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) { 3807 /* We don't have firmware for the crypto engine. 3808 * Must use software-crypto. */ 3809 err = -EOPNOTSUPP; 3810 goto out_unlock; 3811 } 3812 3813 err = -EINVAL; 3814 switch (key->cipher) { 3815 case WLAN_CIPHER_SUITE_WEP40: 3816 algorithm = B43_SEC_ALGO_WEP40; 3817 break; 3818 case WLAN_CIPHER_SUITE_WEP104: 3819 algorithm = B43_SEC_ALGO_WEP104; 3820 break; 3821 case WLAN_CIPHER_SUITE_TKIP: 3822 algorithm = B43_SEC_ALGO_TKIP; 3823 break; 3824 case WLAN_CIPHER_SUITE_CCMP: 3825 algorithm = B43_SEC_ALGO_AES; 3826 break; 3827 default: 3828 B43_WARN_ON(1); 3829 goto out_unlock; 3830 } 3831 index = (u8) (key->keyidx); 3832 if (index > 3) 3833 goto out_unlock; 3834 3835 switch (cmd) { 3836 case SET_KEY: 3837 if (algorithm == B43_SEC_ALGO_TKIP && 3838 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) || 3839 !modparam_hwtkip)) { 3840 /* We support only pairwise key */ 3841 err = -EOPNOTSUPP; 3842 goto out_unlock; 3843 } 3844 3845 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 3846 if (WARN_ON(!sta)) { 3847 err = -EOPNOTSUPP; 3848 goto out_unlock; 3849 } 3850 /* Pairwise key with an assigned MAC address. */ 3851 err = b43_key_write(dev, -1, algorithm, 3852 key->key, key->keylen, 3853 sta->addr, key); 3854 } else { 3855 /* Group key */ 3856 err = b43_key_write(dev, index, algorithm, 3857 key->key, key->keylen, NULL, key); 3858 } 3859 if (err) 3860 goto out_unlock; 3861 3862 if (algorithm == B43_SEC_ALGO_WEP40 || 3863 algorithm == B43_SEC_ALGO_WEP104) { 3864 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 3865 } else { 3866 b43_hf_write(dev, 3867 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 3868 } 3869 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 3870 if (algorithm == B43_SEC_ALGO_TKIP) 3871 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 3872 break; 3873 case DISABLE_KEY: { 3874 err = b43_key_clear(dev, key->hw_key_idx); 3875 if (err) 3876 goto out_unlock; 3877 break; 3878 } 3879 default: 3880 B43_WARN_ON(1); 3881 } 3882 3883out_unlock: 3884 if (!err) { 3885 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 3886 "mac: %pM\n", 3887 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 3888 sta ? sta->addr : bcast_addr); 3889 b43_dump_keymemory(dev); 3890 } 3891 mutex_unlock(&wl->mutex); 3892 3893 return err; 3894} 3895 3896static void b43_op_configure_filter(struct ieee80211_hw *hw, 3897 unsigned int changed, unsigned int *fflags, 3898 u64 multicast) 3899{ 3900 struct b43_wl *wl = hw_to_b43_wl(hw); 3901 struct b43_wldev *dev; 3902 3903 mutex_lock(&wl->mutex); 3904 dev = wl->current_dev; 3905 if (!dev) { 3906 *fflags = 0; 3907 goto out_unlock; 3908 } 3909 3910 *fflags &= FIF_PROMISC_IN_BSS | 3911 FIF_ALLMULTI | 3912 FIF_FCSFAIL | 3913 FIF_PLCPFAIL | 3914 FIF_CONTROL | 3915 FIF_OTHER_BSS | 3916 FIF_BCN_PRBRESP_PROMISC; 3917 3918 changed &= FIF_PROMISC_IN_BSS | 3919 FIF_ALLMULTI | 3920 FIF_FCSFAIL | 3921 FIF_PLCPFAIL | 3922 FIF_CONTROL | 3923 FIF_OTHER_BSS | 3924 FIF_BCN_PRBRESP_PROMISC; 3925 3926 wl->filter_flags = *fflags; 3927 3928 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 3929 b43_adjust_opmode(dev); 3930 3931out_unlock: 3932 mutex_unlock(&wl->mutex); 3933} 3934 3935/* Locking: wl->mutex 3936 * Returns the current dev. This might be different from the passed in dev, 3937 * because the core might be gone away while we unlocked the mutex. */ 3938static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev) 3939{ 3940 struct b43_wl *wl = dev->wl; 3941 struct b43_wldev *orig_dev; 3942 u32 mask; 3943 3944redo: 3945 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3946 return dev; 3947 3948 /* Cancel work. Unlock to avoid deadlocks. */ 3949 mutex_unlock(&wl->mutex); 3950 cancel_delayed_work_sync(&dev->periodic_work); 3951 cancel_work_sync(&wl->tx_work); 3952 mutex_lock(&wl->mutex); 3953 dev = wl->current_dev; 3954 if (!dev || b43_status(dev) < B43_STAT_STARTED) { 3955 /* Whoops, aliens ate up the device while we were unlocked. */ 3956 return dev; 3957 } 3958 3959 /* Disable interrupts on the device. */ 3960 b43_set_status(dev, B43_STAT_INITIALIZED); 3961 if (b43_bus_host_is_sdio(dev->dev)) { 3962 /* wl->mutex is locked. That is enough. */ 3963 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 3964 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 3965 } else { 3966 spin_lock_irq(&wl->hardirq_lock); 3967 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 3968 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 3969 spin_unlock_irq(&wl->hardirq_lock); 3970 } 3971 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ 3972 orig_dev = dev; 3973 mutex_unlock(&wl->mutex); 3974 if (b43_bus_host_is_sdio(dev->dev)) { 3975 b43_sdio_free_irq(dev); 3976 } else { 3977 synchronize_irq(dev->dev->irq); 3978 free_irq(dev->dev->irq, dev); 3979 } 3980 mutex_lock(&wl->mutex); 3981 dev = wl->current_dev; 3982 if (!dev) 3983 return dev; 3984 if (dev != orig_dev) { 3985 if (b43_status(dev) >= B43_STAT_STARTED) 3986 goto redo; 3987 return dev; 3988 } 3989 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 3990 B43_WARN_ON(mask != 0xFFFFFFFF && mask); 3991 3992 /* Drain the TX queue */ 3993 while (skb_queue_len(&wl->tx_queue)) 3994 dev_kfree_skb(skb_dequeue(&wl->tx_queue)); 3995 3996 b43_mac_suspend(dev); 3997 b43_leds_exit(dev); 3998 b43dbg(wl, "Wireless interface stopped\n"); 3999 4000 return dev; 4001} 4002 4003/* Locking: wl->mutex */ 4004static int b43_wireless_core_start(struct b43_wldev *dev) 4005{ 4006 int err; 4007 4008 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 4009 4010 drain_txstatus_queue(dev); 4011 if (b43_bus_host_is_sdio(dev->dev)) { 4012 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); 4013 if (err) { 4014 b43err(dev->wl, "Cannot request SDIO IRQ\n"); 4015 goto out; 4016 } 4017 } else { 4018 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler, 4019 b43_interrupt_thread_handler, 4020 IRQF_SHARED, KBUILD_MODNAME, dev); 4021 if (err) { 4022 b43err(dev->wl, "Cannot request IRQ-%d\n", 4023 dev->dev->irq); 4024 goto out; 4025 } 4026 } 4027 4028 /* We are ready to run. */ 4029 ieee80211_wake_queues(dev->wl->hw); 4030 b43_set_status(dev, B43_STAT_STARTED); 4031 4032 /* Start data flow (TX/RX). */ 4033 b43_mac_enable(dev); 4034 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 4035 4036 /* Start maintenance work */ 4037 b43_periodic_tasks_setup(dev); 4038 4039 b43_leds_init(dev); 4040 4041 b43dbg(dev->wl, "Wireless interface started\n"); 4042out: 4043 return err; 4044} 4045 4046/* Get PHY and RADIO versioning numbers */ 4047static int b43_phy_versioning(struct b43_wldev *dev) 4048{ 4049 struct b43_phy *phy = &dev->phy; 4050 u32 tmp; 4051 u8 analog_type; 4052 u8 phy_type; 4053 u8 phy_rev; 4054 u16 radio_manuf; 4055 u16 radio_ver; 4056 u16 radio_rev; 4057 int unsupported = 0; 4058 4059 /* Get PHY versioning */ 4060 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 4061 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 4062 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 4063 phy_rev = (tmp & B43_PHYVER_VERSION); 4064 switch (phy_type) { 4065 case B43_PHYTYPE_A: 4066 if (phy_rev >= 4) 4067 unsupported = 1; 4068 break; 4069 case B43_PHYTYPE_B: 4070 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 4071 && phy_rev != 7) 4072 unsupported = 1; 4073 break; 4074 case B43_PHYTYPE_G: 4075 if (phy_rev > 9) 4076 unsupported = 1; 4077 break; 4078#ifdef CONFIG_B43_PHY_N 4079 case B43_PHYTYPE_N: 4080 if (phy_rev > 9) 4081 unsupported = 1; 4082 break; 4083#endif 4084#ifdef CONFIG_B43_PHY_LP 4085 case B43_PHYTYPE_LP: 4086 if (phy_rev > 2) 4087 unsupported = 1; 4088 break; 4089#endif 4090 default: 4091 unsupported = 1; 4092 }; 4093 if (unsupported) { 4094 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 4095 "(Analog %u, Type %u, Revision %u)\n", 4096 analog_type, phy_type, phy_rev); 4097 return -EOPNOTSUPP; 4098 } 4099 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 4100 analog_type, phy_type, phy_rev); 4101 4102 /* Get RADIO versioning */ 4103 if (dev->dev->chip_id == 0x4317) { 4104 if (dev->dev->chip_rev == 0) 4105 tmp = 0x3205017F; 4106 else if (dev->dev->chip_rev == 1) 4107 tmp = 0x4205017F; 4108 else 4109 tmp = 0x5205017F; 4110 } else { 4111 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 4112 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 4113 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 4114 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; 4115 } 4116 radio_manuf = (tmp & 0x00000FFF); 4117 radio_ver = (tmp & 0x0FFFF000) >> 12; 4118 radio_rev = (tmp & 0xF0000000) >> 28; 4119 if (radio_manuf != 0x17F /* Broadcom */) 4120 unsupported = 1; 4121 switch (phy_type) { 4122 case B43_PHYTYPE_A: 4123 if (radio_ver != 0x2060) 4124 unsupported = 1; 4125 if (radio_rev != 1) 4126 unsupported = 1; 4127 if (radio_manuf != 0x17F) 4128 unsupported = 1; 4129 break; 4130 case B43_PHYTYPE_B: 4131 if ((radio_ver & 0xFFF0) != 0x2050) 4132 unsupported = 1; 4133 break; 4134 case B43_PHYTYPE_G: 4135 if (radio_ver != 0x2050) 4136 unsupported = 1; 4137 break; 4138 case B43_PHYTYPE_N: 4139 if (radio_ver != 0x2055 && radio_ver != 0x2056) 4140 unsupported = 1; 4141 break; 4142 case B43_PHYTYPE_LP: 4143 if (radio_ver != 0x2062 && radio_ver != 0x2063) 4144 unsupported = 1; 4145 break; 4146 default: 4147 B43_WARN_ON(1); 4148 } 4149 if (unsupported) { 4150 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 4151 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 4152 radio_manuf, radio_ver, radio_rev); 4153 return -EOPNOTSUPP; 4154 } 4155 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 4156 radio_manuf, radio_ver, radio_rev); 4157 4158 phy->radio_manuf = radio_manuf; 4159 phy->radio_ver = radio_ver; 4160 phy->radio_rev = radio_rev; 4161 4162 phy->analog = analog_type; 4163 phy->type = phy_type; 4164 phy->rev = phy_rev; 4165 4166 return 0; 4167} 4168 4169static void setup_struct_phy_for_init(struct b43_wldev *dev, 4170 struct b43_phy *phy) 4171{ 4172 phy->hardware_power_control = !!modparam_hwpctl; 4173 phy->next_txpwr_check_time = jiffies; 4174 /* PHY TX errors counter. */ 4175 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 4176 4177#if B43_DEBUG 4178 phy->phy_locked = 0; 4179 phy->radio_locked = 0; 4180#endif 4181} 4182 4183static void setup_struct_wldev_for_init(struct b43_wldev *dev) 4184{ 4185 dev->dfq_valid = 0; 4186 4187 /* Assume the radio is enabled. If it's not enabled, the state will 4188 * immediately get fixed on the first periodic work run. */ 4189 dev->radio_hw_enable = 1; 4190 4191 /* Stats */ 4192 memset(&dev->stats, 0, sizeof(dev->stats)); 4193 4194 setup_struct_phy_for_init(dev, &dev->phy); 4195 4196 /* IRQ related flags */ 4197 dev->irq_reason = 0; 4198 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 4199 dev->irq_mask = B43_IRQ_MASKTEMPLATE; 4200 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 4201 dev->irq_mask &= ~B43_IRQ_PHY_TXERR; 4202 4203 dev->mac_suspended = 1; 4204 4205 /* Noise calculation context */ 4206 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 4207} 4208 4209static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 4210{ 4211 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4212 u64 hf; 4213 4214 if (!modparam_btcoex) 4215 return; 4216 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 4217 return; 4218 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 4219 return; 4220 4221 hf = b43_hf_read(dev); 4222 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 4223 hf |= B43_HF_BTCOEXALT; 4224 else 4225 hf |= B43_HF_BTCOEX; 4226 b43_hf_write(dev, hf); 4227} 4228 4229static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 4230{ 4231 if (!modparam_btcoex) 4232 return; 4233 //TODO 4234} 4235 4236static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 4237{ 4238 struct ssb_bus *bus; 4239 u32 tmp; 4240 4241 if (dev->dev->bus_type != B43_BUS_SSB) 4242 return; 4243 4244 bus = dev->dev->sdev->bus; 4245 4246 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || 4247 (bus->chip_id == 0x4312)) { 4248 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO); 4249 tmp &= ~SSB_IMCFGLO_REQTO; 4250 tmp &= ~SSB_IMCFGLO_SERTO; 4251 tmp |= 0x3; 4252 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp); 4253 ssb_commit_settings(bus); 4254 } 4255} 4256 4257static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) 4258{ 4259 u16 pu_delay; 4260 4261 /* The time value is in microseconds. */ 4262 if (dev->phy.type == B43_PHYTYPE_A) 4263 pu_delay = 3700; 4264 else 4265 pu_delay = 1050; 4266 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) 4267 pu_delay = 500; 4268 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) 4269 pu_delay = max(pu_delay, (u16)2400); 4270 4271 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); 4272} 4273 4274/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ 4275static void b43_set_pretbtt(struct b43_wldev *dev) 4276{ 4277 u16 pretbtt; 4278 4279 /* The time value is in microseconds. */ 4280 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) { 4281 pretbtt = 2; 4282 } else { 4283 if (dev->phy.type == B43_PHYTYPE_A) 4284 pretbtt = 120; 4285 else 4286 pretbtt = 250; 4287 } 4288 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); 4289 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); 4290} 4291 4292/* Shutdown a wireless core */ 4293/* Locking: wl->mutex */ 4294static void b43_wireless_core_exit(struct b43_wldev *dev) 4295{ 4296 u32 macctl; 4297 4298 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED); 4299 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED) 4300 return; 4301 4302 /* Unregister HW RNG driver */ 4303 b43_rng_exit(dev->wl); 4304 4305 b43_set_status(dev, B43_STAT_UNINIT); 4306 4307 /* Stop the microcode PSM. */ 4308 macctl = b43_read32(dev, B43_MMIO_MACCTL); 4309 macctl &= ~B43_MACCTL_PSM_RUN; 4310 macctl |= B43_MACCTL_PSM_JMP0; 4311 b43_write32(dev, B43_MMIO_MACCTL, macctl); 4312 4313 b43_dma_free(dev); 4314 b43_pio_free(dev); 4315 b43_chip_exit(dev); 4316 dev->phy.ops->switch_analog(dev, 0); 4317 if (dev->wl->current_beacon) { 4318 dev_kfree_skb_any(dev->wl->current_beacon); 4319 dev->wl->current_beacon = NULL; 4320 } 4321 4322 b43_device_disable(dev, 0); 4323 b43_bus_may_powerdown(dev); 4324} 4325 4326/* Initialize a wireless core */ 4327static int b43_wireless_core_init(struct b43_wldev *dev) 4328{ 4329 struct ssb_bus *bus = dev->sdev->bus; 4330 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4331 struct b43_phy *phy = &dev->phy; 4332 int err; 4333 u64 hf; 4334 4335 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4336 4337 err = b43_bus_powerup(dev, 0); 4338 if (err) 4339 goto out; 4340 if (!b43_device_is_enabled(dev)) 4341 b43_wireless_core_reset(dev, phy->gmode); 4342 4343 /* Reset all data structures. */ 4344 setup_struct_wldev_for_init(dev); 4345 phy->ops->prepare_structs(dev); 4346 4347 /* Enable IRQ routing to this device. */ 4348 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->sdev); 4349 4350 b43_imcfglo_timeouts_workaround(dev); 4351 b43_bluetooth_coext_disable(dev); 4352 if (phy->ops->prepare_hardware) { 4353 err = phy->ops->prepare_hardware(dev); 4354 if (err) 4355 goto err_busdown; 4356 } 4357 err = b43_chip_init(dev); 4358 if (err) 4359 goto err_busdown; 4360 b43_shm_write16(dev, B43_SHM_SHARED, 4361 B43_SHM_SH_WLCOREREV, dev->dev->core_rev); 4362 hf = b43_hf_read(dev); 4363 if (phy->type == B43_PHYTYPE_G) { 4364 hf |= B43_HF_SYMW; 4365 if (phy->rev == 1) 4366 hf |= B43_HF_GDCW; 4367 if (sprom->boardflags_lo & B43_BFL_PACTRL) 4368 hf |= B43_HF_OFDMPABOOST; 4369 } 4370 if (phy->radio_ver == 0x2050) { 4371 if (phy->radio_rev == 6) 4372 hf |= B43_HF_4318TSSI; 4373 if (phy->radio_rev < 6) 4374 hf |= B43_HF_VCORECALC; 4375 } 4376 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) 4377 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ 4378#ifdef CONFIG_SSB_DRIVER_PCICORE 4379 if ((bus->bustype == SSB_BUSTYPE_PCI) && 4380 (bus->pcicore.dev->id.revision <= 10)) 4381 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ 4382#endif 4383 hf &= ~B43_HF_SKCFPUP; 4384 b43_hf_write(dev, hf); 4385 4386 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 4387 B43_DEFAULT_LONG_RETRY_LIMIT); 4388 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 4389 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 4390 4391 /* Disable sending probe responses from firmware. 4392 * Setting the MaxTime to one usec will always trigger 4393 * a timeout, so we never send any probe resp. 4394 * A timeout of zero is infinite. */ 4395 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 4396 4397 b43_rate_memory_init(dev); 4398 b43_set_phytxctl_defaults(dev); 4399 4400 /* Minimum Contention Window */ 4401 if (phy->type == B43_PHYTYPE_B) 4402 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 4403 else 4404 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 4405 /* Maximum Contention Window */ 4406 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 4407 4408 if (b43_bus_host_is_pcmcia(dev->dev) || 4409 b43_bus_host_is_sdio(dev->dev) || 4410 dev->use_pio) { 4411 dev->__using_pio_transfers = 1; 4412 err = b43_pio_init(dev); 4413 } else { 4414 dev->__using_pio_transfers = 0; 4415 err = b43_dma_init(dev); 4416 } 4417 if (err) 4418 goto err_chip_exit; 4419 b43_qos_init(dev); 4420 b43_set_synth_pu_delay(dev, 1); 4421 b43_bluetooth_coext_enable(dev); 4422 4423 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); 4424 b43_upload_card_macaddress(dev); 4425 b43_security_init(dev); 4426 4427 ieee80211_wake_queues(dev->wl->hw); 4428 4429 b43_set_status(dev, B43_STAT_INITIALIZED); 4430 4431 /* Register HW RNG driver */ 4432 b43_rng_init(dev->wl); 4433 4434out: 4435 return err; 4436 4437err_chip_exit: 4438 b43_chip_exit(dev); 4439err_busdown: 4440 b43_bus_may_powerdown(dev); 4441 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4442 return err; 4443} 4444 4445static int b43_op_add_interface(struct ieee80211_hw *hw, 4446 struct ieee80211_vif *vif) 4447{ 4448 struct b43_wl *wl = hw_to_b43_wl(hw); 4449 struct b43_wldev *dev; 4450 int err = -EOPNOTSUPP; 4451 4452 /* TODO: allow WDS/AP devices to coexist */ 4453 4454 if (vif->type != NL80211_IFTYPE_AP && 4455 vif->type != NL80211_IFTYPE_MESH_POINT && 4456 vif->type != NL80211_IFTYPE_STATION && 4457 vif->type != NL80211_IFTYPE_WDS && 4458 vif->type != NL80211_IFTYPE_ADHOC) 4459 return -EOPNOTSUPP; 4460 4461 mutex_lock(&wl->mutex); 4462 if (wl->operating) 4463 goto out_mutex_unlock; 4464 4465 b43dbg(wl, "Adding Interface type %d\n", vif->type); 4466 4467 dev = wl->current_dev; 4468 wl->operating = 1; 4469 wl->vif = vif; 4470 wl->if_type = vif->type; 4471 memcpy(wl->mac_addr, vif->addr, ETH_ALEN); 4472 4473 b43_adjust_opmode(dev); 4474 b43_set_pretbtt(dev); 4475 b43_set_synth_pu_delay(dev, 0); 4476 b43_upload_card_macaddress(dev); 4477 4478 err = 0; 4479 out_mutex_unlock: 4480 mutex_unlock(&wl->mutex); 4481 4482 return err; 4483} 4484 4485static void b43_op_remove_interface(struct ieee80211_hw *hw, 4486 struct ieee80211_vif *vif) 4487{ 4488 struct b43_wl *wl = hw_to_b43_wl(hw); 4489 struct b43_wldev *dev = wl->current_dev; 4490 4491 b43dbg(wl, "Removing Interface type %d\n", vif->type); 4492 4493 mutex_lock(&wl->mutex); 4494 4495 B43_WARN_ON(!wl->operating); 4496 B43_WARN_ON(wl->vif != vif); 4497 wl->vif = NULL; 4498 4499 wl->operating = 0; 4500 4501 b43_adjust_opmode(dev); 4502 memset(wl->mac_addr, 0, ETH_ALEN); 4503 b43_upload_card_macaddress(dev); 4504 4505 mutex_unlock(&wl->mutex); 4506} 4507 4508static int b43_op_start(struct ieee80211_hw *hw) 4509{ 4510 struct b43_wl *wl = hw_to_b43_wl(hw); 4511 struct b43_wldev *dev = wl->current_dev; 4512 int did_init = 0; 4513 int err = 0; 4514 4515 /* Kill all old instance specific information to make sure 4516 * the card won't use it in the short timeframe between start 4517 * and mac80211 reconfiguring it. */ 4518 memset(wl->bssid, 0, ETH_ALEN); 4519 memset(wl->mac_addr, 0, ETH_ALEN); 4520 wl->filter_flags = 0; 4521 wl->radiotap_enabled = 0; 4522 b43_qos_clear(wl); 4523 wl->beacon0_uploaded = 0; 4524 wl->beacon1_uploaded = 0; 4525 wl->beacon_templates_virgin = 1; 4526 wl->radio_enabled = 1; 4527 4528 mutex_lock(&wl->mutex); 4529 4530 if (b43_status(dev) < B43_STAT_INITIALIZED) { 4531 err = b43_wireless_core_init(dev); 4532 if (err) 4533 goto out_mutex_unlock; 4534 did_init = 1; 4535 } 4536 4537 if (b43_status(dev) < B43_STAT_STARTED) { 4538 err = b43_wireless_core_start(dev); 4539 if (err) { 4540 if (did_init) 4541 b43_wireless_core_exit(dev); 4542 goto out_mutex_unlock; 4543 } 4544 } 4545 4546 /* XXX: only do if device doesn't support rfkill irq */ 4547 wiphy_rfkill_start_polling(hw->wiphy); 4548 4549 out_mutex_unlock: 4550 mutex_unlock(&wl->mutex); 4551 4552 return err; 4553} 4554 4555static void b43_op_stop(struct ieee80211_hw *hw) 4556{ 4557 struct b43_wl *wl = hw_to_b43_wl(hw); 4558 struct b43_wldev *dev = wl->current_dev; 4559 4560 cancel_work_sync(&(wl->beacon_update_trigger)); 4561 4562 mutex_lock(&wl->mutex); 4563 if (b43_status(dev) >= B43_STAT_STARTED) { 4564 dev = b43_wireless_core_stop(dev); 4565 if (!dev) 4566 goto out_unlock; 4567 } 4568 b43_wireless_core_exit(dev); 4569 wl->radio_enabled = 0; 4570 4571out_unlock: 4572 mutex_unlock(&wl->mutex); 4573 4574 cancel_work_sync(&(wl->txpower_adjust_work)); 4575} 4576 4577static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, 4578 struct ieee80211_sta *sta, bool set) 4579{ 4580 struct b43_wl *wl = hw_to_b43_wl(hw); 4581 4582 /* FIXME: add locking */ 4583 b43_update_templates(wl); 4584 4585 return 0; 4586} 4587 4588static void b43_op_sta_notify(struct ieee80211_hw *hw, 4589 struct ieee80211_vif *vif, 4590 enum sta_notify_cmd notify_cmd, 4591 struct ieee80211_sta *sta) 4592{ 4593 struct b43_wl *wl = hw_to_b43_wl(hw); 4594 4595 B43_WARN_ON(!vif || wl->vif != vif); 4596} 4597 4598static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw) 4599{ 4600 struct b43_wl *wl = hw_to_b43_wl(hw); 4601 struct b43_wldev *dev; 4602 4603 mutex_lock(&wl->mutex); 4604 dev = wl->current_dev; 4605 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4606 /* Disable CFP update during scan on other channels. */ 4607 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP); 4608 } 4609 mutex_unlock(&wl->mutex); 4610} 4611 4612static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw) 4613{ 4614 struct b43_wl *wl = hw_to_b43_wl(hw); 4615 struct b43_wldev *dev; 4616 4617 mutex_lock(&wl->mutex); 4618 dev = wl->current_dev; 4619 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4620 /* Re-enable CFP update. */ 4621 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP); 4622 } 4623 mutex_unlock(&wl->mutex); 4624} 4625 4626static int b43_op_get_survey(struct ieee80211_hw *hw, int idx, 4627 struct survey_info *survey) 4628{ 4629 struct b43_wl *wl = hw_to_b43_wl(hw); 4630 struct b43_wldev *dev = wl->current_dev; 4631 struct ieee80211_conf *conf = &hw->conf; 4632 4633 if (idx != 0) 4634 return -ENOENT; 4635 4636 survey->channel = conf->channel; 4637 survey->filled = SURVEY_INFO_NOISE_DBM; 4638 survey->noise = dev->stats.link_noise; 4639 4640 return 0; 4641} 4642 4643static const struct ieee80211_ops b43_hw_ops = { 4644 .tx = b43_op_tx, 4645 .conf_tx = b43_op_conf_tx, 4646 .add_interface = b43_op_add_interface, 4647 .remove_interface = b43_op_remove_interface, 4648 .config = b43_op_config, 4649 .bss_info_changed = b43_op_bss_info_changed, 4650 .configure_filter = b43_op_configure_filter, 4651 .set_key = b43_op_set_key, 4652 .update_tkip_key = b43_op_update_tkip_key, 4653 .get_stats = b43_op_get_stats, 4654 .get_tsf = b43_op_get_tsf, 4655 .set_tsf = b43_op_set_tsf, 4656 .start = b43_op_start, 4657 .stop = b43_op_stop, 4658 .set_tim = b43_op_beacon_set_tim, 4659 .sta_notify = b43_op_sta_notify, 4660 .sw_scan_start = b43_op_sw_scan_start_notifier, 4661 .sw_scan_complete = b43_op_sw_scan_complete_notifier, 4662 .get_survey = b43_op_get_survey, 4663 .rfkill_poll = b43_rfkill_poll, 4664}; 4665 4666/* Hard-reset the chip. Do not call this directly. 4667 * Use b43_controller_restart() 4668 */ 4669static void b43_chip_reset(struct work_struct *work) 4670{ 4671 struct b43_wldev *dev = 4672 container_of(work, struct b43_wldev, restart_work); 4673 struct b43_wl *wl = dev->wl; 4674 int err = 0; 4675 int prev_status; 4676 4677 mutex_lock(&wl->mutex); 4678 4679 prev_status = b43_status(dev); 4680 /* Bring the device down... */ 4681 if (prev_status >= B43_STAT_STARTED) { 4682 dev = b43_wireless_core_stop(dev); 4683 if (!dev) { 4684 err = -ENODEV; 4685 goto out; 4686 } 4687 } 4688 if (prev_status >= B43_STAT_INITIALIZED) 4689 b43_wireless_core_exit(dev); 4690 4691 /* ...and up again. */ 4692 if (prev_status >= B43_STAT_INITIALIZED) { 4693 err = b43_wireless_core_init(dev); 4694 if (err) 4695 goto out; 4696 } 4697 if (prev_status >= B43_STAT_STARTED) { 4698 err = b43_wireless_core_start(dev); 4699 if (err) { 4700 b43_wireless_core_exit(dev); 4701 goto out; 4702 } 4703 } 4704out: 4705 if (err) 4706 wl->current_dev = NULL; /* Failed to init the dev. */ 4707 mutex_unlock(&wl->mutex); 4708 if (err) 4709 b43err(wl, "Controller restart FAILED\n"); 4710 else 4711 b43info(wl, "Controller restarted\n"); 4712} 4713 4714static int b43_setup_bands(struct b43_wldev *dev, 4715 bool have_2ghz_phy, bool have_5ghz_phy) 4716{ 4717 struct ieee80211_hw *hw = dev->wl->hw; 4718 4719 if (have_2ghz_phy) 4720 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz; 4721 if (dev->phy.type == B43_PHYTYPE_N) { 4722 if (have_5ghz_phy) 4723 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy; 4724 } else { 4725 if (have_5ghz_phy) 4726 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy; 4727 } 4728 4729 dev->phy.supports_2ghz = have_2ghz_phy; 4730 dev->phy.supports_5ghz = have_5ghz_phy; 4731 4732 return 0; 4733} 4734 4735static void b43_wireless_core_detach(struct b43_wldev *dev) 4736{ 4737 /* We release firmware that late to not be required to re-request 4738 * is all the time when we reinit the core. */ 4739 b43_release_firmware(dev); 4740 b43_phy_free(dev); 4741} 4742 4743static int b43_wireless_core_attach(struct b43_wldev *dev) 4744{ 4745 struct b43_wl *wl = dev->wl; 4746 struct ssb_bus *bus = dev->sdev->bus; 4747 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL; 4748 int err; 4749 bool have_2ghz_phy = 0, have_5ghz_phy = 0; 4750 4751 /* Do NOT do any device initialization here. 4752 * Do it in wireless_core_init() instead. 4753 * This function is for gathering basic information about the HW, only. 4754 * Also some structs may be set up here. But most likely you want to have 4755 * that in core_init(), too. 4756 */ 4757 4758 err = b43_bus_powerup(dev, 0); 4759 if (err) { 4760 b43err(wl, "Bus powerup failed\n"); 4761 goto out; 4762 } 4763 /* Get the PHY type. */ 4764 if (dev->dev->core_rev >= 5) { 4765 u32 tmshigh; 4766 4767 tmshigh = ssb_read32(dev->sdev, SSB_TMSHIGH); 4768 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY); 4769 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY); 4770 } else 4771 B43_WARN_ON(1); 4772 4773 dev->phy.gmode = have_2ghz_phy; 4774 dev->phy.radio_on = 1; 4775 b43_wireless_core_reset(dev, dev->phy.gmode); 4776 4777 err = b43_phy_versioning(dev); 4778 if (err) 4779 goto err_powerdown; 4780 /* Check if this device supports multiband. */ 4781 if (!pdev || 4782 (pdev->device != 0x4312 && 4783 pdev->device != 0x4319 && pdev->device != 0x4324)) { 4784 /* No multiband support. */ 4785 have_2ghz_phy = 0; 4786 have_5ghz_phy = 0; 4787 switch (dev->phy.type) { 4788 case B43_PHYTYPE_A: 4789 have_5ghz_phy = 1; 4790 break; 4791 case B43_PHYTYPE_LP: //FIXME not always! 4792#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference 4793 have_5ghz_phy = 1; 4794#endif 4795 case B43_PHYTYPE_G: 4796 case B43_PHYTYPE_N: 4797 have_2ghz_phy = 1; 4798 break; 4799 default: 4800 B43_WARN_ON(1); 4801 } 4802 } 4803 if (dev->phy.type == B43_PHYTYPE_A) { 4804 /* FIXME */ 4805 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 4806 err = -EOPNOTSUPP; 4807 goto err_powerdown; 4808 } 4809 if (1 /* disable A-PHY */) { 4810 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */ 4811 if (dev->phy.type != B43_PHYTYPE_N && 4812 dev->phy.type != B43_PHYTYPE_LP) { 4813 have_2ghz_phy = 1; 4814 have_5ghz_phy = 0; 4815 } 4816 } 4817 4818 err = b43_phy_allocate(dev); 4819 if (err) 4820 goto err_powerdown; 4821 4822 dev->phy.gmode = have_2ghz_phy; 4823 b43_wireless_core_reset(dev, dev->phy.gmode); 4824 4825 err = b43_validate_chipaccess(dev); 4826 if (err) 4827 goto err_phy_free; 4828 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); 4829 if (err) 4830 goto err_phy_free; 4831 4832 /* Now set some default "current_dev" */ 4833 if (!wl->current_dev) 4834 wl->current_dev = dev; 4835 INIT_WORK(&dev->restart_work, b43_chip_reset); 4836 4837 dev->phy.ops->switch_analog(dev, 0); 4838 b43_device_disable(dev, 0); 4839 b43_bus_may_powerdown(dev); 4840 4841out: 4842 return err; 4843 4844err_phy_free: 4845 b43_phy_free(dev); 4846err_powerdown: 4847 b43_bus_may_powerdown(dev); 4848 return err; 4849} 4850 4851static void b43_one_core_detach(struct b43_bus_dev *dev) 4852{ 4853 struct b43_wldev *wldev; 4854 struct b43_wl *wl; 4855 4856 /* Do not cancel ieee80211-workqueue based work here. 4857 * See comment in b43_remove(). */ 4858 4859 wldev = ssb_get_drvdata(dev->sdev); 4860 wl = wldev->wl; 4861 b43_debugfs_remove_device(wldev); 4862 b43_wireless_core_detach(wldev); 4863 list_del(&wldev->list); 4864 wl->nr_devs--; 4865 ssb_set_drvdata(dev->sdev, NULL); 4866 kfree(wldev); 4867} 4868 4869static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl) 4870{ 4871 struct b43_wldev *wldev; 4872 int err = -ENOMEM; 4873 4874 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 4875 if (!wldev) 4876 goto out; 4877 4878 wldev->use_pio = b43_modparam_pio; 4879 wldev->dev = dev; 4880 wldev->sdev = dev->sdev; /* TODO: Remove when not needed */ 4881 wldev->wl = wl; 4882 b43_set_status(wldev, B43_STAT_UNINIT); 4883 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 4884 INIT_LIST_HEAD(&wldev->list); 4885 4886 err = b43_wireless_core_attach(wldev); 4887 if (err) 4888 goto err_kfree_wldev; 4889 4890 list_add(&wldev->list, &wl->devlist); 4891 wl->nr_devs++; 4892 ssb_set_drvdata(dev->sdev, wldev); 4893 b43_debugfs_add_device(wldev); 4894 4895 out: 4896 return err; 4897 4898 err_kfree_wldev: 4899 kfree(wldev); 4900 return err; 4901} 4902 4903#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ 4904 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ 4905 (pdev->device == _device) && \ 4906 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ 4907 (pdev->subsystem_device == _subdevice) ) 4908 4909static void b43_sprom_fixup(struct ssb_bus *bus) 4910{ 4911 struct pci_dev *pdev; 4912 4913 /* boardflags workarounds */ 4914 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 4915 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 4916 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 4917 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 4918 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 4919 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 4920 if (bus->bustype == SSB_BUSTYPE_PCI) { 4921 pdev = bus->host_pci; 4922 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || 4923 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || 4924 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || 4925 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || 4926 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || 4927 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || 4928 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) 4929 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; 4930 } 4931} 4932 4933static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl) 4934{ 4935 struct ieee80211_hw *hw = wl->hw; 4936 4937 ssb_set_devtypedata(dev->sdev, NULL); 4938 ieee80211_free_hw(hw); 4939} 4940 4941static struct b43_wl *b43_wireless_init(struct ssb_device *dev) 4942{ 4943 struct ssb_sprom *sprom = &dev->bus->sprom; 4944 struct ieee80211_hw *hw; 4945 struct b43_wl *wl; 4946 4947 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 4948 if (!hw) { 4949 b43err(NULL, "Could not allocate ieee80211 device\n"); 4950 return ERR_PTR(-ENOMEM); 4951 } 4952 wl = hw_to_b43_wl(hw); 4953 4954 /* fill hw info */ 4955 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 4956 IEEE80211_HW_SIGNAL_DBM; 4957 4958 hw->wiphy->interface_modes = 4959 BIT(NL80211_IFTYPE_AP) | 4960 BIT(NL80211_IFTYPE_MESH_POINT) | 4961 BIT(NL80211_IFTYPE_STATION) | 4962 BIT(NL80211_IFTYPE_WDS) | 4963 BIT(NL80211_IFTYPE_ADHOC); 4964 4965 hw->queues = modparam_qos ? 4 : 1; 4966 wl->mac80211_initially_registered_queues = hw->queues; 4967 hw->max_rates = 2; 4968 SET_IEEE80211_DEV(hw, dev->dev); 4969 if (is_valid_ether_addr(sprom->et1mac)) 4970 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 4971 else 4972 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 4973 4974 /* Initialize struct b43_wl */ 4975 wl->hw = hw; 4976 mutex_init(&wl->mutex); 4977 spin_lock_init(&wl->hardirq_lock); 4978 INIT_LIST_HEAD(&wl->devlist); 4979 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); 4980 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work); 4981 INIT_WORK(&wl->tx_work, b43_tx_work); 4982 skb_queue_head_init(&wl->tx_queue); 4983 4984 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n", 4985 dev->bus->chip_id, dev->id.revision); 4986 return wl; 4987} 4988 4989static 4990int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id) 4991{ 4992 struct b43_bus_dev *dev; 4993 struct b43_wl *wl; 4994 int err; 4995 int first = 0; 4996 4997 dev = b43_bus_dev_ssb_init(sdev); 4998 4999 wl = ssb_get_devtypedata(sdev); 5000 if (!wl) { 5001 /* Probing the first core. Must setup common struct b43_wl */ 5002 first = 1; 5003 b43_sprom_fixup(sdev->bus); 5004 wl = b43_wireless_init(sdev); 5005 if (IS_ERR(wl)) { 5006 err = PTR_ERR(wl); 5007 goto out; 5008 } 5009 ssb_set_devtypedata(sdev, wl); 5010 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl); 5011 } 5012 err = b43_one_core_attach(dev, wl); 5013 if (err) 5014 goto err_wireless_exit; 5015 5016 if (first) { 5017 err = ieee80211_register_hw(wl->hw); 5018 if (err) 5019 goto err_one_core_detach; 5020 b43_leds_register(wl->current_dev); 5021 } 5022 5023 out: 5024 return err; 5025 5026 err_one_core_detach: 5027 b43_one_core_detach(dev); 5028 err_wireless_exit: 5029 if (first) 5030 b43_wireless_exit(dev, wl); 5031 return err; 5032} 5033 5034static void b43_ssb_remove(struct ssb_device *sdev) 5035{ 5036 struct b43_wl *wl = ssb_get_devtypedata(sdev); 5037 struct b43_wldev *wldev = ssb_get_drvdata(sdev); 5038 5039 /* We must cancel any work here before unregistering from ieee80211, 5040 * as the ieee80211 unreg will destroy the workqueue. */ 5041 cancel_work_sync(&wldev->restart_work); 5042 5043 B43_WARN_ON(!wl); 5044 if (wl->current_dev == wldev) { 5045 /* Restore the queues count before unregistering, because firmware detect 5046 * might have modified it. Restoring is important, so the networking 5047 * stack can properly free resources. */ 5048 wl->hw->queues = wl->mac80211_initially_registered_queues; 5049 b43_leds_stop(wldev); 5050 ieee80211_unregister_hw(wl->hw); 5051 } 5052 5053 b43_one_core_detach(wldev->dev); 5054 5055 if (list_empty(&wl->devlist)) { 5056 b43_leds_unregister(wl); 5057 /* Last core on the chip unregistered. 5058 * We can destroy common struct b43_wl. 5059 */ 5060 b43_wireless_exit(wldev->dev, wl); 5061 } 5062} 5063 5064/* Perform a hardware reset. This can be called from any context. */ 5065void b43_controller_restart(struct b43_wldev *dev, const char *reason) 5066{ 5067 /* Must avoid requeueing, if we are in shutdown. */ 5068 if (b43_status(dev) < B43_STAT_INITIALIZED) 5069 return; 5070 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 5071 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 5072} 5073 5074static struct ssb_driver b43_ssb_driver = { 5075 .name = KBUILD_MODNAME, 5076 .id_table = b43_ssb_tbl, 5077 .probe = b43_ssb_probe, 5078 .remove = b43_ssb_remove, 5079}; 5080 5081static void b43_print_driverinfo(void) 5082{ 5083 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", 5084 *feat_leds = "", *feat_sdio = ""; 5085 5086#ifdef CONFIG_B43_PCI_AUTOSELECT 5087 feat_pci = "P"; 5088#endif 5089#ifdef CONFIG_B43_PCMCIA 5090 feat_pcmcia = "M"; 5091#endif 5092#ifdef CONFIG_B43_PHY_N 5093 feat_nphy = "N"; 5094#endif 5095#ifdef CONFIG_B43_LEDS 5096 feat_leds = "L"; 5097#endif 5098#ifdef CONFIG_B43_SDIO 5099 feat_sdio = "S"; 5100#endif 5101 printk(KERN_INFO "Broadcom 43xx driver loaded " 5102 "[ Features: %s%s%s%s%s, Firmware-ID: " 5103 B43_SUPPORTED_FIRMWARE_ID " ]\n", 5104 feat_pci, feat_pcmcia, feat_nphy, 5105 feat_leds, feat_sdio); 5106} 5107 5108static int __init b43_init(void) 5109{ 5110 int err; 5111 5112 b43_debugfs_init(); 5113 err = b43_pcmcia_init(); 5114 if (err) 5115 goto err_dfs_exit; 5116 err = b43_sdio_init(); 5117 if (err) 5118 goto err_pcmcia_exit; 5119 err = ssb_driver_register(&b43_ssb_driver); 5120 if (err) 5121 goto err_sdio_exit; 5122 b43_print_driverinfo(); 5123 5124 return err; 5125 5126err_sdio_exit: 5127 b43_sdio_exit(); 5128err_pcmcia_exit: 5129 b43_pcmcia_exit(); 5130err_dfs_exit: 5131 b43_debugfs_exit(); 5132 return err; 5133} 5134 5135static void __exit b43_exit(void) 5136{ 5137 ssb_driver_unregister(&b43_ssb_driver); 5138 b43_sdio_exit(); 5139 b43_pcmcia_exit(); 5140 b43_debugfs_exit(); 5141} 5142 5143module_init(b43_init) 5144module_exit(b43_exit) 5145