main.c revision 53a6e2342d73d509318836e320f70cd286acd69c
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 Some parts of the code in this file are derived from the ipw2200 12 driver Copyright(c) 2003 - 2004 Intel Corporation. 13 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; either version 2 of the License, or 17 (at your option) any later version. 18 19 This program is distributed in the hope that it will be useful, 20 but WITHOUT ANY WARRANTY; without even the implied warranty of 21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 GNU General Public License for more details. 23 24 You should have received a copy of the GNU General Public License 25 along with this program; see the file COPYING. If not, write to 26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 27 Boston, MA 02110-1301, USA. 28 29*/ 30 31#include <linux/delay.h> 32#include <linux/init.h> 33#include <linux/moduleparam.h> 34#include <linux/if_arp.h> 35#include <linux/etherdevice.h> 36#include <linux/version.h> 37#include <linux/firmware.h> 38#include <linux/wireless.h> 39#include <linux/workqueue.h> 40#include <linux/skbuff.h> 41#include <linux/dma-mapping.h> 42#include <asm/unaligned.h> 43 44#include "b43.h" 45#include "main.h" 46#include "debugfs.h" 47#include "phy.h" 48#include "dma.h" 49#include "sysfs.h" 50#include "xmit.h" 51#include "lo.h" 52#include "pcmcia.h" 53 54MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 55MODULE_AUTHOR("Martin Langer"); 56MODULE_AUTHOR("Stefano Brivio"); 57MODULE_AUTHOR("Michael Buesch"); 58MODULE_LICENSE("GPL"); 59 60 61static int modparam_bad_frames_preempt; 62module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 63MODULE_PARM_DESC(bad_frames_preempt, 64 "enable(1) / disable(0) Bad Frames Preemption"); 65 66static char modparam_fwpostfix[16]; 67module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 68MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 69 70static int modparam_hwpctl; 71module_param_named(hwpctl, modparam_hwpctl, int, 0444); 72MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 73 74static int modparam_nohwcrypt; 75module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 76MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 77 78static const struct ssb_device_id b43_ssb_tbl[] = { 79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 86 SSB_DEVTABLE_END 87}; 88 89MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 90 91/* Channel and ratetables are shared for all devices. 92 * They can't be const, because ieee80211 puts some precalculated 93 * data in there. This data is the same for all devices, so we don't 94 * get concurrency issues */ 95#define RATETAB_ENT(_rateid, _flags) \ 96 { \ 97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \ 98 .val = (_rateid), \ 99 .val2 = (_rateid), \ 100 .flags = (_flags), \ 101 } 102static struct ieee80211_rate __b43_ratetable[] = { 103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK), 104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2), 105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2), 106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2), 107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM), 108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM), 109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM), 110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM), 111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM), 112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM), 113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM), 114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM), 115}; 116 117#define b43_a_ratetable (__b43_ratetable + 4) 118#define b43_a_ratetable_size 8 119#define b43_b_ratetable (__b43_ratetable + 0) 120#define b43_b_ratetable_size 4 121#define b43_g_ratetable (__b43_ratetable + 0) 122#define b43_g_ratetable_size 12 123 124#define CHANTAB_ENT(_chanid, _freq) \ 125 { \ 126 .chan = (_chanid), \ 127 .freq = (_freq), \ 128 .val = (_chanid), \ 129 .flag = IEEE80211_CHAN_W_SCAN | \ 130 IEEE80211_CHAN_W_ACTIVE_SCAN | \ 131 IEEE80211_CHAN_W_IBSS, \ 132 .power_level = 0xFF, \ 133 .antenna_max = 0xFF, \ 134 } 135static struct ieee80211_channel b43_2ghz_chantable[] = { 136 CHANTAB_ENT(1, 2412), 137 CHANTAB_ENT(2, 2417), 138 CHANTAB_ENT(3, 2422), 139 CHANTAB_ENT(4, 2427), 140 CHANTAB_ENT(5, 2432), 141 CHANTAB_ENT(6, 2437), 142 CHANTAB_ENT(7, 2442), 143 CHANTAB_ENT(8, 2447), 144 CHANTAB_ENT(9, 2452), 145 CHANTAB_ENT(10, 2457), 146 CHANTAB_ENT(11, 2462), 147 CHANTAB_ENT(12, 2467), 148 CHANTAB_ENT(13, 2472), 149 CHANTAB_ENT(14, 2484), 150}; 151#define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable) 152 153#if 0 154static struct ieee80211_channel b43_5ghz_chantable[] = { 155 CHANTAB_ENT(36, 5180), 156 CHANTAB_ENT(40, 5200), 157 CHANTAB_ENT(44, 5220), 158 CHANTAB_ENT(48, 5240), 159 CHANTAB_ENT(52, 5260), 160 CHANTAB_ENT(56, 5280), 161 CHANTAB_ENT(60, 5300), 162 CHANTAB_ENT(64, 5320), 163 CHANTAB_ENT(149, 5745), 164 CHANTAB_ENT(153, 5765), 165 CHANTAB_ENT(157, 5785), 166 CHANTAB_ENT(161, 5805), 167 CHANTAB_ENT(165, 5825), 168}; 169#define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable) 170#endif 171 172static void b43_wireless_core_exit(struct b43_wldev *dev); 173static int b43_wireless_core_init(struct b43_wldev *dev); 174static void b43_wireless_core_stop(struct b43_wldev *dev); 175static int b43_wireless_core_start(struct b43_wldev *dev); 176 177static int b43_ratelimit(struct b43_wl *wl) 178{ 179 if (!wl || !wl->current_dev) 180 return 1; 181 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 182 return 1; 183 /* We are up and running. 184 * Ratelimit the messages to avoid DoS over the net. */ 185 return net_ratelimit(); 186} 187 188void b43info(struct b43_wl *wl, const char *fmt, ...) 189{ 190 va_list args; 191 192 if (!b43_ratelimit(wl)) 193 return; 194 va_start(args, fmt); 195 printk(KERN_INFO "b43-%s: ", 196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 197 vprintk(fmt, args); 198 va_end(args); 199} 200 201void b43err(struct b43_wl *wl, const char *fmt, ...) 202{ 203 va_list args; 204 205 if (!b43_ratelimit(wl)) 206 return; 207 va_start(args, fmt); 208 printk(KERN_ERR "b43-%s ERROR: ", 209 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 210 vprintk(fmt, args); 211 va_end(args); 212} 213 214void b43warn(struct b43_wl *wl, const char *fmt, ...) 215{ 216 va_list args; 217 218 if (!b43_ratelimit(wl)) 219 return; 220 va_start(args, fmt); 221 printk(KERN_WARNING "b43-%s warning: ", 222 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 223 vprintk(fmt, args); 224 va_end(args); 225} 226 227#if B43_DEBUG 228void b43dbg(struct b43_wl *wl, const char *fmt, ...) 229{ 230 va_list args; 231 232 va_start(args, fmt); 233 printk(KERN_DEBUG "b43-%s debug: ", 234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 235 vprintk(fmt, args); 236 va_end(args); 237} 238#endif /* DEBUG */ 239 240static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 241{ 242 u32 macctl; 243 244 B43_WARN_ON(offset % 4 != 0); 245 246 macctl = b43_read32(dev, B43_MMIO_MACCTL); 247 if (macctl & B43_MACCTL_BE) 248 val = swab32(val); 249 250 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 251 mmiowb(); 252 b43_write32(dev, B43_MMIO_RAM_DATA, val); 253} 254 255static inline void b43_shm_control_word(struct b43_wldev *dev, 256 u16 routing, u16 offset) 257{ 258 u32 control; 259 260 /* "offset" is the WORD offset. */ 261 control = routing; 262 control <<= 16; 263 control |= offset; 264 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 265} 266 267u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 268{ 269 struct b43_wl *wl = dev->wl; 270 unsigned long flags; 271 u32 ret; 272 273 spin_lock_irqsave(&wl->shm_lock, flags); 274 if (routing == B43_SHM_SHARED) { 275 B43_WARN_ON(offset & 0x0001); 276 if (offset & 0x0003) { 277 /* Unaligned access */ 278 b43_shm_control_word(dev, routing, offset >> 2); 279 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 280 ret <<= 16; 281 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 282 ret |= b43_read16(dev, B43_MMIO_SHM_DATA); 283 284 goto out; 285 } 286 offset >>= 2; 287 } 288 b43_shm_control_word(dev, routing, offset); 289 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 290out: 291 spin_unlock_irqrestore(&wl->shm_lock, flags); 292 293 return ret; 294} 295 296u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset) 297{ 298 struct b43_wl *wl = dev->wl; 299 unsigned long flags; 300 u16 ret; 301 302 spin_lock_irqsave(&wl->shm_lock, flags); 303 if (routing == B43_SHM_SHARED) { 304 B43_WARN_ON(offset & 0x0001); 305 if (offset & 0x0003) { 306 /* Unaligned access */ 307 b43_shm_control_word(dev, routing, offset >> 2); 308 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 309 310 goto out; 311 } 312 offset >>= 2; 313 } 314 b43_shm_control_word(dev, routing, offset); 315 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 316out: 317 spin_unlock_irqrestore(&wl->shm_lock, flags); 318 319 return ret; 320} 321 322void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 323{ 324 struct b43_wl *wl = dev->wl; 325 unsigned long flags; 326 327 spin_lock_irqsave(&wl->shm_lock, flags); 328 if (routing == B43_SHM_SHARED) { 329 B43_WARN_ON(offset & 0x0001); 330 if (offset & 0x0003) { 331 /* Unaligned access */ 332 b43_shm_control_word(dev, routing, offset >> 2); 333 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 334 (value >> 16) & 0xffff); 335 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 336 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff); 337 goto out; 338 } 339 offset >>= 2; 340 } 341 b43_shm_control_word(dev, routing, offset); 342 b43_write32(dev, B43_MMIO_SHM_DATA, value); 343out: 344 spin_unlock_irqrestore(&wl->shm_lock, flags); 345} 346 347void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 348{ 349 struct b43_wl *wl = dev->wl; 350 unsigned long flags; 351 352 spin_lock_irqsave(&wl->shm_lock, flags); 353 if (routing == B43_SHM_SHARED) { 354 B43_WARN_ON(offset & 0x0001); 355 if (offset & 0x0003) { 356 /* Unaligned access */ 357 b43_shm_control_word(dev, routing, offset >> 2); 358 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 359 goto out; 360 } 361 offset >>= 2; 362 } 363 b43_shm_control_word(dev, routing, offset); 364 b43_write16(dev, B43_MMIO_SHM_DATA, value); 365out: 366 spin_unlock_irqrestore(&wl->shm_lock, flags); 367} 368 369/* Read HostFlags */ 370u32 b43_hf_read(struct b43_wldev * dev) 371{ 372 u32 ret; 373 374 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 375 ret <<= 16; 376 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 377 378 return ret; 379} 380 381/* Write HostFlags */ 382void b43_hf_write(struct b43_wldev *dev, u32 value) 383{ 384 b43_shm_write16(dev, B43_SHM_SHARED, 385 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF)); 386 b43_shm_write16(dev, B43_SHM_SHARED, 387 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16)); 388} 389 390void b43_tsf_read(struct b43_wldev *dev, u64 * tsf) 391{ 392 /* We need to be careful. As we read the TSF from multiple 393 * registers, we should take care of register overflows. 394 * In theory, the whole tsf read process should be atomic. 395 * We try to be atomic here, by restaring the read process, 396 * if any of the high registers changed (overflew). 397 */ 398 if (dev->dev->id.revision >= 3) { 399 u32 low, high, high2; 400 401 do { 402 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 403 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 404 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 405 } while (unlikely(high != high2)); 406 407 *tsf = high; 408 *tsf <<= 32; 409 *tsf |= low; 410 } else { 411 u64 tmp; 412 u16 v0, v1, v2, v3; 413 u16 test1, test2, test3; 414 415 do { 416 v3 = b43_read16(dev, B43_MMIO_TSF_3); 417 v2 = b43_read16(dev, B43_MMIO_TSF_2); 418 v1 = b43_read16(dev, B43_MMIO_TSF_1); 419 v0 = b43_read16(dev, B43_MMIO_TSF_0); 420 421 test3 = b43_read16(dev, B43_MMIO_TSF_3); 422 test2 = b43_read16(dev, B43_MMIO_TSF_2); 423 test1 = b43_read16(dev, B43_MMIO_TSF_1); 424 } while (v3 != test3 || v2 != test2 || v1 != test1); 425 426 *tsf = v3; 427 *tsf <<= 48; 428 tmp = v2; 429 tmp <<= 32; 430 *tsf |= tmp; 431 tmp = v1; 432 tmp <<= 16; 433 *tsf |= tmp; 434 *tsf |= v0; 435 } 436} 437 438static void b43_time_lock(struct b43_wldev *dev) 439{ 440 u32 macctl; 441 442 macctl = b43_read32(dev, B43_MMIO_MACCTL); 443 macctl |= B43_MACCTL_TBTTHOLD; 444 b43_write32(dev, B43_MMIO_MACCTL, macctl); 445 /* Commit the write */ 446 b43_read32(dev, B43_MMIO_MACCTL); 447} 448 449static void b43_time_unlock(struct b43_wldev *dev) 450{ 451 u32 macctl; 452 453 macctl = b43_read32(dev, B43_MMIO_MACCTL); 454 macctl &= ~B43_MACCTL_TBTTHOLD; 455 b43_write32(dev, B43_MMIO_MACCTL, macctl); 456 /* Commit the write */ 457 b43_read32(dev, B43_MMIO_MACCTL); 458} 459 460static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 461{ 462 /* Be careful with the in-progress timer. 463 * First zero out the low register, so we have a full 464 * register-overflow duration to complete the operation. 465 */ 466 if (dev->dev->id.revision >= 3) { 467 u32 lo = (tsf & 0x00000000FFFFFFFFULL); 468 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32; 469 470 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0); 471 mmiowb(); 472 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi); 473 mmiowb(); 474 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo); 475 } else { 476 u16 v0 = (tsf & 0x000000000000FFFFULL); 477 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16; 478 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32; 479 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; 480 481 b43_write16(dev, B43_MMIO_TSF_0, 0); 482 mmiowb(); 483 b43_write16(dev, B43_MMIO_TSF_3, v3); 484 mmiowb(); 485 b43_write16(dev, B43_MMIO_TSF_2, v2); 486 mmiowb(); 487 b43_write16(dev, B43_MMIO_TSF_1, v1); 488 mmiowb(); 489 b43_write16(dev, B43_MMIO_TSF_0, v0); 490 } 491} 492 493void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 494{ 495 b43_time_lock(dev); 496 b43_tsf_write_locked(dev, tsf); 497 b43_time_unlock(dev); 498} 499 500static 501void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac) 502{ 503 static const u8 zero_addr[ETH_ALEN] = { 0 }; 504 u16 data; 505 506 if (!mac) 507 mac = zero_addr; 508 509 offset |= 0x0020; 510 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 511 512 data = mac[0]; 513 data |= mac[1] << 8; 514 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 515 data = mac[2]; 516 data |= mac[3] << 8; 517 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 518 data = mac[4]; 519 data |= mac[5] << 8; 520 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 521} 522 523static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 524{ 525 const u8 *mac; 526 const u8 *bssid; 527 u8 mac_bssid[ETH_ALEN * 2]; 528 int i; 529 u32 tmp; 530 531 bssid = dev->wl->bssid; 532 mac = dev->wl->mac_addr; 533 534 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 535 536 memcpy(mac_bssid, mac, ETH_ALEN); 537 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 538 539 /* Write our MAC address and BSSID to template ram */ 540 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 541 tmp = (u32) (mac_bssid[i + 0]); 542 tmp |= (u32) (mac_bssid[i + 1]) << 8; 543 tmp |= (u32) (mac_bssid[i + 2]) << 16; 544 tmp |= (u32) (mac_bssid[i + 3]) << 24; 545 b43_ram_write(dev, 0x20 + i, tmp); 546 } 547} 548 549static void b43_upload_card_macaddress(struct b43_wldev *dev) 550{ 551 b43_write_mac_bssid_templates(dev); 552 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 553} 554 555static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 556{ 557 /* slot_time is in usec. */ 558 if (dev->phy.type != B43_PHYTYPE_G) 559 return; 560 b43_write16(dev, 0x684, 510 + slot_time); 561 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 562} 563 564static void b43_short_slot_timing_enable(struct b43_wldev *dev) 565{ 566 b43_set_slot_time(dev, 9); 567 dev->short_slot = 1; 568} 569 570static void b43_short_slot_timing_disable(struct b43_wldev *dev) 571{ 572 b43_set_slot_time(dev, 20); 573 dev->short_slot = 0; 574} 575 576/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable. 577 * Returns the _previously_ enabled IRQ mask. 578 */ 579static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask) 580{ 581 u32 old_mask; 582 583 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 584 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask); 585 586 return old_mask; 587} 588 589/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable. 590 * Returns the _previously_ enabled IRQ mask. 591 */ 592static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask) 593{ 594 u32 old_mask; 595 596 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 597 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask); 598 599 return old_mask; 600} 601 602/* Synchronize IRQ top- and bottom-half. 603 * IRQs must be masked before calling this. 604 * This must not be called with the irq_lock held. 605 */ 606static void b43_synchronize_irq(struct b43_wldev *dev) 607{ 608 synchronize_irq(dev->dev->irq); 609 tasklet_kill(&dev->isr_tasklet); 610} 611 612/* DummyTransmission function, as documented on 613 * http://bcm-specs.sipsolutions.net/DummyTransmission 614 */ 615void b43_dummy_transmission(struct b43_wldev *dev) 616{ 617 struct b43_phy *phy = &dev->phy; 618 unsigned int i, max_loop; 619 u16 value; 620 u32 buffer[5] = { 621 0x00000000, 622 0x00D40000, 623 0x00000000, 624 0x01000000, 625 0x00000000, 626 }; 627 628 switch (phy->type) { 629 case B43_PHYTYPE_A: 630 max_loop = 0x1E; 631 buffer[0] = 0x000201CC; 632 break; 633 case B43_PHYTYPE_B: 634 case B43_PHYTYPE_G: 635 max_loop = 0xFA; 636 buffer[0] = 0x000B846E; 637 break; 638 default: 639 B43_WARN_ON(1); 640 return; 641 } 642 643 for (i = 0; i < 5; i++) 644 b43_ram_write(dev, i * 4, buffer[i]); 645 646 /* Commit writes */ 647 b43_read32(dev, B43_MMIO_MACCTL); 648 649 b43_write16(dev, 0x0568, 0x0000); 650 b43_write16(dev, 0x07C0, 0x0000); 651 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0); 652 b43_write16(dev, 0x050C, value); 653 b43_write16(dev, 0x0508, 0x0000); 654 b43_write16(dev, 0x050A, 0x0000); 655 b43_write16(dev, 0x054C, 0x0000); 656 b43_write16(dev, 0x056A, 0x0014); 657 b43_write16(dev, 0x0568, 0x0826); 658 b43_write16(dev, 0x0500, 0x0000); 659 b43_write16(dev, 0x0502, 0x0030); 660 661 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 662 b43_radio_write16(dev, 0x0051, 0x0017); 663 for (i = 0x00; i < max_loop; i++) { 664 value = b43_read16(dev, 0x050E); 665 if (value & 0x0080) 666 break; 667 udelay(10); 668 } 669 for (i = 0x00; i < 0x0A; i++) { 670 value = b43_read16(dev, 0x050E); 671 if (value & 0x0400) 672 break; 673 udelay(10); 674 } 675 for (i = 0x00; i < 0x0A; i++) { 676 value = b43_read16(dev, 0x0690); 677 if (!(value & 0x0100)) 678 break; 679 udelay(10); 680 } 681 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 682 b43_radio_write16(dev, 0x0051, 0x0037); 683} 684 685static void key_write(struct b43_wldev *dev, 686 u8 index, u8 algorithm, const u8 * key) 687{ 688 unsigned int i; 689 u32 offset; 690 u16 value; 691 u16 kidx; 692 693 /* Key index/algo block */ 694 kidx = b43_kidx_to_fw(dev, index); 695 value = ((kidx << 4) | algorithm); 696 b43_shm_write16(dev, B43_SHM_SHARED, 697 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 698 699 /* Write the key to the Key Table Pointer offset */ 700 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 701 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 702 value = key[i]; 703 value |= (u16) (key[i + 1]) << 8; 704 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 705 } 706} 707 708static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr) 709{ 710 u32 addrtmp[2] = { 0, 0, }; 711 u8 per_sta_keys_start = 8; 712 713 if (b43_new_kidx_api(dev)) 714 per_sta_keys_start = 4; 715 716 B43_WARN_ON(index < per_sta_keys_start); 717 /* We have two default TX keys and possibly two default RX keys. 718 * Physical mac 0 is mapped to physical key 4 or 8, depending 719 * on the firmware version. 720 * So we must adjust the index here. 721 */ 722 index -= per_sta_keys_start; 723 724 if (addr) { 725 addrtmp[0] = addr[0]; 726 addrtmp[0] |= ((u32) (addr[1]) << 8); 727 addrtmp[0] |= ((u32) (addr[2]) << 16); 728 addrtmp[0] |= ((u32) (addr[3]) << 24); 729 addrtmp[1] = addr[4]; 730 addrtmp[1] |= ((u32) (addr[5]) << 8); 731 } 732 733 if (dev->dev->id.revision >= 5) { 734 /* Receive match transmitter address mechanism */ 735 b43_shm_write32(dev, B43_SHM_RCMTA, 736 (index * 2) + 0, addrtmp[0]); 737 b43_shm_write16(dev, B43_SHM_RCMTA, 738 (index * 2) + 1, addrtmp[1]); 739 } else { 740 /* RXE (Receive Engine) and 741 * PSM (Programmable State Machine) mechanism 742 */ 743 if (index < 8) { 744 /* TODO write to RCM 16, 19, 22 and 25 */ 745 } else { 746 b43_shm_write32(dev, B43_SHM_SHARED, 747 B43_SHM_SH_PSM + (index * 6) + 0, 748 addrtmp[0]); 749 b43_shm_write16(dev, B43_SHM_SHARED, 750 B43_SHM_SH_PSM + (index * 6) + 4, 751 addrtmp[1]); 752 } 753 } 754} 755 756static void do_key_write(struct b43_wldev *dev, 757 u8 index, u8 algorithm, 758 const u8 * key, size_t key_len, const u8 * mac_addr) 759{ 760 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 761 u8 per_sta_keys_start = 8; 762 763 if (b43_new_kidx_api(dev)) 764 per_sta_keys_start = 4; 765 766 B43_WARN_ON(index >= dev->max_nr_keys); 767 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 768 769 if (index >= per_sta_keys_start) 770 keymac_write(dev, index, NULL); /* First zero out mac. */ 771 if (key) 772 memcpy(buf, key, key_len); 773 key_write(dev, index, algorithm, buf); 774 if (index >= per_sta_keys_start) 775 keymac_write(dev, index, mac_addr); 776 777 dev->key[index].algorithm = algorithm; 778} 779 780static int b43_key_write(struct b43_wldev *dev, 781 int index, u8 algorithm, 782 const u8 * key, size_t key_len, 783 const u8 * mac_addr, 784 struct ieee80211_key_conf *keyconf) 785{ 786 int i; 787 int sta_keys_start; 788 789 if (key_len > B43_SEC_KEYSIZE) 790 return -EINVAL; 791 for (i = 0; i < dev->max_nr_keys; i++) { 792 /* Check that we don't already have this key. */ 793 B43_WARN_ON(dev->key[i].keyconf == keyconf); 794 } 795 if (index < 0) { 796 /* Either pairwise key or address is 00:00:00:00:00:00 797 * for transmit-only keys. Search the index. */ 798 if (b43_new_kidx_api(dev)) 799 sta_keys_start = 4; 800 else 801 sta_keys_start = 8; 802 for (i = sta_keys_start; i < dev->max_nr_keys; i++) { 803 if (!dev->key[i].keyconf) { 804 /* found empty */ 805 index = i; 806 break; 807 } 808 } 809 if (index < 0) { 810 b43err(dev->wl, "Out of hardware key memory\n"); 811 return -ENOSPC; 812 } 813 } else 814 B43_WARN_ON(index > 3); 815 816 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 817 if ((index <= 3) && !b43_new_kidx_api(dev)) { 818 /* Default RX key */ 819 B43_WARN_ON(mac_addr); 820 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 821 } 822 keyconf->hw_key_idx = index; 823 dev->key[index].keyconf = keyconf; 824 825 return 0; 826} 827 828static int b43_key_clear(struct b43_wldev *dev, int index) 829{ 830 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys))) 831 return -EINVAL; 832 do_key_write(dev, index, B43_SEC_ALGO_NONE, 833 NULL, B43_SEC_KEYSIZE, NULL); 834 if ((index <= 3) && !b43_new_kidx_api(dev)) { 835 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 836 NULL, B43_SEC_KEYSIZE, NULL); 837 } 838 dev->key[index].keyconf = NULL; 839 840 return 0; 841} 842 843static void b43_clear_keys(struct b43_wldev *dev) 844{ 845 int i; 846 847 for (i = 0; i < dev->max_nr_keys; i++) 848 b43_key_clear(dev, i); 849} 850 851void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 852{ 853 u32 macctl; 854 u16 ucstat; 855 bool hwps; 856 bool awake; 857 int i; 858 859 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 860 (ps_flags & B43_PS_DISABLED)); 861 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 862 863 if (ps_flags & B43_PS_ENABLED) { 864 hwps = 1; 865 } else if (ps_flags & B43_PS_DISABLED) { 866 hwps = 0; 867 } else { 868 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 869 // and thus is not an AP and we are associated, set bit 25 870 } 871 if (ps_flags & B43_PS_AWAKE) { 872 awake = 1; 873 } else if (ps_flags & B43_PS_ASLEEP) { 874 awake = 0; 875 } else { 876 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 877 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 878 // successful, set bit26 879 } 880 881/* FIXME: For now we force awake-on and hwps-off */ 882 hwps = 0; 883 awake = 1; 884 885 macctl = b43_read32(dev, B43_MMIO_MACCTL); 886 if (hwps) 887 macctl |= B43_MACCTL_HWPS; 888 else 889 macctl &= ~B43_MACCTL_HWPS; 890 if (awake) 891 macctl |= B43_MACCTL_AWAKE; 892 else 893 macctl &= ~B43_MACCTL_AWAKE; 894 b43_write32(dev, B43_MMIO_MACCTL, macctl); 895 /* Commit write */ 896 b43_read32(dev, B43_MMIO_MACCTL); 897 if (awake && dev->dev->id.revision >= 5) { 898 /* Wait for the microcode to wake up. */ 899 for (i = 0; i < 100; i++) { 900 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 901 B43_SHM_SH_UCODESTAT); 902 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 903 break; 904 udelay(10); 905 } 906 } 907} 908 909/* Turn the Analog ON/OFF */ 910static void b43_switch_analog(struct b43_wldev *dev, int on) 911{ 912 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); 913} 914 915void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 916{ 917 u32 tmslow; 918 u32 macctl; 919 920 flags |= B43_TMSLOW_PHYCLKEN; 921 flags |= B43_TMSLOW_PHYRESET; 922 ssb_device_enable(dev->dev, flags); 923 msleep(2); /* Wait for the PLL to turn on. */ 924 925 /* Now take the PHY out of Reset again */ 926 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 927 tmslow |= SSB_TMSLOW_FGC; 928 tmslow &= ~B43_TMSLOW_PHYRESET; 929 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 930 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 931 msleep(1); 932 tmslow &= ~SSB_TMSLOW_FGC; 933 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 934 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 935 msleep(1); 936 937 /* Turn Analog ON */ 938 b43_switch_analog(dev, 1); 939 940 macctl = b43_read32(dev, B43_MMIO_MACCTL); 941 macctl &= ~B43_MACCTL_GMODE; 942 if (flags & B43_TMSLOW_GMODE) 943 macctl |= B43_MACCTL_GMODE; 944 macctl |= B43_MACCTL_IHR_ENABLED; 945 b43_write32(dev, B43_MMIO_MACCTL, macctl); 946} 947 948static void handle_irq_transmit_status(struct b43_wldev *dev) 949{ 950 u32 v0, v1; 951 u16 tmp; 952 struct b43_txstatus stat; 953 954 while (1) { 955 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 956 if (!(v0 & 0x00000001)) 957 break; 958 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 959 960 stat.cookie = (v0 >> 16); 961 stat.seq = (v1 & 0x0000FFFF); 962 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 963 tmp = (v0 & 0x0000FFFF); 964 stat.frame_count = ((tmp & 0xF000) >> 12); 965 stat.rts_count = ((tmp & 0x0F00) >> 8); 966 stat.supp_reason = ((tmp & 0x001C) >> 2); 967 stat.pm_indicated = !!(tmp & 0x0080); 968 stat.intermediate = !!(tmp & 0x0040); 969 stat.for_ampdu = !!(tmp & 0x0020); 970 stat.acked = !!(tmp & 0x0002); 971 972 b43_handle_txstatus(dev, &stat); 973 } 974} 975 976static void drain_txstatus_queue(struct b43_wldev *dev) 977{ 978 u32 dummy; 979 980 if (dev->dev->id.revision < 5) 981 return; 982 /* Read all entries from the microcode TXstatus FIFO 983 * and throw them away. 984 */ 985 while (1) { 986 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 987 if (!(dummy & 0x00000001)) 988 break; 989 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 990 } 991} 992 993static u32 b43_jssi_read(struct b43_wldev *dev) 994{ 995 u32 val = 0; 996 997 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 998 val <<= 16; 999 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1000 1001 return val; 1002} 1003 1004static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1005{ 1006 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1007 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1008} 1009 1010static void b43_generate_noise_sample(struct b43_wldev *dev) 1011{ 1012 b43_jssi_write(dev, 0x7F7F7F7F); 1013 b43_write32(dev, B43_MMIO_MACCMD, 1014 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1015 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel); 1016} 1017 1018static void b43_calculate_link_quality(struct b43_wldev *dev) 1019{ 1020 /* Top half of Link Quality calculation. */ 1021 1022 if (dev->noisecalc.calculation_running) 1023 return; 1024 dev->noisecalc.channel_at_start = dev->phy.channel; 1025 dev->noisecalc.calculation_running = 1; 1026 dev->noisecalc.nr_samples = 0; 1027 1028 b43_generate_noise_sample(dev); 1029} 1030 1031static void handle_irq_noise(struct b43_wldev *dev) 1032{ 1033 struct b43_phy *phy = &dev->phy; 1034 u16 tmp; 1035 u8 noise[4]; 1036 u8 i, j; 1037 s32 average; 1038 1039 /* Bottom half of Link Quality calculation. */ 1040 1041 B43_WARN_ON(!dev->noisecalc.calculation_running); 1042 if (dev->noisecalc.channel_at_start != phy->channel) 1043 goto drop_calculation; 1044 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1045 if (noise[0] == 0x7F || noise[1] == 0x7F || 1046 noise[2] == 0x7F || noise[3] == 0x7F) 1047 goto generate_new; 1048 1049 /* Get the noise samples. */ 1050 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1051 i = dev->noisecalc.nr_samples; 1052 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1053 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1054 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1055 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1056 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1057 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1058 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1059 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1060 dev->noisecalc.nr_samples++; 1061 if (dev->noisecalc.nr_samples == 8) { 1062 /* Calculate the Link Quality by the noise samples. */ 1063 average = 0; 1064 for (i = 0; i < 8; i++) { 1065 for (j = 0; j < 4; j++) 1066 average += dev->noisecalc.samples[i][j]; 1067 } 1068 average /= (8 * 4); 1069 average *= 125; 1070 average += 64; 1071 average /= 128; 1072 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1073 tmp = (tmp / 128) & 0x1F; 1074 if (tmp >= 8) 1075 average += 2; 1076 else 1077 average -= 25; 1078 if (tmp == 8) 1079 average -= 72; 1080 else 1081 average -= 48; 1082 1083 dev->stats.link_noise = average; 1084 drop_calculation: 1085 dev->noisecalc.calculation_running = 0; 1086 return; 1087 } 1088 generate_new: 1089 b43_generate_noise_sample(dev); 1090} 1091 1092static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1093{ 1094 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) { 1095 ///TODO: PS TBTT 1096 } else { 1097 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1098 b43_power_saving_ctl_bits(dev, 0); 1099 } 1100 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) 1101 dev->dfq_valid = 1; 1102} 1103 1104static void handle_irq_atim_end(struct b43_wldev *dev) 1105{ 1106 if (dev->dfq_valid) { 1107 b43_write32(dev, B43_MMIO_MACCMD, 1108 b43_read32(dev, B43_MMIO_MACCMD) 1109 | B43_MACCMD_DFQ_VALID); 1110 dev->dfq_valid = 0; 1111 } 1112} 1113 1114static void handle_irq_pmq(struct b43_wldev *dev) 1115{ 1116 u32 tmp; 1117 1118 //TODO: AP mode. 1119 1120 while (1) { 1121 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1122 if (!(tmp & 0x00000008)) 1123 break; 1124 } 1125 /* 16bit write is odd, but correct. */ 1126 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1127} 1128 1129static void b43_write_template_common(struct b43_wldev *dev, 1130 const u8 * data, u16 size, 1131 u16 ram_offset, 1132 u16 shm_size_offset, u8 rate) 1133{ 1134 u32 i, tmp; 1135 struct b43_plcp_hdr4 plcp; 1136 1137 plcp.data = 0; 1138 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1139 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1140 ram_offset += sizeof(u32); 1141 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1142 * So leave the first two bytes of the next write blank. 1143 */ 1144 tmp = (u32) (data[0]) << 16; 1145 tmp |= (u32) (data[1]) << 24; 1146 b43_ram_write(dev, ram_offset, tmp); 1147 ram_offset += sizeof(u32); 1148 for (i = 2; i < size; i += sizeof(u32)) { 1149 tmp = (u32) (data[i + 0]); 1150 if (i + 1 < size) 1151 tmp |= (u32) (data[i + 1]) << 8; 1152 if (i + 2 < size) 1153 tmp |= (u32) (data[i + 2]) << 16; 1154 if (i + 3 < size) 1155 tmp |= (u32) (data[i + 3]) << 24; 1156 b43_ram_write(dev, ram_offset + i - 2, tmp); 1157 } 1158 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1159 size + sizeof(struct b43_plcp_hdr6)); 1160} 1161 1162static void b43_write_beacon_template(struct b43_wldev *dev, 1163 u16 ram_offset, 1164 u16 shm_size_offset, u8 rate) 1165{ 1166 unsigned int i, len, variable_len; 1167 const struct ieee80211_mgmt *bcn; 1168 const u8 *ie; 1169 bool tim_found = 0; 1170 1171 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1172 len = min((size_t) dev->wl->current_beacon->len, 1173 0x200 - sizeof(struct b43_plcp_hdr6)); 1174 1175 b43_write_template_common(dev, (const u8 *)bcn, 1176 len, ram_offset, shm_size_offset, rate); 1177 1178 /* Find the position of the TIM and the DTIM_period value 1179 * and write them to SHM. */ 1180 ie = bcn->u.beacon.variable; 1181 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1182 for (i = 0; i < variable_len - 2; ) { 1183 uint8_t ie_id, ie_len; 1184 1185 ie_id = ie[i]; 1186 ie_len = ie[i + 1]; 1187 if (ie_id == 5) { 1188 u16 tim_position; 1189 u16 dtim_period; 1190 /* This is the TIM Information Element */ 1191 1192 /* Check whether the ie_len is in the beacon data range. */ 1193 if (variable_len < ie_len + 2 + i) 1194 break; 1195 /* A valid TIM is at least 4 bytes long. */ 1196 if (ie_len < 4) 1197 break; 1198 tim_found = 1; 1199 1200 tim_position = sizeof(struct b43_plcp_hdr6); 1201 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1202 tim_position += i; 1203 1204 dtim_period = ie[i + 3]; 1205 1206 b43_shm_write16(dev, B43_SHM_SHARED, 1207 B43_SHM_SH_TIMBPOS, tim_position); 1208 b43_shm_write16(dev, B43_SHM_SHARED, 1209 B43_SHM_SH_DTIMPER, dtim_period); 1210 break; 1211 } 1212 i += ie_len + 2; 1213 } 1214 if (!tim_found) { 1215 b43warn(dev->wl, "Did not find a valid TIM IE in " 1216 "the beacon template packet. AP or IBSS operation " 1217 "may be broken.\n"); 1218 } 1219} 1220 1221static void b43_write_probe_resp_plcp(struct b43_wldev *dev, 1222 u16 shm_offset, u16 size, u8 rate) 1223{ 1224 struct b43_plcp_hdr4 plcp; 1225 u32 tmp; 1226 __le16 dur; 1227 1228 plcp.data = 0; 1229 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1230 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1231 dev->wl->vif, size, 1232 B43_RATE_TO_BASE100KBPS(rate)); 1233 /* Write PLCP in two parts and timing for packet transfer */ 1234 tmp = le32_to_cpu(plcp.data); 1235 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF); 1236 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16); 1237 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur)); 1238} 1239 1240/* Instead of using custom probe response template, this function 1241 * just patches custom beacon template by: 1242 * 1) Changing packet type 1243 * 2) Patching duration field 1244 * 3) Stripping TIM 1245 */ 1246static const u8 * b43_generate_probe_resp(struct b43_wldev *dev, 1247 u16 *dest_size, u8 rate) 1248{ 1249 const u8 *src_data; 1250 u8 *dest_data; 1251 u16 src_size, elem_size, src_pos, dest_pos; 1252 __le16 dur; 1253 struct ieee80211_hdr *hdr; 1254 size_t ie_start; 1255 1256 src_size = dev->wl->current_beacon->len; 1257 src_data = (const u8 *)dev->wl->current_beacon->data; 1258 1259 /* Get the start offset of the variable IEs in the packet. */ 1260 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable); 1261 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable)); 1262 1263 if (B43_WARN_ON(src_size < ie_start)) 1264 return NULL; 1265 1266 dest_data = kmalloc(src_size, GFP_ATOMIC); 1267 if (unlikely(!dest_data)) 1268 return NULL; 1269 1270 /* Copy the static data and all Information Elements, except the TIM. */ 1271 memcpy(dest_data, src_data, ie_start); 1272 src_pos = ie_start; 1273 dest_pos = ie_start; 1274 for ( ; src_pos < src_size - 2; src_pos += elem_size) { 1275 elem_size = src_data[src_pos + 1] + 2; 1276 if (src_data[src_pos] == 5) { 1277 /* This is the TIM. */ 1278 continue; 1279 } 1280 memcpy(dest_data + dest_pos, src_data + src_pos, 1281 elem_size); 1282 dest_pos += elem_size; 1283 } 1284 *dest_size = dest_pos; 1285 hdr = (struct ieee80211_hdr *)dest_data; 1286 1287 /* Set the frame control. */ 1288 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | 1289 IEEE80211_STYPE_PROBE_RESP); 1290 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1291 dev->wl->vif, *dest_size, 1292 B43_RATE_TO_BASE100KBPS(rate)); 1293 hdr->duration_id = dur; 1294 1295 return dest_data; 1296} 1297 1298static void b43_write_probe_resp_template(struct b43_wldev *dev, 1299 u16 ram_offset, 1300 u16 shm_size_offset, u8 rate) 1301{ 1302 const u8 *probe_resp_data; 1303 u16 size; 1304 1305 size = dev->wl->current_beacon->len; 1306 probe_resp_data = b43_generate_probe_resp(dev, &size, rate); 1307 if (unlikely(!probe_resp_data)) 1308 return; 1309 1310 /* Looks like PLCP headers plus packet timings are stored for 1311 * all possible basic rates 1312 */ 1313 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB); 1314 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB); 1315 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB); 1316 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB); 1317 1318 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6)); 1319 b43_write_template_common(dev, probe_resp_data, 1320 size, ram_offset, shm_size_offset, rate); 1321 kfree(probe_resp_data); 1322} 1323 1324/* Asynchronously update the packet templates in template RAM. 1325 * Locking: Requires wl->irq_lock to be locked. */ 1326static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon) 1327{ 1328 /* This is the top half of the ansynchronous beacon update. 1329 * The bottom half is the beacon IRQ. 1330 * Beacon update must be asynchronous to avoid sending an 1331 * invalid beacon. This can happen for example, if the firmware 1332 * transmits a beacon while we are updating it. */ 1333 1334 if (wl->current_beacon) 1335 dev_kfree_skb_any(wl->current_beacon); 1336 wl->current_beacon = beacon; 1337 wl->beacon0_uploaded = 0; 1338 wl->beacon1_uploaded = 0; 1339} 1340 1341static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len) 1342{ 1343 u32 tmp; 1344 u16 i, len; 1345 1346 len = min((u16) ssid_len, (u16) 0x100); 1347 for (i = 0; i < len; i += sizeof(u32)) { 1348 tmp = (u32) (ssid[i + 0]); 1349 if (i + 1 < len) 1350 tmp |= (u32) (ssid[i + 1]) << 8; 1351 if (i + 2 < len) 1352 tmp |= (u32) (ssid[i + 2]) << 16; 1353 if (i + 3 < len) 1354 tmp |= (u32) (ssid[i + 3]) << 24; 1355 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp); 1356 } 1357 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len); 1358} 1359 1360static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1361{ 1362 b43_time_lock(dev); 1363 if (dev->dev->id.revision >= 3) { 1364 b43_write32(dev, 0x188, (beacon_int << 16)); 1365 } else { 1366 b43_write16(dev, 0x606, (beacon_int >> 6)); 1367 b43_write16(dev, 0x610, beacon_int); 1368 } 1369 b43_time_unlock(dev); 1370} 1371 1372static void handle_irq_beacon(struct b43_wldev *dev) 1373{ 1374 struct b43_wl *wl = dev->wl; 1375 u32 cmd; 1376 1377 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 1378 return; 1379 1380 /* This is the bottom half of the asynchronous beacon update. */ 1381 1382 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1383 if (!(cmd & B43_MACCMD_BEACON0_VALID)) { 1384 if (!wl->beacon0_uploaded) { 1385 b43_write_beacon_template(dev, 0x68, 0x18, 1386 B43_CCK_RATE_1MB); 1387 b43_write_probe_resp_template(dev, 0x268, 0x4A, 1388 B43_CCK_RATE_11MB); 1389 wl->beacon0_uploaded = 1; 1390 } 1391 cmd |= B43_MACCMD_BEACON0_VALID; 1392 } 1393 if (!(cmd & B43_MACCMD_BEACON1_VALID)) { 1394 if (!wl->beacon1_uploaded) { 1395 b43_write_beacon_template(dev, 0x468, 0x1A, 1396 B43_CCK_RATE_1MB); 1397 wl->beacon1_uploaded = 1; 1398 } 1399 cmd |= B43_MACCMD_BEACON1_VALID; 1400 } 1401 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1402} 1403 1404static void handle_irq_ucode_debug(struct b43_wldev *dev) 1405{ 1406 //TODO 1407} 1408 1409/* Interrupt handler bottom-half */ 1410static void b43_interrupt_tasklet(struct b43_wldev *dev) 1411{ 1412 u32 reason; 1413 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1414 u32 merged_dma_reason = 0; 1415 int i; 1416 unsigned long flags; 1417 1418 spin_lock_irqsave(&dev->wl->irq_lock, flags); 1419 1420 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED); 1421 1422 reason = dev->irq_reason; 1423 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1424 dma_reason[i] = dev->dma_reason[i]; 1425 merged_dma_reason |= dma_reason[i]; 1426 } 1427 1428 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1429 b43err(dev->wl, "MAC transmission error\n"); 1430 1431 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1432 b43err(dev->wl, "PHY transmission error\n"); 1433 rmb(); 1434 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1435 atomic_set(&dev->phy.txerr_cnt, 1436 B43_PHY_TX_BADNESS_LIMIT); 1437 b43err(dev->wl, "Too many PHY TX errors, " 1438 "restarting the controller\n"); 1439 b43_controller_restart(dev, "PHY TX errors"); 1440 } 1441 } 1442 1443 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1444 B43_DMAIRQ_NONFATALMASK))) { 1445 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1446 b43err(dev->wl, "Fatal DMA error: " 1447 "0x%08X, 0x%08X, 0x%08X, " 1448 "0x%08X, 0x%08X, 0x%08X\n", 1449 dma_reason[0], dma_reason[1], 1450 dma_reason[2], dma_reason[3], 1451 dma_reason[4], dma_reason[5]); 1452 b43_controller_restart(dev, "DMA error"); 1453 mmiowb(); 1454 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1455 return; 1456 } 1457 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1458 b43err(dev->wl, "DMA error: " 1459 "0x%08X, 0x%08X, 0x%08X, " 1460 "0x%08X, 0x%08X, 0x%08X\n", 1461 dma_reason[0], dma_reason[1], 1462 dma_reason[2], dma_reason[3], 1463 dma_reason[4], dma_reason[5]); 1464 } 1465 } 1466 1467 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1468 handle_irq_ucode_debug(dev); 1469 if (reason & B43_IRQ_TBTT_INDI) 1470 handle_irq_tbtt_indication(dev); 1471 if (reason & B43_IRQ_ATIM_END) 1472 handle_irq_atim_end(dev); 1473 if (reason & B43_IRQ_BEACON) 1474 handle_irq_beacon(dev); 1475 if (reason & B43_IRQ_PMQ) 1476 handle_irq_pmq(dev); 1477 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1478 ;/* TODO */ 1479 if (reason & B43_IRQ_NOISESAMPLE_OK) 1480 handle_irq_noise(dev); 1481 1482 /* Check the DMA reason registers for received data. */ 1483 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) 1484 b43_dma_rx(dev->dma.rx_ring0); 1485 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) 1486 b43_dma_rx(dev->dma.rx_ring3); 1487 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1488 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1489 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1490 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1491 1492 if (reason & B43_IRQ_TX_OK) 1493 handle_irq_transmit_status(dev); 1494 1495 b43_interrupt_enable(dev, dev->irq_savedstate); 1496 mmiowb(); 1497 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1498} 1499 1500static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason) 1501{ 1502 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1503 1504 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1505 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1506 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1507 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1508 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1509 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1510} 1511 1512/* Interrupt handler top-half */ 1513static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1514{ 1515 irqreturn_t ret = IRQ_NONE; 1516 struct b43_wldev *dev = dev_id; 1517 u32 reason; 1518 1519 if (!dev) 1520 return IRQ_NONE; 1521 1522 spin_lock(&dev->wl->irq_lock); 1523 1524 if (b43_status(dev) < B43_STAT_STARTED) 1525 goto out; 1526 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1527 if (reason == 0xffffffff) /* shared IRQ */ 1528 goto out; 1529 ret = IRQ_HANDLED; 1530 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 1531 if (!reason) 1532 goto out; 1533 1534 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1535 & 0x0001DC00; 1536 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1537 & 0x0000DC00; 1538 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1539 & 0x0000DC00; 1540 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1541 & 0x0001DC00; 1542 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1543 & 0x0000DC00; 1544 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1545 & 0x0000DC00; 1546 1547 b43_interrupt_ack(dev, reason); 1548 /* disable all IRQs. They are enabled again in the bottom half. */ 1549 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 1550 /* save the reason code and call our bottom half. */ 1551 dev->irq_reason = reason; 1552 tasklet_schedule(&dev->isr_tasklet); 1553 out: 1554 mmiowb(); 1555 spin_unlock(&dev->wl->irq_lock); 1556 1557 return ret; 1558} 1559 1560static void b43_release_firmware(struct b43_wldev *dev) 1561{ 1562 release_firmware(dev->fw.ucode); 1563 dev->fw.ucode = NULL; 1564 release_firmware(dev->fw.pcm); 1565 dev->fw.pcm = NULL; 1566 release_firmware(dev->fw.initvals); 1567 dev->fw.initvals = NULL; 1568 release_firmware(dev->fw.initvals_band); 1569 dev->fw.initvals_band = NULL; 1570} 1571 1572static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 1573{ 1574 const char *text; 1575 1576 text = "You must go to " 1577 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware " 1578 "and download the latest firmware (version 4).\n"; 1579 if (error) 1580 b43err(wl, text); 1581 else 1582 b43warn(wl, text); 1583} 1584 1585static int do_request_fw(struct b43_wldev *dev, 1586 const char *name, 1587 const struct firmware **fw) 1588{ 1589 char path[sizeof(modparam_fwpostfix) + 32]; 1590 struct b43_fw_header *hdr; 1591 u32 size; 1592 int err; 1593 1594 if (!name) 1595 return 0; 1596 1597 snprintf(path, ARRAY_SIZE(path), 1598 "b43%s/%s.fw", 1599 modparam_fwpostfix, name); 1600 err = request_firmware(fw, path, dev->dev->dev); 1601 if (err) { 1602 b43err(dev->wl, "Firmware file \"%s\" not found " 1603 "or load failed.\n", path); 1604 return err; 1605 } 1606 if ((*fw)->size < sizeof(struct b43_fw_header)) 1607 goto err_format; 1608 hdr = (struct b43_fw_header *)((*fw)->data); 1609 switch (hdr->type) { 1610 case B43_FW_TYPE_UCODE: 1611 case B43_FW_TYPE_PCM: 1612 size = be32_to_cpu(hdr->size); 1613 if (size != (*fw)->size - sizeof(struct b43_fw_header)) 1614 goto err_format; 1615 /* fallthrough */ 1616 case B43_FW_TYPE_IV: 1617 if (hdr->ver != 1) 1618 goto err_format; 1619 break; 1620 default: 1621 goto err_format; 1622 } 1623 1624 return err; 1625 1626err_format: 1627 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path); 1628 return -EPROTO; 1629} 1630 1631static int b43_request_firmware(struct b43_wldev *dev) 1632{ 1633 struct b43_firmware *fw = &dev->fw; 1634 const u8 rev = dev->dev->id.revision; 1635 const char *filename; 1636 u32 tmshigh; 1637 int err; 1638 1639 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 1640 if (!fw->ucode) { 1641 if ((rev >= 5) && (rev <= 10)) 1642 filename = "ucode5"; 1643 else if ((rev >= 11) && (rev <= 12)) 1644 filename = "ucode11"; 1645 else if (rev >= 13) 1646 filename = "ucode13"; 1647 else 1648 goto err_no_ucode; 1649 err = do_request_fw(dev, filename, &fw->ucode); 1650 if (err) 1651 goto err_load; 1652 } 1653 if (!fw->pcm) { 1654 if ((rev >= 5) && (rev <= 10)) 1655 filename = "pcm5"; 1656 else if (rev >= 11) 1657 filename = NULL; 1658 else 1659 goto err_no_pcm; 1660 err = do_request_fw(dev, filename, &fw->pcm); 1661 if (err) 1662 goto err_load; 1663 } 1664 if (!fw->initvals) { 1665 switch (dev->phy.type) { 1666 case B43_PHYTYPE_A: 1667 if ((rev >= 5) && (rev <= 10)) { 1668 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 1669 filename = "a0g1initvals5"; 1670 else 1671 filename = "a0g0initvals5"; 1672 } else 1673 goto err_no_initvals; 1674 break; 1675 case B43_PHYTYPE_G: 1676 if ((rev >= 5) && (rev <= 10)) 1677 filename = "b0g0initvals5"; 1678 else if (rev >= 13) 1679 filename = "lp0initvals13"; 1680 else 1681 goto err_no_initvals; 1682 break; 1683 case B43_PHYTYPE_N: 1684 if ((rev >= 11) && (rev <= 12)) 1685 filename = "n0initvals11"; 1686 else 1687 goto err_no_initvals; 1688 break; 1689 default: 1690 goto err_no_initvals; 1691 } 1692 err = do_request_fw(dev, filename, &fw->initvals); 1693 if (err) 1694 goto err_load; 1695 } 1696 if (!fw->initvals_band) { 1697 switch (dev->phy.type) { 1698 case B43_PHYTYPE_A: 1699 if ((rev >= 5) && (rev <= 10)) { 1700 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 1701 filename = "a0g1bsinitvals5"; 1702 else 1703 filename = "a0g0bsinitvals5"; 1704 } else if (rev >= 11) 1705 filename = NULL; 1706 else 1707 goto err_no_initvals; 1708 break; 1709 case B43_PHYTYPE_G: 1710 if ((rev >= 5) && (rev <= 10)) 1711 filename = "b0g0bsinitvals5"; 1712 else if (rev >= 11) 1713 filename = NULL; 1714 else 1715 goto err_no_initvals; 1716 break; 1717 case B43_PHYTYPE_N: 1718 if ((rev >= 11) && (rev <= 12)) 1719 filename = "n0bsinitvals11"; 1720 else 1721 goto err_no_initvals; 1722 break; 1723 default: 1724 goto err_no_initvals; 1725 } 1726 err = do_request_fw(dev, filename, &fw->initvals_band); 1727 if (err) 1728 goto err_load; 1729 } 1730 1731 return 0; 1732 1733err_load: 1734 b43_print_fw_helptext(dev->wl, 1); 1735 goto error; 1736 1737err_no_ucode: 1738 err = -ENODEV; 1739 b43err(dev->wl, "No microcode available for core rev %u\n", rev); 1740 goto error; 1741 1742err_no_pcm: 1743 err = -ENODEV; 1744 b43err(dev->wl, "No PCM available for core rev %u\n", rev); 1745 goto error; 1746 1747err_no_initvals: 1748 err = -ENODEV; 1749 b43err(dev->wl, "No Initial Values firmware file for PHY %u, " 1750 "core rev %u\n", dev->phy.type, rev); 1751 goto error; 1752 1753error: 1754 b43_release_firmware(dev); 1755 return err; 1756} 1757 1758static int b43_upload_microcode(struct b43_wldev *dev) 1759{ 1760 const size_t hdr_len = sizeof(struct b43_fw_header); 1761 const __be32 *data; 1762 unsigned int i, len; 1763 u16 fwrev, fwpatch, fwdate, fwtime; 1764 u32 tmp; 1765 int err = 0; 1766 1767 /* Upload Microcode. */ 1768 data = (__be32 *) (dev->fw.ucode->data + hdr_len); 1769 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32); 1770 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 1771 for (i = 0; i < len; i++) { 1772 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1773 udelay(10); 1774 } 1775 1776 if (dev->fw.pcm) { 1777 /* Upload PCM data. */ 1778 data = (__be32 *) (dev->fw.pcm->data + hdr_len); 1779 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32); 1780 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 1781 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 1782 /* No need for autoinc bit in SHM_HW */ 1783 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 1784 for (i = 0; i < len; i++) { 1785 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1786 udelay(10); 1787 } 1788 } 1789 1790 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 1791 b43_write32(dev, B43_MMIO_MACCTL, 1792 B43_MACCTL_PSM_RUN | 1793 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA); 1794 1795 /* Wait for the microcode to load and respond */ 1796 i = 0; 1797 while (1) { 1798 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1799 if (tmp == B43_IRQ_MAC_SUSPENDED) 1800 break; 1801 i++; 1802 if (i >= 50) { 1803 b43err(dev->wl, "Microcode not responding\n"); 1804 b43_print_fw_helptext(dev->wl, 1); 1805 err = -ENODEV; 1806 goto out; 1807 } 1808 udelay(10); 1809 } 1810 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 1811 1812 /* Get and check the revisions. */ 1813 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 1814 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 1815 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 1816 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 1817 1818 if (fwrev <= 0x128) { 1819 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 1820 "binary drivers older than version 4.x is unsupported. " 1821 "You must upgrade your firmware files.\n"); 1822 b43_print_fw_helptext(dev->wl, 1); 1823 b43_write32(dev, B43_MMIO_MACCTL, 0); 1824 err = -EOPNOTSUPP; 1825 goto out; 1826 } 1827 b43dbg(dev->wl, "Loading firmware version %u.%u " 1828 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 1829 fwrev, fwpatch, 1830 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 1831 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 1832 1833 dev->fw.rev = fwrev; 1834 dev->fw.patch = fwpatch; 1835 1836 if (b43_is_old_txhdr_format(dev)) { 1837 b43warn(dev->wl, "You are using an old firmware image. " 1838 "Support for old firmware will be removed in July 2008.\n"); 1839 b43_print_fw_helptext(dev->wl, 0); 1840 } 1841 1842out: 1843 return err; 1844} 1845 1846static int b43_write_initvals(struct b43_wldev *dev, 1847 const struct b43_iv *ivals, 1848 size_t count, 1849 size_t array_size) 1850{ 1851 const struct b43_iv *iv; 1852 u16 offset; 1853 size_t i; 1854 bool bit32; 1855 1856 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 1857 iv = ivals; 1858 for (i = 0; i < count; i++) { 1859 if (array_size < sizeof(iv->offset_size)) 1860 goto err_format; 1861 array_size -= sizeof(iv->offset_size); 1862 offset = be16_to_cpu(iv->offset_size); 1863 bit32 = !!(offset & B43_IV_32BIT); 1864 offset &= B43_IV_OFFSET_MASK; 1865 if (offset >= 0x1000) 1866 goto err_format; 1867 if (bit32) { 1868 u32 value; 1869 1870 if (array_size < sizeof(iv->data.d32)) 1871 goto err_format; 1872 array_size -= sizeof(iv->data.d32); 1873 1874 value = be32_to_cpu(get_unaligned(&iv->data.d32)); 1875 b43_write32(dev, offset, value); 1876 1877 iv = (const struct b43_iv *)((const uint8_t *)iv + 1878 sizeof(__be16) + 1879 sizeof(__be32)); 1880 } else { 1881 u16 value; 1882 1883 if (array_size < sizeof(iv->data.d16)) 1884 goto err_format; 1885 array_size -= sizeof(iv->data.d16); 1886 1887 value = be16_to_cpu(iv->data.d16); 1888 b43_write16(dev, offset, value); 1889 1890 iv = (const struct b43_iv *)((const uint8_t *)iv + 1891 sizeof(__be16) + 1892 sizeof(__be16)); 1893 } 1894 } 1895 if (array_size) 1896 goto err_format; 1897 1898 return 0; 1899 1900err_format: 1901 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 1902 b43_print_fw_helptext(dev->wl, 1); 1903 1904 return -EPROTO; 1905} 1906 1907static int b43_upload_initvals(struct b43_wldev *dev) 1908{ 1909 const size_t hdr_len = sizeof(struct b43_fw_header); 1910 const struct b43_fw_header *hdr; 1911 struct b43_firmware *fw = &dev->fw; 1912 const struct b43_iv *ivals; 1913 size_t count; 1914 int err; 1915 1916 hdr = (const struct b43_fw_header *)(fw->initvals->data); 1917 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len); 1918 count = be32_to_cpu(hdr->size); 1919 err = b43_write_initvals(dev, ivals, count, 1920 fw->initvals->size - hdr_len); 1921 if (err) 1922 goto out; 1923 if (fw->initvals_band) { 1924 hdr = (const struct b43_fw_header *)(fw->initvals_band->data); 1925 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len); 1926 count = be32_to_cpu(hdr->size); 1927 err = b43_write_initvals(dev, ivals, count, 1928 fw->initvals_band->size - hdr_len); 1929 if (err) 1930 goto out; 1931 } 1932out: 1933 1934 return err; 1935} 1936 1937/* Initialize the GPIOs 1938 * http://bcm-specs.sipsolutions.net/GPIO 1939 */ 1940static int b43_gpio_init(struct b43_wldev *dev) 1941{ 1942 struct ssb_bus *bus = dev->dev->bus; 1943 struct ssb_device *gpiodev, *pcidev = NULL; 1944 u32 mask, set; 1945 1946 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 1947 & ~B43_MACCTL_GPOUTSMSK); 1948 1949 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 1950 | 0x000F); 1951 1952 mask = 0x0000001F; 1953 set = 0x0000000F; 1954 if (dev->dev->bus->chip_id == 0x4301) { 1955 mask |= 0x0060; 1956 set |= 0x0060; 1957 } 1958 if (0 /* FIXME: conditional unknown */ ) { 1959 b43_write16(dev, B43_MMIO_GPIO_MASK, 1960 b43_read16(dev, B43_MMIO_GPIO_MASK) 1961 | 0x0100); 1962 mask |= 0x0180; 1963 set |= 0x0180; 1964 } 1965 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) { 1966 b43_write16(dev, B43_MMIO_GPIO_MASK, 1967 b43_read16(dev, B43_MMIO_GPIO_MASK) 1968 | 0x0200); 1969 mask |= 0x0200; 1970 set |= 0x0200; 1971 } 1972 if (dev->dev->id.revision >= 2) 1973 mask |= 0x0010; /* FIXME: This is redundant. */ 1974 1975#ifdef CONFIG_SSB_DRIVER_PCICORE 1976 pcidev = bus->pcicore.dev; 1977#endif 1978 gpiodev = bus->chipco.dev ? : pcidev; 1979 if (!gpiodev) 1980 return 0; 1981 ssb_write32(gpiodev, B43_GPIO_CONTROL, 1982 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 1983 & mask) | set); 1984 1985 return 0; 1986} 1987 1988/* Turn off all GPIO stuff. Call this on module unload, for example. */ 1989static void b43_gpio_cleanup(struct b43_wldev *dev) 1990{ 1991 struct ssb_bus *bus = dev->dev->bus; 1992 struct ssb_device *gpiodev, *pcidev = NULL; 1993 1994#ifdef CONFIG_SSB_DRIVER_PCICORE 1995 pcidev = bus->pcicore.dev; 1996#endif 1997 gpiodev = bus->chipco.dev ? : pcidev; 1998 if (!gpiodev) 1999 return; 2000 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2001} 2002 2003/* http://bcm-specs.sipsolutions.net/EnableMac */ 2004void b43_mac_enable(struct b43_wldev *dev) 2005{ 2006 dev->mac_suspended--; 2007 B43_WARN_ON(dev->mac_suspended < 0); 2008 B43_WARN_ON(irqs_disabled()); 2009 if (dev->mac_suspended == 0) { 2010 b43_write32(dev, B43_MMIO_MACCTL, 2011 b43_read32(dev, B43_MMIO_MACCTL) 2012 | B43_MACCTL_ENABLED); 2013 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2014 B43_IRQ_MAC_SUSPENDED); 2015 /* Commit writes */ 2016 b43_read32(dev, B43_MMIO_MACCTL); 2017 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2018 b43_power_saving_ctl_bits(dev, 0); 2019 2020 /* Re-enable IRQs. */ 2021 spin_lock_irq(&dev->wl->irq_lock); 2022 b43_interrupt_enable(dev, dev->irq_savedstate); 2023 spin_unlock_irq(&dev->wl->irq_lock); 2024 } 2025} 2026 2027/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2028void b43_mac_suspend(struct b43_wldev *dev) 2029{ 2030 int i; 2031 u32 tmp; 2032 2033 might_sleep(); 2034 B43_WARN_ON(irqs_disabled()); 2035 B43_WARN_ON(dev->mac_suspended < 0); 2036 2037 if (dev->mac_suspended == 0) { 2038 /* Mask IRQs before suspending MAC. Otherwise 2039 * the MAC stays busy and won't suspend. */ 2040 spin_lock_irq(&dev->wl->irq_lock); 2041 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL); 2042 spin_unlock_irq(&dev->wl->irq_lock); 2043 b43_synchronize_irq(dev); 2044 dev->irq_savedstate = tmp; 2045 2046 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2047 b43_write32(dev, B43_MMIO_MACCTL, 2048 b43_read32(dev, B43_MMIO_MACCTL) 2049 & ~B43_MACCTL_ENABLED); 2050 /* force pci to flush the write */ 2051 b43_read32(dev, B43_MMIO_MACCTL); 2052 for (i = 40; i; i--) { 2053 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2054 if (tmp & B43_IRQ_MAC_SUSPENDED) 2055 goto out; 2056 msleep(1); 2057 } 2058 b43err(dev->wl, "MAC suspend failed\n"); 2059 } 2060out: 2061 dev->mac_suspended++; 2062} 2063 2064static void b43_adjust_opmode(struct b43_wldev *dev) 2065{ 2066 struct b43_wl *wl = dev->wl; 2067 u32 ctl; 2068 u16 cfp_pretbtt; 2069 2070 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2071 /* Reset status to STA infrastructure mode. */ 2072 ctl &= ~B43_MACCTL_AP; 2073 ctl &= ~B43_MACCTL_KEEP_CTL; 2074 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2075 ctl &= ~B43_MACCTL_KEEP_BAD; 2076 ctl &= ~B43_MACCTL_PROMISC; 2077 ctl &= ~B43_MACCTL_BEACPROMISC; 2078 ctl |= B43_MACCTL_INFRA; 2079 2080 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2081 ctl |= B43_MACCTL_AP; 2082 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) 2083 ctl &= ~B43_MACCTL_INFRA; 2084 2085 if (wl->filter_flags & FIF_CONTROL) 2086 ctl |= B43_MACCTL_KEEP_CTL; 2087 if (wl->filter_flags & FIF_FCSFAIL) 2088 ctl |= B43_MACCTL_KEEP_BAD; 2089 if (wl->filter_flags & FIF_PLCPFAIL) 2090 ctl |= B43_MACCTL_KEEP_BADPLCP; 2091 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2092 ctl |= B43_MACCTL_PROMISC; 2093 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2094 ctl |= B43_MACCTL_BEACPROMISC; 2095 2096 /* Workaround: On old hardware the HW-MAC-address-filter 2097 * doesn't work properly, so always run promisc in filter 2098 * it in software. */ 2099 if (dev->dev->id.revision <= 4) 2100 ctl |= B43_MACCTL_PROMISC; 2101 2102 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2103 2104 cfp_pretbtt = 2; 2105 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2106 if (dev->dev->bus->chip_id == 0x4306 && 2107 dev->dev->bus->chip_rev == 3) 2108 cfp_pretbtt = 100; 2109 else 2110 cfp_pretbtt = 50; 2111 } 2112 b43_write16(dev, 0x612, cfp_pretbtt); 2113} 2114 2115static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2116{ 2117 u16 offset; 2118 2119 if (is_ofdm) { 2120 offset = 0x480; 2121 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2122 } else { 2123 offset = 0x4C0; 2124 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2125 } 2126 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2127 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2128} 2129 2130static void b43_rate_memory_init(struct b43_wldev *dev) 2131{ 2132 switch (dev->phy.type) { 2133 case B43_PHYTYPE_A: 2134 case B43_PHYTYPE_G: 2135 case B43_PHYTYPE_N: 2136 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2137 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2138 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2139 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2140 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2141 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2142 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2143 if (dev->phy.type == B43_PHYTYPE_A) 2144 break; 2145 /* fallthrough */ 2146 case B43_PHYTYPE_B: 2147 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2148 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2149 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2150 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2151 break; 2152 default: 2153 B43_WARN_ON(1); 2154 } 2155} 2156 2157/* Set the TX-Antenna for management frames sent by firmware. */ 2158static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2159{ 2160 u16 ant = 0; 2161 u16 tmp; 2162 2163 switch (antenna) { 2164 case B43_ANTENNA0: 2165 ant |= B43_TXH_PHY_ANT0; 2166 break; 2167 case B43_ANTENNA1: 2168 ant |= B43_TXH_PHY_ANT1; 2169 break; 2170 case B43_ANTENNA2: 2171 ant |= B43_TXH_PHY_ANT2; 2172 break; 2173 case B43_ANTENNA3: 2174 ant |= B43_TXH_PHY_ANT3; 2175 break; 2176 case B43_ANTENNA_AUTO: 2177 ant |= B43_TXH_PHY_ANT01AUTO; 2178 break; 2179 default: 2180 B43_WARN_ON(1); 2181 } 2182 2183 /* FIXME We also need to set the other flags of the PHY control field somewhere. */ 2184 2185 /* For Beacons */ 2186 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 2187 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2188 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp); 2189 /* For ACK/CTS */ 2190 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2191 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2192 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2193 /* For Probe Resposes */ 2194 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2195 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2196 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2197} 2198 2199/* This is the opposite of b43_chip_init() */ 2200static void b43_chip_exit(struct b43_wldev *dev) 2201{ 2202 b43_radio_turn_off(dev, 1); 2203 b43_gpio_cleanup(dev); 2204 /* firmware is released later */ 2205} 2206 2207/* Initialize the chip 2208 * http://bcm-specs.sipsolutions.net/ChipInit 2209 */ 2210static int b43_chip_init(struct b43_wldev *dev) 2211{ 2212 struct b43_phy *phy = &dev->phy; 2213 int err, tmp; 2214 u32 value32; 2215 u16 value16; 2216 2217 b43_write32(dev, B43_MMIO_MACCTL, 2218 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED); 2219 2220 err = b43_request_firmware(dev); 2221 if (err) 2222 goto out; 2223 err = b43_upload_microcode(dev); 2224 if (err) 2225 goto out; /* firmware is released later */ 2226 2227 err = b43_gpio_init(dev); 2228 if (err) 2229 goto out; /* firmware is released later */ 2230 2231 err = b43_upload_initvals(dev); 2232 if (err) 2233 goto err_gpio_clean; 2234 b43_radio_turn_on(dev); 2235 2236 b43_write16(dev, 0x03E6, 0x0000); 2237 err = b43_phy_init(dev); 2238 if (err) 2239 goto err_radio_off; 2240 2241 /* Select initial Interference Mitigation. */ 2242 tmp = phy->interfmode; 2243 phy->interfmode = B43_INTERFMODE_NONE; 2244 b43_radio_set_interference_mitigation(dev, tmp); 2245 2246 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2247 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2248 2249 if (phy->type == B43_PHYTYPE_B) { 2250 value16 = b43_read16(dev, 0x005E); 2251 value16 |= 0x0004; 2252 b43_write16(dev, 0x005E, value16); 2253 } 2254 b43_write32(dev, 0x0100, 0x01000000); 2255 if (dev->dev->id.revision < 5) 2256 b43_write32(dev, 0x010C, 0x01000000); 2257 2258 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2259 & ~B43_MACCTL_INFRA); 2260 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2261 | B43_MACCTL_INFRA); 2262 2263 /* Probe Response Timeout value */ 2264 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2265 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2266 2267 /* Initially set the wireless operation mode. */ 2268 b43_adjust_opmode(dev); 2269 2270 if (dev->dev->id.revision < 3) { 2271 b43_write16(dev, 0x060E, 0x0000); 2272 b43_write16(dev, 0x0610, 0x8000); 2273 b43_write16(dev, 0x0604, 0x0000); 2274 b43_write16(dev, 0x0606, 0x0200); 2275 } else { 2276 b43_write32(dev, 0x0188, 0x80000000); 2277 b43_write32(dev, 0x018C, 0x02000000); 2278 } 2279 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2280 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2281 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2282 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2283 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2284 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2285 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2286 2287 value32 = ssb_read32(dev->dev, SSB_TMSLOW); 2288 value32 |= 0x00100000; 2289 ssb_write32(dev->dev, SSB_TMSLOW, value32); 2290 2291 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2292 dev->dev->bus->chipco.fast_pwrup_delay); 2293 2294 err = 0; 2295 b43dbg(dev->wl, "Chip initialized\n"); 2296out: 2297 return err; 2298 2299err_radio_off: 2300 b43_radio_turn_off(dev, 1); 2301err_gpio_clean: 2302 b43_gpio_cleanup(dev); 2303 return err; 2304} 2305 2306static void b43_periodic_every120sec(struct b43_wldev *dev) 2307{ 2308 struct b43_phy *phy = &dev->phy; 2309 2310 if (phy->type != B43_PHYTYPE_G || phy->rev < 2) 2311 return; 2312 2313 b43_mac_suspend(dev); 2314 b43_lo_g_measure(dev); 2315 b43_mac_enable(dev); 2316 if (b43_has_hardware_pctl(phy)) 2317 b43_lo_g_ctl_mark_all_unused(dev); 2318} 2319 2320static void b43_periodic_every60sec(struct b43_wldev *dev) 2321{ 2322 struct b43_phy *phy = &dev->phy; 2323 2324 if (phy->type != B43_PHYTYPE_G) 2325 return; 2326 if (!b43_has_hardware_pctl(phy)) 2327 b43_lo_g_ctl_mark_all_unused(dev); 2328 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) { 2329 b43_mac_suspend(dev); 2330 b43_calc_nrssi_slope(dev); 2331 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { 2332 u8 old_chan = phy->channel; 2333 2334 /* VCO Calibration */ 2335 if (old_chan >= 8) 2336 b43_radio_selectchannel(dev, 1, 0); 2337 else 2338 b43_radio_selectchannel(dev, 13, 0); 2339 b43_radio_selectchannel(dev, old_chan, 0); 2340 } 2341 b43_mac_enable(dev); 2342 } 2343} 2344 2345static void b43_periodic_every30sec(struct b43_wldev *dev) 2346{ 2347 /* Update device statistics. */ 2348 b43_calculate_link_quality(dev); 2349} 2350 2351static void b43_periodic_every15sec(struct b43_wldev *dev) 2352{ 2353 struct b43_phy *phy = &dev->phy; 2354 2355 if (phy->type == B43_PHYTYPE_G) { 2356 //TODO: update_aci_moving_average 2357 if (phy->aci_enable && phy->aci_wlan_automatic) { 2358 b43_mac_suspend(dev); 2359 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) { 2360 if (0 /*TODO: bunch of conditions */ ) { 2361 b43_radio_set_interference_mitigation 2362 (dev, B43_INTERFMODE_MANUALWLAN); 2363 } 2364 } else if (1 /*TODO*/) { 2365 /* 2366 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) { 2367 b43_radio_set_interference_mitigation(dev, 2368 B43_INTERFMODE_NONE); 2369 } 2370 */ 2371 } 2372 b43_mac_enable(dev); 2373 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN && 2374 phy->rev == 1) { 2375 //TODO: implement rev1 workaround 2376 } 2377 } 2378 b43_phy_xmitpower(dev); //FIXME: unless scanning? 2379 //TODO for APHY (temperature?) 2380 2381 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 2382 wmb(); 2383} 2384 2385static void do_periodic_work(struct b43_wldev *dev) 2386{ 2387 unsigned int state; 2388 2389 state = dev->periodic_state; 2390 if (state % 8 == 0) 2391 b43_periodic_every120sec(dev); 2392 if (state % 4 == 0) 2393 b43_periodic_every60sec(dev); 2394 if (state % 2 == 0) 2395 b43_periodic_every30sec(dev); 2396 b43_periodic_every15sec(dev); 2397} 2398 2399/* Periodic work locking policy: 2400 * The whole periodic work handler is protected by 2401 * wl->mutex. If another lock is needed somewhere in the 2402 * pwork callchain, it's aquired in-place, where it's needed. 2403 */ 2404static void b43_periodic_work_handler(struct work_struct *work) 2405{ 2406 struct b43_wldev *dev = container_of(work, struct b43_wldev, 2407 periodic_work.work); 2408 struct b43_wl *wl = dev->wl; 2409 unsigned long delay; 2410 2411 mutex_lock(&wl->mutex); 2412 2413 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 2414 goto out; 2415 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 2416 goto out_requeue; 2417 2418 do_periodic_work(dev); 2419 2420 dev->periodic_state++; 2421out_requeue: 2422 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 2423 delay = msecs_to_jiffies(50); 2424 else 2425 delay = round_jiffies_relative(HZ * 15); 2426 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay); 2427out: 2428 mutex_unlock(&wl->mutex); 2429} 2430 2431static void b43_periodic_tasks_setup(struct b43_wldev *dev) 2432{ 2433 struct delayed_work *work = &dev->periodic_work; 2434 2435 dev->periodic_state = 0; 2436 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 2437 queue_delayed_work(dev->wl->hw->workqueue, work, 0); 2438} 2439 2440/* Check if communication with the device works correctly. */ 2441static int b43_validate_chipaccess(struct b43_wldev *dev) 2442{ 2443 u32 v, backup; 2444 2445 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0); 2446 2447 /* Check for read/write and endianness problems. */ 2448 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 2449 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 2450 goto error; 2451 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 2452 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 2453 goto error; 2454 2455 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup); 2456 2457 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) { 2458 /* The 32bit register shadows the two 16bit registers 2459 * with update sideeffects. Validate this. */ 2460 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 2461 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 2462 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 2463 goto error; 2464 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 2465 goto error; 2466 } 2467 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 2468 2469 v = b43_read32(dev, B43_MMIO_MACCTL); 2470 v |= B43_MACCTL_GMODE; 2471 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 2472 goto error; 2473 2474 return 0; 2475error: 2476 b43err(dev->wl, "Failed to validate the chipaccess\n"); 2477 return -ENODEV; 2478} 2479 2480static void b43_security_init(struct b43_wldev *dev) 2481{ 2482 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20; 2483 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key)); 2484 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 2485 /* KTP is a word address, but we address SHM bytewise. 2486 * So multiply by two. 2487 */ 2488 dev->ktp *= 2; 2489 if (dev->dev->id.revision >= 5) { 2490 /* Number of RCMTA address slots */ 2491 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8); 2492 } 2493 b43_clear_keys(dev); 2494} 2495 2496static int b43_rng_read(struct hwrng *rng, u32 * data) 2497{ 2498 struct b43_wl *wl = (struct b43_wl *)rng->priv; 2499 unsigned long flags; 2500 2501 /* Don't take wl->mutex here, as it could deadlock with 2502 * hwrng internal locking. It's not needed to take 2503 * wl->mutex here, anyway. */ 2504 2505 spin_lock_irqsave(&wl->irq_lock, flags); 2506 *data = b43_read16(wl->current_dev, B43_MMIO_RNG); 2507 spin_unlock_irqrestore(&wl->irq_lock, flags); 2508 2509 return (sizeof(u16)); 2510} 2511 2512static void b43_rng_exit(struct b43_wl *wl) 2513{ 2514 if (wl->rng_initialized) 2515 hwrng_unregister(&wl->rng); 2516} 2517 2518static int b43_rng_init(struct b43_wl *wl) 2519{ 2520 int err; 2521 2522 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 2523 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 2524 wl->rng.name = wl->rng_name; 2525 wl->rng.data_read = b43_rng_read; 2526 wl->rng.priv = (unsigned long)wl; 2527 wl->rng_initialized = 1; 2528 err = hwrng_register(&wl->rng); 2529 if (err) { 2530 wl->rng_initialized = 0; 2531 b43err(wl, "Failed to register the random " 2532 "number generator (%d)\n", err); 2533 } 2534 2535 return err; 2536} 2537 2538static int b43_op_tx(struct ieee80211_hw *hw, 2539 struct sk_buff *skb, 2540 struct ieee80211_tx_control *ctl) 2541{ 2542 struct b43_wl *wl = hw_to_b43_wl(hw); 2543 struct b43_wldev *dev = wl->current_dev; 2544 int err = -ENODEV; 2545 2546 if (unlikely(!dev)) 2547 goto out; 2548 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2549 goto out; 2550 /* DMA-TX is done without a global lock. */ 2551 err = b43_dma_tx(dev, skb, ctl); 2552out: 2553 if (unlikely(err)) 2554 return NETDEV_TX_BUSY; 2555 return NETDEV_TX_OK; 2556} 2557 2558static int b43_op_conf_tx(struct ieee80211_hw *hw, 2559 int queue, 2560 const struct ieee80211_tx_queue_params *params) 2561{ 2562 return 0; 2563} 2564 2565static int b43_op_get_tx_stats(struct ieee80211_hw *hw, 2566 struct ieee80211_tx_queue_stats *stats) 2567{ 2568 struct b43_wl *wl = hw_to_b43_wl(hw); 2569 struct b43_wldev *dev = wl->current_dev; 2570 unsigned long flags; 2571 int err = -ENODEV; 2572 2573 if (!dev) 2574 goto out; 2575 spin_lock_irqsave(&wl->irq_lock, flags); 2576 if (likely(b43_status(dev) >= B43_STAT_STARTED)) { 2577 b43_dma_get_tx_stats(dev, stats); 2578 err = 0; 2579 } 2580 spin_unlock_irqrestore(&wl->irq_lock, flags); 2581out: 2582 return err; 2583} 2584 2585static int b43_op_get_stats(struct ieee80211_hw *hw, 2586 struct ieee80211_low_level_stats *stats) 2587{ 2588 struct b43_wl *wl = hw_to_b43_wl(hw); 2589 unsigned long flags; 2590 2591 spin_lock_irqsave(&wl->irq_lock, flags); 2592 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 2593 spin_unlock_irqrestore(&wl->irq_lock, flags); 2594 2595 return 0; 2596} 2597 2598static const char *phymode_to_string(unsigned int phymode) 2599{ 2600 switch (phymode) { 2601 case B43_PHYMODE_A: 2602 return "A"; 2603 case B43_PHYMODE_B: 2604 return "B"; 2605 case B43_PHYMODE_G: 2606 return "G"; 2607 default: 2608 B43_WARN_ON(1); 2609 } 2610 return ""; 2611} 2612 2613static int find_wldev_for_phymode(struct b43_wl *wl, 2614 unsigned int phymode, 2615 struct b43_wldev **dev, bool * gmode) 2616{ 2617 struct b43_wldev *d; 2618 2619 list_for_each_entry(d, &wl->devlist, list) { 2620 if (d->phy.possible_phymodes & phymode) { 2621 /* Ok, this device supports the PHY-mode. 2622 * Now figure out how the gmode bit has to be 2623 * set to support it. */ 2624 if (phymode == B43_PHYMODE_A) 2625 *gmode = 0; 2626 else 2627 *gmode = 1; 2628 *dev = d; 2629 2630 return 0; 2631 } 2632 } 2633 2634 return -ESRCH; 2635} 2636 2637static void b43_put_phy_into_reset(struct b43_wldev *dev) 2638{ 2639 struct ssb_device *sdev = dev->dev; 2640 u32 tmslow; 2641 2642 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2643 tmslow &= ~B43_TMSLOW_GMODE; 2644 tmslow |= B43_TMSLOW_PHYRESET; 2645 tmslow |= SSB_TMSLOW_FGC; 2646 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2647 msleep(1); 2648 2649 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2650 tmslow &= ~SSB_TMSLOW_FGC; 2651 tmslow |= B43_TMSLOW_PHYRESET; 2652 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2653 msleep(1); 2654} 2655 2656/* Expects wl->mutex locked */ 2657static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode) 2658{ 2659 struct b43_wldev *up_dev; 2660 struct b43_wldev *down_dev; 2661 int err; 2662 bool gmode = 0; 2663 int prev_status; 2664 2665 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode); 2666 if (err) { 2667 b43err(wl, "Could not find a device for %s-PHY mode\n", 2668 phymode_to_string(new_mode)); 2669 return err; 2670 } 2671 if ((up_dev == wl->current_dev) && 2672 (!!wl->current_dev->phy.gmode == !!gmode)) { 2673 /* This device is already running. */ 2674 return 0; 2675 } 2676 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n", 2677 phymode_to_string(new_mode)); 2678 down_dev = wl->current_dev; 2679 2680 prev_status = b43_status(down_dev); 2681 /* Shutdown the currently running core. */ 2682 if (prev_status >= B43_STAT_STARTED) 2683 b43_wireless_core_stop(down_dev); 2684 if (prev_status >= B43_STAT_INITIALIZED) 2685 b43_wireless_core_exit(down_dev); 2686 2687 if (down_dev != up_dev) { 2688 /* We switch to a different core, so we put PHY into 2689 * RESET on the old core. */ 2690 b43_put_phy_into_reset(down_dev); 2691 } 2692 2693 /* Now start the new core. */ 2694 up_dev->phy.gmode = gmode; 2695 if (prev_status >= B43_STAT_INITIALIZED) { 2696 err = b43_wireless_core_init(up_dev); 2697 if (err) { 2698 b43err(wl, "Fatal: Could not initialize device for " 2699 "newly selected %s-PHY mode\n", 2700 phymode_to_string(new_mode)); 2701 goto init_failure; 2702 } 2703 } 2704 if (prev_status >= B43_STAT_STARTED) { 2705 err = b43_wireless_core_start(up_dev); 2706 if (err) { 2707 b43err(wl, "Fatal: Coult not start device for " 2708 "newly selected %s-PHY mode\n", 2709 phymode_to_string(new_mode)); 2710 b43_wireless_core_exit(up_dev); 2711 goto init_failure; 2712 } 2713 } 2714 B43_WARN_ON(b43_status(up_dev) != prev_status); 2715 2716 wl->current_dev = up_dev; 2717 2718 return 0; 2719 init_failure: 2720 /* Whoops, failed to init the new core. No core is operating now. */ 2721 wl->current_dev = NULL; 2722 return err; 2723} 2724 2725/* Check if the use of the antenna that ieee80211 told us to 2726 * use is possible. This will fall back to DEFAULT. 2727 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 2728u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 2729 u8 antenna_nr) 2730{ 2731 u8 antenna_mask; 2732 2733 if (antenna_nr == 0) { 2734 /* Zero means "use default antenna". That's always OK. */ 2735 return 0; 2736 } 2737 2738 /* Get the mask of available antennas. */ 2739 if (dev->phy.gmode) 2740 antenna_mask = dev->dev->bus->sprom.ant_available_bg; 2741 else 2742 antenna_mask = dev->dev->bus->sprom.ant_available_a; 2743 2744 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 2745 /* This antenna is not available. Fall back to default. */ 2746 return 0; 2747 } 2748 2749 return antenna_nr; 2750} 2751 2752static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna) 2753{ 2754 antenna = b43_ieee80211_antenna_sanitize(dev, antenna); 2755 switch (antenna) { 2756 case 0: /* default/diversity */ 2757 return B43_ANTENNA_DEFAULT; 2758 case 1: /* Antenna 0 */ 2759 return B43_ANTENNA0; 2760 case 2: /* Antenna 1 */ 2761 return B43_ANTENNA1; 2762 case 3: /* Antenna 2 */ 2763 return B43_ANTENNA2; 2764 case 4: /* Antenna 3 */ 2765 return B43_ANTENNA3; 2766 default: 2767 return B43_ANTENNA_DEFAULT; 2768 } 2769} 2770 2771static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) 2772{ 2773 struct b43_wl *wl = hw_to_b43_wl(hw); 2774 struct b43_wldev *dev; 2775 struct b43_phy *phy; 2776 unsigned long flags; 2777 unsigned int new_phymode = 0xFFFF; 2778 int antenna; 2779 int err = 0; 2780 u32 savedirqs; 2781 2782 mutex_lock(&wl->mutex); 2783 2784 /* Switch the PHY mode (if necessary). */ 2785 switch (conf->phymode) { 2786 case MODE_IEEE80211A: 2787 new_phymode = B43_PHYMODE_A; 2788 break; 2789 case MODE_IEEE80211B: 2790 new_phymode = B43_PHYMODE_B; 2791 break; 2792 case MODE_IEEE80211G: 2793 new_phymode = B43_PHYMODE_G; 2794 break; 2795 default: 2796 B43_WARN_ON(1); 2797 } 2798 err = b43_switch_phymode(wl, new_phymode); 2799 if (err) 2800 goto out_unlock_mutex; 2801 dev = wl->current_dev; 2802 phy = &dev->phy; 2803 2804 /* Disable IRQs while reconfiguring the device. 2805 * This makes it possible to drop the spinlock throughout 2806 * the reconfiguration process. */ 2807 spin_lock_irqsave(&wl->irq_lock, flags); 2808 if (b43_status(dev) < B43_STAT_STARTED) { 2809 spin_unlock_irqrestore(&wl->irq_lock, flags); 2810 goto out_unlock_mutex; 2811 } 2812 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL); 2813 spin_unlock_irqrestore(&wl->irq_lock, flags); 2814 b43_synchronize_irq(dev); 2815 2816 /* Switch to the requested channel. 2817 * The firmware takes care of races with the TX handler. */ 2818 if (conf->channel_val != phy->channel) 2819 b43_radio_selectchannel(dev, conf->channel_val, 0); 2820 2821 /* Enable/Disable ShortSlot timing. */ 2822 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != 2823 dev->short_slot) { 2824 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2825 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) 2826 b43_short_slot_timing_enable(dev); 2827 else 2828 b43_short_slot_timing_disable(dev); 2829 } 2830 2831 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP); 2832 2833 /* Adjust the desired TX power level. */ 2834 if (conf->power_level != 0) { 2835 if (conf->power_level != phy->power_level) { 2836 phy->power_level = conf->power_level; 2837 b43_phy_xmitpower(dev); 2838 } 2839 } 2840 2841 /* Antennas for RX and management frame TX. */ 2842 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx); 2843 b43_mgmtframe_txantenna(dev, antenna); 2844 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx); 2845 b43_set_rx_antenna(dev, antenna); 2846 2847 /* Update templates for AP mode. */ 2848 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2849 b43_set_beacon_int(dev, conf->beacon_int); 2850 2851 if (!!conf->radio_enabled != phy->radio_on) { 2852 if (conf->radio_enabled) { 2853 b43_radio_turn_on(dev); 2854 b43info(dev->wl, "Radio turned on by software\n"); 2855 if (!dev->radio_hw_enable) { 2856 b43info(dev->wl, "The hardware RF-kill button " 2857 "still turns the radio physically off. " 2858 "Press the button to turn it on.\n"); 2859 } 2860 } else { 2861 b43_radio_turn_off(dev, 0); 2862 b43info(dev->wl, "Radio turned off by software\n"); 2863 } 2864 } 2865 2866 spin_lock_irqsave(&wl->irq_lock, flags); 2867 b43_interrupt_enable(dev, savedirqs); 2868 mmiowb(); 2869 spin_unlock_irqrestore(&wl->irq_lock, flags); 2870 out_unlock_mutex: 2871 mutex_unlock(&wl->mutex); 2872 2873 return err; 2874} 2875 2876static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 2877 const u8 *local_addr, const u8 *addr, 2878 struct ieee80211_key_conf *key) 2879{ 2880 struct b43_wl *wl = hw_to_b43_wl(hw); 2881 struct b43_wldev *dev; 2882 unsigned long flags; 2883 u8 algorithm; 2884 u8 index; 2885 int err; 2886 DECLARE_MAC_BUF(mac); 2887 2888 if (modparam_nohwcrypt) 2889 return -ENOSPC; /* User disabled HW-crypto */ 2890 2891 mutex_lock(&wl->mutex); 2892 spin_lock_irqsave(&wl->irq_lock, flags); 2893 2894 dev = wl->current_dev; 2895 err = -ENODEV; 2896 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 2897 goto out_unlock; 2898 2899 err = -EINVAL; 2900 switch (key->alg) { 2901 case ALG_WEP: 2902 if (key->keylen == 5) 2903 algorithm = B43_SEC_ALGO_WEP40; 2904 else 2905 algorithm = B43_SEC_ALGO_WEP104; 2906 break; 2907 case ALG_TKIP: 2908 algorithm = B43_SEC_ALGO_TKIP; 2909 break; 2910 case ALG_CCMP: 2911 algorithm = B43_SEC_ALGO_AES; 2912 break; 2913 default: 2914 B43_WARN_ON(1); 2915 goto out_unlock; 2916 } 2917 index = (u8) (key->keyidx); 2918 if (index > 3) 2919 goto out_unlock; 2920 2921 switch (cmd) { 2922 case SET_KEY: 2923 if (algorithm == B43_SEC_ALGO_TKIP) { 2924 /* FIXME: No TKIP hardware encryption for now. */ 2925 err = -EOPNOTSUPP; 2926 goto out_unlock; 2927 } 2928 2929 if (is_broadcast_ether_addr(addr)) { 2930 /* addr is FF:FF:FF:FF:FF:FF for default keys */ 2931 err = b43_key_write(dev, index, algorithm, 2932 key->key, key->keylen, NULL, key); 2933 } else { 2934 /* 2935 * either pairwise key or address is 00:00:00:00:00:00 2936 * for transmit-only keys 2937 */ 2938 err = b43_key_write(dev, -1, algorithm, 2939 key->key, key->keylen, addr, key); 2940 } 2941 if (err) 2942 goto out_unlock; 2943 2944 if (algorithm == B43_SEC_ALGO_WEP40 || 2945 algorithm == B43_SEC_ALGO_WEP104) { 2946 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 2947 } else { 2948 b43_hf_write(dev, 2949 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 2950 } 2951 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 2952 break; 2953 case DISABLE_KEY: { 2954 err = b43_key_clear(dev, key->hw_key_idx); 2955 if (err) 2956 goto out_unlock; 2957 break; 2958 } 2959 default: 2960 B43_WARN_ON(1); 2961 } 2962out_unlock: 2963 spin_unlock_irqrestore(&wl->irq_lock, flags); 2964 mutex_unlock(&wl->mutex); 2965 if (!err) { 2966 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 2967 "mac: %s\n", 2968 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 2969 print_mac(mac, addr)); 2970 } 2971 return err; 2972} 2973 2974static void b43_op_configure_filter(struct ieee80211_hw *hw, 2975 unsigned int changed, unsigned int *fflags, 2976 int mc_count, struct dev_addr_list *mc_list) 2977{ 2978 struct b43_wl *wl = hw_to_b43_wl(hw); 2979 struct b43_wldev *dev = wl->current_dev; 2980 unsigned long flags; 2981 2982 if (!dev) { 2983 *fflags = 0; 2984 return; 2985 } 2986 2987 spin_lock_irqsave(&wl->irq_lock, flags); 2988 *fflags &= FIF_PROMISC_IN_BSS | 2989 FIF_ALLMULTI | 2990 FIF_FCSFAIL | 2991 FIF_PLCPFAIL | 2992 FIF_CONTROL | 2993 FIF_OTHER_BSS | 2994 FIF_BCN_PRBRESP_PROMISC; 2995 2996 changed &= FIF_PROMISC_IN_BSS | 2997 FIF_ALLMULTI | 2998 FIF_FCSFAIL | 2999 FIF_PLCPFAIL | 3000 FIF_CONTROL | 3001 FIF_OTHER_BSS | 3002 FIF_BCN_PRBRESP_PROMISC; 3003 3004 wl->filter_flags = *fflags; 3005 3006 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 3007 b43_adjust_opmode(dev); 3008 spin_unlock_irqrestore(&wl->irq_lock, flags); 3009} 3010 3011static int b43_op_config_interface(struct ieee80211_hw *hw, 3012 struct ieee80211_vif *vif, 3013 struct ieee80211_if_conf *conf) 3014{ 3015 struct b43_wl *wl = hw_to_b43_wl(hw); 3016 struct b43_wldev *dev = wl->current_dev; 3017 unsigned long flags; 3018 3019 if (!dev) 3020 return -ENODEV; 3021 mutex_lock(&wl->mutex); 3022 spin_lock_irqsave(&wl->irq_lock, flags); 3023 B43_WARN_ON(wl->vif != vif); 3024 if (conf->bssid) 3025 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3026 else 3027 memset(wl->bssid, 0, ETH_ALEN); 3028 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3029 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) { 3030 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); 3031 b43_set_ssid(dev, conf->ssid, conf->ssid_len); 3032 if (conf->beacon) 3033 b43_update_templates(wl, conf->beacon); 3034 } 3035 b43_write_mac_bssid_templates(dev); 3036 } 3037 spin_unlock_irqrestore(&wl->irq_lock, flags); 3038 mutex_unlock(&wl->mutex); 3039 3040 return 0; 3041} 3042 3043/* Locking: wl->mutex */ 3044static void b43_wireless_core_stop(struct b43_wldev *dev) 3045{ 3046 struct b43_wl *wl = dev->wl; 3047 unsigned long flags; 3048 3049 if (b43_status(dev) < B43_STAT_STARTED) 3050 return; 3051 3052 /* Disable and sync interrupts. We must do this before than 3053 * setting the status to INITIALIZED, as the interrupt handler 3054 * won't care about IRQs then. */ 3055 spin_lock_irqsave(&wl->irq_lock, flags); 3056 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 3057 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */ 3058 spin_unlock_irqrestore(&wl->irq_lock, flags); 3059 b43_synchronize_irq(dev); 3060 3061 b43_set_status(dev, B43_STAT_INITIALIZED); 3062 3063 mutex_unlock(&wl->mutex); 3064 /* Must unlock as it would otherwise deadlock. No races here. 3065 * Cancel the possibly running self-rearming periodic work. */ 3066 cancel_delayed_work_sync(&dev->periodic_work); 3067 mutex_lock(&wl->mutex); 3068 3069 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy. 3070 3071 b43_mac_suspend(dev); 3072 free_irq(dev->dev->irq, dev); 3073 b43dbg(wl, "Wireless interface stopped\n"); 3074} 3075 3076/* Locking: wl->mutex */ 3077static int b43_wireless_core_start(struct b43_wldev *dev) 3078{ 3079 int err; 3080 3081 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 3082 3083 drain_txstatus_queue(dev); 3084 err = request_irq(dev->dev->irq, b43_interrupt_handler, 3085 IRQF_SHARED, KBUILD_MODNAME, dev); 3086 if (err) { 3087 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); 3088 goto out; 3089 } 3090 3091 /* We are ready to run. */ 3092 b43_set_status(dev, B43_STAT_STARTED); 3093 3094 /* Start data flow (TX/RX). */ 3095 b43_mac_enable(dev); 3096 b43_interrupt_enable(dev, dev->irq_savedstate); 3097 ieee80211_start_queues(dev->wl->hw); 3098 3099 /* Start maintainance work */ 3100 b43_periodic_tasks_setup(dev); 3101 3102 b43dbg(dev->wl, "Wireless interface started\n"); 3103 out: 3104 return err; 3105} 3106 3107/* Get PHY and RADIO versioning numbers */ 3108static int b43_phy_versioning(struct b43_wldev *dev) 3109{ 3110 struct b43_phy *phy = &dev->phy; 3111 u32 tmp; 3112 u8 analog_type; 3113 u8 phy_type; 3114 u8 phy_rev; 3115 u16 radio_manuf; 3116 u16 radio_ver; 3117 u16 radio_rev; 3118 int unsupported = 0; 3119 3120 /* Get PHY versioning */ 3121 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 3122 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 3123 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 3124 phy_rev = (tmp & B43_PHYVER_VERSION); 3125 switch (phy_type) { 3126 case B43_PHYTYPE_A: 3127 if (phy_rev >= 4) 3128 unsupported = 1; 3129 break; 3130 case B43_PHYTYPE_B: 3131 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 3132 && phy_rev != 7) 3133 unsupported = 1; 3134 break; 3135 case B43_PHYTYPE_G: 3136 if (phy_rev > 9) 3137 unsupported = 1; 3138 break; 3139#ifdef CONFIG_B43_NPHY 3140 case B43_PHYTYPE_N: 3141 if (phy_rev > 1) 3142 unsupported = 1; 3143 break; 3144#endif 3145 default: 3146 unsupported = 1; 3147 }; 3148 if (unsupported) { 3149 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 3150 "(Analog %u, Type %u, Revision %u)\n", 3151 analog_type, phy_type, phy_rev); 3152 return -EOPNOTSUPP; 3153 } 3154 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 3155 analog_type, phy_type, phy_rev); 3156 3157 /* Get RADIO versioning */ 3158 if (dev->dev->bus->chip_id == 0x4317) { 3159 if (dev->dev->bus->chip_rev == 0) 3160 tmp = 0x3205017F; 3161 else if (dev->dev->bus->chip_rev == 1) 3162 tmp = 0x4205017F; 3163 else 3164 tmp = 0x5205017F; 3165 } else { 3166 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3167 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3168 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3169 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; 3170 } 3171 radio_manuf = (tmp & 0x00000FFF); 3172 radio_ver = (tmp & 0x0FFFF000) >> 12; 3173 radio_rev = (tmp & 0xF0000000) >> 28; 3174 if (radio_manuf != 0x17F /* Broadcom */) 3175 unsupported = 1; 3176 switch (phy_type) { 3177 case B43_PHYTYPE_A: 3178 if (radio_ver != 0x2060) 3179 unsupported = 1; 3180 if (radio_rev != 1) 3181 unsupported = 1; 3182 if (radio_manuf != 0x17F) 3183 unsupported = 1; 3184 break; 3185 case B43_PHYTYPE_B: 3186 if ((radio_ver & 0xFFF0) != 0x2050) 3187 unsupported = 1; 3188 break; 3189 case B43_PHYTYPE_G: 3190 if (radio_ver != 0x2050) 3191 unsupported = 1; 3192 break; 3193 case B43_PHYTYPE_N: 3194 if (radio_ver != 0x2055) 3195 unsupported = 1; 3196 break; 3197 default: 3198 B43_WARN_ON(1); 3199 } 3200 if (unsupported) { 3201 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 3202 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 3203 radio_manuf, radio_ver, radio_rev); 3204 return -EOPNOTSUPP; 3205 } 3206 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 3207 radio_manuf, radio_ver, radio_rev); 3208 3209 phy->radio_manuf = radio_manuf; 3210 phy->radio_ver = radio_ver; 3211 phy->radio_rev = radio_rev; 3212 3213 phy->analog = analog_type; 3214 phy->type = phy_type; 3215 phy->rev = phy_rev; 3216 3217 return 0; 3218} 3219 3220static void setup_struct_phy_for_init(struct b43_wldev *dev, 3221 struct b43_phy *phy) 3222{ 3223 struct b43_txpower_lo_control *lo; 3224 int i; 3225 3226 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); 3227 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); 3228 3229 phy->aci_enable = 0; 3230 phy->aci_wlan_automatic = 0; 3231 phy->aci_hw_rssi = 0; 3232 3233 phy->radio_off_context.valid = 0; 3234 3235 lo = phy->lo_control; 3236 if (lo) { 3237 memset(lo, 0, sizeof(*(phy->lo_control))); 3238 lo->rebuild = 1; 3239 lo->tx_bias = 0xFF; 3240 } 3241 phy->max_lb_gain = 0; 3242 phy->trsw_rx_gain = 0; 3243 phy->txpwr_offset = 0; 3244 3245 /* NRSSI */ 3246 phy->nrssislope = 0; 3247 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) 3248 phy->nrssi[i] = -1000; 3249 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) 3250 phy->nrssi_lt[i] = i; 3251 3252 phy->lofcal = 0xFFFF; 3253 phy->initval = 0xFFFF; 3254 3255 phy->interfmode = B43_INTERFMODE_NONE; 3256 phy->channel = 0xFF; 3257 3258 phy->hardware_power_control = !!modparam_hwpctl; 3259 3260 /* PHY TX errors counter. */ 3261 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3262 3263 /* OFDM-table address caching. */ 3264 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN; 3265} 3266 3267static void setup_struct_wldev_for_init(struct b43_wldev *dev) 3268{ 3269 dev->dfq_valid = 0; 3270 3271 /* Assume the radio is enabled. If it's not enabled, the state will 3272 * immediately get fixed on the first periodic work run. */ 3273 dev->radio_hw_enable = 1; 3274 3275 /* Stats */ 3276 memset(&dev->stats, 0, sizeof(dev->stats)); 3277 3278 setup_struct_phy_for_init(dev, &dev->phy); 3279 3280 /* IRQ related flags */ 3281 dev->irq_reason = 0; 3282 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 3283 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE; 3284 3285 dev->mac_suspended = 1; 3286 3287 /* Noise calculation context */ 3288 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 3289} 3290 3291static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 3292{ 3293 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 3294 u32 hf; 3295 3296 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 3297 return; 3298 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 3299 return; 3300 3301 hf = b43_hf_read(dev); 3302 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 3303 hf |= B43_HF_BTCOEXALT; 3304 else 3305 hf |= B43_HF_BTCOEX; 3306 b43_hf_write(dev, hf); 3307 //TODO 3308} 3309 3310static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 3311{ //TODO 3312} 3313 3314static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 3315{ 3316#ifdef CONFIG_SSB_DRIVER_PCICORE 3317 struct ssb_bus *bus = dev->dev->bus; 3318 u32 tmp; 3319 3320 if (bus->pcicore.dev && 3321 bus->pcicore.dev->id.coreid == SSB_DEV_PCI && 3322 bus->pcicore.dev->id.revision <= 5) { 3323 /* IMCFGLO timeouts workaround. */ 3324 tmp = ssb_read32(dev->dev, SSB_IMCFGLO); 3325 tmp &= ~SSB_IMCFGLO_REQTO; 3326 tmp &= ~SSB_IMCFGLO_SERTO; 3327 switch (bus->bustype) { 3328 case SSB_BUSTYPE_PCI: 3329 case SSB_BUSTYPE_PCMCIA: 3330 tmp |= 0x32; 3331 break; 3332 case SSB_BUSTYPE_SSB: 3333 tmp |= 0x53; 3334 break; 3335 } 3336 ssb_write32(dev->dev, SSB_IMCFGLO, tmp); 3337 } 3338#endif /* CONFIG_SSB_DRIVER_PCICORE */ 3339} 3340 3341/* Write the short and long frame retry limit values. */ 3342static void b43_set_retry_limits(struct b43_wldev *dev, 3343 unsigned int short_retry, 3344 unsigned int long_retry) 3345{ 3346 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3347 * the chip-internal counter. */ 3348 short_retry = min(short_retry, (unsigned int)0xF); 3349 long_retry = min(long_retry, (unsigned int)0xF); 3350 3351 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3352 short_retry); 3353 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3354 long_retry); 3355} 3356 3357/* Shutdown a wireless core */ 3358/* Locking: wl->mutex */ 3359static void b43_wireless_core_exit(struct b43_wldev *dev) 3360{ 3361 struct b43_phy *phy = &dev->phy; 3362 3363 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED); 3364 if (b43_status(dev) != B43_STAT_INITIALIZED) 3365 return; 3366 b43_set_status(dev, B43_STAT_UNINIT); 3367 3368 b43_leds_exit(dev); 3369 b43_rng_exit(dev->wl); 3370 b43_dma_free(dev); 3371 b43_chip_exit(dev); 3372 b43_radio_turn_off(dev, 1); 3373 b43_switch_analog(dev, 0); 3374 if (phy->dyn_tssi_tbl) 3375 kfree(phy->tssi2dbm); 3376 kfree(phy->lo_control); 3377 phy->lo_control = NULL; 3378 if (dev->wl->current_beacon) { 3379 dev_kfree_skb_any(dev->wl->current_beacon); 3380 dev->wl->current_beacon = NULL; 3381 } 3382 3383 ssb_device_disable(dev->dev, 0); 3384 ssb_bus_may_powerdown(dev->dev->bus); 3385} 3386 3387/* Initialize a wireless core */ 3388static int b43_wireless_core_init(struct b43_wldev *dev) 3389{ 3390 struct b43_wl *wl = dev->wl; 3391 struct ssb_bus *bus = dev->dev->bus; 3392 struct ssb_sprom *sprom = &bus->sprom; 3393 struct b43_phy *phy = &dev->phy; 3394 int err; 3395 u32 hf, tmp; 3396 3397 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3398 3399 err = ssb_bus_powerup(bus, 0); 3400 if (err) 3401 goto out; 3402 if (!ssb_device_is_enabled(dev->dev)) { 3403 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 3404 b43_wireless_core_reset(dev, tmp); 3405 } 3406 3407 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) { 3408 phy->lo_control = 3409 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL); 3410 if (!phy->lo_control) { 3411 err = -ENOMEM; 3412 goto err_busdown; 3413 } 3414 } 3415 setup_struct_wldev_for_init(dev); 3416 3417 err = b43_phy_init_tssi2dbm_table(dev); 3418 if (err) 3419 goto err_kfree_lo_control; 3420 3421 /* Enable IRQ routing to this device. */ 3422 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 3423 3424 b43_imcfglo_timeouts_workaround(dev); 3425 b43_bluetooth_coext_disable(dev); 3426 b43_phy_early_init(dev); 3427 err = b43_chip_init(dev); 3428 if (err) 3429 goto err_kfree_tssitbl; 3430 b43_shm_write16(dev, B43_SHM_SHARED, 3431 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 3432 hf = b43_hf_read(dev); 3433 if (phy->type == B43_PHYTYPE_G) { 3434 hf |= B43_HF_SYMW; 3435 if (phy->rev == 1) 3436 hf |= B43_HF_GDCW; 3437 if (sprom->boardflags_lo & B43_BFL_PACTRL) 3438 hf |= B43_HF_OFDMPABOOST; 3439 } else if (phy->type == B43_PHYTYPE_B) { 3440 hf |= B43_HF_SYMW; 3441 if (phy->rev >= 2 && phy->radio_ver == 0x2050) 3442 hf &= ~B43_HF_GDCW; 3443 } 3444 b43_hf_write(dev, hf); 3445 3446 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 3447 B43_DEFAULT_LONG_RETRY_LIMIT); 3448 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 3449 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 3450 3451 /* Disable sending probe responses from firmware. 3452 * Setting the MaxTime to one usec will always trigger 3453 * a timeout, so we never send any probe resp. 3454 * A timeout of zero is infinite. */ 3455 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 3456 3457 b43_rate_memory_init(dev); 3458 3459 /* Minimum Contention Window */ 3460 if (phy->type == B43_PHYTYPE_B) { 3461 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 3462 } else { 3463 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 3464 } 3465 /* Maximum Contention Window */ 3466 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 3467 3468 err = b43_dma_init(dev); 3469 if (err) 3470 goto err_chip_exit; 3471 b43_qos_init(dev); 3472 3473//FIXME 3474#if 1 3475 b43_write16(dev, 0x0612, 0x0050); 3476 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050); 3477 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4); 3478#endif 3479 3480 b43_bluetooth_coext_enable(dev); 3481 3482 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */ 3483 memset(wl->bssid, 0, ETH_ALEN); 3484 memset(wl->mac_addr, 0, ETH_ALEN); 3485 b43_upload_card_macaddress(dev); 3486 b43_security_init(dev); 3487 b43_rng_init(wl); 3488 3489 b43_set_status(dev, B43_STAT_INITIALIZED); 3490 3491 b43_leds_init(dev); 3492out: 3493 return err; 3494 3495 err_chip_exit: 3496 b43_chip_exit(dev); 3497 err_kfree_tssitbl: 3498 if (phy->dyn_tssi_tbl) 3499 kfree(phy->tssi2dbm); 3500 err_kfree_lo_control: 3501 kfree(phy->lo_control); 3502 phy->lo_control = NULL; 3503 err_busdown: 3504 ssb_bus_may_powerdown(bus); 3505 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3506 return err; 3507} 3508 3509static int b43_op_add_interface(struct ieee80211_hw *hw, 3510 struct ieee80211_if_init_conf *conf) 3511{ 3512 struct b43_wl *wl = hw_to_b43_wl(hw); 3513 struct b43_wldev *dev; 3514 unsigned long flags; 3515 int err = -EOPNOTSUPP; 3516 3517 /* TODO: allow WDS/AP devices to coexist */ 3518 3519 if (conf->type != IEEE80211_IF_TYPE_AP && 3520 conf->type != IEEE80211_IF_TYPE_STA && 3521 conf->type != IEEE80211_IF_TYPE_WDS && 3522 conf->type != IEEE80211_IF_TYPE_IBSS) 3523 return -EOPNOTSUPP; 3524 3525 mutex_lock(&wl->mutex); 3526 if (wl->operating) 3527 goto out_mutex_unlock; 3528 3529 b43dbg(wl, "Adding Interface type %d\n", conf->type); 3530 3531 dev = wl->current_dev; 3532 wl->operating = 1; 3533 wl->vif = conf->vif; 3534 wl->if_type = conf->type; 3535 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN); 3536 3537 spin_lock_irqsave(&wl->irq_lock, flags); 3538 b43_adjust_opmode(dev); 3539 b43_upload_card_macaddress(dev); 3540 spin_unlock_irqrestore(&wl->irq_lock, flags); 3541 3542 err = 0; 3543 out_mutex_unlock: 3544 mutex_unlock(&wl->mutex); 3545 3546 return err; 3547} 3548 3549static void b43_op_remove_interface(struct ieee80211_hw *hw, 3550 struct ieee80211_if_init_conf *conf) 3551{ 3552 struct b43_wl *wl = hw_to_b43_wl(hw); 3553 struct b43_wldev *dev = wl->current_dev; 3554 unsigned long flags; 3555 3556 b43dbg(wl, "Removing Interface type %d\n", conf->type); 3557 3558 mutex_lock(&wl->mutex); 3559 3560 B43_WARN_ON(!wl->operating); 3561 B43_WARN_ON(wl->vif != conf->vif); 3562 wl->vif = NULL; 3563 3564 wl->operating = 0; 3565 3566 spin_lock_irqsave(&wl->irq_lock, flags); 3567 b43_adjust_opmode(dev); 3568 memset(wl->mac_addr, 0, ETH_ALEN); 3569 b43_upload_card_macaddress(dev); 3570 spin_unlock_irqrestore(&wl->irq_lock, flags); 3571 3572 mutex_unlock(&wl->mutex); 3573} 3574 3575static int b43_op_start(struct ieee80211_hw *hw) 3576{ 3577 struct b43_wl *wl = hw_to_b43_wl(hw); 3578 struct b43_wldev *dev = wl->current_dev; 3579 int did_init = 0; 3580 int err = 0; 3581 3582 /* First register RFkill. 3583 * LEDs that are registered later depend on it. */ 3584 b43_rfkill_init(dev); 3585 3586 mutex_lock(&wl->mutex); 3587 3588 if (b43_status(dev) < B43_STAT_INITIALIZED) { 3589 err = b43_wireless_core_init(dev); 3590 if (err) 3591 goto out_mutex_unlock; 3592 did_init = 1; 3593 } 3594 3595 if (b43_status(dev) < B43_STAT_STARTED) { 3596 err = b43_wireless_core_start(dev); 3597 if (err) { 3598 if (did_init) 3599 b43_wireless_core_exit(dev); 3600 goto out_mutex_unlock; 3601 } 3602 } 3603 3604 out_mutex_unlock: 3605 mutex_unlock(&wl->mutex); 3606 3607 return err; 3608} 3609 3610static void b43_op_stop(struct ieee80211_hw *hw) 3611{ 3612 struct b43_wl *wl = hw_to_b43_wl(hw); 3613 struct b43_wldev *dev = wl->current_dev; 3614 3615 b43_rfkill_exit(dev); 3616 3617 mutex_lock(&wl->mutex); 3618 if (b43_status(dev) >= B43_STAT_STARTED) 3619 b43_wireless_core_stop(dev); 3620 b43_wireless_core_exit(dev); 3621 mutex_unlock(&wl->mutex); 3622} 3623 3624static int b43_op_set_retry_limit(struct ieee80211_hw *hw, 3625 u32 short_retry_limit, u32 long_retry_limit) 3626{ 3627 struct b43_wl *wl = hw_to_b43_wl(hw); 3628 struct b43_wldev *dev; 3629 int err = 0; 3630 3631 mutex_lock(&wl->mutex); 3632 dev = wl->current_dev; 3633 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) { 3634 err = -ENODEV; 3635 goto out_unlock; 3636 } 3637 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit); 3638out_unlock: 3639 mutex_unlock(&wl->mutex); 3640 3641 return err; 3642} 3643 3644static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set) 3645{ 3646 struct b43_wl *wl = hw_to_b43_wl(hw); 3647 struct sk_buff *beacon; 3648 unsigned long flags; 3649 3650 /* We could modify the existing beacon and set the aid bit in 3651 * the TIM field, but that would probably require resizing and 3652 * moving of data within the beacon template. 3653 * Simply request a new beacon and let mac80211 do the hard work. */ 3654 beacon = ieee80211_beacon_get(hw, wl->vif, NULL); 3655 if (unlikely(!beacon)) 3656 return -ENOMEM; 3657 spin_lock_irqsave(&wl->irq_lock, flags); 3658 b43_update_templates(wl, beacon); 3659 spin_unlock_irqrestore(&wl->irq_lock, flags); 3660 3661 return 0; 3662} 3663 3664static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw, 3665 struct sk_buff *beacon, 3666 struct ieee80211_tx_control *ctl) 3667{ 3668 struct b43_wl *wl = hw_to_b43_wl(hw); 3669 unsigned long flags; 3670 3671 spin_lock_irqsave(&wl->irq_lock, flags); 3672 b43_update_templates(wl, beacon); 3673 spin_unlock_irqrestore(&wl->irq_lock, flags); 3674 3675 return 0; 3676} 3677 3678static const struct ieee80211_ops b43_hw_ops = { 3679 .tx = b43_op_tx, 3680 .conf_tx = b43_op_conf_tx, 3681 .add_interface = b43_op_add_interface, 3682 .remove_interface = b43_op_remove_interface, 3683 .config = b43_op_config, 3684 .config_interface = b43_op_config_interface, 3685 .configure_filter = b43_op_configure_filter, 3686 .set_key = b43_op_set_key, 3687 .get_stats = b43_op_get_stats, 3688 .get_tx_stats = b43_op_get_tx_stats, 3689 .start = b43_op_start, 3690 .stop = b43_op_stop, 3691 .set_retry_limit = b43_op_set_retry_limit, 3692 .set_tim = b43_op_beacon_set_tim, 3693 .beacon_update = b43_op_ibss_beacon_update, 3694}; 3695 3696/* Hard-reset the chip. Do not call this directly. 3697 * Use b43_controller_restart() 3698 */ 3699static void b43_chip_reset(struct work_struct *work) 3700{ 3701 struct b43_wldev *dev = 3702 container_of(work, struct b43_wldev, restart_work); 3703 struct b43_wl *wl = dev->wl; 3704 int err = 0; 3705 int prev_status; 3706 3707 mutex_lock(&wl->mutex); 3708 3709 prev_status = b43_status(dev); 3710 /* Bring the device down... */ 3711 if (prev_status >= B43_STAT_STARTED) 3712 b43_wireless_core_stop(dev); 3713 if (prev_status >= B43_STAT_INITIALIZED) 3714 b43_wireless_core_exit(dev); 3715 3716 /* ...and up again. */ 3717 if (prev_status >= B43_STAT_INITIALIZED) { 3718 err = b43_wireless_core_init(dev); 3719 if (err) 3720 goto out; 3721 } 3722 if (prev_status >= B43_STAT_STARTED) { 3723 err = b43_wireless_core_start(dev); 3724 if (err) { 3725 b43_wireless_core_exit(dev); 3726 goto out; 3727 } 3728 } 3729 out: 3730 mutex_unlock(&wl->mutex); 3731 if (err) 3732 b43err(wl, "Controller restart FAILED\n"); 3733 else 3734 b43info(wl, "Controller restarted\n"); 3735} 3736 3737static int b43_setup_modes(struct b43_wldev *dev, 3738 bool have_2ghz_phy, bool have_5ghz_phy) 3739{ 3740 struct ieee80211_hw *hw = dev->wl->hw; 3741 struct ieee80211_hw_mode *mode; 3742 struct b43_phy *phy = &dev->phy; 3743 int err; 3744 3745 /* XXX: This function will go away soon, when mac80211 3746 * band stuff is rewritten. So this is just a hack. 3747 * For now we always claim GPHY mode, as there is no 3748 * support for NPHY and APHY in the device, yet. 3749 * This assumption is OK, as any B, N or A PHY will already 3750 * have died a horrible sanity check death earlier. */ 3751 3752 mode = &phy->hwmodes[0]; 3753 mode->mode = MODE_IEEE80211G; 3754 mode->num_channels = b43_2ghz_chantable_size; 3755 mode->channels = b43_2ghz_chantable; 3756 mode->num_rates = b43_g_ratetable_size; 3757 mode->rates = b43_g_ratetable; 3758 err = ieee80211_register_hwmode(hw, mode); 3759 if (err) 3760 return err; 3761 phy->possible_phymodes |= B43_PHYMODE_G; 3762 3763 return 0; 3764} 3765 3766static void b43_wireless_core_detach(struct b43_wldev *dev) 3767{ 3768 /* We release firmware that late to not be required to re-request 3769 * is all the time when we reinit the core. */ 3770 b43_release_firmware(dev); 3771} 3772 3773static int b43_wireless_core_attach(struct b43_wldev *dev) 3774{ 3775 struct b43_wl *wl = dev->wl; 3776 struct ssb_bus *bus = dev->dev->bus; 3777 struct pci_dev *pdev = bus->host_pci; 3778 int err; 3779 bool have_2ghz_phy = 0, have_5ghz_phy = 0; 3780 u32 tmp; 3781 3782 /* Do NOT do any device initialization here. 3783 * Do it in wireless_core_init() instead. 3784 * This function is for gathering basic information about the HW, only. 3785 * Also some structs may be set up here. But most likely you want to have 3786 * that in core_init(), too. 3787 */ 3788 3789 err = ssb_bus_powerup(bus, 0); 3790 if (err) { 3791 b43err(wl, "Bus powerup failed\n"); 3792 goto out; 3793 } 3794 /* Get the PHY type. */ 3795 if (dev->dev->id.revision >= 5) { 3796 u32 tmshigh; 3797 3798 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 3799 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY); 3800 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY); 3801 } else 3802 B43_WARN_ON(1); 3803 3804 dev->phy.gmode = have_2ghz_phy; 3805 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3806 b43_wireless_core_reset(dev, tmp); 3807 3808 err = b43_phy_versioning(dev); 3809 if (err) 3810 goto err_powerdown; 3811 /* Check if this device supports multiband. */ 3812 if (!pdev || 3813 (pdev->device != 0x4312 && 3814 pdev->device != 0x4319 && pdev->device != 0x4324)) { 3815 /* No multiband support. */ 3816 have_2ghz_phy = 0; 3817 have_5ghz_phy = 0; 3818 switch (dev->phy.type) { 3819 case B43_PHYTYPE_A: 3820 have_5ghz_phy = 1; 3821 break; 3822 case B43_PHYTYPE_G: 3823 case B43_PHYTYPE_N: 3824 have_2ghz_phy = 1; 3825 break; 3826 default: 3827 B43_WARN_ON(1); 3828 } 3829 } 3830 if (dev->phy.type == B43_PHYTYPE_A) { 3831 /* FIXME */ 3832 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 3833 err = -EOPNOTSUPP; 3834 goto err_powerdown; 3835 } 3836 dev->phy.gmode = have_2ghz_phy; 3837 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3838 b43_wireless_core_reset(dev, tmp); 3839 3840 err = b43_validate_chipaccess(dev); 3841 if (err) 3842 goto err_powerdown; 3843 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy); 3844 if (err) 3845 goto err_powerdown; 3846 3847 /* Now set some default "current_dev" */ 3848 if (!wl->current_dev) 3849 wl->current_dev = dev; 3850 INIT_WORK(&dev->restart_work, b43_chip_reset); 3851 3852 b43_radio_turn_off(dev, 1); 3853 b43_switch_analog(dev, 0); 3854 ssb_device_disable(dev->dev, 0); 3855 ssb_bus_may_powerdown(bus); 3856 3857out: 3858 return err; 3859 3860err_powerdown: 3861 ssb_bus_may_powerdown(bus); 3862 return err; 3863} 3864 3865static void b43_one_core_detach(struct ssb_device *dev) 3866{ 3867 struct b43_wldev *wldev; 3868 struct b43_wl *wl; 3869 3870 wldev = ssb_get_drvdata(dev); 3871 wl = wldev->wl; 3872 cancel_work_sync(&wldev->restart_work); 3873 b43_debugfs_remove_device(wldev); 3874 b43_wireless_core_detach(wldev); 3875 list_del(&wldev->list); 3876 wl->nr_devs--; 3877 ssb_set_drvdata(dev, NULL); 3878 kfree(wldev); 3879} 3880 3881static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 3882{ 3883 struct b43_wldev *wldev; 3884 struct pci_dev *pdev; 3885 int err = -ENOMEM; 3886 3887 if (!list_empty(&wl->devlist)) { 3888 /* We are not the first core on this chip. */ 3889 pdev = dev->bus->host_pci; 3890 /* Only special chips support more than one wireless 3891 * core, although some of the other chips have more than 3892 * one wireless core as well. Check for this and 3893 * bail out early. 3894 */ 3895 if (!pdev || 3896 ((pdev->device != 0x4321) && 3897 (pdev->device != 0x4313) && (pdev->device != 0x431A))) { 3898 b43dbg(wl, "Ignoring unconnected 802.11 core\n"); 3899 return -ENODEV; 3900 } 3901 } 3902 3903 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 3904 if (!wldev) 3905 goto out; 3906 3907 wldev->dev = dev; 3908 wldev->wl = wl; 3909 b43_set_status(wldev, B43_STAT_UNINIT); 3910 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 3911 tasklet_init(&wldev->isr_tasklet, 3912 (void (*)(unsigned long))b43_interrupt_tasklet, 3913 (unsigned long)wldev); 3914 INIT_LIST_HEAD(&wldev->list); 3915 3916 err = b43_wireless_core_attach(wldev); 3917 if (err) 3918 goto err_kfree_wldev; 3919 3920 list_add(&wldev->list, &wl->devlist); 3921 wl->nr_devs++; 3922 ssb_set_drvdata(dev, wldev); 3923 b43_debugfs_add_device(wldev); 3924 3925 out: 3926 return err; 3927 3928 err_kfree_wldev: 3929 kfree(wldev); 3930 return err; 3931} 3932 3933static void b43_sprom_fixup(struct ssb_bus *bus) 3934{ 3935 /* boardflags workarounds */ 3936 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 3937 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 3938 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 3939 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3940 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 3941 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 3942} 3943 3944static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 3945{ 3946 struct ieee80211_hw *hw = wl->hw; 3947 3948 ssb_set_devtypedata(dev, NULL); 3949 ieee80211_free_hw(hw); 3950} 3951 3952static int b43_wireless_init(struct ssb_device *dev) 3953{ 3954 struct ssb_sprom *sprom = &dev->bus->sprom; 3955 struct ieee80211_hw *hw; 3956 struct b43_wl *wl; 3957 int err = -ENOMEM; 3958 3959 b43_sprom_fixup(dev->bus); 3960 3961 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 3962 if (!hw) { 3963 b43err(NULL, "Could not allocate ieee80211 device\n"); 3964 goto out; 3965 } 3966 3967 /* fill hw info */ 3968 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 3969 IEEE80211_HW_RX_INCLUDES_FCS; 3970 hw->max_signal = 100; 3971 hw->max_rssi = -110; 3972 hw->max_noise = -110; 3973 hw->queues = 1; /* FIXME: hardware has more queues */ 3974 SET_IEEE80211_DEV(hw, dev->dev); 3975 if (is_valid_ether_addr(sprom->et1mac)) 3976 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 3977 else 3978 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 3979 3980 /* Get and initialize struct b43_wl */ 3981 wl = hw_to_b43_wl(hw); 3982 memset(wl, 0, sizeof(*wl)); 3983 wl->hw = hw; 3984 spin_lock_init(&wl->irq_lock); 3985 spin_lock_init(&wl->leds_lock); 3986 spin_lock_init(&wl->shm_lock); 3987 mutex_init(&wl->mutex); 3988 INIT_LIST_HEAD(&wl->devlist); 3989 3990 ssb_set_devtypedata(dev, wl); 3991 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id); 3992 err = 0; 3993 out: 3994 return err; 3995} 3996 3997static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id) 3998{ 3999 struct b43_wl *wl; 4000 int err; 4001 int first = 0; 4002 4003 wl = ssb_get_devtypedata(dev); 4004 if (!wl) { 4005 /* Probing the first core. Must setup common struct b43_wl */ 4006 first = 1; 4007 err = b43_wireless_init(dev); 4008 if (err) 4009 goto out; 4010 wl = ssb_get_devtypedata(dev); 4011 B43_WARN_ON(!wl); 4012 } 4013 err = b43_one_core_attach(dev, wl); 4014 if (err) 4015 goto err_wireless_exit; 4016 4017 if (first) { 4018 err = ieee80211_register_hw(wl->hw); 4019 if (err) 4020 goto err_one_core_detach; 4021 } 4022 4023 out: 4024 return err; 4025 4026 err_one_core_detach: 4027 b43_one_core_detach(dev); 4028 err_wireless_exit: 4029 if (first) 4030 b43_wireless_exit(dev, wl); 4031 return err; 4032} 4033 4034static void b43_remove(struct ssb_device *dev) 4035{ 4036 struct b43_wl *wl = ssb_get_devtypedata(dev); 4037 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4038 4039 B43_WARN_ON(!wl); 4040 if (wl->current_dev == wldev) 4041 ieee80211_unregister_hw(wl->hw); 4042 4043 b43_one_core_detach(dev); 4044 4045 if (list_empty(&wl->devlist)) { 4046 /* Last core on the chip unregistered. 4047 * We can destroy common struct b43_wl. 4048 */ 4049 b43_wireless_exit(dev, wl); 4050 } 4051} 4052 4053/* Perform a hardware reset. This can be called from any context. */ 4054void b43_controller_restart(struct b43_wldev *dev, const char *reason) 4055{ 4056 /* Must avoid requeueing, if we are in shutdown. */ 4057 if (b43_status(dev) < B43_STAT_INITIALIZED) 4058 return; 4059 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 4060 queue_work(dev->wl->hw->workqueue, &dev->restart_work); 4061} 4062 4063#ifdef CONFIG_PM 4064 4065static int b43_suspend(struct ssb_device *dev, pm_message_t state) 4066{ 4067 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4068 struct b43_wl *wl = wldev->wl; 4069 4070 b43dbg(wl, "Suspending...\n"); 4071 4072 mutex_lock(&wl->mutex); 4073 wldev->suspend_init_status = b43_status(wldev); 4074 if (wldev->suspend_init_status >= B43_STAT_STARTED) 4075 b43_wireless_core_stop(wldev); 4076 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) 4077 b43_wireless_core_exit(wldev); 4078 mutex_unlock(&wl->mutex); 4079 4080 b43dbg(wl, "Device suspended.\n"); 4081 4082 return 0; 4083} 4084 4085static int b43_resume(struct ssb_device *dev) 4086{ 4087 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4088 struct b43_wl *wl = wldev->wl; 4089 int err = 0; 4090 4091 b43dbg(wl, "Resuming...\n"); 4092 4093 mutex_lock(&wl->mutex); 4094 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) { 4095 err = b43_wireless_core_init(wldev); 4096 if (err) { 4097 b43err(wl, "Resume failed at core init\n"); 4098 goto out; 4099 } 4100 } 4101 if (wldev->suspend_init_status >= B43_STAT_STARTED) { 4102 err = b43_wireless_core_start(wldev); 4103 if (err) { 4104 b43_wireless_core_exit(wldev); 4105 b43err(wl, "Resume failed at core start\n"); 4106 goto out; 4107 } 4108 } 4109 mutex_unlock(&wl->mutex); 4110 4111 b43dbg(wl, "Device resumed.\n"); 4112 out: 4113 return err; 4114} 4115 4116#else /* CONFIG_PM */ 4117# define b43_suspend NULL 4118# define b43_resume NULL 4119#endif /* CONFIG_PM */ 4120 4121static struct ssb_driver b43_ssb_driver = { 4122 .name = KBUILD_MODNAME, 4123 .id_table = b43_ssb_tbl, 4124 .probe = b43_probe, 4125 .remove = b43_remove, 4126 .suspend = b43_suspend, 4127 .resume = b43_resume, 4128}; 4129 4130static int __init b43_init(void) 4131{ 4132 int err; 4133 4134 b43_debugfs_init(); 4135 err = b43_pcmcia_init(); 4136 if (err) 4137 goto err_dfs_exit; 4138 err = ssb_driver_register(&b43_ssb_driver); 4139 if (err) 4140 goto err_pcmcia_exit; 4141 4142 return err; 4143 4144err_pcmcia_exit: 4145 b43_pcmcia_exit(); 4146err_dfs_exit: 4147 b43_debugfs_exit(); 4148 return err; 4149} 4150 4151static void __exit b43_exit(void) 4152{ 4153 ssb_driver_unregister(&b43_ssb_driver); 4154 b43_pcmcia_exit(); 4155 b43_debugfs_exit(); 4156} 4157 4158module_init(b43_init) 4159module_exit(b43_exit) 4160