main.c revision 61cb5dd6d1c81fbb5629f60db4e2a7faa7124b7a
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 Some parts of the code in this file are derived from the ipw2200 12 driver Copyright(c) 2003 - 2004 Intel Corporation. 13 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; either version 2 of the License, or 17 (at your option) any later version. 18 19 This program is distributed in the hope that it will be useful, 20 but WITHOUT ANY WARRANTY; without even the implied warranty of 21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 GNU General Public License for more details. 23 24 You should have received a copy of the GNU General Public License 25 along with this program; see the file COPYING. If not, write to 26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 27 Boston, MA 02110-1301, USA. 28 29*/ 30 31#include <linux/delay.h> 32#include <linux/init.h> 33#include <linux/moduleparam.h> 34#include <linux/if_arp.h> 35#include <linux/etherdevice.h> 36#include <linux/version.h> 37#include <linux/firmware.h> 38#include <linux/wireless.h> 39#include <linux/workqueue.h> 40#include <linux/skbuff.h> 41#include <linux/dma-mapping.h> 42#include <asm/unaligned.h> 43 44#include "b43.h" 45#include "main.h" 46#include "debugfs.h" 47#include "phy.h" 48#include "dma.h" 49#include "sysfs.h" 50#include "xmit.h" 51#include "lo.h" 52#include "pcmcia.h" 53 54MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 55MODULE_AUTHOR("Martin Langer"); 56MODULE_AUTHOR("Stefano Brivio"); 57MODULE_AUTHOR("Michael Buesch"); 58MODULE_LICENSE("GPL"); 59 60 61static int modparam_bad_frames_preempt; 62module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 63MODULE_PARM_DESC(bad_frames_preempt, 64 "enable(1) / disable(0) Bad Frames Preemption"); 65 66static char modparam_fwpostfix[16]; 67module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 68MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 69 70static int modparam_hwpctl; 71module_param_named(hwpctl, modparam_hwpctl, int, 0444); 72MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 73 74static int modparam_nohwcrypt; 75module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 76MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 77 78static const struct ssb_device_id b43_ssb_tbl[] = { 79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 86 SSB_DEVTABLE_END 87}; 88 89MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 90 91/* Channel and ratetables are shared for all devices. 92 * They can't be const, because ieee80211 puts some precalculated 93 * data in there. This data is the same for all devices, so we don't 94 * get concurrency issues */ 95#define RATETAB_ENT(_rateid, _flags) \ 96 { \ 97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \ 98 .val = (_rateid), \ 99 .val2 = (_rateid), \ 100 .flags = (_flags), \ 101 } 102static struct ieee80211_rate __b43_ratetable[] = { 103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK), 104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2), 105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2), 106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2), 107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM), 108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM), 109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM), 110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM), 111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM), 112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM), 113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM), 114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM), 115}; 116 117#define b43_a_ratetable (__b43_ratetable + 4) 118#define b43_a_ratetable_size 8 119#define b43_b_ratetable (__b43_ratetable + 0) 120#define b43_b_ratetable_size 4 121#define b43_g_ratetable (__b43_ratetable + 0) 122#define b43_g_ratetable_size 12 123 124#define CHANTAB_ENT(_chanid, _freq) \ 125 { \ 126 .chan = (_chanid), \ 127 .freq = (_freq), \ 128 .val = (_chanid), \ 129 .flag = IEEE80211_CHAN_W_SCAN | \ 130 IEEE80211_CHAN_W_ACTIVE_SCAN | \ 131 IEEE80211_CHAN_W_IBSS, \ 132 .power_level = 0xFF, \ 133 .antenna_max = 0xFF, \ 134 } 135static struct ieee80211_channel b43_2ghz_chantable[] = { 136 CHANTAB_ENT(1, 2412), 137 CHANTAB_ENT(2, 2417), 138 CHANTAB_ENT(3, 2422), 139 CHANTAB_ENT(4, 2427), 140 CHANTAB_ENT(5, 2432), 141 CHANTAB_ENT(6, 2437), 142 CHANTAB_ENT(7, 2442), 143 CHANTAB_ENT(8, 2447), 144 CHANTAB_ENT(9, 2452), 145 CHANTAB_ENT(10, 2457), 146 CHANTAB_ENT(11, 2462), 147 CHANTAB_ENT(12, 2467), 148 CHANTAB_ENT(13, 2472), 149 CHANTAB_ENT(14, 2484), 150}; 151#define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable) 152 153#if 0 154static struct ieee80211_channel b43_5ghz_chantable[] = { 155 CHANTAB_ENT(36, 5180), 156 CHANTAB_ENT(40, 5200), 157 CHANTAB_ENT(44, 5220), 158 CHANTAB_ENT(48, 5240), 159 CHANTAB_ENT(52, 5260), 160 CHANTAB_ENT(56, 5280), 161 CHANTAB_ENT(60, 5300), 162 CHANTAB_ENT(64, 5320), 163 CHANTAB_ENT(149, 5745), 164 CHANTAB_ENT(153, 5765), 165 CHANTAB_ENT(157, 5785), 166 CHANTAB_ENT(161, 5805), 167 CHANTAB_ENT(165, 5825), 168}; 169#define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable) 170#endif 171 172static void b43_wireless_core_exit(struct b43_wldev *dev); 173static int b43_wireless_core_init(struct b43_wldev *dev); 174static void b43_wireless_core_stop(struct b43_wldev *dev); 175static int b43_wireless_core_start(struct b43_wldev *dev); 176 177static int b43_ratelimit(struct b43_wl *wl) 178{ 179 if (!wl || !wl->current_dev) 180 return 1; 181 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 182 return 1; 183 /* We are up and running. 184 * Ratelimit the messages to avoid DoS over the net. */ 185 return net_ratelimit(); 186} 187 188void b43info(struct b43_wl *wl, const char *fmt, ...) 189{ 190 va_list args; 191 192 if (!b43_ratelimit(wl)) 193 return; 194 va_start(args, fmt); 195 printk(KERN_INFO "b43-%s: ", 196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 197 vprintk(fmt, args); 198 va_end(args); 199} 200 201void b43err(struct b43_wl *wl, const char *fmt, ...) 202{ 203 va_list args; 204 205 if (!b43_ratelimit(wl)) 206 return; 207 va_start(args, fmt); 208 printk(KERN_ERR "b43-%s ERROR: ", 209 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 210 vprintk(fmt, args); 211 va_end(args); 212} 213 214void b43warn(struct b43_wl *wl, const char *fmt, ...) 215{ 216 va_list args; 217 218 if (!b43_ratelimit(wl)) 219 return; 220 va_start(args, fmt); 221 printk(KERN_WARNING "b43-%s warning: ", 222 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 223 vprintk(fmt, args); 224 va_end(args); 225} 226 227#if B43_DEBUG 228void b43dbg(struct b43_wl *wl, const char *fmt, ...) 229{ 230 va_list args; 231 232 va_start(args, fmt); 233 printk(KERN_DEBUG "b43-%s debug: ", 234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 235 vprintk(fmt, args); 236 va_end(args); 237} 238#endif /* DEBUG */ 239 240static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 241{ 242 u32 macctl; 243 244 B43_WARN_ON(offset % 4 != 0); 245 246 macctl = b43_read32(dev, B43_MMIO_MACCTL); 247 if (macctl & B43_MACCTL_BE) 248 val = swab32(val); 249 250 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 251 mmiowb(); 252 b43_write32(dev, B43_MMIO_RAM_DATA, val); 253} 254 255static inline void b43_shm_control_word(struct b43_wldev *dev, 256 u16 routing, u16 offset) 257{ 258 u32 control; 259 260 /* "offset" is the WORD offset. */ 261 control = routing; 262 control <<= 16; 263 control |= offset; 264 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 265} 266 267u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 268{ 269 struct b43_wl *wl = dev->wl; 270 unsigned long flags; 271 u32 ret; 272 273 spin_lock_irqsave(&wl->shm_lock, flags); 274 if (routing == B43_SHM_SHARED) { 275 B43_WARN_ON(offset & 0x0001); 276 if (offset & 0x0003) { 277 /* Unaligned access */ 278 b43_shm_control_word(dev, routing, offset >> 2); 279 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 280 ret <<= 16; 281 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 282 ret |= b43_read16(dev, B43_MMIO_SHM_DATA); 283 284 goto out; 285 } 286 offset >>= 2; 287 } 288 b43_shm_control_word(dev, routing, offset); 289 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 290out: 291 spin_unlock_irqrestore(&wl->shm_lock, flags); 292 293 return ret; 294} 295 296u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset) 297{ 298 struct b43_wl *wl = dev->wl; 299 unsigned long flags; 300 u16 ret; 301 302 spin_lock_irqsave(&wl->shm_lock, flags); 303 if (routing == B43_SHM_SHARED) { 304 B43_WARN_ON(offset & 0x0001); 305 if (offset & 0x0003) { 306 /* Unaligned access */ 307 b43_shm_control_word(dev, routing, offset >> 2); 308 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 309 310 goto out; 311 } 312 offset >>= 2; 313 } 314 b43_shm_control_word(dev, routing, offset); 315 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 316out: 317 spin_unlock_irqrestore(&wl->shm_lock, flags); 318 319 return ret; 320} 321 322void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 323{ 324 struct b43_wl *wl = dev->wl; 325 unsigned long flags; 326 327 spin_lock_irqsave(&wl->shm_lock, flags); 328 if (routing == B43_SHM_SHARED) { 329 B43_WARN_ON(offset & 0x0001); 330 if (offset & 0x0003) { 331 /* Unaligned access */ 332 b43_shm_control_word(dev, routing, offset >> 2); 333 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 334 (value >> 16) & 0xffff); 335 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 336 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff); 337 goto out; 338 } 339 offset >>= 2; 340 } 341 b43_shm_control_word(dev, routing, offset); 342 b43_write32(dev, B43_MMIO_SHM_DATA, value); 343out: 344 spin_unlock_irqrestore(&wl->shm_lock, flags); 345} 346 347void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 348{ 349 struct b43_wl *wl = dev->wl; 350 unsigned long flags; 351 352 spin_lock_irqsave(&wl->shm_lock, flags); 353 if (routing == B43_SHM_SHARED) { 354 B43_WARN_ON(offset & 0x0001); 355 if (offset & 0x0003) { 356 /* Unaligned access */ 357 b43_shm_control_word(dev, routing, offset >> 2); 358 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 359 goto out; 360 } 361 offset >>= 2; 362 } 363 b43_shm_control_word(dev, routing, offset); 364 b43_write16(dev, B43_MMIO_SHM_DATA, value); 365out: 366 spin_unlock_irqrestore(&wl->shm_lock, flags); 367} 368 369/* Read HostFlags */ 370u32 b43_hf_read(struct b43_wldev * dev) 371{ 372 u32 ret; 373 374 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 375 ret <<= 16; 376 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 377 378 return ret; 379} 380 381/* Write HostFlags */ 382void b43_hf_write(struct b43_wldev *dev, u32 value) 383{ 384 b43_shm_write16(dev, B43_SHM_SHARED, 385 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF)); 386 b43_shm_write16(dev, B43_SHM_SHARED, 387 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16)); 388} 389 390void b43_tsf_read(struct b43_wldev *dev, u64 * tsf) 391{ 392 /* We need to be careful. As we read the TSF from multiple 393 * registers, we should take care of register overflows. 394 * In theory, the whole tsf read process should be atomic. 395 * We try to be atomic here, by restaring the read process, 396 * if any of the high registers changed (overflew). 397 */ 398 if (dev->dev->id.revision >= 3) { 399 u32 low, high, high2; 400 401 do { 402 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 403 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 404 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 405 } while (unlikely(high != high2)); 406 407 *tsf = high; 408 *tsf <<= 32; 409 *tsf |= low; 410 } else { 411 u64 tmp; 412 u16 v0, v1, v2, v3; 413 u16 test1, test2, test3; 414 415 do { 416 v3 = b43_read16(dev, B43_MMIO_TSF_3); 417 v2 = b43_read16(dev, B43_MMIO_TSF_2); 418 v1 = b43_read16(dev, B43_MMIO_TSF_1); 419 v0 = b43_read16(dev, B43_MMIO_TSF_0); 420 421 test3 = b43_read16(dev, B43_MMIO_TSF_3); 422 test2 = b43_read16(dev, B43_MMIO_TSF_2); 423 test1 = b43_read16(dev, B43_MMIO_TSF_1); 424 } while (v3 != test3 || v2 != test2 || v1 != test1); 425 426 *tsf = v3; 427 *tsf <<= 48; 428 tmp = v2; 429 tmp <<= 32; 430 *tsf |= tmp; 431 tmp = v1; 432 tmp <<= 16; 433 *tsf |= tmp; 434 *tsf |= v0; 435 } 436} 437 438static void b43_time_lock(struct b43_wldev *dev) 439{ 440 u32 macctl; 441 442 macctl = b43_read32(dev, B43_MMIO_MACCTL); 443 macctl |= B43_MACCTL_TBTTHOLD; 444 b43_write32(dev, B43_MMIO_MACCTL, macctl); 445 /* Commit the write */ 446 b43_read32(dev, B43_MMIO_MACCTL); 447} 448 449static void b43_time_unlock(struct b43_wldev *dev) 450{ 451 u32 macctl; 452 453 macctl = b43_read32(dev, B43_MMIO_MACCTL); 454 macctl &= ~B43_MACCTL_TBTTHOLD; 455 b43_write32(dev, B43_MMIO_MACCTL, macctl); 456 /* Commit the write */ 457 b43_read32(dev, B43_MMIO_MACCTL); 458} 459 460static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 461{ 462 /* Be careful with the in-progress timer. 463 * First zero out the low register, so we have a full 464 * register-overflow duration to complete the operation. 465 */ 466 if (dev->dev->id.revision >= 3) { 467 u32 lo = (tsf & 0x00000000FFFFFFFFULL); 468 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32; 469 470 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0); 471 mmiowb(); 472 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi); 473 mmiowb(); 474 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo); 475 } else { 476 u16 v0 = (tsf & 0x000000000000FFFFULL); 477 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16; 478 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32; 479 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; 480 481 b43_write16(dev, B43_MMIO_TSF_0, 0); 482 mmiowb(); 483 b43_write16(dev, B43_MMIO_TSF_3, v3); 484 mmiowb(); 485 b43_write16(dev, B43_MMIO_TSF_2, v2); 486 mmiowb(); 487 b43_write16(dev, B43_MMIO_TSF_1, v1); 488 mmiowb(); 489 b43_write16(dev, B43_MMIO_TSF_0, v0); 490 } 491} 492 493void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 494{ 495 b43_time_lock(dev); 496 b43_tsf_write_locked(dev, tsf); 497 b43_time_unlock(dev); 498} 499 500static 501void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac) 502{ 503 static const u8 zero_addr[ETH_ALEN] = { 0 }; 504 u16 data; 505 506 if (!mac) 507 mac = zero_addr; 508 509 offset |= 0x0020; 510 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 511 512 data = mac[0]; 513 data |= mac[1] << 8; 514 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 515 data = mac[2]; 516 data |= mac[3] << 8; 517 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 518 data = mac[4]; 519 data |= mac[5] << 8; 520 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 521} 522 523static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 524{ 525 const u8 *mac; 526 const u8 *bssid; 527 u8 mac_bssid[ETH_ALEN * 2]; 528 int i; 529 u32 tmp; 530 531 bssid = dev->wl->bssid; 532 mac = dev->wl->mac_addr; 533 534 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 535 536 memcpy(mac_bssid, mac, ETH_ALEN); 537 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 538 539 /* Write our MAC address and BSSID to template ram */ 540 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 541 tmp = (u32) (mac_bssid[i + 0]); 542 tmp |= (u32) (mac_bssid[i + 1]) << 8; 543 tmp |= (u32) (mac_bssid[i + 2]) << 16; 544 tmp |= (u32) (mac_bssid[i + 3]) << 24; 545 b43_ram_write(dev, 0x20 + i, tmp); 546 } 547} 548 549static void b43_upload_card_macaddress(struct b43_wldev *dev) 550{ 551 b43_write_mac_bssid_templates(dev); 552 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 553} 554 555static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 556{ 557 /* slot_time is in usec. */ 558 if (dev->phy.type != B43_PHYTYPE_G) 559 return; 560 b43_write16(dev, 0x684, 510 + slot_time); 561 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 562} 563 564static void b43_short_slot_timing_enable(struct b43_wldev *dev) 565{ 566 b43_set_slot_time(dev, 9); 567 dev->short_slot = 1; 568} 569 570static void b43_short_slot_timing_disable(struct b43_wldev *dev) 571{ 572 b43_set_slot_time(dev, 20); 573 dev->short_slot = 0; 574} 575 576/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable. 577 * Returns the _previously_ enabled IRQ mask. 578 */ 579static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask) 580{ 581 u32 old_mask; 582 583 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 584 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask); 585 586 return old_mask; 587} 588 589/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable. 590 * Returns the _previously_ enabled IRQ mask. 591 */ 592static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask) 593{ 594 u32 old_mask; 595 596 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 597 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask); 598 599 return old_mask; 600} 601 602/* Synchronize IRQ top- and bottom-half. 603 * IRQs must be masked before calling this. 604 * This must not be called with the irq_lock held. 605 */ 606static void b43_synchronize_irq(struct b43_wldev *dev) 607{ 608 synchronize_irq(dev->dev->irq); 609 tasklet_kill(&dev->isr_tasklet); 610} 611 612/* DummyTransmission function, as documented on 613 * http://bcm-specs.sipsolutions.net/DummyTransmission 614 */ 615void b43_dummy_transmission(struct b43_wldev *dev) 616{ 617 struct b43_phy *phy = &dev->phy; 618 unsigned int i, max_loop; 619 u16 value; 620 u32 buffer[5] = { 621 0x00000000, 622 0x00D40000, 623 0x00000000, 624 0x01000000, 625 0x00000000, 626 }; 627 628 switch (phy->type) { 629 case B43_PHYTYPE_A: 630 max_loop = 0x1E; 631 buffer[0] = 0x000201CC; 632 break; 633 case B43_PHYTYPE_B: 634 case B43_PHYTYPE_G: 635 max_loop = 0xFA; 636 buffer[0] = 0x000B846E; 637 break; 638 default: 639 B43_WARN_ON(1); 640 return; 641 } 642 643 for (i = 0; i < 5; i++) 644 b43_ram_write(dev, i * 4, buffer[i]); 645 646 /* Commit writes */ 647 b43_read32(dev, B43_MMIO_MACCTL); 648 649 b43_write16(dev, 0x0568, 0x0000); 650 b43_write16(dev, 0x07C0, 0x0000); 651 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0); 652 b43_write16(dev, 0x050C, value); 653 b43_write16(dev, 0x0508, 0x0000); 654 b43_write16(dev, 0x050A, 0x0000); 655 b43_write16(dev, 0x054C, 0x0000); 656 b43_write16(dev, 0x056A, 0x0014); 657 b43_write16(dev, 0x0568, 0x0826); 658 b43_write16(dev, 0x0500, 0x0000); 659 b43_write16(dev, 0x0502, 0x0030); 660 661 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 662 b43_radio_write16(dev, 0x0051, 0x0017); 663 for (i = 0x00; i < max_loop; i++) { 664 value = b43_read16(dev, 0x050E); 665 if (value & 0x0080) 666 break; 667 udelay(10); 668 } 669 for (i = 0x00; i < 0x0A; i++) { 670 value = b43_read16(dev, 0x050E); 671 if (value & 0x0400) 672 break; 673 udelay(10); 674 } 675 for (i = 0x00; i < 0x0A; i++) { 676 value = b43_read16(dev, 0x0690); 677 if (!(value & 0x0100)) 678 break; 679 udelay(10); 680 } 681 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 682 b43_radio_write16(dev, 0x0051, 0x0037); 683} 684 685static void key_write(struct b43_wldev *dev, 686 u8 index, u8 algorithm, const u8 * key) 687{ 688 unsigned int i; 689 u32 offset; 690 u16 value; 691 u16 kidx; 692 693 /* Key index/algo block */ 694 kidx = b43_kidx_to_fw(dev, index); 695 value = ((kidx << 4) | algorithm); 696 b43_shm_write16(dev, B43_SHM_SHARED, 697 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 698 699 /* Write the key to the Key Table Pointer offset */ 700 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 701 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 702 value = key[i]; 703 value |= (u16) (key[i + 1]) << 8; 704 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 705 } 706} 707 708static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr) 709{ 710 u32 addrtmp[2] = { 0, 0, }; 711 u8 per_sta_keys_start = 8; 712 713 if (b43_new_kidx_api(dev)) 714 per_sta_keys_start = 4; 715 716 B43_WARN_ON(index < per_sta_keys_start); 717 /* We have two default TX keys and possibly two default RX keys. 718 * Physical mac 0 is mapped to physical key 4 or 8, depending 719 * on the firmware version. 720 * So we must adjust the index here. 721 */ 722 index -= per_sta_keys_start; 723 724 if (addr) { 725 addrtmp[0] = addr[0]; 726 addrtmp[0] |= ((u32) (addr[1]) << 8); 727 addrtmp[0] |= ((u32) (addr[2]) << 16); 728 addrtmp[0] |= ((u32) (addr[3]) << 24); 729 addrtmp[1] = addr[4]; 730 addrtmp[1] |= ((u32) (addr[5]) << 8); 731 } 732 733 if (dev->dev->id.revision >= 5) { 734 /* Receive match transmitter address mechanism */ 735 b43_shm_write32(dev, B43_SHM_RCMTA, 736 (index * 2) + 0, addrtmp[0]); 737 b43_shm_write16(dev, B43_SHM_RCMTA, 738 (index * 2) + 1, addrtmp[1]); 739 } else { 740 /* RXE (Receive Engine) and 741 * PSM (Programmable State Machine) mechanism 742 */ 743 if (index < 8) { 744 /* TODO write to RCM 16, 19, 22 and 25 */ 745 } else { 746 b43_shm_write32(dev, B43_SHM_SHARED, 747 B43_SHM_SH_PSM + (index * 6) + 0, 748 addrtmp[0]); 749 b43_shm_write16(dev, B43_SHM_SHARED, 750 B43_SHM_SH_PSM + (index * 6) + 4, 751 addrtmp[1]); 752 } 753 } 754} 755 756static void do_key_write(struct b43_wldev *dev, 757 u8 index, u8 algorithm, 758 const u8 * key, size_t key_len, const u8 * mac_addr) 759{ 760 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 761 u8 per_sta_keys_start = 8; 762 763 if (b43_new_kidx_api(dev)) 764 per_sta_keys_start = 4; 765 766 B43_WARN_ON(index >= dev->max_nr_keys); 767 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 768 769 if (index >= per_sta_keys_start) 770 keymac_write(dev, index, NULL); /* First zero out mac. */ 771 if (key) 772 memcpy(buf, key, key_len); 773 key_write(dev, index, algorithm, buf); 774 if (index >= per_sta_keys_start) 775 keymac_write(dev, index, mac_addr); 776 777 dev->key[index].algorithm = algorithm; 778} 779 780static int b43_key_write(struct b43_wldev *dev, 781 int index, u8 algorithm, 782 const u8 * key, size_t key_len, 783 const u8 * mac_addr, 784 struct ieee80211_key_conf *keyconf) 785{ 786 int i; 787 int sta_keys_start; 788 789 if (key_len > B43_SEC_KEYSIZE) 790 return -EINVAL; 791 for (i = 0; i < dev->max_nr_keys; i++) { 792 /* Check that we don't already have this key. */ 793 B43_WARN_ON(dev->key[i].keyconf == keyconf); 794 } 795 if (index < 0) { 796 /* Either pairwise key or address is 00:00:00:00:00:00 797 * for transmit-only keys. Search the index. */ 798 if (b43_new_kidx_api(dev)) 799 sta_keys_start = 4; 800 else 801 sta_keys_start = 8; 802 for (i = sta_keys_start; i < dev->max_nr_keys; i++) { 803 if (!dev->key[i].keyconf) { 804 /* found empty */ 805 index = i; 806 break; 807 } 808 } 809 if (index < 0) { 810 b43err(dev->wl, "Out of hardware key memory\n"); 811 return -ENOSPC; 812 } 813 } else 814 B43_WARN_ON(index > 3); 815 816 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 817 if ((index <= 3) && !b43_new_kidx_api(dev)) { 818 /* Default RX key */ 819 B43_WARN_ON(mac_addr); 820 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 821 } 822 keyconf->hw_key_idx = index; 823 dev->key[index].keyconf = keyconf; 824 825 return 0; 826} 827 828static int b43_key_clear(struct b43_wldev *dev, int index) 829{ 830 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys))) 831 return -EINVAL; 832 do_key_write(dev, index, B43_SEC_ALGO_NONE, 833 NULL, B43_SEC_KEYSIZE, NULL); 834 if ((index <= 3) && !b43_new_kidx_api(dev)) { 835 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 836 NULL, B43_SEC_KEYSIZE, NULL); 837 } 838 dev->key[index].keyconf = NULL; 839 840 return 0; 841} 842 843static void b43_clear_keys(struct b43_wldev *dev) 844{ 845 int i; 846 847 for (i = 0; i < dev->max_nr_keys; i++) 848 b43_key_clear(dev, i); 849} 850 851void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 852{ 853 u32 macctl; 854 u16 ucstat; 855 bool hwps; 856 bool awake; 857 int i; 858 859 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 860 (ps_flags & B43_PS_DISABLED)); 861 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 862 863 if (ps_flags & B43_PS_ENABLED) { 864 hwps = 1; 865 } else if (ps_flags & B43_PS_DISABLED) { 866 hwps = 0; 867 } else { 868 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 869 // and thus is not an AP and we are associated, set bit 25 870 } 871 if (ps_flags & B43_PS_AWAKE) { 872 awake = 1; 873 } else if (ps_flags & B43_PS_ASLEEP) { 874 awake = 0; 875 } else { 876 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 877 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 878 // successful, set bit26 879 } 880 881/* FIXME: For now we force awake-on and hwps-off */ 882 hwps = 0; 883 awake = 1; 884 885 macctl = b43_read32(dev, B43_MMIO_MACCTL); 886 if (hwps) 887 macctl |= B43_MACCTL_HWPS; 888 else 889 macctl &= ~B43_MACCTL_HWPS; 890 if (awake) 891 macctl |= B43_MACCTL_AWAKE; 892 else 893 macctl &= ~B43_MACCTL_AWAKE; 894 b43_write32(dev, B43_MMIO_MACCTL, macctl); 895 /* Commit write */ 896 b43_read32(dev, B43_MMIO_MACCTL); 897 if (awake && dev->dev->id.revision >= 5) { 898 /* Wait for the microcode to wake up. */ 899 for (i = 0; i < 100; i++) { 900 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 901 B43_SHM_SH_UCODESTAT); 902 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 903 break; 904 udelay(10); 905 } 906 } 907} 908 909/* Turn the Analog ON/OFF */ 910static void b43_switch_analog(struct b43_wldev *dev, int on) 911{ 912 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); 913} 914 915void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 916{ 917 u32 tmslow; 918 u32 macctl; 919 920 flags |= B43_TMSLOW_PHYCLKEN; 921 flags |= B43_TMSLOW_PHYRESET; 922 ssb_device_enable(dev->dev, flags); 923 msleep(2); /* Wait for the PLL to turn on. */ 924 925 /* Now take the PHY out of Reset again */ 926 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 927 tmslow |= SSB_TMSLOW_FGC; 928 tmslow &= ~B43_TMSLOW_PHYRESET; 929 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 930 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 931 msleep(1); 932 tmslow &= ~SSB_TMSLOW_FGC; 933 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 934 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 935 msleep(1); 936 937 /* Turn Analog ON */ 938 b43_switch_analog(dev, 1); 939 940 macctl = b43_read32(dev, B43_MMIO_MACCTL); 941 macctl &= ~B43_MACCTL_GMODE; 942 if (flags & B43_TMSLOW_GMODE) 943 macctl |= B43_MACCTL_GMODE; 944 macctl |= B43_MACCTL_IHR_ENABLED; 945 b43_write32(dev, B43_MMIO_MACCTL, macctl); 946} 947 948static void handle_irq_transmit_status(struct b43_wldev *dev) 949{ 950 u32 v0, v1; 951 u16 tmp; 952 struct b43_txstatus stat; 953 954 while (1) { 955 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 956 if (!(v0 & 0x00000001)) 957 break; 958 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 959 960 stat.cookie = (v0 >> 16); 961 stat.seq = (v1 & 0x0000FFFF); 962 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 963 tmp = (v0 & 0x0000FFFF); 964 stat.frame_count = ((tmp & 0xF000) >> 12); 965 stat.rts_count = ((tmp & 0x0F00) >> 8); 966 stat.supp_reason = ((tmp & 0x001C) >> 2); 967 stat.pm_indicated = !!(tmp & 0x0080); 968 stat.intermediate = !!(tmp & 0x0040); 969 stat.for_ampdu = !!(tmp & 0x0020); 970 stat.acked = !!(tmp & 0x0002); 971 972 b43_handle_txstatus(dev, &stat); 973 } 974} 975 976static void drain_txstatus_queue(struct b43_wldev *dev) 977{ 978 u32 dummy; 979 980 if (dev->dev->id.revision < 5) 981 return; 982 /* Read all entries from the microcode TXstatus FIFO 983 * and throw them away. 984 */ 985 while (1) { 986 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 987 if (!(dummy & 0x00000001)) 988 break; 989 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 990 } 991} 992 993static u32 b43_jssi_read(struct b43_wldev *dev) 994{ 995 u32 val = 0; 996 997 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 998 val <<= 16; 999 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1000 1001 return val; 1002} 1003 1004static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1005{ 1006 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1007 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1008} 1009 1010static void b43_generate_noise_sample(struct b43_wldev *dev) 1011{ 1012 b43_jssi_write(dev, 0x7F7F7F7F); 1013 b43_write32(dev, B43_MMIO_MACCMD, 1014 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1015 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel); 1016} 1017 1018static void b43_calculate_link_quality(struct b43_wldev *dev) 1019{ 1020 /* Top half of Link Quality calculation. */ 1021 1022 if (dev->noisecalc.calculation_running) 1023 return; 1024 dev->noisecalc.channel_at_start = dev->phy.channel; 1025 dev->noisecalc.calculation_running = 1; 1026 dev->noisecalc.nr_samples = 0; 1027 1028 b43_generate_noise_sample(dev); 1029} 1030 1031static void handle_irq_noise(struct b43_wldev *dev) 1032{ 1033 struct b43_phy *phy = &dev->phy; 1034 u16 tmp; 1035 u8 noise[4]; 1036 u8 i, j; 1037 s32 average; 1038 1039 /* Bottom half of Link Quality calculation. */ 1040 1041 B43_WARN_ON(!dev->noisecalc.calculation_running); 1042 if (dev->noisecalc.channel_at_start != phy->channel) 1043 goto drop_calculation; 1044 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1045 if (noise[0] == 0x7F || noise[1] == 0x7F || 1046 noise[2] == 0x7F || noise[3] == 0x7F) 1047 goto generate_new; 1048 1049 /* Get the noise samples. */ 1050 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1051 i = dev->noisecalc.nr_samples; 1052 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1053 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1054 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1055 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1056 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1057 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1058 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1059 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1060 dev->noisecalc.nr_samples++; 1061 if (dev->noisecalc.nr_samples == 8) { 1062 /* Calculate the Link Quality by the noise samples. */ 1063 average = 0; 1064 for (i = 0; i < 8; i++) { 1065 for (j = 0; j < 4; j++) 1066 average += dev->noisecalc.samples[i][j]; 1067 } 1068 average /= (8 * 4); 1069 average *= 125; 1070 average += 64; 1071 average /= 128; 1072 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1073 tmp = (tmp / 128) & 0x1F; 1074 if (tmp >= 8) 1075 average += 2; 1076 else 1077 average -= 25; 1078 if (tmp == 8) 1079 average -= 72; 1080 else 1081 average -= 48; 1082 1083 dev->stats.link_noise = average; 1084 drop_calculation: 1085 dev->noisecalc.calculation_running = 0; 1086 return; 1087 } 1088 generate_new: 1089 b43_generate_noise_sample(dev); 1090} 1091 1092static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1093{ 1094 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) { 1095 ///TODO: PS TBTT 1096 } else { 1097 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1098 b43_power_saving_ctl_bits(dev, 0); 1099 } 1100 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) 1101 dev->dfq_valid = 1; 1102} 1103 1104static void handle_irq_atim_end(struct b43_wldev *dev) 1105{ 1106 if (dev->dfq_valid) { 1107 b43_write32(dev, B43_MMIO_MACCMD, 1108 b43_read32(dev, B43_MMIO_MACCMD) 1109 | B43_MACCMD_DFQ_VALID); 1110 dev->dfq_valid = 0; 1111 } 1112} 1113 1114static void handle_irq_pmq(struct b43_wldev *dev) 1115{ 1116 u32 tmp; 1117 1118 //TODO: AP mode. 1119 1120 while (1) { 1121 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1122 if (!(tmp & 0x00000008)) 1123 break; 1124 } 1125 /* 16bit write is odd, but correct. */ 1126 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1127} 1128 1129static void b43_write_template_common(struct b43_wldev *dev, 1130 const u8 * data, u16 size, 1131 u16 ram_offset, 1132 u16 shm_size_offset, u8 rate) 1133{ 1134 u32 i, tmp; 1135 struct b43_plcp_hdr4 plcp; 1136 1137 plcp.data = 0; 1138 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1139 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1140 ram_offset += sizeof(u32); 1141 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1142 * So leave the first two bytes of the next write blank. 1143 */ 1144 tmp = (u32) (data[0]) << 16; 1145 tmp |= (u32) (data[1]) << 24; 1146 b43_ram_write(dev, ram_offset, tmp); 1147 ram_offset += sizeof(u32); 1148 for (i = 2; i < size; i += sizeof(u32)) { 1149 tmp = (u32) (data[i + 0]); 1150 if (i + 1 < size) 1151 tmp |= (u32) (data[i + 1]) << 8; 1152 if (i + 2 < size) 1153 tmp |= (u32) (data[i + 2]) << 16; 1154 if (i + 3 < size) 1155 tmp |= (u32) (data[i + 3]) << 24; 1156 b43_ram_write(dev, ram_offset + i - 2, tmp); 1157 } 1158 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1159 size + sizeof(struct b43_plcp_hdr6)); 1160} 1161 1162static void b43_write_beacon_template(struct b43_wldev *dev, 1163 u16 ram_offset, 1164 u16 shm_size_offset, u8 rate) 1165{ 1166 unsigned int i, len, variable_len; 1167 const struct ieee80211_mgmt *bcn; 1168 const u8 *ie; 1169 bool tim_found = 0; 1170 1171 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1172 len = min((size_t) dev->wl->current_beacon->len, 1173 0x200 - sizeof(struct b43_plcp_hdr6)); 1174 1175 b43_write_template_common(dev, (const u8 *)bcn, 1176 len, ram_offset, shm_size_offset, rate); 1177 1178 /* Find the position of the TIM and the DTIM_period value 1179 * and write them to SHM. */ 1180 ie = bcn->u.beacon.variable; 1181 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1182 for (i = 0; i < variable_len - 2; ) { 1183 uint8_t ie_id, ie_len; 1184 1185 ie_id = ie[i]; 1186 ie_len = ie[i + 1]; 1187 if (ie_id == 5) { 1188 u16 tim_position; 1189 u16 dtim_period; 1190 /* This is the TIM Information Element */ 1191 1192 /* Check whether the ie_len is in the beacon data range. */ 1193 if (variable_len < ie_len + 2 + i) 1194 break; 1195 /* A valid TIM is at least 4 bytes long. */ 1196 if (ie_len < 4) 1197 break; 1198 tim_found = 1; 1199 1200 tim_position = sizeof(struct b43_plcp_hdr6); 1201 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1202 tim_position += i; 1203 1204 dtim_period = ie[i + 3]; 1205 1206 b43_shm_write16(dev, B43_SHM_SHARED, 1207 B43_SHM_SH_TIMBPOS, tim_position); 1208 b43_shm_write16(dev, B43_SHM_SHARED, 1209 B43_SHM_SH_DTIMPER, dtim_period); 1210 break; 1211 } 1212 i += ie_len + 2; 1213 } 1214 if (!tim_found) { 1215 b43warn(dev->wl, "Did not find a valid TIM IE in " 1216 "the beacon template packet. AP or IBSS operation " 1217 "may be broken.\n"); 1218 } 1219} 1220 1221static void b43_write_probe_resp_plcp(struct b43_wldev *dev, 1222 u16 shm_offset, u16 size, u8 rate) 1223{ 1224 struct b43_plcp_hdr4 plcp; 1225 u32 tmp; 1226 __le16 dur; 1227 1228 plcp.data = 0; 1229 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1230 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1231 dev->wl->vif, size, 1232 B43_RATE_TO_BASE100KBPS(rate)); 1233 /* Write PLCP in two parts and timing for packet transfer */ 1234 tmp = le32_to_cpu(plcp.data); 1235 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF); 1236 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16); 1237 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur)); 1238} 1239 1240/* Instead of using custom probe response template, this function 1241 * just patches custom beacon template by: 1242 * 1) Changing packet type 1243 * 2) Patching duration field 1244 * 3) Stripping TIM 1245 */ 1246static const u8 * b43_generate_probe_resp(struct b43_wldev *dev, 1247 u16 *dest_size, u8 rate) 1248{ 1249 const u8 *src_data; 1250 u8 *dest_data; 1251 u16 src_size, elem_size, src_pos, dest_pos; 1252 __le16 dur; 1253 struct ieee80211_hdr *hdr; 1254 size_t ie_start; 1255 1256 src_size = dev->wl->current_beacon->len; 1257 src_data = (const u8 *)dev->wl->current_beacon->data; 1258 1259 /* Get the start offset of the variable IEs in the packet. */ 1260 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable); 1261 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable)); 1262 1263 if (B43_WARN_ON(src_size < ie_start)) 1264 return NULL; 1265 1266 dest_data = kmalloc(src_size, GFP_ATOMIC); 1267 if (unlikely(!dest_data)) 1268 return NULL; 1269 1270 /* Copy the static data and all Information Elements, except the TIM. */ 1271 memcpy(dest_data, src_data, ie_start); 1272 src_pos = ie_start; 1273 dest_pos = ie_start; 1274 for ( ; src_pos < src_size - 2; src_pos += elem_size) { 1275 elem_size = src_data[src_pos + 1] + 2; 1276 if (src_data[src_pos] == 5) { 1277 /* This is the TIM. */ 1278 continue; 1279 } 1280 memcpy(dest_data + dest_pos, src_data + src_pos, 1281 elem_size); 1282 dest_pos += elem_size; 1283 } 1284 *dest_size = dest_pos; 1285 hdr = (struct ieee80211_hdr *)dest_data; 1286 1287 /* Set the frame control. */ 1288 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | 1289 IEEE80211_STYPE_PROBE_RESP); 1290 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1291 dev->wl->vif, *dest_size, 1292 B43_RATE_TO_BASE100KBPS(rate)); 1293 hdr->duration_id = dur; 1294 1295 return dest_data; 1296} 1297 1298static void b43_write_probe_resp_template(struct b43_wldev *dev, 1299 u16 ram_offset, 1300 u16 shm_size_offset, u8 rate) 1301{ 1302 const u8 *probe_resp_data; 1303 u16 size; 1304 1305 size = dev->wl->current_beacon->len; 1306 probe_resp_data = b43_generate_probe_resp(dev, &size, rate); 1307 if (unlikely(!probe_resp_data)) 1308 return; 1309 1310 /* Looks like PLCP headers plus packet timings are stored for 1311 * all possible basic rates 1312 */ 1313 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB); 1314 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB); 1315 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB); 1316 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB); 1317 1318 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6)); 1319 b43_write_template_common(dev, probe_resp_data, 1320 size, ram_offset, shm_size_offset, rate); 1321 kfree(probe_resp_data); 1322} 1323 1324/* Asynchronously update the packet templates in template RAM. 1325 * Locking: Requires wl->irq_lock to be locked. */ 1326static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon) 1327{ 1328 /* This is the top half of the ansynchronous beacon update. 1329 * The bottom half is the beacon IRQ. 1330 * Beacon update must be asynchronous to avoid sending an 1331 * invalid beacon. This can happen for example, if the firmware 1332 * transmits a beacon while we are updating it. */ 1333 1334 if (wl->current_beacon) 1335 dev_kfree_skb_any(wl->current_beacon); 1336 wl->current_beacon = beacon; 1337 wl->beacon0_uploaded = 0; 1338 wl->beacon1_uploaded = 0; 1339} 1340 1341static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len) 1342{ 1343 u32 tmp; 1344 u16 i, len; 1345 1346 len = min((u16) ssid_len, (u16) 0x100); 1347 for (i = 0; i < len; i += sizeof(u32)) { 1348 tmp = (u32) (ssid[i + 0]); 1349 if (i + 1 < len) 1350 tmp |= (u32) (ssid[i + 1]) << 8; 1351 if (i + 2 < len) 1352 tmp |= (u32) (ssid[i + 2]) << 16; 1353 if (i + 3 < len) 1354 tmp |= (u32) (ssid[i + 3]) << 24; 1355 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp); 1356 } 1357 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len); 1358} 1359 1360static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1361{ 1362 b43_time_lock(dev); 1363 if (dev->dev->id.revision >= 3) { 1364 b43_write32(dev, 0x188, (beacon_int << 16)); 1365 } else { 1366 b43_write16(dev, 0x606, (beacon_int >> 6)); 1367 b43_write16(dev, 0x610, beacon_int); 1368 } 1369 b43_time_unlock(dev); 1370} 1371 1372static void handle_irq_beacon(struct b43_wldev *dev) 1373{ 1374 struct b43_wl *wl = dev->wl; 1375 u32 cmd; 1376 1377 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 1378 return; 1379 1380 /* This is the bottom half of the asynchronous beacon update. */ 1381 1382 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1383 if (!(cmd & B43_MACCMD_BEACON0_VALID)) { 1384 if (!wl->beacon0_uploaded) { 1385 b43_write_beacon_template(dev, 0x68, 0x18, 1386 B43_CCK_RATE_1MB); 1387 b43_write_probe_resp_template(dev, 0x268, 0x4A, 1388 B43_CCK_RATE_11MB); 1389 wl->beacon0_uploaded = 1; 1390 } 1391 cmd |= B43_MACCMD_BEACON0_VALID; 1392 } 1393 if (!(cmd & B43_MACCMD_BEACON1_VALID)) { 1394 if (!wl->beacon1_uploaded) { 1395 b43_write_beacon_template(dev, 0x468, 0x1A, 1396 B43_CCK_RATE_1MB); 1397 wl->beacon1_uploaded = 1; 1398 } 1399 cmd |= B43_MACCMD_BEACON1_VALID; 1400 } 1401 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1402} 1403 1404static void handle_irq_ucode_debug(struct b43_wldev *dev) 1405{ 1406 //TODO 1407} 1408 1409/* Interrupt handler bottom-half */ 1410static void b43_interrupt_tasklet(struct b43_wldev *dev) 1411{ 1412 u32 reason; 1413 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1414 u32 merged_dma_reason = 0; 1415 int i; 1416 unsigned long flags; 1417 1418 spin_lock_irqsave(&dev->wl->irq_lock, flags); 1419 1420 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED); 1421 1422 reason = dev->irq_reason; 1423 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1424 dma_reason[i] = dev->dma_reason[i]; 1425 merged_dma_reason |= dma_reason[i]; 1426 } 1427 1428 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1429 b43err(dev->wl, "MAC transmission error\n"); 1430 1431 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1432 b43err(dev->wl, "PHY transmission error\n"); 1433 rmb(); 1434 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1435 atomic_set(&dev->phy.txerr_cnt, 1436 B43_PHY_TX_BADNESS_LIMIT); 1437 b43err(dev->wl, "Too many PHY TX errors, " 1438 "restarting the controller\n"); 1439 b43_controller_restart(dev, "PHY TX errors"); 1440 } 1441 } 1442 1443 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1444 B43_DMAIRQ_NONFATALMASK))) { 1445 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1446 b43err(dev->wl, "Fatal DMA error: " 1447 "0x%08X, 0x%08X, 0x%08X, " 1448 "0x%08X, 0x%08X, 0x%08X\n", 1449 dma_reason[0], dma_reason[1], 1450 dma_reason[2], dma_reason[3], 1451 dma_reason[4], dma_reason[5]); 1452 b43_controller_restart(dev, "DMA error"); 1453 mmiowb(); 1454 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1455 return; 1456 } 1457 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1458 b43err(dev->wl, "DMA error: " 1459 "0x%08X, 0x%08X, 0x%08X, " 1460 "0x%08X, 0x%08X, 0x%08X\n", 1461 dma_reason[0], dma_reason[1], 1462 dma_reason[2], dma_reason[3], 1463 dma_reason[4], dma_reason[5]); 1464 } 1465 } 1466 1467 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1468 handle_irq_ucode_debug(dev); 1469 if (reason & B43_IRQ_TBTT_INDI) 1470 handle_irq_tbtt_indication(dev); 1471 if (reason & B43_IRQ_ATIM_END) 1472 handle_irq_atim_end(dev); 1473 if (reason & B43_IRQ_BEACON) 1474 handle_irq_beacon(dev); 1475 if (reason & B43_IRQ_PMQ) 1476 handle_irq_pmq(dev); 1477 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1478 ;/* TODO */ 1479 if (reason & B43_IRQ_NOISESAMPLE_OK) 1480 handle_irq_noise(dev); 1481 1482 /* Check the DMA reason registers for received data. */ 1483 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) 1484 b43_dma_rx(dev->dma.rx_ring0); 1485 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) 1486 b43_dma_rx(dev->dma.rx_ring3); 1487 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1488 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1489 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1490 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1491 1492 if (reason & B43_IRQ_TX_OK) 1493 handle_irq_transmit_status(dev); 1494 1495 b43_interrupt_enable(dev, dev->irq_savedstate); 1496 mmiowb(); 1497 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1498} 1499 1500static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason) 1501{ 1502 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1503 1504 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1505 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1506 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1507 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1508 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1509 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1510} 1511 1512/* Interrupt handler top-half */ 1513static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1514{ 1515 irqreturn_t ret = IRQ_NONE; 1516 struct b43_wldev *dev = dev_id; 1517 u32 reason; 1518 1519 if (!dev) 1520 return IRQ_NONE; 1521 1522 spin_lock(&dev->wl->irq_lock); 1523 1524 if (b43_status(dev) < B43_STAT_STARTED) 1525 goto out; 1526 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1527 if (reason == 0xffffffff) /* shared IRQ */ 1528 goto out; 1529 ret = IRQ_HANDLED; 1530 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 1531 if (!reason) 1532 goto out; 1533 1534 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1535 & 0x0001DC00; 1536 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1537 & 0x0000DC00; 1538 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1539 & 0x0000DC00; 1540 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1541 & 0x0001DC00; 1542 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1543 & 0x0000DC00; 1544 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1545 & 0x0000DC00; 1546 1547 b43_interrupt_ack(dev, reason); 1548 /* disable all IRQs. They are enabled again in the bottom half. */ 1549 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 1550 /* save the reason code and call our bottom half. */ 1551 dev->irq_reason = reason; 1552 tasklet_schedule(&dev->isr_tasklet); 1553 out: 1554 mmiowb(); 1555 spin_unlock(&dev->wl->irq_lock); 1556 1557 return ret; 1558} 1559 1560static void do_release_fw(struct b43_firmware_file *fw) 1561{ 1562 release_firmware(fw->data); 1563 fw->data = NULL; 1564 fw->filename = NULL; 1565} 1566 1567static void b43_release_firmware(struct b43_wldev *dev) 1568{ 1569 do_release_fw(&dev->fw.ucode); 1570 do_release_fw(&dev->fw.pcm); 1571 do_release_fw(&dev->fw.initvals); 1572 do_release_fw(&dev->fw.initvals_band); 1573} 1574 1575static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 1576{ 1577 const char *text; 1578 1579 text = "You must go to " 1580 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware " 1581 "and download the latest firmware (version 4).\n"; 1582 if (error) 1583 b43err(wl, text); 1584 else 1585 b43warn(wl, text); 1586} 1587 1588static int do_request_fw(struct b43_wldev *dev, 1589 const char *name, 1590 struct b43_firmware_file *fw) 1591{ 1592 char path[sizeof(modparam_fwpostfix) + 32]; 1593 const struct firmware *blob; 1594 struct b43_fw_header *hdr; 1595 u32 size; 1596 int err; 1597 1598 if (!name) { 1599 /* Don't fetch anything. Free possibly cached firmware. */ 1600 do_release_fw(fw); 1601 return 0; 1602 } 1603 if (fw->filename) { 1604 if (strcmp(fw->filename, name) == 0) 1605 return 0; /* Already have this fw. */ 1606 /* Free the cached firmware first. */ 1607 do_release_fw(fw); 1608 } 1609 1610 snprintf(path, ARRAY_SIZE(path), 1611 "b43%s/%s.fw", 1612 modparam_fwpostfix, name); 1613 err = request_firmware(&blob, path, dev->dev->dev); 1614 if (err) { 1615 b43err(dev->wl, "Firmware file \"%s\" not found " 1616 "or load failed.\n", path); 1617 return err; 1618 } 1619 if (blob->size < sizeof(struct b43_fw_header)) 1620 goto err_format; 1621 hdr = (struct b43_fw_header *)(blob->data); 1622 switch (hdr->type) { 1623 case B43_FW_TYPE_UCODE: 1624 case B43_FW_TYPE_PCM: 1625 size = be32_to_cpu(hdr->size); 1626 if (size != blob->size - sizeof(struct b43_fw_header)) 1627 goto err_format; 1628 /* fallthrough */ 1629 case B43_FW_TYPE_IV: 1630 if (hdr->ver != 1) 1631 goto err_format; 1632 break; 1633 default: 1634 goto err_format; 1635 } 1636 1637 fw->data = blob; 1638 fw->filename = name; 1639 1640 return 0; 1641 1642err_format: 1643 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path); 1644 release_firmware(blob); 1645 1646 return -EPROTO; 1647} 1648 1649static int b43_request_firmware(struct b43_wldev *dev) 1650{ 1651 struct b43_firmware *fw = &dev->fw; 1652 const u8 rev = dev->dev->id.revision; 1653 const char *filename; 1654 u32 tmshigh; 1655 int err; 1656 1657 /* Get microcode */ 1658 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 1659 if ((rev >= 5) && (rev <= 10)) 1660 filename = "ucode5"; 1661 else if ((rev >= 11) && (rev <= 12)) 1662 filename = "ucode11"; 1663 else if (rev >= 13) 1664 filename = "ucode13"; 1665 else 1666 goto err_no_ucode; 1667 err = do_request_fw(dev, filename, &fw->ucode); 1668 if (err) 1669 goto err_load; 1670 1671 /* Get PCM code */ 1672 if ((rev >= 5) && (rev <= 10)) 1673 filename = "pcm5"; 1674 else if (rev >= 11) 1675 filename = NULL; 1676 else 1677 goto err_no_pcm; 1678 err = do_request_fw(dev, filename, &fw->pcm); 1679 if (err) 1680 goto err_load; 1681 1682 /* Get initvals */ 1683 switch (dev->phy.type) { 1684 case B43_PHYTYPE_A: 1685 if ((rev >= 5) && (rev <= 10)) { 1686 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 1687 filename = "a0g1initvals5"; 1688 else 1689 filename = "a0g0initvals5"; 1690 } else 1691 goto err_no_initvals; 1692 break; 1693 case B43_PHYTYPE_G: 1694 if ((rev >= 5) && (rev <= 10)) 1695 filename = "b0g0initvals5"; 1696 else if (rev >= 13) 1697 filename = "lp0initvals13"; 1698 else 1699 goto err_no_initvals; 1700 break; 1701 case B43_PHYTYPE_N: 1702 if ((rev >= 11) && (rev <= 12)) 1703 filename = "n0initvals11"; 1704 else 1705 goto err_no_initvals; 1706 break; 1707 default: 1708 goto err_no_initvals; 1709 } 1710 err = do_request_fw(dev, filename, &fw->initvals); 1711 if (err) 1712 goto err_load; 1713 1714 /* Get bandswitch initvals */ 1715 switch (dev->phy.type) { 1716 case B43_PHYTYPE_A: 1717 if ((rev >= 5) && (rev <= 10)) { 1718 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 1719 filename = "a0g1bsinitvals5"; 1720 else 1721 filename = "a0g0bsinitvals5"; 1722 } else if (rev >= 11) 1723 filename = NULL; 1724 else 1725 goto err_no_initvals; 1726 break; 1727 case B43_PHYTYPE_G: 1728 if ((rev >= 5) && (rev <= 10)) 1729 filename = "b0g0bsinitvals5"; 1730 else if (rev >= 11) 1731 filename = NULL; 1732 else 1733 goto err_no_initvals; 1734 break; 1735 case B43_PHYTYPE_N: 1736 if ((rev >= 11) && (rev <= 12)) 1737 filename = "n0bsinitvals11"; 1738 else 1739 goto err_no_initvals; 1740 break; 1741 default: 1742 goto err_no_initvals; 1743 } 1744 err = do_request_fw(dev, filename, &fw->initvals_band); 1745 if (err) 1746 goto err_load; 1747 1748 return 0; 1749 1750err_load: 1751 b43_print_fw_helptext(dev->wl, 1); 1752 goto error; 1753 1754err_no_ucode: 1755 err = -ENODEV; 1756 b43err(dev->wl, "No microcode available for core rev %u\n", rev); 1757 goto error; 1758 1759err_no_pcm: 1760 err = -ENODEV; 1761 b43err(dev->wl, "No PCM available for core rev %u\n", rev); 1762 goto error; 1763 1764err_no_initvals: 1765 err = -ENODEV; 1766 b43err(dev->wl, "No Initial Values firmware file for PHY %u, " 1767 "core rev %u\n", dev->phy.type, rev); 1768 goto error; 1769 1770error: 1771 b43_release_firmware(dev); 1772 return err; 1773} 1774 1775static int b43_upload_microcode(struct b43_wldev *dev) 1776{ 1777 const size_t hdr_len = sizeof(struct b43_fw_header); 1778 const __be32 *data; 1779 unsigned int i, len; 1780 u16 fwrev, fwpatch, fwdate, fwtime; 1781 u32 tmp; 1782 int err = 0; 1783 1784 /* Upload Microcode. */ 1785 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); 1786 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); 1787 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 1788 for (i = 0; i < len; i++) { 1789 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1790 udelay(10); 1791 } 1792 1793 if (dev->fw.pcm.data) { 1794 /* Upload PCM data. */ 1795 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); 1796 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); 1797 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 1798 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 1799 /* No need for autoinc bit in SHM_HW */ 1800 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 1801 for (i = 0; i < len; i++) { 1802 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1803 udelay(10); 1804 } 1805 } 1806 1807 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 1808 b43_write32(dev, B43_MMIO_MACCTL, 1809 B43_MACCTL_PSM_RUN | 1810 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA); 1811 1812 /* Wait for the microcode to load and respond */ 1813 i = 0; 1814 while (1) { 1815 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1816 if (tmp == B43_IRQ_MAC_SUSPENDED) 1817 break; 1818 i++; 1819 if (i >= 50) { 1820 b43err(dev->wl, "Microcode not responding\n"); 1821 b43_print_fw_helptext(dev->wl, 1); 1822 err = -ENODEV; 1823 goto out; 1824 } 1825 udelay(10); 1826 } 1827 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 1828 1829 /* Get and check the revisions. */ 1830 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 1831 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 1832 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 1833 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 1834 1835 if (fwrev <= 0x128) { 1836 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 1837 "binary drivers older than version 4.x is unsupported. " 1838 "You must upgrade your firmware files.\n"); 1839 b43_print_fw_helptext(dev->wl, 1); 1840 b43_write32(dev, B43_MMIO_MACCTL, 0); 1841 err = -EOPNOTSUPP; 1842 goto out; 1843 } 1844 b43dbg(dev->wl, "Loading firmware version %u.%u " 1845 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 1846 fwrev, fwpatch, 1847 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 1848 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 1849 1850 dev->fw.rev = fwrev; 1851 dev->fw.patch = fwpatch; 1852 1853 if (b43_is_old_txhdr_format(dev)) { 1854 b43warn(dev->wl, "You are using an old firmware image. " 1855 "Support for old firmware will be removed in July 2008.\n"); 1856 b43_print_fw_helptext(dev->wl, 0); 1857 } 1858 1859out: 1860 return err; 1861} 1862 1863static int b43_write_initvals(struct b43_wldev *dev, 1864 const struct b43_iv *ivals, 1865 size_t count, 1866 size_t array_size) 1867{ 1868 const struct b43_iv *iv; 1869 u16 offset; 1870 size_t i; 1871 bool bit32; 1872 1873 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 1874 iv = ivals; 1875 for (i = 0; i < count; i++) { 1876 if (array_size < sizeof(iv->offset_size)) 1877 goto err_format; 1878 array_size -= sizeof(iv->offset_size); 1879 offset = be16_to_cpu(iv->offset_size); 1880 bit32 = !!(offset & B43_IV_32BIT); 1881 offset &= B43_IV_OFFSET_MASK; 1882 if (offset >= 0x1000) 1883 goto err_format; 1884 if (bit32) { 1885 u32 value; 1886 1887 if (array_size < sizeof(iv->data.d32)) 1888 goto err_format; 1889 array_size -= sizeof(iv->data.d32); 1890 1891 value = be32_to_cpu(get_unaligned(&iv->data.d32)); 1892 b43_write32(dev, offset, value); 1893 1894 iv = (const struct b43_iv *)((const uint8_t *)iv + 1895 sizeof(__be16) + 1896 sizeof(__be32)); 1897 } else { 1898 u16 value; 1899 1900 if (array_size < sizeof(iv->data.d16)) 1901 goto err_format; 1902 array_size -= sizeof(iv->data.d16); 1903 1904 value = be16_to_cpu(iv->data.d16); 1905 b43_write16(dev, offset, value); 1906 1907 iv = (const struct b43_iv *)((const uint8_t *)iv + 1908 sizeof(__be16) + 1909 sizeof(__be16)); 1910 } 1911 } 1912 if (array_size) 1913 goto err_format; 1914 1915 return 0; 1916 1917err_format: 1918 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 1919 b43_print_fw_helptext(dev->wl, 1); 1920 1921 return -EPROTO; 1922} 1923 1924static int b43_upload_initvals(struct b43_wldev *dev) 1925{ 1926 const size_t hdr_len = sizeof(struct b43_fw_header); 1927 const struct b43_fw_header *hdr; 1928 struct b43_firmware *fw = &dev->fw; 1929 const struct b43_iv *ivals; 1930 size_t count; 1931 int err; 1932 1933 hdr = (const struct b43_fw_header *)(fw->initvals.data->data); 1934 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); 1935 count = be32_to_cpu(hdr->size); 1936 err = b43_write_initvals(dev, ivals, count, 1937 fw->initvals.data->size - hdr_len); 1938 if (err) 1939 goto out; 1940 if (fw->initvals_band.data) { 1941 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); 1942 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); 1943 count = be32_to_cpu(hdr->size); 1944 err = b43_write_initvals(dev, ivals, count, 1945 fw->initvals_band.data->size - hdr_len); 1946 if (err) 1947 goto out; 1948 } 1949out: 1950 1951 return err; 1952} 1953 1954/* Initialize the GPIOs 1955 * http://bcm-specs.sipsolutions.net/GPIO 1956 */ 1957static int b43_gpio_init(struct b43_wldev *dev) 1958{ 1959 struct ssb_bus *bus = dev->dev->bus; 1960 struct ssb_device *gpiodev, *pcidev = NULL; 1961 u32 mask, set; 1962 1963 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 1964 & ~B43_MACCTL_GPOUTSMSK); 1965 1966 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 1967 | 0x000F); 1968 1969 mask = 0x0000001F; 1970 set = 0x0000000F; 1971 if (dev->dev->bus->chip_id == 0x4301) { 1972 mask |= 0x0060; 1973 set |= 0x0060; 1974 } 1975 if (0 /* FIXME: conditional unknown */ ) { 1976 b43_write16(dev, B43_MMIO_GPIO_MASK, 1977 b43_read16(dev, B43_MMIO_GPIO_MASK) 1978 | 0x0100); 1979 mask |= 0x0180; 1980 set |= 0x0180; 1981 } 1982 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) { 1983 b43_write16(dev, B43_MMIO_GPIO_MASK, 1984 b43_read16(dev, B43_MMIO_GPIO_MASK) 1985 | 0x0200); 1986 mask |= 0x0200; 1987 set |= 0x0200; 1988 } 1989 if (dev->dev->id.revision >= 2) 1990 mask |= 0x0010; /* FIXME: This is redundant. */ 1991 1992#ifdef CONFIG_SSB_DRIVER_PCICORE 1993 pcidev = bus->pcicore.dev; 1994#endif 1995 gpiodev = bus->chipco.dev ? : pcidev; 1996 if (!gpiodev) 1997 return 0; 1998 ssb_write32(gpiodev, B43_GPIO_CONTROL, 1999 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2000 & mask) | set); 2001 2002 return 0; 2003} 2004 2005/* Turn off all GPIO stuff. Call this on module unload, for example. */ 2006static void b43_gpio_cleanup(struct b43_wldev *dev) 2007{ 2008 struct ssb_bus *bus = dev->dev->bus; 2009 struct ssb_device *gpiodev, *pcidev = NULL; 2010 2011#ifdef CONFIG_SSB_DRIVER_PCICORE 2012 pcidev = bus->pcicore.dev; 2013#endif 2014 gpiodev = bus->chipco.dev ? : pcidev; 2015 if (!gpiodev) 2016 return; 2017 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2018} 2019 2020/* http://bcm-specs.sipsolutions.net/EnableMac */ 2021void b43_mac_enable(struct b43_wldev *dev) 2022{ 2023 dev->mac_suspended--; 2024 B43_WARN_ON(dev->mac_suspended < 0); 2025 B43_WARN_ON(irqs_disabled()); 2026 if (dev->mac_suspended == 0) { 2027 b43_write32(dev, B43_MMIO_MACCTL, 2028 b43_read32(dev, B43_MMIO_MACCTL) 2029 | B43_MACCTL_ENABLED); 2030 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2031 B43_IRQ_MAC_SUSPENDED); 2032 /* Commit writes */ 2033 b43_read32(dev, B43_MMIO_MACCTL); 2034 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2035 b43_power_saving_ctl_bits(dev, 0); 2036 2037 /* Re-enable IRQs. */ 2038 spin_lock_irq(&dev->wl->irq_lock); 2039 b43_interrupt_enable(dev, dev->irq_savedstate); 2040 spin_unlock_irq(&dev->wl->irq_lock); 2041 } 2042} 2043 2044/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2045void b43_mac_suspend(struct b43_wldev *dev) 2046{ 2047 int i; 2048 u32 tmp; 2049 2050 might_sleep(); 2051 B43_WARN_ON(irqs_disabled()); 2052 B43_WARN_ON(dev->mac_suspended < 0); 2053 2054 if (dev->mac_suspended == 0) { 2055 /* Mask IRQs before suspending MAC. Otherwise 2056 * the MAC stays busy and won't suspend. */ 2057 spin_lock_irq(&dev->wl->irq_lock); 2058 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL); 2059 spin_unlock_irq(&dev->wl->irq_lock); 2060 b43_synchronize_irq(dev); 2061 dev->irq_savedstate = tmp; 2062 2063 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2064 b43_write32(dev, B43_MMIO_MACCTL, 2065 b43_read32(dev, B43_MMIO_MACCTL) 2066 & ~B43_MACCTL_ENABLED); 2067 /* force pci to flush the write */ 2068 b43_read32(dev, B43_MMIO_MACCTL); 2069 for (i = 40; i; i--) { 2070 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2071 if (tmp & B43_IRQ_MAC_SUSPENDED) 2072 goto out; 2073 msleep(1); 2074 } 2075 b43err(dev->wl, "MAC suspend failed\n"); 2076 } 2077out: 2078 dev->mac_suspended++; 2079} 2080 2081static void b43_adjust_opmode(struct b43_wldev *dev) 2082{ 2083 struct b43_wl *wl = dev->wl; 2084 u32 ctl; 2085 u16 cfp_pretbtt; 2086 2087 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2088 /* Reset status to STA infrastructure mode. */ 2089 ctl &= ~B43_MACCTL_AP; 2090 ctl &= ~B43_MACCTL_KEEP_CTL; 2091 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2092 ctl &= ~B43_MACCTL_KEEP_BAD; 2093 ctl &= ~B43_MACCTL_PROMISC; 2094 ctl &= ~B43_MACCTL_BEACPROMISC; 2095 ctl |= B43_MACCTL_INFRA; 2096 2097 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2098 ctl |= B43_MACCTL_AP; 2099 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) 2100 ctl &= ~B43_MACCTL_INFRA; 2101 2102 if (wl->filter_flags & FIF_CONTROL) 2103 ctl |= B43_MACCTL_KEEP_CTL; 2104 if (wl->filter_flags & FIF_FCSFAIL) 2105 ctl |= B43_MACCTL_KEEP_BAD; 2106 if (wl->filter_flags & FIF_PLCPFAIL) 2107 ctl |= B43_MACCTL_KEEP_BADPLCP; 2108 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2109 ctl |= B43_MACCTL_PROMISC; 2110 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2111 ctl |= B43_MACCTL_BEACPROMISC; 2112 2113 /* Workaround: On old hardware the HW-MAC-address-filter 2114 * doesn't work properly, so always run promisc in filter 2115 * it in software. */ 2116 if (dev->dev->id.revision <= 4) 2117 ctl |= B43_MACCTL_PROMISC; 2118 2119 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2120 2121 cfp_pretbtt = 2; 2122 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2123 if (dev->dev->bus->chip_id == 0x4306 && 2124 dev->dev->bus->chip_rev == 3) 2125 cfp_pretbtt = 100; 2126 else 2127 cfp_pretbtt = 50; 2128 } 2129 b43_write16(dev, 0x612, cfp_pretbtt); 2130} 2131 2132static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2133{ 2134 u16 offset; 2135 2136 if (is_ofdm) { 2137 offset = 0x480; 2138 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2139 } else { 2140 offset = 0x4C0; 2141 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2142 } 2143 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2144 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2145} 2146 2147static void b43_rate_memory_init(struct b43_wldev *dev) 2148{ 2149 switch (dev->phy.type) { 2150 case B43_PHYTYPE_A: 2151 case B43_PHYTYPE_G: 2152 case B43_PHYTYPE_N: 2153 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2154 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2155 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2156 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2157 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2158 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2159 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2160 if (dev->phy.type == B43_PHYTYPE_A) 2161 break; 2162 /* fallthrough */ 2163 case B43_PHYTYPE_B: 2164 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2165 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2166 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2167 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2168 break; 2169 default: 2170 B43_WARN_ON(1); 2171 } 2172} 2173 2174/* Set the TX-Antenna for management frames sent by firmware. */ 2175static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2176{ 2177 u16 ant = 0; 2178 u16 tmp; 2179 2180 switch (antenna) { 2181 case B43_ANTENNA0: 2182 ant |= B43_TXH_PHY_ANT0; 2183 break; 2184 case B43_ANTENNA1: 2185 ant |= B43_TXH_PHY_ANT1; 2186 break; 2187 case B43_ANTENNA2: 2188 ant |= B43_TXH_PHY_ANT2; 2189 break; 2190 case B43_ANTENNA3: 2191 ant |= B43_TXH_PHY_ANT3; 2192 break; 2193 case B43_ANTENNA_AUTO: 2194 ant |= B43_TXH_PHY_ANT01AUTO; 2195 break; 2196 default: 2197 B43_WARN_ON(1); 2198 } 2199 2200 /* FIXME We also need to set the other flags of the PHY control field somewhere. */ 2201 2202 /* For Beacons */ 2203 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 2204 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2205 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp); 2206 /* For ACK/CTS */ 2207 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2208 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2209 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2210 /* For Probe Resposes */ 2211 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2212 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2213 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2214} 2215 2216/* This is the opposite of b43_chip_init() */ 2217static void b43_chip_exit(struct b43_wldev *dev) 2218{ 2219 b43_radio_turn_off(dev, 1); 2220 b43_gpio_cleanup(dev); 2221 /* firmware is released later */ 2222} 2223 2224/* Initialize the chip 2225 * http://bcm-specs.sipsolutions.net/ChipInit 2226 */ 2227static int b43_chip_init(struct b43_wldev *dev) 2228{ 2229 struct b43_phy *phy = &dev->phy; 2230 int err, tmp; 2231 u32 value32; 2232 u16 value16; 2233 2234 b43_write32(dev, B43_MMIO_MACCTL, 2235 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED); 2236 2237 err = b43_request_firmware(dev); 2238 if (err) 2239 goto out; 2240 err = b43_upload_microcode(dev); 2241 if (err) 2242 goto out; /* firmware is released later */ 2243 2244 err = b43_gpio_init(dev); 2245 if (err) 2246 goto out; /* firmware is released later */ 2247 2248 err = b43_upload_initvals(dev); 2249 if (err) 2250 goto err_gpio_clean; 2251 b43_radio_turn_on(dev); 2252 2253 b43_write16(dev, 0x03E6, 0x0000); 2254 err = b43_phy_init(dev); 2255 if (err) 2256 goto err_radio_off; 2257 2258 /* Select initial Interference Mitigation. */ 2259 tmp = phy->interfmode; 2260 phy->interfmode = B43_INTERFMODE_NONE; 2261 b43_radio_set_interference_mitigation(dev, tmp); 2262 2263 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2264 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2265 2266 if (phy->type == B43_PHYTYPE_B) { 2267 value16 = b43_read16(dev, 0x005E); 2268 value16 |= 0x0004; 2269 b43_write16(dev, 0x005E, value16); 2270 } 2271 b43_write32(dev, 0x0100, 0x01000000); 2272 if (dev->dev->id.revision < 5) 2273 b43_write32(dev, 0x010C, 0x01000000); 2274 2275 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2276 & ~B43_MACCTL_INFRA); 2277 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2278 | B43_MACCTL_INFRA); 2279 2280 /* Probe Response Timeout value */ 2281 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2282 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2283 2284 /* Initially set the wireless operation mode. */ 2285 b43_adjust_opmode(dev); 2286 2287 if (dev->dev->id.revision < 3) { 2288 b43_write16(dev, 0x060E, 0x0000); 2289 b43_write16(dev, 0x0610, 0x8000); 2290 b43_write16(dev, 0x0604, 0x0000); 2291 b43_write16(dev, 0x0606, 0x0200); 2292 } else { 2293 b43_write32(dev, 0x0188, 0x80000000); 2294 b43_write32(dev, 0x018C, 0x02000000); 2295 } 2296 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2297 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2298 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2299 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2300 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2301 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2302 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2303 2304 value32 = ssb_read32(dev->dev, SSB_TMSLOW); 2305 value32 |= 0x00100000; 2306 ssb_write32(dev->dev, SSB_TMSLOW, value32); 2307 2308 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2309 dev->dev->bus->chipco.fast_pwrup_delay); 2310 2311 err = 0; 2312 b43dbg(dev->wl, "Chip initialized\n"); 2313out: 2314 return err; 2315 2316err_radio_off: 2317 b43_radio_turn_off(dev, 1); 2318err_gpio_clean: 2319 b43_gpio_cleanup(dev); 2320 return err; 2321} 2322 2323static void b43_periodic_every120sec(struct b43_wldev *dev) 2324{ 2325 struct b43_phy *phy = &dev->phy; 2326 2327 if (phy->type != B43_PHYTYPE_G || phy->rev < 2) 2328 return; 2329 2330 b43_mac_suspend(dev); 2331 b43_lo_g_measure(dev); 2332 b43_mac_enable(dev); 2333 if (b43_has_hardware_pctl(phy)) 2334 b43_lo_g_ctl_mark_all_unused(dev); 2335} 2336 2337static void b43_periodic_every60sec(struct b43_wldev *dev) 2338{ 2339 struct b43_phy *phy = &dev->phy; 2340 2341 if (phy->type != B43_PHYTYPE_G) 2342 return; 2343 if (!b43_has_hardware_pctl(phy)) 2344 b43_lo_g_ctl_mark_all_unused(dev); 2345 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) { 2346 b43_mac_suspend(dev); 2347 b43_calc_nrssi_slope(dev); 2348 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { 2349 u8 old_chan = phy->channel; 2350 2351 /* VCO Calibration */ 2352 if (old_chan >= 8) 2353 b43_radio_selectchannel(dev, 1, 0); 2354 else 2355 b43_radio_selectchannel(dev, 13, 0); 2356 b43_radio_selectchannel(dev, old_chan, 0); 2357 } 2358 b43_mac_enable(dev); 2359 } 2360} 2361 2362static void b43_periodic_every30sec(struct b43_wldev *dev) 2363{ 2364 /* Update device statistics. */ 2365 b43_calculate_link_quality(dev); 2366} 2367 2368static void b43_periodic_every15sec(struct b43_wldev *dev) 2369{ 2370 struct b43_phy *phy = &dev->phy; 2371 2372 if (phy->type == B43_PHYTYPE_G) { 2373 //TODO: update_aci_moving_average 2374 if (phy->aci_enable && phy->aci_wlan_automatic) { 2375 b43_mac_suspend(dev); 2376 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) { 2377 if (0 /*TODO: bunch of conditions */ ) { 2378 b43_radio_set_interference_mitigation 2379 (dev, B43_INTERFMODE_MANUALWLAN); 2380 } 2381 } else if (1 /*TODO*/) { 2382 /* 2383 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) { 2384 b43_radio_set_interference_mitigation(dev, 2385 B43_INTERFMODE_NONE); 2386 } 2387 */ 2388 } 2389 b43_mac_enable(dev); 2390 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN && 2391 phy->rev == 1) { 2392 //TODO: implement rev1 workaround 2393 } 2394 } 2395 b43_phy_xmitpower(dev); //FIXME: unless scanning? 2396 //TODO for APHY (temperature?) 2397 2398 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 2399 wmb(); 2400} 2401 2402static void do_periodic_work(struct b43_wldev *dev) 2403{ 2404 unsigned int state; 2405 2406 state = dev->periodic_state; 2407 if (state % 8 == 0) 2408 b43_periodic_every120sec(dev); 2409 if (state % 4 == 0) 2410 b43_periodic_every60sec(dev); 2411 if (state % 2 == 0) 2412 b43_periodic_every30sec(dev); 2413 b43_periodic_every15sec(dev); 2414} 2415 2416/* Periodic work locking policy: 2417 * The whole periodic work handler is protected by 2418 * wl->mutex. If another lock is needed somewhere in the 2419 * pwork callchain, it's aquired in-place, where it's needed. 2420 */ 2421static void b43_periodic_work_handler(struct work_struct *work) 2422{ 2423 struct b43_wldev *dev = container_of(work, struct b43_wldev, 2424 periodic_work.work); 2425 struct b43_wl *wl = dev->wl; 2426 unsigned long delay; 2427 2428 mutex_lock(&wl->mutex); 2429 2430 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 2431 goto out; 2432 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 2433 goto out_requeue; 2434 2435 do_periodic_work(dev); 2436 2437 dev->periodic_state++; 2438out_requeue: 2439 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 2440 delay = msecs_to_jiffies(50); 2441 else 2442 delay = round_jiffies_relative(HZ * 15); 2443 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay); 2444out: 2445 mutex_unlock(&wl->mutex); 2446} 2447 2448static void b43_periodic_tasks_setup(struct b43_wldev *dev) 2449{ 2450 struct delayed_work *work = &dev->periodic_work; 2451 2452 dev->periodic_state = 0; 2453 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 2454 queue_delayed_work(dev->wl->hw->workqueue, work, 0); 2455} 2456 2457/* Check if communication with the device works correctly. */ 2458static int b43_validate_chipaccess(struct b43_wldev *dev) 2459{ 2460 u32 v, backup; 2461 2462 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0); 2463 2464 /* Check for read/write and endianness problems. */ 2465 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 2466 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 2467 goto error; 2468 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 2469 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 2470 goto error; 2471 2472 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup); 2473 2474 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) { 2475 /* The 32bit register shadows the two 16bit registers 2476 * with update sideeffects. Validate this. */ 2477 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 2478 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 2479 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 2480 goto error; 2481 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 2482 goto error; 2483 } 2484 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 2485 2486 v = b43_read32(dev, B43_MMIO_MACCTL); 2487 v |= B43_MACCTL_GMODE; 2488 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 2489 goto error; 2490 2491 return 0; 2492error: 2493 b43err(dev->wl, "Failed to validate the chipaccess\n"); 2494 return -ENODEV; 2495} 2496 2497static void b43_security_init(struct b43_wldev *dev) 2498{ 2499 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20; 2500 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key)); 2501 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 2502 /* KTP is a word address, but we address SHM bytewise. 2503 * So multiply by two. 2504 */ 2505 dev->ktp *= 2; 2506 if (dev->dev->id.revision >= 5) { 2507 /* Number of RCMTA address slots */ 2508 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8); 2509 } 2510 b43_clear_keys(dev); 2511} 2512 2513static int b43_rng_read(struct hwrng *rng, u32 * data) 2514{ 2515 struct b43_wl *wl = (struct b43_wl *)rng->priv; 2516 unsigned long flags; 2517 2518 /* Don't take wl->mutex here, as it could deadlock with 2519 * hwrng internal locking. It's not needed to take 2520 * wl->mutex here, anyway. */ 2521 2522 spin_lock_irqsave(&wl->irq_lock, flags); 2523 *data = b43_read16(wl->current_dev, B43_MMIO_RNG); 2524 spin_unlock_irqrestore(&wl->irq_lock, flags); 2525 2526 return (sizeof(u16)); 2527} 2528 2529static void b43_rng_exit(struct b43_wl *wl) 2530{ 2531 if (wl->rng_initialized) 2532 hwrng_unregister(&wl->rng); 2533} 2534 2535static int b43_rng_init(struct b43_wl *wl) 2536{ 2537 int err; 2538 2539 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 2540 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 2541 wl->rng.name = wl->rng_name; 2542 wl->rng.data_read = b43_rng_read; 2543 wl->rng.priv = (unsigned long)wl; 2544 wl->rng_initialized = 1; 2545 err = hwrng_register(&wl->rng); 2546 if (err) { 2547 wl->rng_initialized = 0; 2548 b43err(wl, "Failed to register the random " 2549 "number generator (%d)\n", err); 2550 } 2551 2552 return err; 2553} 2554 2555static int b43_op_tx(struct ieee80211_hw *hw, 2556 struct sk_buff *skb, 2557 struct ieee80211_tx_control *ctl) 2558{ 2559 struct b43_wl *wl = hw_to_b43_wl(hw); 2560 struct b43_wldev *dev = wl->current_dev; 2561 int err = -ENODEV; 2562 2563 if (unlikely(!dev)) 2564 goto out; 2565 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2566 goto out; 2567 /* DMA-TX is done without a global lock. */ 2568 err = b43_dma_tx(dev, skb, ctl); 2569out: 2570 if (unlikely(err)) 2571 return NETDEV_TX_BUSY; 2572 return NETDEV_TX_OK; 2573} 2574 2575static int b43_op_conf_tx(struct ieee80211_hw *hw, 2576 int queue, 2577 const struct ieee80211_tx_queue_params *params) 2578{ 2579 return 0; 2580} 2581 2582static int b43_op_get_tx_stats(struct ieee80211_hw *hw, 2583 struct ieee80211_tx_queue_stats *stats) 2584{ 2585 struct b43_wl *wl = hw_to_b43_wl(hw); 2586 struct b43_wldev *dev = wl->current_dev; 2587 unsigned long flags; 2588 int err = -ENODEV; 2589 2590 if (!dev) 2591 goto out; 2592 spin_lock_irqsave(&wl->irq_lock, flags); 2593 if (likely(b43_status(dev) >= B43_STAT_STARTED)) { 2594 b43_dma_get_tx_stats(dev, stats); 2595 err = 0; 2596 } 2597 spin_unlock_irqrestore(&wl->irq_lock, flags); 2598out: 2599 return err; 2600} 2601 2602static int b43_op_get_stats(struct ieee80211_hw *hw, 2603 struct ieee80211_low_level_stats *stats) 2604{ 2605 struct b43_wl *wl = hw_to_b43_wl(hw); 2606 unsigned long flags; 2607 2608 spin_lock_irqsave(&wl->irq_lock, flags); 2609 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 2610 spin_unlock_irqrestore(&wl->irq_lock, flags); 2611 2612 return 0; 2613} 2614 2615static const char *phymode_to_string(unsigned int phymode) 2616{ 2617 switch (phymode) { 2618 case B43_PHYMODE_A: 2619 return "A"; 2620 case B43_PHYMODE_B: 2621 return "B"; 2622 case B43_PHYMODE_G: 2623 return "G"; 2624 default: 2625 B43_WARN_ON(1); 2626 } 2627 return ""; 2628} 2629 2630static int find_wldev_for_phymode(struct b43_wl *wl, 2631 unsigned int phymode, 2632 struct b43_wldev **dev, bool * gmode) 2633{ 2634 struct b43_wldev *d; 2635 2636 list_for_each_entry(d, &wl->devlist, list) { 2637 if (d->phy.possible_phymodes & phymode) { 2638 /* Ok, this device supports the PHY-mode. 2639 * Now figure out how the gmode bit has to be 2640 * set to support it. */ 2641 if (phymode == B43_PHYMODE_A) 2642 *gmode = 0; 2643 else 2644 *gmode = 1; 2645 *dev = d; 2646 2647 return 0; 2648 } 2649 } 2650 2651 return -ESRCH; 2652} 2653 2654static void b43_put_phy_into_reset(struct b43_wldev *dev) 2655{ 2656 struct ssb_device *sdev = dev->dev; 2657 u32 tmslow; 2658 2659 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2660 tmslow &= ~B43_TMSLOW_GMODE; 2661 tmslow |= B43_TMSLOW_PHYRESET; 2662 tmslow |= SSB_TMSLOW_FGC; 2663 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2664 msleep(1); 2665 2666 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2667 tmslow &= ~SSB_TMSLOW_FGC; 2668 tmslow |= B43_TMSLOW_PHYRESET; 2669 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2670 msleep(1); 2671} 2672 2673/* Expects wl->mutex locked */ 2674static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode) 2675{ 2676 struct b43_wldev *up_dev; 2677 struct b43_wldev *down_dev; 2678 int err; 2679 bool gmode = 0; 2680 int prev_status; 2681 2682 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode); 2683 if (err) { 2684 b43err(wl, "Could not find a device for %s-PHY mode\n", 2685 phymode_to_string(new_mode)); 2686 return err; 2687 } 2688 if ((up_dev == wl->current_dev) && 2689 (!!wl->current_dev->phy.gmode == !!gmode)) { 2690 /* This device is already running. */ 2691 return 0; 2692 } 2693 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n", 2694 phymode_to_string(new_mode)); 2695 down_dev = wl->current_dev; 2696 2697 prev_status = b43_status(down_dev); 2698 /* Shutdown the currently running core. */ 2699 if (prev_status >= B43_STAT_STARTED) 2700 b43_wireless_core_stop(down_dev); 2701 if (prev_status >= B43_STAT_INITIALIZED) 2702 b43_wireless_core_exit(down_dev); 2703 2704 if (down_dev != up_dev) { 2705 /* We switch to a different core, so we put PHY into 2706 * RESET on the old core. */ 2707 b43_put_phy_into_reset(down_dev); 2708 } 2709 2710 /* Now start the new core. */ 2711 up_dev->phy.gmode = gmode; 2712 if (prev_status >= B43_STAT_INITIALIZED) { 2713 err = b43_wireless_core_init(up_dev); 2714 if (err) { 2715 b43err(wl, "Fatal: Could not initialize device for " 2716 "newly selected %s-PHY mode\n", 2717 phymode_to_string(new_mode)); 2718 goto init_failure; 2719 } 2720 } 2721 if (prev_status >= B43_STAT_STARTED) { 2722 err = b43_wireless_core_start(up_dev); 2723 if (err) { 2724 b43err(wl, "Fatal: Coult not start device for " 2725 "newly selected %s-PHY mode\n", 2726 phymode_to_string(new_mode)); 2727 b43_wireless_core_exit(up_dev); 2728 goto init_failure; 2729 } 2730 } 2731 B43_WARN_ON(b43_status(up_dev) != prev_status); 2732 2733 wl->current_dev = up_dev; 2734 2735 return 0; 2736 init_failure: 2737 /* Whoops, failed to init the new core. No core is operating now. */ 2738 wl->current_dev = NULL; 2739 return err; 2740} 2741 2742/* Check if the use of the antenna that ieee80211 told us to 2743 * use is possible. This will fall back to DEFAULT. 2744 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 2745u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 2746 u8 antenna_nr) 2747{ 2748 u8 antenna_mask; 2749 2750 if (antenna_nr == 0) { 2751 /* Zero means "use default antenna". That's always OK. */ 2752 return 0; 2753 } 2754 2755 /* Get the mask of available antennas. */ 2756 if (dev->phy.gmode) 2757 antenna_mask = dev->dev->bus->sprom.ant_available_bg; 2758 else 2759 antenna_mask = dev->dev->bus->sprom.ant_available_a; 2760 2761 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 2762 /* This antenna is not available. Fall back to default. */ 2763 return 0; 2764 } 2765 2766 return antenna_nr; 2767} 2768 2769static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna) 2770{ 2771 antenna = b43_ieee80211_antenna_sanitize(dev, antenna); 2772 switch (antenna) { 2773 case 0: /* default/diversity */ 2774 return B43_ANTENNA_DEFAULT; 2775 case 1: /* Antenna 0 */ 2776 return B43_ANTENNA0; 2777 case 2: /* Antenna 1 */ 2778 return B43_ANTENNA1; 2779 case 3: /* Antenna 2 */ 2780 return B43_ANTENNA2; 2781 case 4: /* Antenna 3 */ 2782 return B43_ANTENNA3; 2783 default: 2784 return B43_ANTENNA_DEFAULT; 2785 } 2786} 2787 2788static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) 2789{ 2790 struct b43_wl *wl = hw_to_b43_wl(hw); 2791 struct b43_wldev *dev; 2792 struct b43_phy *phy; 2793 unsigned long flags; 2794 unsigned int new_phymode = 0xFFFF; 2795 int antenna; 2796 int err = 0; 2797 u32 savedirqs; 2798 2799 mutex_lock(&wl->mutex); 2800 2801 /* Switch the PHY mode (if necessary). */ 2802 switch (conf->phymode) { 2803 case MODE_IEEE80211A: 2804 new_phymode = B43_PHYMODE_A; 2805 break; 2806 case MODE_IEEE80211B: 2807 new_phymode = B43_PHYMODE_B; 2808 break; 2809 case MODE_IEEE80211G: 2810 new_phymode = B43_PHYMODE_G; 2811 break; 2812 default: 2813 B43_WARN_ON(1); 2814 } 2815 err = b43_switch_phymode(wl, new_phymode); 2816 if (err) 2817 goto out_unlock_mutex; 2818 dev = wl->current_dev; 2819 phy = &dev->phy; 2820 2821 /* Disable IRQs while reconfiguring the device. 2822 * This makes it possible to drop the spinlock throughout 2823 * the reconfiguration process. */ 2824 spin_lock_irqsave(&wl->irq_lock, flags); 2825 if (b43_status(dev) < B43_STAT_STARTED) { 2826 spin_unlock_irqrestore(&wl->irq_lock, flags); 2827 goto out_unlock_mutex; 2828 } 2829 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL); 2830 spin_unlock_irqrestore(&wl->irq_lock, flags); 2831 b43_synchronize_irq(dev); 2832 2833 /* Switch to the requested channel. 2834 * The firmware takes care of races with the TX handler. */ 2835 if (conf->channel_val != phy->channel) 2836 b43_radio_selectchannel(dev, conf->channel_val, 0); 2837 2838 /* Enable/Disable ShortSlot timing. */ 2839 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != 2840 dev->short_slot) { 2841 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2842 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) 2843 b43_short_slot_timing_enable(dev); 2844 else 2845 b43_short_slot_timing_disable(dev); 2846 } 2847 2848 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP); 2849 2850 /* Adjust the desired TX power level. */ 2851 if (conf->power_level != 0) { 2852 if (conf->power_level != phy->power_level) { 2853 phy->power_level = conf->power_level; 2854 b43_phy_xmitpower(dev); 2855 } 2856 } 2857 2858 /* Antennas for RX and management frame TX. */ 2859 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx); 2860 b43_mgmtframe_txantenna(dev, antenna); 2861 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx); 2862 b43_set_rx_antenna(dev, antenna); 2863 2864 /* Update templates for AP mode. */ 2865 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2866 b43_set_beacon_int(dev, conf->beacon_int); 2867 2868 if (!!conf->radio_enabled != phy->radio_on) { 2869 if (conf->radio_enabled) { 2870 b43_radio_turn_on(dev); 2871 b43info(dev->wl, "Radio turned on by software\n"); 2872 if (!dev->radio_hw_enable) { 2873 b43info(dev->wl, "The hardware RF-kill button " 2874 "still turns the radio physically off. " 2875 "Press the button to turn it on.\n"); 2876 } 2877 } else { 2878 b43_radio_turn_off(dev, 0); 2879 b43info(dev->wl, "Radio turned off by software\n"); 2880 } 2881 } 2882 2883 spin_lock_irqsave(&wl->irq_lock, flags); 2884 b43_interrupt_enable(dev, savedirqs); 2885 mmiowb(); 2886 spin_unlock_irqrestore(&wl->irq_lock, flags); 2887 out_unlock_mutex: 2888 mutex_unlock(&wl->mutex); 2889 2890 return err; 2891} 2892 2893static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 2894 const u8 *local_addr, const u8 *addr, 2895 struct ieee80211_key_conf *key) 2896{ 2897 struct b43_wl *wl = hw_to_b43_wl(hw); 2898 struct b43_wldev *dev; 2899 unsigned long flags; 2900 u8 algorithm; 2901 u8 index; 2902 int err; 2903 DECLARE_MAC_BUF(mac); 2904 2905 if (modparam_nohwcrypt) 2906 return -ENOSPC; /* User disabled HW-crypto */ 2907 2908 mutex_lock(&wl->mutex); 2909 spin_lock_irqsave(&wl->irq_lock, flags); 2910 2911 dev = wl->current_dev; 2912 err = -ENODEV; 2913 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 2914 goto out_unlock; 2915 2916 err = -EINVAL; 2917 switch (key->alg) { 2918 case ALG_WEP: 2919 if (key->keylen == 5) 2920 algorithm = B43_SEC_ALGO_WEP40; 2921 else 2922 algorithm = B43_SEC_ALGO_WEP104; 2923 break; 2924 case ALG_TKIP: 2925 algorithm = B43_SEC_ALGO_TKIP; 2926 break; 2927 case ALG_CCMP: 2928 algorithm = B43_SEC_ALGO_AES; 2929 break; 2930 default: 2931 B43_WARN_ON(1); 2932 goto out_unlock; 2933 } 2934 index = (u8) (key->keyidx); 2935 if (index > 3) 2936 goto out_unlock; 2937 2938 switch (cmd) { 2939 case SET_KEY: 2940 if (algorithm == B43_SEC_ALGO_TKIP) { 2941 /* FIXME: No TKIP hardware encryption for now. */ 2942 err = -EOPNOTSUPP; 2943 goto out_unlock; 2944 } 2945 2946 if (is_broadcast_ether_addr(addr)) { 2947 /* addr is FF:FF:FF:FF:FF:FF for default keys */ 2948 err = b43_key_write(dev, index, algorithm, 2949 key->key, key->keylen, NULL, key); 2950 } else { 2951 /* 2952 * either pairwise key or address is 00:00:00:00:00:00 2953 * for transmit-only keys 2954 */ 2955 err = b43_key_write(dev, -1, algorithm, 2956 key->key, key->keylen, addr, key); 2957 } 2958 if (err) 2959 goto out_unlock; 2960 2961 if (algorithm == B43_SEC_ALGO_WEP40 || 2962 algorithm == B43_SEC_ALGO_WEP104) { 2963 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 2964 } else { 2965 b43_hf_write(dev, 2966 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 2967 } 2968 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 2969 break; 2970 case DISABLE_KEY: { 2971 err = b43_key_clear(dev, key->hw_key_idx); 2972 if (err) 2973 goto out_unlock; 2974 break; 2975 } 2976 default: 2977 B43_WARN_ON(1); 2978 } 2979out_unlock: 2980 spin_unlock_irqrestore(&wl->irq_lock, flags); 2981 mutex_unlock(&wl->mutex); 2982 if (!err) { 2983 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 2984 "mac: %s\n", 2985 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 2986 print_mac(mac, addr)); 2987 } 2988 return err; 2989} 2990 2991static void b43_op_configure_filter(struct ieee80211_hw *hw, 2992 unsigned int changed, unsigned int *fflags, 2993 int mc_count, struct dev_addr_list *mc_list) 2994{ 2995 struct b43_wl *wl = hw_to_b43_wl(hw); 2996 struct b43_wldev *dev = wl->current_dev; 2997 unsigned long flags; 2998 2999 if (!dev) { 3000 *fflags = 0; 3001 return; 3002 } 3003 3004 spin_lock_irqsave(&wl->irq_lock, flags); 3005 *fflags &= FIF_PROMISC_IN_BSS | 3006 FIF_ALLMULTI | 3007 FIF_FCSFAIL | 3008 FIF_PLCPFAIL | 3009 FIF_CONTROL | 3010 FIF_OTHER_BSS | 3011 FIF_BCN_PRBRESP_PROMISC; 3012 3013 changed &= FIF_PROMISC_IN_BSS | 3014 FIF_ALLMULTI | 3015 FIF_FCSFAIL | 3016 FIF_PLCPFAIL | 3017 FIF_CONTROL | 3018 FIF_OTHER_BSS | 3019 FIF_BCN_PRBRESP_PROMISC; 3020 3021 wl->filter_flags = *fflags; 3022 3023 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 3024 b43_adjust_opmode(dev); 3025 spin_unlock_irqrestore(&wl->irq_lock, flags); 3026} 3027 3028static int b43_op_config_interface(struct ieee80211_hw *hw, 3029 struct ieee80211_vif *vif, 3030 struct ieee80211_if_conf *conf) 3031{ 3032 struct b43_wl *wl = hw_to_b43_wl(hw); 3033 struct b43_wldev *dev = wl->current_dev; 3034 unsigned long flags; 3035 3036 if (!dev) 3037 return -ENODEV; 3038 mutex_lock(&wl->mutex); 3039 spin_lock_irqsave(&wl->irq_lock, flags); 3040 B43_WARN_ON(wl->vif != vif); 3041 if (conf->bssid) 3042 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3043 else 3044 memset(wl->bssid, 0, ETH_ALEN); 3045 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3046 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) { 3047 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); 3048 b43_set_ssid(dev, conf->ssid, conf->ssid_len); 3049 if (conf->beacon) 3050 b43_update_templates(wl, conf->beacon); 3051 } 3052 b43_write_mac_bssid_templates(dev); 3053 } 3054 spin_unlock_irqrestore(&wl->irq_lock, flags); 3055 mutex_unlock(&wl->mutex); 3056 3057 return 0; 3058} 3059 3060/* Locking: wl->mutex */ 3061static void b43_wireless_core_stop(struct b43_wldev *dev) 3062{ 3063 struct b43_wl *wl = dev->wl; 3064 unsigned long flags; 3065 3066 if (b43_status(dev) < B43_STAT_STARTED) 3067 return; 3068 3069 /* Disable and sync interrupts. We must do this before than 3070 * setting the status to INITIALIZED, as the interrupt handler 3071 * won't care about IRQs then. */ 3072 spin_lock_irqsave(&wl->irq_lock, flags); 3073 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 3074 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */ 3075 spin_unlock_irqrestore(&wl->irq_lock, flags); 3076 b43_synchronize_irq(dev); 3077 3078 b43_set_status(dev, B43_STAT_INITIALIZED); 3079 3080 mutex_unlock(&wl->mutex); 3081 /* Must unlock as it would otherwise deadlock. No races here. 3082 * Cancel the possibly running self-rearming periodic work. */ 3083 cancel_delayed_work_sync(&dev->periodic_work); 3084 mutex_lock(&wl->mutex); 3085 3086 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy. 3087 3088 b43_mac_suspend(dev); 3089 free_irq(dev->dev->irq, dev); 3090 b43dbg(wl, "Wireless interface stopped\n"); 3091} 3092 3093/* Locking: wl->mutex */ 3094static int b43_wireless_core_start(struct b43_wldev *dev) 3095{ 3096 int err; 3097 3098 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 3099 3100 drain_txstatus_queue(dev); 3101 err = request_irq(dev->dev->irq, b43_interrupt_handler, 3102 IRQF_SHARED, KBUILD_MODNAME, dev); 3103 if (err) { 3104 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); 3105 goto out; 3106 } 3107 3108 /* We are ready to run. */ 3109 b43_set_status(dev, B43_STAT_STARTED); 3110 3111 /* Start data flow (TX/RX). */ 3112 b43_mac_enable(dev); 3113 b43_interrupt_enable(dev, dev->irq_savedstate); 3114 ieee80211_start_queues(dev->wl->hw); 3115 3116 /* Start maintainance work */ 3117 b43_periodic_tasks_setup(dev); 3118 3119 b43dbg(dev->wl, "Wireless interface started\n"); 3120 out: 3121 return err; 3122} 3123 3124/* Get PHY and RADIO versioning numbers */ 3125static int b43_phy_versioning(struct b43_wldev *dev) 3126{ 3127 struct b43_phy *phy = &dev->phy; 3128 u32 tmp; 3129 u8 analog_type; 3130 u8 phy_type; 3131 u8 phy_rev; 3132 u16 radio_manuf; 3133 u16 radio_ver; 3134 u16 radio_rev; 3135 int unsupported = 0; 3136 3137 /* Get PHY versioning */ 3138 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 3139 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 3140 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 3141 phy_rev = (tmp & B43_PHYVER_VERSION); 3142 switch (phy_type) { 3143 case B43_PHYTYPE_A: 3144 if (phy_rev >= 4) 3145 unsupported = 1; 3146 break; 3147 case B43_PHYTYPE_B: 3148 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 3149 && phy_rev != 7) 3150 unsupported = 1; 3151 break; 3152 case B43_PHYTYPE_G: 3153 if (phy_rev > 9) 3154 unsupported = 1; 3155 break; 3156#ifdef CONFIG_B43_NPHY 3157 case B43_PHYTYPE_N: 3158 if (phy_rev > 1) 3159 unsupported = 1; 3160 break; 3161#endif 3162 default: 3163 unsupported = 1; 3164 }; 3165 if (unsupported) { 3166 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 3167 "(Analog %u, Type %u, Revision %u)\n", 3168 analog_type, phy_type, phy_rev); 3169 return -EOPNOTSUPP; 3170 } 3171 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 3172 analog_type, phy_type, phy_rev); 3173 3174 /* Get RADIO versioning */ 3175 if (dev->dev->bus->chip_id == 0x4317) { 3176 if (dev->dev->bus->chip_rev == 0) 3177 tmp = 0x3205017F; 3178 else if (dev->dev->bus->chip_rev == 1) 3179 tmp = 0x4205017F; 3180 else 3181 tmp = 0x5205017F; 3182 } else { 3183 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3184 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3185 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3186 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; 3187 } 3188 radio_manuf = (tmp & 0x00000FFF); 3189 radio_ver = (tmp & 0x0FFFF000) >> 12; 3190 radio_rev = (tmp & 0xF0000000) >> 28; 3191 if (radio_manuf != 0x17F /* Broadcom */) 3192 unsupported = 1; 3193 switch (phy_type) { 3194 case B43_PHYTYPE_A: 3195 if (radio_ver != 0x2060) 3196 unsupported = 1; 3197 if (radio_rev != 1) 3198 unsupported = 1; 3199 if (radio_manuf != 0x17F) 3200 unsupported = 1; 3201 break; 3202 case B43_PHYTYPE_B: 3203 if ((radio_ver & 0xFFF0) != 0x2050) 3204 unsupported = 1; 3205 break; 3206 case B43_PHYTYPE_G: 3207 if (radio_ver != 0x2050) 3208 unsupported = 1; 3209 break; 3210 case B43_PHYTYPE_N: 3211 if (radio_ver != 0x2055) 3212 unsupported = 1; 3213 break; 3214 default: 3215 B43_WARN_ON(1); 3216 } 3217 if (unsupported) { 3218 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 3219 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 3220 radio_manuf, radio_ver, radio_rev); 3221 return -EOPNOTSUPP; 3222 } 3223 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 3224 radio_manuf, radio_ver, radio_rev); 3225 3226 phy->radio_manuf = radio_manuf; 3227 phy->radio_ver = radio_ver; 3228 phy->radio_rev = radio_rev; 3229 3230 phy->analog = analog_type; 3231 phy->type = phy_type; 3232 phy->rev = phy_rev; 3233 3234 return 0; 3235} 3236 3237static void setup_struct_phy_for_init(struct b43_wldev *dev, 3238 struct b43_phy *phy) 3239{ 3240 struct b43_txpower_lo_control *lo; 3241 int i; 3242 3243 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); 3244 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); 3245 3246 phy->aci_enable = 0; 3247 phy->aci_wlan_automatic = 0; 3248 phy->aci_hw_rssi = 0; 3249 3250 phy->radio_off_context.valid = 0; 3251 3252 lo = phy->lo_control; 3253 if (lo) { 3254 memset(lo, 0, sizeof(*(phy->lo_control))); 3255 lo->rebuild = 1; 3256 lo->tx_bias = 0xFF; 3257 } 3258 phy->max_lb_gain = 0; 3259 phy->trsw_rx_gain = 0; 3260 phy->txpwr_offset = 0; 3261 3262 /* NRSSI */ 3263 phy->nrssislope = 0; 3264 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) 3265 phy->nrssi[i] = -1000; 3266 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) 3267 phy->nrssi_lt[i] = i; 3268 3269 phy->lofcal = 0xFFFF; 3270 phy->initval = 0xFFFF; 3271 3272 phy->interfmode = B43_INTERFMODE_NONE; 3273 phy->channel = 0xFF; 3274 3275 phy->hardware_power_control = !!modparam_hwpctl; 3276 3277 /* PHY TX errors counter. */ 3278 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3279 3280 /* OFDM-table address caching. */ 3281 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN; 3282} 3283 3284static void setup_struct_wldev_for_init(struct b43_wldev *dev) 3285{ 3286 dev->dfq_valid = 0; 3287 3288 /* Assume the radio is enabled. If it's not enabled, the state will 3289 * immediately get fixed on the first periodic work run. */ 3290 dev->radio_hw_enable = 1; 3291 3292 /* Stats */ 3293 memset(&dev->stats, 0, sizeof(dev->stats)); 3294 3295 setup_struct_phy_for_init(dev, &dev->phy); 3296 3297 /* IRQ related flags */ 3298 dev->irq_reason = 0; 3299 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 3300 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE; 3301 3302 dev->mac_suspended = 1; 3303 3304 /* Noise calculation context */ 3305 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 3306} 3307 3308static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 3309{ 3310 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 3311 u32 hf; 3312 3313 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 3314 return; 3315 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 3316 return; 3317 3318 hf = b43_hf_read(dev); 3319 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 3320 hf |= B43_HF_BTCOEXALT; 3321 else 3322 hf |= B43_HF_BTCOEX; 3323 b43_hf_write(dev, hf); 3324 //TODO 3325} 3326 3327static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 3328{ //TODO 3329} 3330 3331static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 3332{ 3333#ifdef CONFIG_SSB_DRIVER_PCICORE 3334 struct ssb_bus *bus = dev->dev->bus; 3335 u32 tmp; 3336 3337 if (bus->pcicore.dev && 3338 bus->pcicore.dev->id.coreid == SSB_DEV_PCI && 3339 bus->pcicore.dev->id.revision <= 5) { 3340 /* IMCFGLO timeouts workaround. */ 3341 tmp = ssb_read32(dev->dev, SSB_IMCFGLO); 3342 tmp &= ~SSB_IMCFGLO_REQTO; 3343 tmp &= ~SSB_IMCFGLO_SERTO; 3344 switch (bus->bustype) { 3345 case SSB_BUSTYPE_PCI: 3346 case SSB_BUSTYPE_PCMCIA: 3347 tmp |= 0x32; 3348 break; 3349 case SSB_BUSTYPE_SSB: 3350 tmp |= 0x53; 3351 break; 3352 } 3353 ssb_write32(dev->dev, SSB_IMCFGLO, tmp); 3354 } 3355#endif /* CONFIG_SSB_DRIVER_PCICORE */ 3356} 3357 3358/* Write the short and long frame retry limit values. */ 3359static void b43_set_retry_limits(struct b43_wldev *dev, 3360 unsigned int short_retry, 3361 unsigned int long_retry) 3362{ 3363 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3364 * the chip-internal counter. */ 3365 short_retry = min(short_retry, (unsigned int)0xF); 3366 long_retry = min(long_retry, (unsigned int)0xF); 3367 3368 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3369 short_retry); 3370 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3371 long_retry); 3372} 3373 3374/* Shutdown a wireless core */ 3375/* Locking: wl->mutex */ 3376static void b43_wireless_core_exit(struct b43_wldev *dev) 3377{ 3378 struct b43_phy *phy = &dev->phy; 3379 3380 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED); 3381 if (b43_status(dev) != B43_STAT_INITIALIZED) 3382 return; 3383 b43_set_status(dev, B43_STAT_UNINIT); 3384 3385 b43_leds_exit(dev); 3386 b43_rng_exit(dev->wl); 3387 b43_dma_free(dev); 3388 b43_chip_exit(dev); 3389 b43_radio_turn_off(dev, 1); 3390 b43_switch_analog(dev, 0); 3391 if (phy->dyn_tssi_tbl) 3392 kfree(phy->tssi2dbm); 3393 kfree(phy->lo_control); 3394 phy->lo_control = NULL; 3395 if (dev->wl->current_beacon) { 3396 dev_kfree_skb_any(dev->wl->current_beacon); 3397 dev->wl->current_beacon = NULL; 3398 } 3399 3400 ssb_device_disable(dev->dev, 0); 3401 ssb_bus_may_powerdown(dev->dev->bus); 3402} 3403 3404/* Initialize a wireless core */ 3405static int b43_wireless_core_init(struct b43_wldev *dev) 3406{ 3407 struct b43_wl *wl = dev->wl; 3408 struct ssb_bus *bus = dev->dev->bus; 3409 struct ssb_sprom *sprom = &bus->sprom; 3410 struct b43_phy *phy = &dev->phy; 3411 int err; 3412 u32 hf, tmp; 3413 3414 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3415 3416 err = ssb_bus_powerup(bus, 0); 3417 if (err) 3418 goto out; 3419 if (!ssb_device_is_enabled(dev->dev)) { 3420 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 3421 b43_wireless_core_reset(dev, tmp); 3422 } 3423 3424 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) { 3425 phy->lo_control = 3426 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL); 3427 if (!phy->lo_control) { 3428 err = -ENOMEM; 3429 goto err_busdown; 3430 } 3431 } 3432 setup_struct_wldev_for_init(dev); 3433 3434 err = b43_phy_init_tssi2dbm_table(dev); 3435 if (err) 3436 goto err_kfree_lo_control; 3437 3438 /* Enable IRQ routing to this device. */ 3439 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 3440 3441 b43_imcfglo_timeouts_workaround(dev); 3442 b43_bluetooth_coext_disable(dev); 3443 b43_phy_early_init(dev); 3444 err = b43_chip_init(dev); 3445 if (err) 3446 goto err_kfree_tssitbl; 3447 b43_shm_write16(dev, B43_SHM_SHARED, 3448 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 3449 hf = b43_hf_read(dev); 3450 if (phy->type == B43_PHYTYPE_G) { 3451 hf |= B43_HF_SYMW; 3452 if (phy->rev == 1) 3453 hf |= B43_HF_GDCW; 3454 if (sprom->boardflags_lo & B43_BFL_PACTRL) 3455 hf |= B43_HF_OFDMPABOOST; 3456 } else if (phy->type == B43_PHYTYPE_B) { 3457 hf |= B43_HF_SYMW; 3458 if (phy->rev >= 2 && phy->radio_ver == 0x2050) 3459 hf &= ~B43_HF_GDCW; 3460 } 3461 b43_hf_write(dev, hf); 3462 3463 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 3464 B43_DEFAULT_LONG_RETRY_LIMIT); 3465 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 3466 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 3467 3468 /* Disable sending probe responses from firmware. 3469 * Setting the MaxTime to one usec will always trigger 3470 * a timeout, so we never send any probe resp. 3471 * A timeout of zero is infinite. */ 3472 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 3473 3474 b43_rate_memory_init(dev); 3475 3476 /* Minimum Contention Window */ 3477 if (phy->type == B43_PHYTYPE_B) { 3478 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 3479 } else { 3480 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 3481 } 3482 /* Maximum Contention Window */ 3483 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 3484 3485 err = b43_dma_init(dev); 3486 if (err) 3487 goto err_chip_exit; 3488 b43_qos_init(dev); 3489 3490//FIXME 3491#if 1 3492 b43_write16(dev, 0x0612, 0x0050); 3493 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050); 3494 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4); 3495#endif 3496 3497 b43_bluetooth_coext_enable(dev); 3498 3499 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */ 3500 memset(wl->bssid, 0, ETH_ALEN); 3501 memset(wl->mac_addr, 0, ETH_ALEN); 3502 b43_upload_card_macaddress(dev); 3503 b43_security_init(dev); 3504 b43_rng_init(wl); 3505 3506 b43_set_status(dev, B43_STAT_INITIALIZED); 3507 3508 b43_leds_init(dev); 3509out: 3510 return err; 3511 3512 err_chip_exit: 3513 b43_chip_exit(dev); 3514 err_kfree_tssitbl: 3515 if (phy->dyn_tssi_tbl) 3516 kfree(phy->tssi2dbm); 3517 err_kfree_lo_control: 3518 kfree(phy->lo_control); 3519 phy->lo_control = NULL; 3520 err_busdown: 3521 ssb_bus_may_powerdown(bus); 3522 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3523 return err; 3524} 3525 3526static int b43_op_add_interface(struct ieee80211_hw *hw, 3527 struct ieee80211_if_init_conf *conf) 3528{ 3529 struct b43_wl *wl = hw_to_b43_wl(hw); 3530 struct b43_wldev *dev; 3531 unsigned long flags; 3532 int err = -EOPNOTSUPP; 3533 3534 /* TODO: allow WDS/AP devices to coexist */ 3535 3536 if (conf->type != IEEE80211_IF_TYPE_AP && 3537 conf->type != IEEE80211_IF_TYPE_STA && 3538 conf->type != IEEE80211_IF_TYPE_WDS && 3539 conf->type != IEEE80211_IF_TYPE_IBSS) 3540 return -EOPNOTSUPP; 3541 3542 mutex_lock(&wl->mutex); 3543 if (wl->operating) 3544 goto out_mutex_unlock; 3545 3546 b43dbg(wl, "Adding Interface type %d\n", conf->type); 3547 3548 dev = wl->current_dev; 3549 wl->operating = 1; 3550 wl->vif = conf->vif; 3551 wl->if_type = conf->type; 3552 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN); 3553 3554 spin_lock_irqsave(&wl->irq_lock, flags); 3555 b43_adjust_opmode(dev); 3556 b43_upload_card_macaddress(dev); 3557 spin_unlock_irqrestore(&wl->irq_lock, flags); 3558 3559 err = 0; 3560 out_mutex_unlock: 3561 mutex_unlock(&wl->mutex); 3562 3563 return err; 3564} 3565 3566static void b43_op_remove_interface(struct ieee80211_hw *hw, 3567 struct ieee80211_if_init_conf *conf) 3568{ 3569 struct b43_wl *wl = hw_to_b43_wl(hw); 3570 struct b43_wldev *dev = wl->current_dev; 3571 unsigned long flags; 3572 3573 b43dbg(wl, "Removing Interface type %d\n", conf->type); 3574 3575 mutex_lock(&wl->mutex); 3576 3577 B43_WARN_ON(!wl->operating); 3578 B43_WARN_ON(wl->vif != conf->vif); 3579 wl->vif = NULL; 3580 3581 wl->operating = 0; 3582 3583 spin_lock_irqsave(&wl->irq_lock, flags); 3584 b43_adjust_opmode(dev); 3585 memset(wl->mac_addr, 0, ETH_ALEN); 3586 b43_upload_card_macaddress(dev); 3587 spin_unlock_irqrestore(&wl->irq_lock, flags); 3588 3589 mutex_unlock(&wl->mutex); 3590} 3591 3592static int b43_op_start(struct ieee80211_hw *hw) 3593{ 3594 struct b43_wl *wl = hw_to_b43_wl(hw); 3595 struct b43_wldev *dev = wl->current_dev; 3596 int did_init = 0; 3597 int err = 0; 3598 3599 /* First register RFkill. 3600 * LEDs that are registered later depend on it. */ 3601 b43_rfkill_init(dev); 3602 3603 mutex_lock(&wl->mutex); 3604 3605 if (b43_status(dev) < B43_STAT_INITIALIZED) { 3606 err = b43_wireless_core_init(dev); 3607 if (err) 3608 goto out_mutex_unlock; 3609 did_init = 1; 3610 } 3611 3612 if (b43_status(dev) < B43_STAT_STARTED) { 3613 err = b43_wireless_core_start(dev); 3614 if (err) { 3615 if (did_init) 3616 b43_wireless_core_exit(dev); 3617 goto out_mutex_unlock; 3618 } 3619 } 3620 3621 out_mutex_unlock: 3622 mutex_unlock(&wl->mutex); 3623 3624 return err; 3625} 3626 3627static void b43_op_stop(struct ieee80211_hw *hw) 3628{ 3629 struct b43_wl *wl = hw_to_b43_wl(hw); 3630 struct b43_wldev *dev = wl->current_dev; 3631 3632 b43_rfkill_exit(dev); 3633 3634 mutex_lock(&wl->mutex); 3635 if (b43_status(dev) >= B43_STAT_STARTED) 3636 b43_wireless_core_stop(dev); 3637 b43_wireless_core_exit(dev); 3638 mutex_unlock(&wl->mutex); 3639} 3640 3641static int b43_op_set_retry_limit(struct ieee80211_hw *hw, 3642 u32 short_retry_limit, u32 long_retry_limit) 3643{ 3644 struct b43_wl *wl = hw_to_b43_wl(hw); 3645 struct b43_wldev *dev; 3646 int err = 0; 3647 3648 mutex_lock(&wl->mutex); 3649 dev = wl->current_dev; 3650 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) { 3651 err = -ENODEV; 3652 goto out_unlock; 3653 } 3654 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit); 3655out_unlock: 3656 mutex_unlock(&wl->mutex); 3657 3658 return err; 3659} 3660 3661static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set) 3662{ 3663 struct b43_wl *wl = hw_to_b43_wl(hw); 3664 struct sk_buff *beacon; 3665 unsigned long flags; 3666 3667 /* We could modify the existing beacon and set the aid bit in 3668 * the TIM field, but that would probably require resizing and 3669 * moving of data within the beacon template. 3670 * Simply request a new beacon and let mac80211 do the hard work. */ 3671 beacon = ieee80211_beacon_get(hw, wl->vif, NULL); 3672 if (unlikely(!beacon)) 3673 return -ENOMEM; 3674 spin_lock_irqsave(&wl->irq_lock, flags); 3675 b43_update_templates(wl, beacon); 3676 spin_unlock_irqrestore(&wl->irq_lock, flags); 3677 3678 return 0; 3679} 3680 3681static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw, 3682 struct sk_buff *beacon, 3683 struct ieee80211_tx_control *ctl) 3684{ 3685 struct b43_wl *wl = hw_to_b43_wl(hw); 3686 unsigned long flags; 3687 3688 spin_lock_irqsave(&wl->irq_lock, flags); 3689 b43_update_templates(wl, beacon); 3690 spin_unlock_irqrestore(&wl->irq_lock, flags); 3691 3692 return 0; 3693} 3694 3695static const struct ieee80211_ops b43_hw_ops = { 3696 .tx = b43_op_tx, 3697 .conf_tx = b43_op_conf_tx, 3698 .add_interface = b43_op_add_interface, 3699 .remove_interface = b43_op_remove_interface, 3700 .config = b43_op_config, 3701 .config_interface = b43_op_config_interface, 3702 .configure_filter = b43_op_configure_filter, 3703 .set_key = b43_op_set_key, 3704 .get_stats = b43_op_get_stats, 3705 .get_tx_stats = b43_op_get_tx_stats, 3706 .start = b43_op_start, 3707 .stop = b43_op_stop, 3708 .set_retry_limit = b43_op_set_retry_limit, 3709 .set_tim = b43_op_beacon_set_tim, 3710 .beacon_update = b43_op_ibss_beacon_update, 3711}; 3712 3713/* Hard-reset the chip. Do not call this directly. 3714 * Use b43_controller_restart() 3715 */ 3716static void b43_chip_reset(struct work_struct *work) 3717{ 3718 struct b43_wldev *dev = 3719 container_of(work, struct b43_wldev, restart_work); 3720 struct b43_wl *wl = dev->wl; 3721 int err = 0; 3722 int prev_status; 3723 3724 mutex_lock(&wl->mutex); 3725 3726 prev_status = b43_status(dev); 3727 /* Bring the device down... */ 3728 if (prev_status >= B43_STAT_STARTED) 3729 b43_wireless_core_stop(dev); 3730 if (prev_status >= B43_STAT_INITIALIZED) 3731 b43_wireless_core_exit(dev); 3732 3733 /* ...and up again. */ 3734 if (prev_status >= B43_STAT_INITIALIZED) { 3735 err = b43_wireless_core_init(dev); 3736 if (err) 3737 goto out; 3738 } 3739 if (prev_status >= B43_STAT_STARTED) { 3740 err = b43_wireless_core_start(dev); 3741 if (err) { 3742 b43_wireless_core_exit(dev); 3743 goto out; 3744 } 3745 } 3746 out: 3747 mutex_unlock(&wl->mutex); 3748 if (err) 3749 b43err(wl, "Controller restart FAILED\n"); 3750 else 3751 b43info(wl, "Controller restarted\n"); 3752} 3753 3754static int b43_setup_modes(struct b43_wldev *dev, 3755 bool have_2ghz_phy, bool have_5ghz_phy) 3756{ 3757 struct ieee80211_hw *hw = dev->wl->hw; 3758 struct ieee80211_hw_mode *mode; 3759 struct b43_phy *phy = &dev->phy; 3760 int err; 3761 3762 /* XXX: This function will go away soon, when mac80211 3763 * band stuff is rewritten. So this is just a hack. 3764 * For now we always claim GPHY mode, as there is no 3765 * support for NPHY and APHY in the device, yet. 3766 * This assumption is OK, as any B, N or A PHY will already 3767 * have died a horrible sanity check death earlier. */ 3768 3769 mode = &phy->hwmodes[0]; 3770 mode->mode = MODE_IEEE80211G; 3771 mode->num_channels = b43_2ghz_chantable_size; 3772 mode->channels = b43_2ghz_chantable; 3773 mode->num_rates = b43_g_ratetable_size; 3774 mode->rates = b43_g_ratetable; 3775 err = ieee80211_register_hwmode(hw, mode); 3776 if (err) 3777 return err; 3778 phy->possible_phymodes |= B43_PHYMODE_G; 3779 3780 return 0; 3781} 3782 3783static void b43_wireless_core_detach(struct b43_wldev *dev) 3784{ 3785 /* We release firmware that late to not be required to re-request 3786 * is all the time when we reinit the core. */ 3787 b43_release_firmware(dev); 3788} 3789 3790static int b43_wireless_core_attach(struct b43_wldev *dev) 3791{ 3792 struct b43_wl *wl = dev->wl; 3793 struct ssb_bus *bus = dev->dev->bus; 3794 struct pci_dev *pdev = bus->host_pci; 3795 int err; 3796 bool have_2ghz_phy = 0, have_5ghz_phy = 0; 3797 u32 tmp; 3798 3799 /* Do NOT do any device initialization here. 3800 * Do it in wireless_core_init() instead. 3801 * This function is for gathering basic information about the HW, only. 3802 * Also some structs may be set up here. But most likely you want to have 3803 * that in core_init(), too. 3804 */ 3805 3806 err = ssb_bus_powerup(bus, 0); 3807 if (err) { 3808 b43err(wl, "Bus powerup failed\n"); 3809 goto out; 3810 } 3811 /* Get the PHY type. */ 3812 if (dev->dev->id.revision >= 5) { 3813 u32 tmshigh; 3814 3815 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 3816 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY); 3817 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY); 3818 } else 3819 B43_WARN_ON(1); 3820 3821 dev->phy.gmode = have_2ghz_phy; 3822 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3823 b43_wireless_core_reset(dev, tmp); 3824 3825 err = b43_phy_versioning(dev); 3826 if (err) 3827 goto err_powerdown; 3828 /* Check if this device supports multiband. */ 3829 if (!pdev || 3830 (pdev->device != 0x4312 && 3831 pdev->device != 0x4319 && pdev->device != 0x4324)) { 3832 /* No multiband support. */ 3833 have_2ghz_phy = 0; 3834 have_5ghz_phy = 0; 3835 switch (dev->phy.type) { 3836 case B43_PHYTYPE_A: 3837 have_5ghz_phy = 1; 3838 break; 3839 case B43_PHYTYPE_G: 3840 case B43_PHYTYPE_N: 3841 have_2ghz_phy = 1; 3842 break; 3843 default: 3844 B43_WARN_ON(1); 3845 } 3846 } 3847 if (dev->phy.type == B43_PHYTYPE_A) { 3848 /* FIXME */ 3849 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 3850 err = -EOPNOTSUPP; 3851 goto err_powerdown; 3852 } 3853 dev->phy.gmode = have_2ghz_phy; 3854 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3855 b43_wireless_core_reset(dev, tmp); 3856 3857 err = b43_validate_chipaccess(dev); 3858 if (err) 3859 goto err_powerdown; 3860 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy); 3861 if (err) 3862 goto err_powerdown; 3863 3864 /* Now set some default "current_dev" */ 3865 if (!wl->current_dev) 3866 wl->current_dev = dev; 3867 INIT_WORK(&dev->restart_work, b43_chip_reset); 3868 3869 b43_radio_turn_off(dev, 1); 3870 b43_switch_analog(dev, 0); 3871 ssb_device_disable(dev->dev, 0); 3872 ssb_bus_may_powerdown(bus); 3873 3874out: 3875 return err; 3876 3877err_powerdown: 3878 ssb_bus_may_powerdown(bus); 3879 return err; 3880} 3881 3882static void b43_one_core_detach(struct ssb_device *dev) 3883{ 3884 struct b43_wldev *wldev; 3885 struct b43_wl *wl; 3886 3887 wldev = ssb_get_drvdata(dev); 3888 wl = wldev->wl; 3889 cancel_work_sync(&wldev->restart_work); 3890 b43_debugfs_remove_device(wldev); 3891 b43_wireless_core_detach(wldev); 3892 list_del(&wldev->list); 3893 wl->nr_devs--; 3894 ssb_set_drvdata(dev, NULL); 3895 kfree(wldev); 3896} 3897 3898static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 3899{ 3900 struct b43_wldev *wldev; 3901 struct pci_dev *pdev; 3902 int err = -ENOMEM; 3903 3904 if (!list_empty(&wl->devlist)) { 3905 /* We are not the first core on this chip. */ 3906 pdev = dev->bus->host_pci; 3907 /* Only special chips support more than one wireless 3908 * core, although some of the other chips have more than 3909 * one wireless core as well. Check for this and 3910 * bail out early. 3911 */ 3912 if (!pdev || 3913 ((pdev->device != 0x4321) && 3914 (pdev->device != 0x4313) && (pdev->device != 0x431A))) { 3915 b43dbg(wl, "Ignoring unconnected 802.11 core\n"); 3916 return -ENODEV; 3917 } 3918 } 3919 3920 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 3921 if (!wldev) 3922 goto out; 3923 3924 wldev->dev = dev; 3925 wldev->wl = wl; 3926 b43_set_status(wldev, B43_STAT_UNINIT); 3927 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 3928 tasklet_init(&wldev->isr_tasklet, 3929 (void (*)(unsigned long))b43_interrupt_tasklet, 3930 (unsigned long)wldev); 3931 INIT_LIST_HEAD(&wldev->list); 3932 3933 err = b43_wireless_core_attach(wldev); 3934 if (err) 3935 goto err_kfree_wldev; 3936 3937 list_add(&wldev->list, &wl->devlist); 3938 wl->nr_devs++; 3939 ssb_set_drvdata(dev, wldev); 3940 b43_debugfs_add_device(wldev); 3941 3942 out: 3943 return err; 3944 3945 err_kfree_wldev: 3946 kfree(wldev); 3947 return err; 3948} 3949 3950static void b43_sprom_fixup(struct ssb_bus *bus) 3951{ 3952 /* boardflags workarounds */ 3953 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 3954 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 3955 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 3956 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3957 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 3958 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 3959} 3960 3961static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 3962{ 3963 struct ieee80211_hw *hw = wl->hw; 3964 3965 ssb_set_devtypedata(dev, NULL); 3966 ieee80211_free_hw(hw); 3967} 3968 3969static int b43_wireless_init(struct ssb_device *dev) 3970{ 3971 struct ssb_sprom *sprom = &dev->bus->sprom; 3972 struct ieee80211_hw *hw; 3973 struct b43_wl *wl; 3974 int err = -ENOMEM; 3975 3976 b43_sprom_fixup(dev->bus); 3977 3978 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 3979 if (!hw) { 3980 b43err(NULL, "Could not allocate ieee80211 device\n"); 3981 goto out; 3982 } 3983 3984 /* fill hw info */ 3985 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 3986 IEEE80211_HW_RX_INCLUDES_FCS; 3987 hw->max_signal = 100; 3988 hw->max_rssi = -110; 3989 hw->max_noise = -110; 3990 hw->queues = 1; /* FIXME: hardware has more queues */ 3991 SET_IEEE80211_DEV(hw, dev->dev); 3992 if (is_valid_ether_addr(sprom->et1mac)) 3993 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 3994 else 3995 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 3996 3997 /* Get and initialize struct b43_wl */ 3998 wl = hw_to_b43_wl(hw); 3999 memset(wl, 0, sizeof(*wl)); 4000 wl->hw = hw; 4001 spin_lock_init(&wl->irq_lock); 4002 spin_lock_init(&wl->leds_lock); 4003 spin_lock_init(&wl->shm_lock); 4004 mutex_init(&wl->mutex); 4005 INIT_LIST_HEAD(&wl->devlist); 4006 4007 ssb_set_devtypedata(dev, wl); 4008 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id); 4009 err = 0; 4010 out: 4011 return err; 4012} 4013 4014static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id) 4015{ 4016 struct b43_wl *wl; 4017 int err; 4018 int first = 0; 4019 4020 wl = ssb_get_devtypedata(dev); 4021 if (!wl) { 4022 /* Probing the first core. Must setup common struct b43_wl */ 4023 first = 1; 4024 err = b43_wireless_init(dev); 4025 if (err) 4026 goto out; 4027 wl = ssb_get_devtypedata(dev); 4028 B43_WARN_ON(!wl); 4029 } 4030 err = b43_one_core_attach(dev, wl); 4031 if (err) 4032 goto err_wireless_exit; 4033 4034 if (first) { 4035 err = ieee80211_register_hw(wl->hw); 4036 if (err) 4037 goto err_one_core_detach; 4038 } 4039 4040 out: 4041 return err; 4042 4043 err_one_core_detach: 4044 b43_one_core_detach(dev); 4045 err_wireless_exit: 4046 if (first) 4047 b43_wireless_exit(dev, wl); 4048 return err; 4049} 4050 4051static void b43_remove(struct ssb_device *dev) 4052{ 4053 struct b43_wl *wl = ssb_get_devtypedata(dev); 4054 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4055 4056 B43_WARN_ON(!wl); 4057 if (wl->current_dev == wldev) 4058 ieee80211_unregister_hw(wl->hw); 4059 4060 b43_one_core_detach(dev); 4061 4062 if (list_empty(&wl->devlist)) { 4063 /* Last core on the chip unregistered. 4064 * We can destroy common struct b43_wl. 4065 */ 4066 b43_wireless_exit(dev, wl); 4067 } 4068} 4069 4070/* Perform a hardware reset. This can be called from any context. */ 4071void b43_controller_restart(struct b43_wldev *dev, const char *reason) 4072{ 4073 /* Must avoid requeueing, if we are in shutdown. */ 4074 if (b43_status(dev) < B43_STAT_INITIALIZED) 4075 return; 4076 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 4077 queue_work(dev->wl->hw->workqueue, &dev->restart_work); 4078} 4079 4080#ifdef CONFIG_PM 4081 4082static int b43_suspend(struct ssb_device *dev, pm_message_t state) 4083{ 4084 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4085 struct b43_wl *wl = wldev->wl; 4086 4087 b43dbg(wl, "Suspending...\n"); 4088 4089 mutex_lock(&wl->mutex); 4090 wldev->suspend_init_status = b43_status(wldev); 4091 if (wldev->suspend_init_status >= B43_STAT_STARTED) 4092 b43_wireless_core_stop(wldev); 4093 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) 4094 b43_wireless_core_exit(wldev); 4095 mutex_unlock(&wl->mutex); 4096 4097 b43dbg(wl, "Device suspended.\n"); 4098 4099 return 0; 4100} 4101 4102static int b43_resume(struct ssb_device *dev) 4103{ 4104 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4105 struct b43_wl *wl = wldev->wl; 4106 int err = 0; 4107 4108 b43dbg(wl, "Resuming...\n"); 4109 4110 mutex_lock(&wl->mutex); 4111 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) { 4112 err = b43_wireless_core_init(wldev); 4113 if (err) { 4114 b43err(wl, "Resume failed at core init\n"); 4115 goto out; 4116 } 4117 } 4118 if (wldev->suspend_init_status >= B43_STAT_STARTED) { 4119 err = b43_wireless_core_start(wldev); 4120 if (err) { 4121 b43_wireless_core_exit(wldev); 4122 b43err(wl, "Resume failed at core start\n"); 4123 goto out; 4124 } 4125 } 4126 mutex_unlock(&wl->mutex); 4127 4128 b43dbg(wl, "Device resumed.\n"); 4129 out: 4130 return err; 4131} 4132 4133#else /* CONFIG_PM */ 4134# define b43_suspend NULL 4135# define b43_resume NULL 4136#endif /* CONFIG_PM */ 4137 4138static struct ssb_driver b43_ssb_driver = { 4139 .name = KBUILD_MODNAME, 4140 .id_table = b43_ssb_tbl, 4141 .probe = b43_probe, 4142 .remove = b43_remove, 4143 .suspend = b43_suspend, 4144 .resume = b43_resume, 4145}; 4146 4147static int __init b43_init(void) 4148{ 4149 int err; 4150 4151 b43_debugfs_init(); 4152 err = b43_pcmcia_init(); 4153 if (err) 4154 goto err_dfs_exit; 4155 err = ssb_driver_register(&b43_ssb_driver); 4156 if (err) 4157 goto err_pcmcia_exit; 4158 4159 return err; 4160 4161err_pcmcia_exit: 4162 b43_pcmcia_exit(); 4163err_dfs_exit: 4164 b43_debugfs_exit(); 4165 return err; 4166} 4167 4168static void __exit b43_exit(void) 4169{ 4170 ssb_driver_unregister(&b43_ssb_driver); 4171 b43_pcmcia_exit(); 4172 b43_debugfs_exit(); 4173} 4174 4175module_init(b43_init) 4176module_exit(b43_exit) 4177