main.c revision 6a461c23e7051d090751a2030e5febf6356c8d57
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 SDIO support 12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> 13 14 Some parts of the code in this file are derived from the ipw2200 15 driver Copyright(c) 2003 - 2004 Intel Corporation. 16 17 This program is free software; you can redistribute it and/or modify 18 it under the terms of the GNU General Public License as published by 19 the Free Software Foundation; either version 2 of the License, or 20 (at your option) any later version. 21 22 This program is distributed in the hope that it will be useful, 23 but WITHOUT ANY WARRANTY; without even the implied warranty of 24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 GNU General Public License for more details. 26 27 You should have received a copy of the GNU General Public License 28 along with this program; see the file COPYING. If not, write to 29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 30 Boston, MA 02110-1301, USA. 31 32*/ 33 34#include <linux/delay.h> 35#include <linux/init.h> 36#include <linux/moduleparam.h> 37#include <linux/if_arp.h> 38#include <linux/etherdevice.h> 39#include <linux/firmware.h> 40#include <linux/workqueue.h> 41#include <linux/skbuff.h> 42#include <linux/io.h> 43#include <linux/dma-mapping.h> 44#include <linux/slab.h> 45#include <asm/unaligned.h> 46 47#include "b43.h" 48#include "main.h" 49#include "debugfs.h" 50#include "phy_common.h" 51#include "phy_g.h" 52#include "phy_n.h" 53#include "dma.h" 54#include "pio.h" 55#include "sysfs.h" 56#include "xmit.h" 57#include "lo.h" 58#include "pcmcia.h" 59#include "sdio.h" 60#include <linux/mmc/sdio_func.h> 61 62MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 63MODULE_AUTHOR("Martin Langer"); 64MODULE_AUTHOR("Stefano Brivio"); 65MODULE_AUTHOR("Michael Buesch"); 66MODULE_AUTHOR("Gábor Stefanik"); 67MODULE_LICENSE("GPL"); 68 69MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID); 70MODULE_FIRMWARE("b43/ucode11.fw"); 71MODULE_FIRMWARE("b43/ucode13.fw"); 72MODULE_FIRMWARE("b43/ucode14.fw"); 73MODULE_FIRMWARE("b43/ucode15.fw"); 74MODULE_FIRMWARE("b43/ucode16_mimo.fw"); 75MODULE_FIRMWARE("b43/ucode5.fw"); 76MODULE_FIRMWARE("b43/ucode9.fw"); 77 78static int modparam_bad_frames_preempt; 79module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 80MODULE_PARM_DESC(bad_frames_preempt, 81 "enable(1) / disable(0) Bad Frames Preemption"); 82 83static char modparam_fwpostfix[16]; 84module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 85MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 86 87static int modparam_hwpctl; 88module_param_named(hwpctl, modparam_hwpctl, int, 0444); 89MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 90 91static int modparam_nohwcrypt; 92module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 93MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 94 95static int modparam_hwtkip; 96module_param_named(hwtkip, modparam_hwtkip, int, 0444); 97MODULE_PARM_DESC(hwtkip, "Enable hardware tkip."); 98 99static int modparam_qos = 1; 100module_param_named(qos, modparam_qos, int, 0444); 101MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); 102 103static int modparam_btcoex = 1; 104module_param_named(btcoex, modparam_btcoex, int, 0444); 105MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)"); 106 107int b43_modparam_verbose = B43_VERBOSITY_DEFAULT; 108module_param_named(verbose, b43_modparam_verbose, int, 0644); 109MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug"); 110 111static int b43_modparam_pio = B43_PIO_DEFAULT; 112module_param_named(pio, b43_modparam_pio, int, 0644); 113MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO"); 114 115#ifdef CONFIG_B43_BCMA 116static const struct bcma_device_id b43_bcma_tbl[] = { 117 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS), 118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS), 119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS), 120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS), 121 BCMA_CORETABLE_END 122}; 123MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl); 124#endif 125 126#ifdef CONFIG_B43_SSB 127static const struct ssb_device_id b43_ssb_tbl[] = { 128 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12), 135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15), 137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), 138 SSB_DEVTABLE_END 139}; 140MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 141#endif 142 143/* Channel and ratetables are shared for all devices. 144 * They can't be const, because ieee80211 puts some precalculated 145 * data in there. This data is the same for all devices, so we don't 146 * get concurrency issues */ 147#define RATETAB_ENT(_rateid, _flags) \ 148 { \ 149 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ 150 .hw_value = (_rateid), \ 151 .flags = (_flags), \ 152 } 153 154/* 155 * NOTE: When changing this, sync with xmit.c's 156 * b43_plcp_get_bitrate_idx_* functions! 157 */ 158static struct ieee80211_rate __b43_ratetable[] = { 159 RATETAB_ENT(B43_CCK_RATE_1MB, 0), 160 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), 161 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), 162 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), 163 RATETAB_ENT(B43_OFDM_RATE_6MB, 0), 164 RATETAB_ENT(B43_OFDM_RATE_9MB, 0), 165 RATETAB_ENT(B43_OFDM_RATE_12MB, 0), 166 RATETAB_ENT(B43_OFDM_RATE_18MB, 0), 167 RATETAB_ENT(B43_OFDM_RATE_24MB, 0), 168 RATETAB_ENT(B43_OFDM_RATE_36MB, 0), 169 RATETAB_ENT(B43_OFDM_RATE_48MB, 0), 170 RATETAB_ENT(B43_OFDM_RATE_54MB, 0), 171}; 172 173#define b43_a_ratetable (__b43_ratetable + 4) 174#define b43_a_ratetable_size 8 175#define b43_b_ratetable (__b43_ratetable + 0) 176#define b43_b_ratetable_size 4 177#define b43_g_ratetable (__b43_ratetable + 0) 178#define b43_g_ratetable_size 12 179 180#define CHAN4G(_channel, _freq, _flags) { \ 181 .band = IEEE80211_BAND_2GHZ, \ 182 .center_freq = (_freq), \ 183 .hw_value = (_channel), \ 184 .flags = (_flags), \ 185 .max_antenna_gain = 0, \ 186 .max_power = 30, \ 187} 188static struct ieee80211_channel b43_2ghz_chantable[] = { 189 CHAN4G(1, 2412, 0), 190 CHAN4G(2, 2417, 0), 191 CHAN4G(3, 2422, 0), 192 CHAN4G(4, 2427, 0), 193 CHAN4G(5, 2432, 0), 194 CHAN4G(6, 2437, 0), 195 CHAN4G(7, 2442, 0), 196 CHAN4G(8, 2447, 0), 197 CHAN4G(9, 2452, 0), 198 CHAN4G(10, 2457, 0), 199 CHAN4G(11, 2462, 0), 200 CHAN4G(12, 2467, 0), 201 CHAN4G(13, 2472, 0), 202 CHAN4G(14, 2484, 0), 203}; 204#undef CHAN4G 205 206#define CHAN5G(_channel, _flags) { \ 207 .band = IEEE80211_BAND_5GHZ, \ 208 .center_freq = 5000 + (5 * (_channel)), \ 209 .hw_value = (_channel), \ 210 .flags = (_flags), \ 211 .max_antenna_gain = 0, \ 212 .max_power = 30, \ 213} 214static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { 215 CHAN5G(32, 0), CHAN5G(34, 0), 216 CHAN5G(36, 0), CHAN5G(38, 0), 217 CHAN5G(40, 0), CHAN5G(42, 0), 218 CHAN5G(44, 0), CHAN5G(46, 0), 219 CHAN5G(48, 0), CHAN5G(50, 0), 220 CHAN5G(52, 0), CHAN5G(54, 0), 221 CHAN5G(56, 0), CHAN5G(58, 0), 222 CHAN5G(60, 0), CHAN5G(62, 0), 223 CHAN5G(64, 0), CHAN5G(66, 0), 224 CHAN5G(68, 0), CHAN5G(70, 0), 225 CHAN5G(72, 0), CHAN5G(74, 0), 226 CHAN5G(76, 0), CHAN5G(78, 0), 227 CHAN5G(80, 0), CHAN5G(82, 0), 228 CHAN5G(84, 0), CHAN5G(86, 0), 229 CHAN5G(88, 0), CHAN5G(90, 0), 230 CHAN5G(92, 0), CHAN5G(94, 0), 231 CHAN5G(96, 0), CHAN5G(98, 0), 232 CHAN5G(100, 0), CHAN5G(102, 0), 233 CHAN5G(104, 0), CHAN5G(106, 0), 234 CHAN5G(108, 0), CHAN5G(110, 0), 235 CHAN5G(112, 0), CHAN5G(114, 0), 236 CHAN5G(116, 0), CHAN5G(118, 0), 237 CHAN5G(120, 0), CHAN5G(122, 0), 238 CHAN5G(124, 0), CHAN5G(126, 0), 239 CHAN5G(128, 0), CHAN5G(130, 0), 240 CHAN5G(132, 0), CHAN5G(134, 0), 241 CHAN5G(136, 0), CHAN5G(138, 0), 242 CHAN5G(140, 0), CHAN5G(142, 0), 243 CHAN5G(144, 0), CHAN5G(145, 0), 244 CHAN5G(146, 0), CHAN5G(147, 0), 245 CHAN5G(148, 0), CHAN5G(149, 0), 246 CHAN5G(150, 0), CHAN5G(151, 0), 247 CHAN5G(152, 0), CHAN5G(153, 0), 248 CHAN5G(154, 0), CHAN5G(155, 0), 249 CHAN5G(156, 0), CHAN5G(157, 0), 250 CHAN5G(158, 0), CHAN5G(159, 0), 251 CHAN5G(160, 0), CHAN5G(161, 0), 252 CHAN5G(162, 0), CHAN5G(163, 0), 253 CHAN5G(164, 0), CHAN5G(165, 0), 254 CHAN5G(166, 0), CHAN5G(168, 0), 255 CHAN5G(170, 0), CHAN5G(172, 0), 256 CHAN5G(174, 0), CHAN5G(176, 0), 257 CHAN5G(178, 0), CHAN5G(180, 0), 258 CHAN5G(182, 0), CHAN5G(184, 0), 259 CHAN5G(186, 0), CHAN5G(188, 0), 260 CHAN5G(190, 0), CHAN5G(192, 0), 261 CHAN5G(194, 0), CHAN5G(196, 0), 262 CHAN5G(198, 0), CHAN5G(200, 0), 263 CHAN5G(202, 0), CHAN5G(204, 0), 264 CHAN5G(206, 0), CHAN5G(208, 0), 265 CHAN5G(210, 0), CHAN5G(212, 0), 266 CHAN5G(214, 0), CHAN5G(216, 0), 267 CHAN5G(218, 0), CHAN5G(220, 0), 268 CHAN5G(222, 0), CHAN5G(224, 0), 269 CHAN5G(226, 0), CHAN5G(228, 0), 270}; 271 272static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { 273 CHAN5G(34, 0), CHAN5G(36, 0), 274 CHAN5G(38, 0), CHAN5G(40, 0), 275 CHAN5G(42, 0), CHAN5G(44, 0), 276 CHAN5G(46, 0), CHAN5G(48, 0), 277 CHAN5G(52, 0), CHAN5G(56, 0), 278 CHAN5G(60, 0), CHAN5G(64, 0), 279 CHAN5G(100, 0), CHAN5G(104, 0), 280 CHAN5G(108, 0), CHAN5G(112, 0), 281 CHAN5G(116, 0), CHAN5G(120, 0), 282 CHAN5G(124, 0), CHAN5G(128, 0), 283 CHAN5G(132, 0), CHAN5G(136, 0), 284 CHAN5G(140, 0), CHAN5G(149, 0), 285 CHAN5G(153, 0), CHAN5G(157, 0), 286 CHAN5G(161, 0), CHAN5G(165, 0), 287 CHAN5G(184, 0), CHAN5G(188, 0), 288 CHAN5G(192, 0), CHAN5G(196, 0), 289 CHAN5G(200, 0), CHAN5G(204, 0), 290 CHAN5G(208, 0), CHAN5G(212, 0), 291 CHAN5G(216, 0), 292}; 293#undef CHAN5G 294 295static struct ieee80211_supported_band b43_band_5GHz_nphy = { 296 .band = IEEE80211_BAND_5GHZ, 297 .channels = b43_5ghz_nphy_chantable, 298 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), 299 .bitrates = b43_a_ratetable, 300 .n_bitrates = b43_a_ratetable_size, 301}; 302 303static struct ieee80211_supported_band b43_band_5GHz_aphy = { 304 .band = IEEE80211_BAND_5GHZ, 305 .channels = b43_5ghz_aphy_chantable, 306 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), 307 .bitrates = b43_a_ratetable, 308 .n_bitrates = b43_a_ratetable_size, 309}; 310 311static struct ieee80211_supported_band b43_band_2GHz = { 312 .band = IEEE80211_BAND_2GHZ, 313 .channels = b43_2ghz_chantable, 314 .n_channels = ARRAY_SIZE(b43_2ghz_chantable), 315 .bitrates = b43_g_ratetable, 316 .n_bitrates = b43_g_ratetable_size, 317}; 318 319static void b43_wireless_core_exit(struct b43_wldev *dev); 320static int b43_wireless_core_init(struct b43_wldev *dev); 321static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev); 322static int b43_wireless_core_start(struct b43_wldev *dev); 323static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 324 struct ieee80211_vif *vif, 325 struct ieee80211_bss_conf *conf, 326 u32 changed); 327 328static int b43_ratelimit(struct b43_wl *wl) 329{ 330 if (!wl || !wl->current_dev) 331 return 1; 332 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 333 return 1; 334 /* We are up and running. 335 * Ratelimit the messages to avoid DoS over the net. */ 336 return net_ratelimit(); 337} 338 339void b43info(struct b43_wl *wl, const char *fmt, ...) 340{ 341 struct va_format vaf; 342 va_list args; 343 344 if (b43_modparam_verbose < B43_VERBOSITY_INFO) 345 return; 346 if (!b43_ratelimit(wl)) 347 return; 348 349 va_start(args, fmt); 350 351 vaf.fmt = fmt; 352 vaf.va = &args; 353 354 printk(KERN_INFO "b43-%s: %pV", 355 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 356 357 va_end(args); 358} 359 360void b43err(struct b43_wl *wl, const char *fmt, ...) 361{ 362 struct va_format vaf; 363 va_list args; 364 365 if (b43_modparam_verbose < B43_VERBOSITY_ERROR) 366 return; 367 if (!b43_ratelimit(wl)) 368 return; 369 370 va_start(args, fmt); 371 372 vaf.fmt = fmt; 373 vaf.va = &args; 374 375 printk(KERN_ERR "b43-%s ERROR: %pV", 376 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 377 378 va_end(args); 379} 380 381void b43warn(struct b43_wl *wl, const char *fmt, ...) 382{ 383 struct va_format vaf; 384 va_list args; 385 386 if (b43_modparam_verbose < B43_VERBOSITY_WARN) 387 return; 388 if (!b43_ratelimit(wl)) 389 return; 390 391 va_start(args, fmt); 392 393 vaf.fmt = fmt; 394 vaf.va = &args; 395 396 printk(KERN_WARNING "b43-%s warning: %pV", 397 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 398 399 va_end(args); 400} 401 402void b43dbg(struct b43_wl *wl, const char *fmt, ...) 403{ 404 struct va_format vaf; 405 va_list args; 406 407 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 408 return; 409 410 va_start(args, fmt); 411 412 vaf.fmt = fmt; 413 vaf.va = &args; 414 415 printk(KERN_DEBUG "b43-%s debug: %pV", 416 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 417 418 va_end(args); 419} 420 421static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 422{ 423 u32 macctl; 424 425 B43_WARN_ON(offset % 4 != 0); 426 427 macctl = b43_read32(dev, B43_MMIO_MACCTL); 428 if (macctl & B43_MACCTL_BE) 429 val = swab32(val); 430 431 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 432 mmiowb(); 433 b43_write32(dev, B43_MMIO_RAM_DATA, val); 434} 435 436static inline void b43_shm_control_word(struct b43_wldev *dev, 437 u16 routing, u16 offset) 438{ 439 u32 control; 440 441 /* "offset" is the WORD offset. */ 442 control = routing; 443 control <<= 16; 444 control |= offset; 445 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 446} 447 448u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 449{ 450 u32 ret; 451 452 if (routing == B43_SHM_SHARED) { 453 B43_WARN_ON(offset & 0x0001); 454 if (offset & 0x0003) { 455 /* Unaligned access */ 456 b43_shm_control_word(dev, routing, offset >> 2); 457 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 458 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 459 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16; 460 461 goto out; 462 } 463 offset >>= 2; 464 } 465 b43_shm_control_word(dev, routing, offset); 466 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 467out: 468 return ret; 469} 470 471u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset) 472{ 473 u16 ret; 474 475 if (routing == B43_SHM_SHARED) { 476 B43_WARN_ON(offset & 0x0001); 477 if (offset & 0x0003) { 478 /* Unaligned access */ 479 b43_shm_control_word(dev, routing, offset >> 2); 480 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 481 482 goto out; 483 } 484 offset >>= 2; 485 } 486 b43_shm_control_word(dev, routing, offset); 487 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 488out: 489 return ret; 490} 491 492void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 493{ 494 if (routing == B43_SHM_SHARED) { 495 B43_WARN_ON(offset & 0x0001); 496 if (offset & 0x0003) { 497 /* Unaligned access */ 498 b43_shm_control_word(dev, routing, offset >> 2); 499 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 500 value & 0xFFFF); 501 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 502 b43_write16(dev, B43_MMIO_SHM_DATA, 503 (value >> 16) & 0xFFFF); 504 return; 505 } 506 offset >>= 2; 507 } 508 b43_shm_control_word(dev, routing, offset); 509 b43_write32(dev, B43_MMIO_SHM_DATA, value); 510} 511 512void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 513{ 514 if (routing == B43_SHM_SHARED) { 515 B43_WARN_ON(offset & 0x0001); 516 if (offset & 0x0003) { 517 /* Unaligned access */ 518 b43_shm_control_word(dev, routing, offset >> 2); 519 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 520 return; 521 } 522 offset >>= 2; 523 } 524 b43_shm_control_word(dev, routing, offset); 525 b43_write16(dev, B43_MMIO_SHM_DATA, value); 526} 527 528/* Read HostFlags */ 529u64 b43_hf_read(struct b43_wldev *dev) 530{ 531 u64 ret; 532 533 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 534 ret <<= 16; 535 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI); 536 ret <<= 16; 537 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 538 539 return ret; 540} 541 542/* Write HostFlags */ 543void b43_hf_write(struct b43_wldev *dev, u64 value) 544{ 545 u16 lo, mi, hi; 546 547 lo = (value & 0x00000000FFFFULL); 548 mi = (value & 0x0000FFFF0000ULL) >> 16; 549 hi = (value & 0xFFFF00000000ULL) >> 32; 550 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo); 551 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi); 552 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi); 553} 554 555/* Read the firmware capabilities bitmask (Opensource firmware only) */ 556static u16 b43_fwcapa_read(struct b43_wldev *dev) 557{ 558 B43_WARN_ON(!dev->fw.opensource); 559 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA); 560} 561 562void b43_tsf_read(struct b43_wldev *dev, u64 *tsf) 563{ 564 u32 low, high; 565 566 B43_WARN_ON(dev->dev->core_rev < 3); 567 568 /* The hardware guarantees us an atomic read, if we 569 * read the low register first. */ 570 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 571 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 572 573 *tsf = high; 574 *tsf <<= 32; 575 *tsf |= low; 576} 577 578static void b43_time_lock(struct b43_wldev *dev) 579{ 580 u32 macctl; 581 582 macctl = b43_read32(dev, B43_MMIO_MACCTL); 583 macctl |= B43_MACCTL_TBTTHOLD; 584 b43_write32(dev, B43_MMIO_MACCTL, macctl); 585 /* Commit the write */ 586 b43_read32(dev, B43_MMIO_MACCTL); 587} 588 589static void b43_time_unlock(struct b43_wldev *dev) 590{ 591 u32 macctl; 592 593 macctl = b43_read32(dev, B43_MMIO_MACCTL); 594 macctl &= ~B43_MACCTL_TBTTHOLD; 595 b43_write32(dev, B43_MMIO_MACCTL, macctl); 596 /* Commit the write */ 597 b43_read32(dev, B43_MMIO_MACCTL); 598} 599 600static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 601{ 602 u32 low, high; 603 604 B43_WARN_ON(dev->dev->core_rev < 3); 605 606 low = tsf; 607 high = (tsf >> 32); 608 /* The hardware guarantees us an atomic write, if we 609 * write the low register first. */ 610 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low); 611 mmiowb(); 612 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high); 613 mmiowb(); 614} 615 616void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 617{ 618 b43_time_lock(dev); 619 b43_tsf_write_locked(dev, tsf); 620 b43_time_unlock(dev); 621} 622 623static 624void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac) 625{ 626 static const u8 zero_addr[ETH_ALEN] = { 0 }; 627 u16 data; 628 629 if (!mac) 630 mac = zero_addr; 631 632 offset |= 0x0020; 633 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 634 635 data = mac[0]; 636 data |= mac[1] << 8; 637 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 638 data = mac[2]; 639 data |= mac[3] << 8; 640 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 641 data = mac[4]; 642 data |= mac[5] << 8; 643 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 644} 645 646static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 647{ 648 const u8 *mac; 649 const u8 *bssid; 650 u8 mac_bssid[ETH_ALEN * 2]; 651 int i; 652 u32 tmp; 653 654 bssid = dev->wl->bssid; 655 mac = dev->wl->mac_addr; 656 657 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 658 659 memcpy(mac_bssid, mac, ETH_ALEN); 660 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 661 662 /* Write our MAC address and BSSID to template ram */ 663 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 664 tmp = (u32) (mac_bssid[i + 0]); 665 tmp |= (u32) (mac_bssid[i + 1]) << 8; 666 tmp |= (u32) (mac_bssid[i + 2]) << 16; 667 tmp |= (u32) (mac_bssid[i + 3]) << 24; 668 b43_ram_write(dev, 0x20 + i, tmp); 669 } 670} 671 672static void b43_upload_card_macaddress(struct b43_wldev *dev) 673{ 674 b43_write_mac_bssid_templates(dev); 675 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 676} 677 678static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 679{ 680 /* slot_time is in usec. */ 681 /* This test used to exit for all but a G PHY. */ 682 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 683 return; 684 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time); 685 /* Shared memory location 0x0010 is the slot time and should be 686 * set to slot_time; however, this register is initially 0 and changing 687 * the value adversely affects the transmit rate for BCM4311 688 * devices. Until this behavior is unterstood, delete this step 689 * 690 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 691 */ 692} 693 694static void b43_short_slot_timing_enable(struct b43_wldev *dev) 695{ 696 b43_set_slot_time(dev, 9); 697} 698 699static void b43_short_slot_timing_disable(struct b43_wldev *dev) 700{ 701 b43_set_slot_time(dev, 20); 702} 703 704/* DummyTransmission function, as documented on 705 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission 706 */ 707void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) 708{ 709 struct b43_phy *phy = &dev->phy; 710 unsigned int i, max_loop; 711 u16 value; 712 u32 buffer[5] = { 713 0x00000000, 714 0x00D40000, 715 0x00000000, 716 0x01000000, 717 0x00000000, 718 }; 719 720 if (ofdm) { 721 max_loop = 0x1E; 722 buffer[0] = 0x000201CC; 723 } else { 724 max_loop = 0xFA; 725 buffer[0] = 0x000B846E; 726 } 727 728 for (i = 0; i < 5; i++) 729 b43_ram_write(dev, i * 4, buffer[i]); 730 731 b43_write16(dev, 0x0568, 0x0000); 732 if (dev->dev->core_rev < 11) 733 b43_write16(dev, 0x07C0, 0x0000); 734 else 735 b43_write16(dev, 0x07C0, 0x0100); 736 value = (ofdm ? 0x41 : 0x40); 737 b43_write16(dev, 0x050C, value); 738 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP)) 739 b43_write16(dev, 0x0514, 0x1A02); 740 b43_write16(dev, 0x0508, 0x0000); 741 b43_write16(dev, 0x050A, 0x0000); 742 b43_write16(dev, 0x054C, 0x0000); 743 b43_write16(dev, 0x056A, 0x0014); 744 b43_write16(dev, 0x0568, 0x0826); 745 b43_write16(dev, 0x0500, 0x0000); 746 if (!pa_on && (phy->type == B43_PHYTYPE_N)) { 747 //SPEC TODO 748 } 749 750 switch (phy->type) { 751 case B43_PHYTYPE_N: 752 b43_write16(dev, 0x0502, 0x00D0); 753 break; 754 case B43_PHYTYPE_LP: 755 b43_write16(dev, 0x0502, 0x0050); 756 break; 757 default: 758 b43_write16(dev, 0x0502, 0x0030); 759 } 760 761 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 762 b43_radio_write16(dev, 0x0051, 0x0017); 763 for (i = 0x00; i < max_loop; i++) { 764 value = b43_read16(dev, 0x050E); 765 if (value & 0x0080) 766 break; 767 udelay(10); 768 } 769 for (i = 0x00; i < 0x0A; i++) { 770 value = b43_read16(dev, 0x050E); 771 if (value & 0x0400) 772 break; 773 udelay(10); 774 } 775 for (i = 0x00; i < 0x19; i++) { 776 value = b43_read16(dev, 0x0690); 777 if (!(value & 0x0100)) 778 break; 779 udelay(10); 780 } 781 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 782 b43_radio_write16(dev, 0x0051, 0x0037); 783} 784 785static void key_write(struct b43_wldev *dev, 786 u8 index, u8 algorithm, const u8 *key) 787{ 788 unsigned int i; 789 u32 offset; 790 u16 value; 791 u16 kidx; 792 793 /* Key index/algo block */ 794 kidx = b43_kidx_to_fw(dev, index); 795 value = ((kidx << 4) | algorithm); 796 b43_shm_write16(dev, B43_SHM_SHARED, 797 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 798 799 /* Write the key to the Key Table Pointer offset */ 800 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 801 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 802 value = key[i]; 803 value |= (u16) (key[i + 1]) << 8; 804 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 805 } 806} 807 808static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr) 809{ 810 u32 addrtmp[2] = { 0, 0, }; 811 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 812 813 if (b43_new_kidx_api(dev)) 814 pairwise_keys_start = B43_NR_GROUP_KEYS; 815 816 B43_WARN_ON(index < pairwise_keys_start); 817 /* We have four default TX keys and possibly four default RX keys. 818 * Physical mac 0 is mapped to physical key 4 or 8, depending 819 * on the firmware version. 820 * So we must adjust the index here. 821 */ 822 index -= pairwise_keys_start; 823 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 824 825 if (addr) { 826 addrtmp[0] = addr[0]; 827 addrtmp[0] |= ((u32) (addr[1]) << 8); 828 addrtmp[0] |= ((u32) (addr[2]) << 16); 829 addrtmp[0] |= ((u32) (addr[3]) << 24); 830 addrtmp[1] = addr[4]; 831 addrtmp[1] |= ((u32) (addr[5]) << 8); 832 } 833 834 /* Receive match transmitter address (RCMTA) mechanism */ 835 b43_shm_write32(dev, B43_SHM_RCMTA, 836 (index * 2) + 0, addrtmp[0]); 837 b43_shm_write16(dev, B43_SHM_RCMTA, 838 (index * 2) + 1, addrtmp[1]); 839} 840 841/* The ucode will use phase1 key with TEK key to decrypt rx packets. 842 * When a packet is received, the iv32 is checked. 843 * - if it doesn't the packet is returned without modification (and software 844 * decryption can be done). That's what happen when iv16 wrap. 845 * - if it does, the rc4 key is computed, and decryption is tried. 846 * Either it will success and B43_RX_MAC_DEC is returned, 847 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned 848 * and the packet is not usable (it got modified by the ucode). 849 * So in order to never have B43_RX_MAC_DECERR, we should provide 850 * a iv32 and phase1key that match. Because we drop packets in case of 851 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all 852 * packets will be lost without higher layer knowing (ie no resync possible 853 * until next wrap). 854 * 855 * NOTE : this should support 50 key like RCMTA because 856 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50 857 */ 858static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32, 859 u16 *phase1key) 860{ 861 unsigned int i; 862 u32 offset; 863 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 864 865 if (!modparam_hwtkip) 866 return; 867 868 if (b43_new_kidx_api(dev)) 869 pairwise_keys_start = B43_NR_GROUP_KEYS; 870 871 B43_WARN_ON(index < pairwise_keys_start); 872 /* We have four default TX keys and possibly four default RX keys. 873 * Physical mac 0 is mapped to physical key 4 or 8, depending 874 * on the firmware version. 875 * So we must adjust the index here. 876 */ 877 index -= pairwise_keys_start; 878 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 879 880 if (b43_debug(dev, B43_DBG_KEYS)) { 881 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", 882 index, iv32); 883 } 884 /* Write the key to the RX tkip shared mem */ 885 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4); 886 for (i = 0; i < 10; i += 2) { 887 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, 888 phase1key ? phase1key[i / 2] : 0); 889 } 890 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32); 891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16); 892} 893 894static void b43_op_update_tkip_key(struct ieee80211_hw *hw, 895 struct ieee80211_vif *vif, 896 struct ieee80211_key_conf *keyconf, 897 struct ieee80211_sta *sta, 898 u32 iv32, u16 *phase1key) 899{ 900 struct b43_wl *wl = hw_to_b43_wl(hw); 901 struct b43_wldev *dev; 902 int index = keyconf->hw_key_idx; 903 904 if (B43_WARN_ON(!modparam_hwtkip)) 905 return; 906 907 /* This is only called from the RX path through mac80211, where 908 * our mutex is already locked. */ 909 B43_WARN_ON(!mutex_is_locked(&wl->mutex)); 910 dev = wl->current_dev; 911 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED); 912 913 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */ 914 915 rx_tkip_phase1_write(dev, index, iv32, phase1key); 916 /* only pairwise TKIP keys are supported right now */ 917 if (WARN_ON(!sta)) 918 return; 919 keymac_write(dev, index, sta->addr); 920} 921 922static void do_key_write(struct b43_wldev *dev, 923 u8 index, u8 algorithm, 924 const u8 *key, size_t key_len, const u8 *mac_addr) 925{ 926 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 927 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 928 929 if (b43_new_kidx_api(dev)) 930 pairwise_keys_start = B43_NR_GROUP_KEYS; 931 932 B43_WARN_ON(index >= ARRAY_SIZE(dev->key)); 933 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 934 935 if (index >= pairwise_keys_start) 936 keymac_write(dev, index, NULL); /* First zero out mac. */ 937 if (algorithm == B43_SEC_ALGO_TKIP) { 938 /* 939 * We should provide an initial iv32, phase1key pair. 940 * We could start with iv32=0 and compute the corresponding 941 * phase1key, but this means calling ieee80211_get_tkip_key 942 * with a fake skb (or export other tkip function). 943 * Because we are lazy we hope iv32 won't start with 944 * 0xffffffff and let's b43_op_update_tkip_key provide a 945 * correct pair. 946 */ 947 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); 948 } else if (index >= pairwise_keys_start) /* clear it */ 949 rx_tkip_phase1_write(dev, index, 0, NULL); 950 if (key) 951 memcpy(buf, key, key_len); 952 key_write(dev, index, algorithm, buf); 953 if (index >= pairwise_keys_start) 954 keymac_write(dev, index, mac_addr); 955 956 dev->key[index].algorithm = algorithm; 957} 958 959static int b43_key_write(struct b43_wldev *dev, 960 int index, u8 algorithm, 961 const u8 *key, size_t key_len, 962 const u8 *mac_addr, 963 struct ieee80211_key_conf *keyconf) 964{ 965 int i; 966 int pairwise_keys_start; 967 968 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block: 969 * - Temporal Encryption Key (128 bits) 970 * - Temporal Authenticator Tx MIC Key (64 bits) 971 * - Temporal Authenticator Rx MIC Key (64 bits) 972 * 973 * Hardware only store TEK 974 */ 975 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32) 976 key_len = 16; 977 if (key_len > B43_SEC_KEYSIZE) 978 return -EINVAL; 979 for (i = 0; i < ARRAY_SIZE(dev->key); i++) { 980 /* Check that we don't already have this key. */ 981 B43_WARN_ON(dev->key[i].keyconf == keyconf); 982 } 983 if (index < 0) { 984 /* Pairwise key. Get an empty slot for the key. */ 985 if (b43_new_kidx_api(dev)) 986 pairwise_keys_start = B43_NR_GROUP_KEYS; 987 else 988 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 989 for (i = pairwise_keys_start; 990 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS; 991 i++) { 992 B43_WARN_ON(i >= ARRAY_SIZE(dev->key)); 993 if (!dev->key[i].keyconf) { 994 /* found empty */ 995 index = i; 996 break; 997 } 998 } 999 if (index < 0) { 1000 b43warn(dev->wl, "Out of hardware key memory\n"); 1001 return -ENOSPC; 1002 } 1003 } else 1004 B43_WARN_ON(index > 3); 1005 1006 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 1007 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1008 /* Default RX key */ 1009 B43_WARN_ON(mac_addr); 1010 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 1011 } 1012 keyconf->hw_key_idx = index; 1013 dev->key[index].keyconf = keyconf; 1014 1015 return 0; 1016} 1017 1018static int b43_key_clear(struct b43_wldev *dev, int index) 1019{ 1020 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) 1021 return -EINVAL; 1022 do_key_write(dev, index, B43_SEC_ALGO_NONE, 1023 NULL, B43_SEC_KEYSIZE, NULL); 1024 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1025 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 1026 NULL, B43_SEC_KEYSIZE, NULL); 1027 } 1028 dev->key[index].keyconf = NULL; 1029 1030 return 0; 1031} 1032 1033static void b43_clear_keys(struct b43_wldev *dev) 1034{ 1035 int i, count; 1036 1037 if (b43_new_kidx_api(dev)) 1038 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1039 else 1040 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1041 for (i = 0; i < count; i++) 1042 b43_key_clear(dev, i); 1043} 1044 1045static void b43_dump_keymemory(struct b43_wldev *dev) 1046{ 1047 unsigned int i, index, count, offset, pairwise_keys_start; 1048 u8 mac[ETH_ALEN]; 1049 u16 algo; 1050 u32 rcmta0; 1051 u16 rcmta1; 1052 u64 hf; 1053 struct b43_key *key; 1054 1055 if (!b43_debug(dev, B43_DBG_KEYS)) 1056 return; 1057 1058 hf = b43_hf_read(dev); 1059 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n", 1060 !!(hf & B43_HF_USEDEFKEYS)); 1061 if (b43_new_kidx_api(dev)) { 1062 pairwise_keys_start = B43_NR_GROUP_KEYS; 1063 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1064 } else { 1065 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 1066 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1067 } 1068 for (index = 0; index < count; index++) { 1069 key = &(dev->key[index]); 1070 printk(KERN_DEBUG "Key slot %02u: %s", 1071 index, (key->keyconf == NULL) ? " " : "*"); 1072 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 1073 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 1074 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1075 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1076 } 1077 1078 algo = b43_shm_read16(dev, B43_SHM_SHARED, 1079 B43_SHM_SH_KEYIDXBLOCK + (index * 2)); 1080 printk(" Algo: %04X/%02X", algo, key->algorithm); 1081 1082 if (index >= pairwise_keys_start) { 1083 if (key->algorithm == B43_SEC_ALGO_TKIP) { 1084 printk(" TKIP: "); 1085 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4); 1086 for (i = 0; i < 14; i += 2) { 1087 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1088 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1089 } 1090 } 1091 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA, 1092 ((index - pairwise_keys_start) * 2) + 0); 1093 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA, 1094 ((index - pairwise_keys_start) * 2) + 1); 1095 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); 1096 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1); 1097 printk(" MAC: %pM", mac); 1098 } else 1099 printk(" DEFAULT KEY"); 1100 printk("\n"); 1101 } 1102} 1103 1104void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 1105{ 1106 u32 macctl; 1107 u16 ucstat; 1108 bool hwps; 1109 bool awake; 1110 int i; 1111 1112 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 1113 (ps_flags & B43_PS_DISABLED)); 1114 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 1115 1116 if (ps_flags & B43_PS_ENABLED) { 1117 hwps = 1; 1118 } else if (ps_flags & B43_PS_DISABLED) { 1119 hwps = 0; 1120 } else { 1121 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 1122 // and thus is not an AP and we are associated, set bit 25 1123 } 1124 if (ps_flags & B43_PS_AWAKE) { 1125 awake = 1; 1126 } else if (ps_flags & B43_PS_ASLEEP) { 1127 awake = 0; 1128 } else { 1129 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 1130 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 1131 // successful, set bit26 1132 } 1133 1134/* FIXME: For now we force awake-on and hwps-off */ 1135 hwps = 0; 1136 awake = 1; 1137 1138 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1139 if (hwps) 1140 macctl |= B43_MACCTL_HWPS; 1141 else 1142 macctl &= ~B43_MACCTL_HWPS; 1143 if (awake) 1144 macctl |= B43_MACCTL_AWAKE; 1145 else 1146 macctl &= ~B43_MACCTL_AWAKE; 1147 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1148 /* Commit write */ 1149 b43_read32(dev, B43_MMIO_MACCTL); 1150 if (awake && dev->dev->core_rev >= 5) { 1151 /* Wait for the microcode to wake up. */ 1152 for (i = 0; i < 100; i++) { 1153 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 1154 B43_SHM_SH_UCODESTAT); 1155 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 1156 break; 1157 udelay(10); 1158 } 1159 } 1160} 1161 1162#ifdef CONFIG_B43_BCMA 1163static void b43_bcma_phy_reset(struct b43_wldev *dev) 1164{ 1165 u32 flags; 1166 1167 /* Put PHY into reset */ 1168 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1169 flags |= B43_BCMA_IOCTL_PHY_RESET; 1170 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */ 1171 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1172 udelay(2); 1173 1174 /* Take PHY out of reset */ 1175 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1176 flags &= ~B43_BCMA_IOCTL_PHY_RESET; 1177 flags |= BCMA_IOCTL_FGC; 1178 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1179 udelay(1); 1180 1181 /* Do not force clock anymore */ 1182 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1183 flags &= ~BCMA_IOCTL_FGC; 1184 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1185 udelay(1); 1186} 1187 1188static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1189{ 1190 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN); 1191 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST); 1192 b43_bcma_phy_reset(dev); 1193 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true); 1194} 1195#endif 1196 1197static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1198{ 1199 struct ssb_device *sdev = dev->dev->sdev; 1200 u32 tmslow; 1201 u32 flags = 0; 1202 1203 if (gmode) 1204 flags |= B43_TMSLOW_GMODE; 1205 flags |= B43_TMSLOW_PHYCLKEN; 1206 flags |= B43_TMSLOW_PHYRESET; 1207 if (dev->phy.type == B43_PHYTYPE_N) 1208 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */ 1209 b43_device_enable(dev, flags); 1210 msleep(2); /* Wait for the PLL to turn on. */ 1211 1212 /* Now take the PHY out of Reset again */ 1213 tmslow = ssb_read32(sdev, SSB_TMSLOW); 1214 tmslow |= SSB_TMSLOW_FGC; 1215 tmslow &= ~B43_TMSLOW_PHYRESET; 1216 ssb_write32(sdev, SSB_TMSLOW, tmslow); 1217 ssb_read32(sdev, SSB_TMSLOW); /* flush */ 1218 msleep(1); 1219 tmslow &= ~SSB_TMSLOW_FGC; 1220 ssb_write32(sdev, SSB_TMSLOW, tmslow); 1221 ssb_read32(sdev, SSB_TMSLOW); /* flush */ 1222 msleep(1); 1223} 1224 1225void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1226{ 1227 u32 macctl; 1228 1229 switch (dev->dev->bus_type) { 1230#ifdef CONFIG_B43_BCMA 1231 case B43_BUS_BCMA: 1232 b43_bcma_wireless_core_reset(dev, gmode); 1233 break; 1234#endif 1235#ifdef CONFIG_B43_SSB 1236 case B43_BUS_SSB: 1237 b43_ssb_wireless_core_reset(dev, gmode); 1238 break; 1239#endif 1240 } 1241 1242 /* Turn Analog ON, but only if we already know the PHY-type. 1243 * This protects against very early setup where we don't know the 1244 * PHY-type, yet. wireless_core_reset will be called once again later, 1245 * when we know the PHY-type. */ 1246 if (dev->phy.ops) 1247 dev->phy.ops->switch_analog(dev, 1); 1248 1249 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1250 macctl &= ~B43_MACCTL_GMODE; 1251 if (gmode) 1252 macctl |= B43_MACCTL_GMODE; 1253 macctl |= B43_MACCTL_IHR_ENABLED; 1254 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1255} 1256 1257static void handle_irq_transmit_status(struct b43_wldev *dev) 1258{ 1259 u32 v0, v1; 1260 u16 tmp; 1261 struct b43_txstatus stat; 1262 1263 while (1) { 1264 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1265 if (!(v0 & 0x00000001)) 1266 break; 1267 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1268 1269 stat.cookie = (v0 >> 16); 1270 stat.seq = (v1 & 0x0000FFFF); 1271 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 1272 tmp = (v0 & 0x0000FFFF); 1273 stat.frame_count = ((tmp & 0xF000) >> 12); 1274 stat.rts_count = ((tmp & 0x0F00) >> 8); 1275 stat.supp_reason = ((tmp & 0x001C) >> 2); 1276 stat.pm_indicated = !!(tmp & 0x0080); 1277 stat.intermediate = !!(tmp & 0x0040); 1278 stat.for_ampdu = !!(tmp & 0x0020); 1279 stat.acked = !!(tmp & 0x0002); 1280 1281 b43_handle_txstatus(dev, &stat); 1282 } 1283} 1284 1285static void drain_txstatus_queue(struct b43_wldev *dev) 1286{ 1287 u32 dummy; 1288 1289 if (dev->dev->core_rev < 5) 1290 return; 1291 /* Read all entries from the microcode TXstatus FIFO 1292 * and throw them away. 1293 */ 1294 while (1) { 1295 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1296 if (!(dummy & 0x00000001)) 1297 break; 1298 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1299 } 1300} 1301 1302static u32 b43_jssi_read(struct b43_wldev *dev) 1303{ 1304 u32 val = 0; 1305 1306 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 1307 val <<= 16; 1308 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1309 1310 return val; 1311} 1312 1313static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1314{ 1315 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1316 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1317} 1318 1319static void b43_generate_noise_sample(struct b43_wldev *dev) 1320{ 1321 b43_jssi_write(dev, 0x7F7F7F7F); 1322 b43_write32(dev, B43_MMIO_MACCMD, 1323 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1324} 1325 1326static void b43_calculate_link_quality(struct b43_wldev *dev) 1327{ 1328 /* Top half of Link Quality calculation. */ 1329 1330 if (dev->phy.type != B43_PHYTYPE_G) 1331 return; 1332 if (dev->noisecalc.calculation_running) 1333 return; 1334 dev->noisecalc.calculation_running = 1; 1335 dev->noisecalc.nr_samples = 0; 1336 1337 b43_generate_noise_sample(dev); 1338} 1339 1340static void handle_irq_noise(struct b43_wldev *dev) 1341{ 1342 struct b43_phy_g *phy = dev->phy.g; 1343 u16 tmp; 1344 u8 noise[4]; 1345 u8 i, j; 1346 s32 average; 1347 1348 /* Bottom half of Link Quality calculation. */ 1349 1350 if (dev->phy.type != B43_PHYTYPE_G) 1351 return; 1352 1353 /* Possible race condition: It might be possible that the user 1354 * changed to a different channel in the meantime since we 1355 * started the calculation. We ignore that fact, since it's 1356 * not really that much of a problem. The background noise is 1357 * an estimation only anyway. Slightly wrong results will get damped 1358 * by the averaging of the 8 sample rounds. Additionally the 1359 * value is shortlived. So it will be replaced by the next noise 1360 * calculation round soon. */ 1361 1362 B43_WARN_ON(!dev->noisecalc.calculation_running); 1363 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1364 if (noise[0] == 0x7F || noise[1] == 0x7F || 1365 noise[2] == 0x7F || noise[3] == 0x7F) 1366 goto generate_new; 1367 1368 /* Get the noise samples. */ 1369 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1370 i = dev->noisecalc.nr_samples; 1371 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1372 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1373 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1374 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1375 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1376 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1377 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1378 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1379 dev->noisecalc.nr_samples++; 1380 if (dev->noisecalc.nr_samples == 8) { 1381 /* Calculate the Link Quality by the noise samples. */ 1382 average = 0; 1383 for (i = 0; i < 8; i++) { 1384 for (j = 0; j < 4; j++) 1385 average += dev->noisecalc.samples[i][j]; 1386 } 1387 average /= (8 * 4); 1388 average *= 125; 1389 average += 64; 1390 average /= 128; 1391 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1392 tmp = (tmp / 128) & 0x1F; 1393 if (tmp >= 8) 1394 average += 2; 1395 else 1396 average -= 25; 1397 if (tmp == 8) 1398 average -= 72; 1399 else 1400 average -= 48; 1401 1402 dev->stats.link_noise = average; 1403 dev->noisecalc.calculation_running = 0; 1404 return; 1405 } 1406generate_new: 1407 b43_generate_noise_sample(dev); 1408} 1409 1410static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1411{ 1412 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) { 1413 ///TODO: PS TBTT 1414 } else { 1415 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1416 b43_power_saving_ctl_bits(dev, 0); 1417 } 1418 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 1419 dev->dfq_valid = 1; 1420} 1421 1422static void handle_irq_atim_end(struct b43_wldev *dev) 1423{ 1424 if (dev->dfq_valid) { 1425 b43_write32(dev, B43_MMIO_MACCMD, 1426 b43_read32(dev, B43_MMIO_MACCMD) 1427 | B43_MACCMD_DFQ_VALID); 1428 dev->dfq_valid = 0; 1429 } 1430} 1431 1432static void handle_irq_pmq(struct b43_wldev *dev) 1433{ 1434 u32 tmp; 1435 1436 //TODO: AP mode. 1437 1438 while (1) { 1439 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1440 if (!(tmp & 0x00000008)) 1441 break; 1442 } 1443 /* 16bit write is odd, but correct. */ 1444 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1445} 1446 1447static void b43_write_template_common(struct b43_wldev *dev, 1448 const u8 *data, u16 size, 1449 u16 ram_offset, 1450 u16 shm_size_offset, u8 rate) 1451{ 1452 u32 i, tmp; 1453 struct b43_plcp_hdr4 plcp; 1454 1455 plcp.data = 0; 1456 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1457 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1458 ram_offset += sizeof(u32); 1459 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1460 * So leave the first two bytes of the next write blank. 1461 */ 1462 tmp = (u32) (data[0]) << 16; 1463 tmp |= (u32) (data[1]) << 24; 1464 b43_ram_write(dev, ram_offset, tmp); 1465 ram_offset += sizeof(u32); 1466 for (i = 2; i < size; i += sizeof(u32)) { 1467 tmp = (u32) (data[i + 0]); 1468 if (i + 1 < size) 1469 tmp |= (u32) (data[i + 1]) << 8; 1470 if (i + 2 < size) 1471 tmp |= (u32) (data[i + 2]) << 16; 1472 if (i + 3 < size) 1473 tmp |= (u32) (data[i + 3]) << 24; 1474 b43_ram_write(dev, ram_offset + i - 2, tmp); 1475 } 1476 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1477 size + sizeof(struct b43_plcp_hdr6)); 1478} 1479 1480/* Check if the use of the antenna that ieee80211 told us to 1481 * use is possible. This will fall back to DEFAULT. 1482 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 1483u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 1484 u8 antenna_nr) 1485{ 1486 u8 antenna_mask; 1487 1488 if (antenna_nr == 0) { 1489 /* Zero means "use default antenna". That's always OK. */ 1490 return 0; 1491 } 1492 1493 /* Get the mask of available antennas. */ 1494 if (dev->phy.gmode) 1495 antenna_mask = dev->dev->bus_sprom->ant_available_bg; 1496 else 1497 antenna_mask = dev->dev->bus_sprom->ant_available_a; 1498 1499 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 1500 /* This antenna is not available. Fall back to default. */ 1501 return 0; 1502 } 1503 1504 return antenna_nr; 1505} 1506 1507/* Convert a b43 antenna number value to the PHY TX control value. */ 1508static u16 b43_antenna_to_phyctl(int antenna) 1509{ 1510 switch (antenna) { 1511 case B43_ANTENNA0: 1512 return B43_TXH_PHY_ANT0; 1513 case B43_ANTENNA1: 1514 return B43_TXH_PHY_ANT1; 1515 case B43_ANTENNA2: 1516 return B43_TXH_PHY_ANT2; 1517 case B43_ANTENNA3: 1518 return B43_TXH_PHY_ANT3; 1519 case B43_ANTENNA_AUTO0: 1520 case B43_ANTENNA_AUTO1: 1521 return B43_TXH_PHY_ANT01AUTO; 1522 } 1523 B43_WARN_ON(1); 1524 return 0; 1525} 1526 1527static void b43_write_beacon_template(struct b43_wldev *dev, 1528 u16 ram_offset, 1529 u16 shm_size_offset) 1530{ 1531 unsigned int i, len, variable_len; 1532 const struct ieee80211_mgmt *bcn; 1533 const u8 *ie; 1534 bool tim_found = 0; 1535 unsigned int rate; 1536 u16 ctl; 1537 int antenna; 1538 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon); 1539 1540 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1541 len = min((size_t) dev->wl->current_beacon->len, 1542 0x200 - sizeof(struct b43_plcp_hdr6)); 1543 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; 1544 1545 b43_write_template_common(dev, (const u8 *)bcn, 1546 len, ram_offset, shm_size_offset, rate); 1547 1548 /* Write the PHY TX control parameters. */ 1549 antenna = B43_ANTENNA_DEFAULT; 1550 antenna = b43_antenna_to_phyctl(antenna); 1551 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 1552 /* We can't send beacons with short preamble. Would get PHY errors. */ 1553 ctl &= ~B43_TXH_PHY_SHORTPRMBL; 1554 ctl &= ~B43_TXH_PHY_ANT; 1555 ctl &= ~B43_TXH_PHY_ENC; 1556 ctl |= antenna; 1557 if (b43_is_cck_rate(rate)) 1558 ctl |= B43_TXH_PHY_ENC_CCK; 1559 else 1560 ctl |= B43_TXH_PHY_ENC_OFDM; 1561 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 1562 1563 /* Find the position of the TIM and the DTIM_period value 1564 * and write them to SHM. */ 1565 ie = bcn->u.beacon.variable; 1566 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1567 for (i = 0; i < variable_len - 2; ) { 1568 uint8_t ie_id, ie_len; 1569 1570 ie_id = ie[i]; 1571 ie_len = ie[i + 1]; 1572 if (ie_id == 5) { 1573 u16 tim_position; 1574 u16 dtim_period; 1575 /* This is the TIM Information Element */ 1576 1577 /* Check whether the ie_len is in the beacon data range. */ 1578 if (variable_len < ie_len + 2 + i) 1579 break; 1580 /* A valid TIM is at least 4 bytes long. */ 1581 if (ie_len < 4) 1582 break; 1583 tim_found = 1; 1584 1585 tim_position = sizeof(struct b43_plcp_hdr6); 1586 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1587 tim_position += i; 1588 1589 dtim_period = ie[i + 3]; 1590 1591 b43_shm_write16(dev, B43_SHM_SHARED, 1592 B43_SHM_SH_TIMBPOS, tim_position); 1593 b43_shm_write16(dev, B43_SHM_SHARED, 1594 B43_SHM_SH_DTIMPER, dtim_period); 1595 break; 1596 } 1597 i += ie_len + 2; 1598 } 1599 if (!tim_found) { 1600 /* 1601 * If ucode wants to modify TIM do it behind the beacon, this 1602 * will happen, for example, when doing mesh networking. 1603 */ 1604 b43_shm_write16(dev, B43_SHM_SHARED, 1605 B43_SHM_SH_TIMBPOS, 1606 len + sizeof(struct b43_plcp_hdr6)); 1607 b43_shm_write16(dev, B43_SHM_SHARED, 1608 B43_SHM_SH_DTIMPER, 0); 1609 } 1610 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); 1611} 1612 1613static void b43_upload_beacon0(struct b43_wldev *dev) 1614{ 1615 struct b43_wl *wl = dev->wl; 1616 1617 if (wl->beacon0_uploaded) 1618 return; 1619 b43_write_beacon_template(dev, 0x68, 0x18); 1620 wl->beacon0_uploaded = 1; 1621} 1622 1623static void b43_upload_beacon1(struct b43_wldev *dev) 1624{ 1625 struct b43_wl *wl = dev->wl; 1626 1627 if (wl->beacon1_uploaded) 1628 return; 1629 b43_write_beacon_template(dev, 0x468, 0x1A); 1630 wl->beacon1_uploaded = 1; 1631} 1632 1633static void handle_irq_beacon(struct b43_wldev *dev) 1634{ 1635 struct b43_wl *wl = dev->wl; 1636 u32 cmd, beacon0_valid, beacon1_valid; 1637 1638 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && 1639 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 1640 return; 1641 1642 /* This is the bottom half of the asynchronous beacon update. */ 1643 1644 /* Ignore interrupt in the future. */ 1645 dev->irq_mask &= ~B43_IRQ_BEACON; 1646 1647 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1648 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); 1649 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); 1650 1651 /* Schedule interrupt manually, if busy. */ 1652 if (beacon0_valid && beacon1_valid) { 1653 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1654 dev->irq_mask |= B43_IRQ_BEACON; 1655 return; 1656 } 1657 1658 if (unlikely(wl->beacon_templates_virgin)) { 1659 /* We never uploaded a beacon before. 1660 * Upload both templates now, but only mark one valid. */ 1661 wl->beacon_templates_virgin = 0; 1662 b43_upload_beacon0(dev); 1663 b43_upload_beacon1(dev); 1664 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1665 cmd |= B43_MACCMD_BEACON0_VALID; 1666 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1667 } else { 1668 if (!beacon0_valid) { 1669 b43_upload_beacon0(dev); 1670 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1671 cmd |= B43_MACCMD_BEACON0_VALID; 1672 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1673 } else if (!beacon1_valid) { 1674 b43_upload_beacon1(dev); 1675 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1676 cmd |= B43_MACCMD_BEACON1_VALID; 1677 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1678 } 1679 } 1680} 1681 1682static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev) 1683{ 1684 u32 old_irq_mask = dev->irq_mask; 1685 1686 /* update beacon right away or defer to irq */ 1687 handle_irq_beacon(dev); 1688 if (old_irq_mask != dev->irq_mask) { 1689 /* The handler updated the IRQ mask. */ 1690 B43_WARN_ON(!dev->irq_mask); 1691 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) { 1692 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1693 } else { 1694 /* Device interrupts are currently disabled. That means 1695 * we just ran the hardirq handler and scheduled the 1696 * IRQ thread. The thread will write the IRQ mask when 1697 * it finished, so there's nothing to do here. Writing 1698 * the mask _here_ would incorrectly re-enable IRQs. */ 1699 } 1700 } 1701} 1702 1703static void b43_beacon_update_trigger_work(struct work_struct *work) 1704{ 1705 struct b43_wl *wl = container_of(work, struct b43_wl, 1706 beacon_update_trigger); 1707 struct b43_wldev *dev; 1708 1709 mutex_lock(&wl->mutex); 1710 dev = wl->current_dev; 1711 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { 1712 if (b43_bus_host_is_sdio(dev->dev)) { 1713 /* wl->mutex is enough. */ 1714 b43_do_beacon_update_trigger_work(dev); 1715 mmiowb(); 1716 } else { 1717 spin_lock_irq(&wl->hardirq_lock); 1718 b43_do_beacon_update_trigger_work(dev); 1719 mmiowb(); 1720 spin_unlock_irq(&wl->hardirq_lock); 1721 } 1722 } 1723 mutex_unlock(&wl->mutex); 1724} 1725 1726/* Asynchronously update the packet templates in template RAM. 1727 * Locking: Requires wl->mutex to be locked. */ 1728static void b43_update_templates(struct b43_wl *wl) 1729{ 1730 struct sk_buff *beacon; 1731 1732 /* This is the top half of the ansynchronous beacon update. 1733 * The bottom half is the beacon IRQ. 1734 * Beacon update must be asynchronous to avoid sending an 1735 * invalid beacon. This can happen for example, if the firmware 1736 * transmits a beacon while we are updating it. */ 1737 1738 /* We could modify the existing beacon and set the aid bit in 1739 * the TIM field, but that would probably require resizing and 1740 * moving of data within the beacon template. 1741 * Simply request a new beacon and let mac80211 do the hard work. */ 1742 beacon = ieee80211_beacon_get(wl->hw, wl->vif); 1743 if (unlikely(!beacon)) 1744 return; 1745 1746 if (wl->current_beacon) 1747 dev_kfree_skb_any(wl->current_beacon); 1748 wl->current_beacon = beacon; 1749 wl->beacon0_uploaded = 0; 1750 wl->beacon1_uploaded = 0; 1751 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); 1752} 1753 1754static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1755{ 1756 b43_time_lock(dev); 1757 if (dev->dev->core_rev >= 3) { 1758 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); 1759 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); 1760 } else { 1761 b43_write16(dev, 0x606, (beacon_int >> 6)); 1762 b43_write16(dev, 0x610, beacon_int); 1763 } 1764 b43_time_unlock(dev); 1765 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1766} 1767 1768static void b43_handle_firmware_panic(struct b43_wldev *dev) 1769{ 1770 u16 reason; 1771 1772 /* Read the register that contains the reason code for the panic. */ 1773 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG); 1774 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason); 1775 1776 switch (reason) { 1777 default: 1778 b43dbg(dev->wl, "The panic reason is unknown.\n"); 1779 /* fallthrough */ 1780 case B43_FWPANIC_DIE: 1781 /* Do not restart the controller or firmware. 1782 * The device is nonfunctional from now on. 1783 * Restarting would result in this panic to trigger again, 1784 * so we avoid that recursion. */ 1785 break; 1786 case B43_FWPANIC_RESTART: 1787 b43_controller_restart(dev, "Microcode panic"); 1788 break; 1789 } 1790} 1791 1792static void handle_irq_ucode_debug(struct b43_wldev *dev) 1793{ 1794 unsigned int i, cnt; 1795 u16 reason, marker_id, marker_line; 1796 __le16 *buf; 1797 1798 /* The proprietary firmware doesn't have this IRQ. */ 1799 if (!dev->fw.opensource) 1800 return; 1801 1802 /* Read the register that contains the reason code for this IRQ. */ 1803 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG); 1804 1805 switch (reason) { 1806 case B43_DEBUGIRQ_PANIC: 1807 b43_handle_firmware_panic(dev); 1808 break; 1809 case B43_DEBUGIRQ_DUMP_SHM: 1810 if (!B43_DEBUG) 1811 break; /* Only with driver debugging enabled. */ 1812 buf = kmalloc(4096, GFP_ATOMIC); 1813 if (!buf) { 1814 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n"); 1815 goto out; 1816 } 1817 for (i = 0; i < 4096; i += 2) { 1818 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i); 1819 buf[i / 2] = cpu_to_le16(tmp); 1820 } 1821 b43info(dev->wl, "Shared memory dump:\n"); 1822 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 1823 16, 2, buf, 4096, 1); 1824 kfree(buf); 1825 break; 1826 case B43_DEBUGIRQ_DUMP_REGS: 1827 if (!B43_DEBUG) 1828 break; /* Only with driver debugging enabled. */ 1829 b43info(dev->wl, "Microcode register dump:\n"); 1830 for (i = 0, cnt = 0; i < 64; i++) { 1831 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i); 1832 if (cnt == 0) 1833 printk(KERN_INFO); 1834 printk("r%02u: 0x%04X ", i, tmp); 1835 cnt++; 1836 if (cnt == 6) { 1837 printk("\n"); 1838 cnt = 0; 1839 } 1840 } 1841 printk("\n"); 1842 break; 1843 case B43_DEBUGIRQ_MARKER: 1844 if (!B43_DEBUG) 1845 break; /* Only with driver debugging enabled. */ 1846 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH, 1847 B43_MARKER_ID_REG); 1848 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH, 1849 B43_MARKER_LINE_REG); 1850 b43info(dev->wl, "The firmware just executed the MARKER(%u) " 1851 "at line number %u\n", 1852 marker_id, marker_line); 1853 break; 1854 default: 1855 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n", 1856 reason); 1857 } 1858out: 1859 /* Acknowledge the debug-IRQ, so the firmware can continue. */ 1860 b43_shm_write16(dev, B43_SHM_SCRATCH, 1861 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK); 1862} 1863 1864static void b43_do_interrupt_thread(struct b43_wldev *dev) 1865{ 1866 u32 reason; 1867 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1868 u32 merged_dma_reason = 0; 1869 int i; 1870 1871 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 1872 return; 1873 1874 reason = dev->irq_reason; 1875 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1876 dma_reason[i] = dev->dma_reason[i]; 1877 merged_dma_reason |= dma_reason[i]; 1878 } 1879 1880 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1881 b43err(dev->wl, "MAC transmission error\n"); 1882 1883 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1884 b43err(dev->wl, "PHY transmission error\n"); 1885 rmb(); 1886 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1887 atomic_set(&dev->phy.txerr_cnt, 1888 B43_PHY_TX_BADNESS_LIMIT); 1889 b43err(dev->wl, "Too many PHY TX errors, " 1890 "restarting the controller\n"); 1891 b43_controller_restart(dev, "PHY TX errors"); 1892 } 1893 } 1894 1895 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1896 B43_DMAIRQ_NONFATALMASK))) { 1897 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1898 b43err(dev->wl, "Fatal DMA error: " 1899 "0x%08X, 0x%08X, 0x%08X, " 1900 "0x%08X, 0x%08X, 0x%08X\n", 1901 dma_reason[0], dma_reason[1], 1902 dma_reason[2], dma_reason[3], 1903 dma_reason[4], dma_reason[5]); 1904 b43err(dev->wl, "This device does not support DMA " 1905 "on your system. It will now be switched to PIO.\n"); 1906 /* Fall back to PIO transfers if we get fatal DMA errors! */ 1907 dev->use_pio = 1; 1908 b43_controller_restart(dev, "DMA error"); 1909 return; 1910 } 1911 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1912 b43err(dev->wl, "DMA error: " 1913 "0x%08X, 0x%08X, 0x%08X, " 1914 "0x%08X, 0x%08X, 0x%08X\n", 1915 dma_reason[0], dma_reason[1], 1916 dma_reason[2], dma_reason[3], 1917 dma_reason[4], dma_reason[5]); 1918 } 1919 } 1920 1921 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1922 handle_irq_ucode_debug(dev); 1923 if (reason & B43_IRQ_TBTT_INDI) 1924 handle_irq_tbtt_indication(dev); 1925 if (reason & B43_IRQ_ATIM_END) 1926 handle_irq_atim_end(dev); 1927 if (reason & B43_IRQ_BEACON) 1928 handle_irq_beacon(dev); 1929 if (reason & B43_IRQ_PMQ) 1930 handle_irq_pmq(dev); 1931 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1932 ;/* TODO */ 1933 if (reason & B43_IRQ_NOISESAMPLE_OK) 1934 handle_irq_noise(dev); 1935 1936 /* Check the DMA reason registers for received data. */ 1937 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 1938 if (b43_using_pio_transfers(dev)) 1939 b43_pio_rx(dev->pio.rx_queue); 1940 else 1941 b43_dma_rx(dev->dma.rx_ring); 1942 } 1943 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1944 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1945 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); 1946 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1947 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1948 1949 if (reason & B43_IRQ_TX_OK) 1950 handle_irq_transmit_status(dev); 1951 1952 /* Re-enable interrupts on the device by restoring the current interrupt mask. */ 1953 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1954 1955#if B43_DEBUG 1956 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 1957 dev->irq_count++; 1958 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 1959 if (reason & (1 << i)) 1960 dev->irq_bit_count[i]++; 1961 } 1962 } 1963#endif 1964} 1965 1966/* Interrupt thread handler. Handles device interrupts in thread context. */ 1967static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id) 1968{ 1969 struct b43_wldev *dev = dev_id; 1970 1971 mutex_lock(&dev->wl->mutex); 1972 b43_do_interrupt_thread(dev); 1973 mmiowb(); 1974 mutex_unlock(&dev->wl->mutex); 1975 1976 return IRQ_HANDLED; 1977} 1978 1979static irqreturn_t b43_do_interrupt(struct b43_wldev *dev) 1980{ 1981 u32 reason; 1982 1983 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses. 1984 * On SDIO, this runs under wl->mutex. */ 1985 1986 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1987 if (reason == 0xffffffff) /* shared IRQ */ 1988 return IRQ_NONE; 1989 reason &= dev->irq_mask; 1990 if (!reason) 1991 return IRQ_NONE; 1992 1993 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1994 & 0x0001DC00; 1995 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1996 & 0x0000DC00; 1997 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1998 & 0x0000DC00; 1999 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 2000 & 0x0001DC00; 2001 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 2002 & 0x0000DC00; 2003/* Unused ring 2004 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 2005 & 0x0000DC00; 2006*/ 2007 2008 /* ACK the interrupt. */ 2009 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 2010 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 2011 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 2012 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 2013 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 2014 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 2015/* Unused ring 2016 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 2017*/ 2018 2019 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */ 2020 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 2021 /* Save the reason bitmasks for the IRQ thread handler. */ 2022 dev->irq_reason = reason; 2023 2024 return IRQ_WAKE_THREAD; 2025} 2026 2027/* Interrupt handler top-half. This runs with interrupts disabled. */ 2028static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 2029{ 2030 struct b43_wldev *dev = dev_id; 2031 irqreturn_t ret; 2032 2033 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2034 return IRQ_NONE; 2035 2036 spin_lock(&dev->wl->hardirq_lock); 2037 ret = b43_do_interrupt(dev); 2038 mmiowb(); 2039 spin_unlock(&dev->wl->hardirq_lock); 2040 2041 return ret; 2042} 2043 2044/* SDIO interrupt handler. This runs in process context. */ 2045static void b43_sdio_interrupt_handler(struct b43_wldev *dev) 2046{ 2047 struct b43_wl *wl = dev->wl; 2048 irqreturn_t ret; 2049 2050 mutex_lock(&wl->mutex); 2051 2052 ret = b43_do_interrupt(dev); 2053 if (ret == IRQ_WAKE_THREAD) 2054 b43_do_interrupt_thread(dev); 2055 2056 mutex_unlock(&wl->mutex); 2057} 2058 2059void b43_do_release_fw(struct b43_firmware_file *fw) 2060{ 2061 release_firmware(fw->data); 2062 fw->data = NULL; 2063 fw->filename = NULL; 2064} 2065 2066static void b43_release_firmware(struct b43_wldev *dev) 2067{ 2068 b43_do_release_fw(&dev->fw.ucode); 2069 b43_do_release_fw(&dev->fw.pcm); 2070 b43_do_release_fw(&dev->fw.initvals); 2071 b43_do_release_fw(&dev->fw.initvals_band); 2072} 2073 2074static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 2075{ 2076 const char text[] = 2077 "You must go to " \ 2078 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \ 2079 "and download the correct firmware for this driver version. " \ 2080 "Please carefully read all instructions on this website.\n"; 2081 2082 if (error) 2083 b43err(wl, text); 2084 else 2085 b43warn(wl, text); 2086} 2087 2088int b43_do_request_fw(struct b43_request_fw_context *ctx, 2089 const char *name, 2090 struct b43_firmware_file *fw) 2091{ 2092 const struct firmware *blob; 2093 struct b43_fw_header *hdr; 2094 u32 size; 2095 int err; 2096 2097 if (!name) { 2098 /* Don't fetch anything. Free possibly cached firmware. */ 2099 /* FIXME: We should probably keep it anyway, to save some headache 2100 * on suspend/resume with multiband devices. */ 2101 b43_do_release_fw(fw); 2102 return 0; 2103 } 2104 if (fw->filename) { 2105 if ((fw->type == ctx->req_type) && 2106 (strcmp(fw->filename, name) == 0)) 2107 return 0; /* Already have this fw. */ 2108 /* Free the cached firmware first. */ 2109 /* FIXME: We should probably do this later after we successfully 2110 * got the new fw. This could reduce headache with multiband devices. 2111 * We could also redesign this to cache the firmware for all possible 2112 * bands all the time. */ 2113 b43_do_release_fw(fw); 2114 } 2115 2116 switch (ctx->req_type) { 2117 case B43_FWTYPE_PROPRIETARY: 2118 snprintf(ctx->fwname, sizeof(ctx->fwname), 2119 "b43%s/%s.fw", 2120 modparam_fwpostfix, name); 2121 break; 2122 case B43_FWTYPE_OPENSOURCE: 2123 snprintf(ctx->fwname, sizeof(ctx->fwname), 2124 "b43-open%s/%s.fw", 2125 modparam_fwpostfix, name); 2126 break; 2127 default: 2128 B43_WARN_ON(1); 2129 return -ENOSYS; 2130 } 2131 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev); 2132 if (err == -ENOENT) { 2133 snprintf(ctx->errors[ctx->req_type], 2134 sizeof(ctx->errors[ctx->req_type]), 2135 "Firmware file \"%s\" not found\n", ctx->fwname); 2136 return err; 2137 } else if (err) { 2138 snprintf(ctx->errors[ctx->req_type], 2139 sizeof(ctx->errors[ctx->req_type]), 2140 "Firmware file \"%s\" request failed (err=%d)\n", 2141 ctx->fwname, err); 2142 return err; 2143 } 2144 if (blob->size < sizeof(struct b43_fw_header)) 2145 goto err_format; 2146 hdr = (struct b43_fw_header *)(blob->data); 2147 switch (hdr->type) { 2148 case B43_FW_TYPE_UCODE: 2149 case B43_FW_TYPE_PCM: 2150 size = be32_to_cpu(hdr->size); 2151 if (size != blob->size - sizeof(struct b43_fw_header)) 2152 goto err_format; 2153 /* fallthrough */ 2154 case B43_FW_TYPE_IV: 2155 if (hdr->ver != 1) 2156 goto err_format; 2157 break; 2158 default: 2159 goto err_format; 2160 } 2161 2162 fw->data = blob; 2163 fw->filename = name; 2164 fw->type = ctx->req_type; 2165 2166 return 0; 2167 2168err_format: 2169 snprintf(ctx->errors[ctx->req_type], 2170 sizeof(ctx->errors[ctx->req_type]), 2171 "Firmware file \"%s\" format error.\n", ctx->fwname); 2172 release_firmware(blob); 2173 2174 return -EPROTO; 2175} 2176 2177static int b43_try_request_fw(struct b43_request_fw_context *ctx) 2178{ 2179 struct b43_wldev *dev = ctx->dev; 2180 struct b43_firmware *fw = &ctx->dev->fw; 2181 const u8 rev = ctx->dev->dev->core_rev; 2182 const char *filename; 2183 u32 tmshigh; 2184 int err; 2185 2186 /* Files for HT and LCN were found by trying one by one */ 2187 2188 /* Get microcode */ 2189 if ((rev >= 5) && (rev <= 10)) { 2190 filename = "ucode5"; 2191 } else if ((rev >= 11) && (rev <= 12)) { 2192 filename = "ucode11"; 2193 } else if (rev == 13) { 2194 filename = "ucode13"; 2195 } else if (rev == 14) { 2196 filename = "ucode14"; 2197 } else if (rev == 15) { 2198 filename = "ucode15"; 2199 } else { 2200 switch (dev->phy.type) { 2201 case B43_PHYTYPE_N: 2202 if (rev >= 16) 2203 filename = "ucode16_mimo"; 2204 else 2205 goto err_no_ucode; 2206 break; 2207 case B43_PHYTYPE_HT: 2208 if (rev == 29) 2209 filename = "ucode29_mimo"; 2210 else 2211 goto err_no_ucode; 2212 break; 2213 case B43_PHYTYPE_LCN: 2214 if (rev == 24) 2215 filename = "ucode24_mimo"; 2216 else 2217 goto err_no_ucode; 2218 break; 2219 default: 2220 goto err_no_ucode; 2221 } 2222 } 2223 err = b43_do_request_fw(ctx, filename, &fw->ucode); 2224 if (err) 2225 goto err_load; 2226 2227 /* Get PCM code */ 2228 if ((rev >= 5) && (rev <= 10)) 2229 filename = "pcm5"; 2230 else if (rev >= 11) 2231 filename = NULL; 2232 else 2233 goto err_no_pcm; 2234 fw->pcm_request_failed = 0; 2235 err = b43_do_request_fw(ctx, filename, &fw->pcm); 2236 if (err == -ENOENT) { 2237 /* We did not find a PCM file? Not fatal, but 2238 * core rev <= 10 must do without hwcrypto then. */ 2239 fw->pcm_request_failed = 1; 2240 } else if (err) 2241 goto err_load; 2242 2243 /* Get initvals */ 2244 switch (dev->phy.type) { 2245 case B43_PHYTYPE_A: 2246 if ((rev >= 5) && (rev <= 10)) { 2247 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 2248 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2249 filename = "a0g1initvals5"; 2250 else 2251 filename = "a0g0initvals5"; 2252 } else 2253 goto err_no_initvals; 2254 break; 2255 case B43_PHYTYPE_G: 2256 if ((rev >= 5) && (rev <= 10)) 2257 filename = "b0g0initvals5"; 2258 else if (rev >= 13) 2259 filename = "b0g0initvals13"; 2260 else 2261 goto err_no_initvals; 2262 break; 2263 case B43_PHYTYPE_N: 2264 if (rev >= 16) 2265 filename = "n0initvals16"; 2266 else if ((rev >= 11) && (rev <= 12)) 2267 filename = "n0initvals11"; 2268 else 2269 goto err_no_initvals; 2270 break; 2271 case B43_PHYTYPE_LP: 2272 if (rev == 13) 2273 filename = "lp0initvals13"; 2274 else if (rev == 14) 2275 filename = "lp0initvals14"; 2276 else if (rev >= 15) 2277 filename = "lp0initvals15"; 2278 else 2279 goto err_no_initvals; 2280 break; 2281 case B43_PHYTYPE_HT: 2282 if (rev == 29) 2283 filename = "ht0initvals29"; 2284 else 2285 goto err_no_initvals; 2286 break; 2287 case B43_PHYTYPE_LCN: 2288 if (rev == 24) 2289 filename = "lcn0initvals24"; 2290 else 2291 goto err_no_initvals; 2292 break; 2293 default: 2294 goto err_no_initvals; 2295 } 2296 err = b43_do_request_fw(ctx, filename, &fw->initvals); 2297 if (err) 2298 goto err_load; 2299 2300 /* Get bandswitch initvals */ 2301 switch (dev->phy.type) { 2302 case B43_PHYTYPE_A: 2303 if ((rev >= 5) && (rev <= 10)) { 2304 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 2305 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2306 filename = "a0g1bsinitvals5"; 2307 else 2308 filename = "a0g0bsinitvals5"; 2309 } else if (rev >= 11) 2310 filename = NULL; 2311 else 2312 goto err_no_initvals; 2313 break; 2314 case B43_PHYTYPE_G: 2315 if ((rev >= 5) && (rev <= 10)) 2316 filename = "b0g0bsinitvals5"; 2317 else if (rev >= 11) 2318 filename = NULL; 2319 else 2320 goto err_no_initvals; 2321 break; 2322 case B43_PHYTYPE_N: 2323 if (rev >= 16) 2324 filename = "n0bsinitvals16"; 2325 else if ((rev >= 11) && (rev <= 12)) 2326 filename = "n0bsinitvals11"; 2327 else 2328 goto err_no_initvals; 2329 break; 2330 case B43_PHYTYPE_LP: 2331 if (rev == 13) 2332 filename = "lp0bsinitvals13"; 2333 else if (rev == 14) 2334 filename = "lp0bsinitvals14"; 2335 else if (rev >= 15) 2336 filename = "lp0bsinitvals15"; 2337 else 2338 goto err_no_initvals; 2339 break; 2340 case B43_PHYTYPE_HT: 2341 if (rev == 29) 2342 filename = "ht0bsinitvals29"; 2343 else 2344 goto err_no_initvals; 2345 break; 2346 case B43_PHYTYPE_LCN: 2347 if (rev == 24) 2348 filename = "lcn0bsinitvals24"; 2349 else 2350 goto err_no_initvals; 2351 break; 2352 default: 2353 goto err_no_initvals; 2354 } 2355 err = b43_do_request_fw(ctx, filename, &fw->initvals_band); 2356 if (err) 2357 goto err_load; 2358 2359 return 0; 2360 2361err_no_ucode: 2362 err = ctx->fatal_failure = -EOPNOTSUPP; 2363 b43err(dev->wl, "The driver does not know which firmware (ucode) " 2364 "is required for your device (wl-core rev %u)\n", rev); 2365 goto error; 2366 2367err_no_pcm: 2368 err = ctx->fatal_failure = -EOPNOTSUPP; 2369 b43err(dev->wl, "The driver does not know which firmware (PCM) " 2370 "is required for your device (wl-core rev %u)\n", rev); 2371 goto error; 2372 2373err_no_initvals: 2374 err = ctx->fatal_failure = -EOPNOTSUPP; 2375 b43err(dev->wl, "The driver does not know which firmware (initvals) " 2376 "is required for your device (wl-core rev %u)\n", rev); 2377 goto error; 2378 2379err_load: 2380 /* We failed to load this firmware image. The error message 2381 * already is in ctx->errors. Return and let our caller decide 2382 * what to do. */ 2383 goto error; 2384 2385error: 2386 b43_release_firmware(dev); 2387 return err; 2388} 2389 2390static int b43_request_firmware(struct b43_wldev *dev) 2391{ 2392 struct b43_request_fw_context *ctx; 2393 unsigned int i; 2394 int err; 2395 const char *errmsg; 2396 2397 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2398 if (!ctx) 2399 return -ENOMEM; 2400 ctx->dev = dev; 2401 2402 ctx->req_type = B43_FWTYPE_PROPRIETARY; 2403 err = b43_try_request_fw(ctx); 2404 if (!err) 2405 goto out; /* Successfully loaded it. */ 2406 err = ctx->fatal_failure; 2407 if (err) 2408 goto out; 2409 2410 ctx->req_type = B43_FWTYPE_OPENSOURCE; 2411 err = b43_try_request_fw(ctx); 2412 if (!err) 2413 goto out; /* Successfully loaded it. */ 2414 err = ctx->fatal_failure; 2415 if (err) 2416 goto out; 2417 2418 /* Could not find a usable firmware. Print the errors. */ 2419 for (i = 0; i < B43_NR_FWTYPES; i++) { 2420 errmsg = ctx->errors[i]; 2421 if (strlen(errmsg)) 2422 b43err(dev->wl, errmsg); 2423 } 2424 b43_print_fw_helptext(dev->wl, 1); 2425 err = -ENOENT; 2426 2427out: 2428 kfree(ctx); 2429 return err; 2430} 2431 2432static int b43_upload_microcode(struct b43_wldev *dev) 2433{ 2434 struct wiphy *wiphy = dev->wl->hw->wiphy; 2435 const size_t hdr_len = sizeof(struct b43_fw_header); 2436 const __be32 *data; 2437 unsigned int i, len; 2438 u16 fwrev, fwpatch, fwdate, fwtime; 2439 u32 tmp, macctl; 2440 int err = 0; 2441 2442 /* Jump the microcode PSM to offset 0 */ 2443 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2444 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); 2445 macctl |= B43_MACCTL_PSM_JMP0; 2446 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2447 /* Zero out all microcode PSM registers and shared memory. */ 2448 for (i = 0; i < 64; i++) 2449 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); 2450 for (i = 0; i < 4096; i += 2) 2451 b43_shm_write16(dev, B43_SHM_SHARED, i, 0); 2452 2453 /* Upload Microcode. */ 2454 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); 2455 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); 2456 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 2457 for (i = 0; i < len; i++) { 2458 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2459 udelay(10); 2460 } 2461 2462 if (dev->fw.pcm.data) { 2463 /* Upload PCM data. */ 2464 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); 2465 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); 2466 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 2467 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 2468 /* No need for autoinc bit in SHM_HW */ 2469 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 2470 for (i = 0; i < len; i++) { 2471 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2472 udelay(10); 2473 } 2474 } 2475 2476 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 2477 2478 /* Start the microcode PSM */ 2479 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2480 macctl &= ~B43_MACCTL_PSM_JMP0; 2481 macctl |= B43_MACCTL_PSM_RUN; 2482 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2483 2484 /* Wait for the microcode to load and respond */ 2485 i = 0; 2486 while (1) { 2487 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2488 if (tmp == B43_IRQ_MAC_SUSPENDED) 2489 break; 2490 i++; 2491 if (i >= 20) { 2492 b43err(dev->wl, "Microcode not responding\n"); 2493 b43_print_fw_helptext(dev->wl, 1); 2494 err = -ENODEV; 2495 goto error; 2496 } 2497 msleep(50); 2498 } 2499 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 2500 2501 /* Get and check the revisions. */ 2502 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 2503 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 2504 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 2505 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 2506 2507 if (fwrev <= 0x128) { 2508 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 2509 "binary drivers older than version 4.x is unsupported. " 2510 "You must upgrade your firmware files.\n"); 2511 b43_print_fw_helptext(dev->wl, 1); 2512 err = -EOPNOTSUPP; 2513 goto error; 2514 } 2515 dev->fw.rev = fwrev; 2516 dev->fw.patch = fwpatch; 2517 if (dev->fw.rev >= 598) 2518 dev->fw.hdr_format = B43_FW_HDR_598; 2519 else if (dev->fw.rev >= 410) 2520 dev->fw.hdr_format = B43_FW_HDR_410; 2521 else 2522 dev->fw.hdr_format = B43_FW_HDR_351; 2523 dev->fw.opensource = (fwdate == 0xFFFF); 2524 2525 /* Default to use-all-queues. */ 2526 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues; 2527 dev->qos_enabled = !!modparam_qos; 2528 /* Default to firmware/hardware crypto acceleration. */ 2529 dev->hwcrypto_enabled = 1; 2530 2531 if (dev->fw.opensource) { 2532 u16 fwcapa; 2533 2534 /* Patchlevel info is encoded in the "time" field. */ 2535 dev->fw.patch = fwtime; 2536 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n", 2537 dev->fw.rev, dev->fw.patch); 2538 2539 fwcapa = b43_fwcapa_read(dev); 2540 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) { 2541 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n"); 2542 /* Disable hardware crypto and fall back to software crypto. */ 2543 dev->hwcrypto_enabled = 0; 2544 } 2545 if (!(fwcapa & B43_FWCAPA_QOS)) { 2546 b43info(dev->wl, "QoS not supported by firmware\n"); 2547 /* Disable QoS. Tweak hw->queues to 1. It will be restored before 2548 * ieee80211_unregister to make sure the networking core can 2549 * properly free possible resources. */ 2550 dev->wl->hw->queues = 1; 2551 dev->qos_enabled = 0; 2552 } 2553 } else { 2554 b43info(dev->wl, "Loading firmware version %u.%u " 2555 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 2556 fwrev, fwpatch, 2557 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 2558 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 2559 if (dev->fw.pcm_request_failed) { 2560 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. " 2561 "Hardware accelerated cryptography is disabled.\n"); 2562 b43_print_fw_helptext(dev->wl, 0); 2563 } 2564 } 2565 2566 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", 2567 dev->fw.rev, dev->fw.patch); 2568 wiphy->hw_version = dev->dev->core_id; 2569 2570 if (dev->fw.hdr_format == B43_FW_HDR_351) { 2571 /* We're over the deadline, but we keep support for old fw 2572 * until it turns out to be in major conflict with something new. */ 2573 b43warn(dev->wl, "You are using an old firmware image. " 2574 "Support for old firmware will be removed soon " 2575 "(official deadline was July 2008).\n"); 2576 b43_print_fw_helptext(dev->wl, 0); 2577 } 2578 2579 return 0; 2580 2581error: 2582 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2583 macctl &= ~B43_MACCTL_PSM_RUN; 2584 macctl |= B43_MACCTL_PSM_JMP0; 2585 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2586 2587 return err; 2588} 2589 2590static int b43_write_initvals(struct b43_wldev *dev, 2591 const struct b43_iv *ivals, 2592 size_t count, 2593 size_t array_size) 2594{ 2595 const struct b43_iv *iv; 2596 u16 offset; 2597 size_t i; 2598 bool bit32; 2599 2600 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 2601 iv = ivals; 2602 for (i = 0; i < count; i++) { 2603 if (array_size < sizeof(iv->offset_size)) 2604 goto err_format; 2605 array_size -= sizeof(iv->offset_size); 2606 offset = be16_to_cpu(iv->offset_size); 2607 bit32 = !!(offset & B43_IV_32BIT); 2608 offset &= B43_IV_OFFSET_MASK; 2609 if (offset >= 0x1000) 2610 goto err_format; 2611 if (bit32) { 2612 u32 value; 2613 2614 if (array_size < sizeof(iv->data.d32)) 2615 goto err_format; 2616 array_size -= sizeof(iv->data.d32); 2617 2618 value = get_unaligned_be32(&iv->data.d32); 2619 b43_write32(dev, offset, value); 2620 2621 iv = (const struct b43_iv *)((const uint8_t *)iv + 2622 sizeof(__be16) + 2623 sizeof(__be32)); 2624 } else { 2625 u16 value; 2626 2627 if (array_size < sizeof(iv->data.d16)) 2628 goto err_format; 2629 array_size -= sizeof(iv->data.d16); 2630 2631 value = be16_to_cpu(iv->data.d16); 2632 b43_write16(dev, offset, value); 2633 2634 iv = (const struct b43_iv *)((const uint8_t *)iv + 2635 sizeof(__be16) + 2636 sizeof(__be16)); 2637 } 2638 } 2639 if (array_size) 2640 goto err_format; 2641 2642 return 0; 2643 2644err_format: 2645 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 2646 b43_print_fw_helptext(dev->wl, 1); 2647 2648 return -EPROTO; 2649} 2650 2651static int b43_upload_initvals(struct b43_wldev *dev) 2652{ 2653 const size_t hdr_len = sizeof(struct b43_fw_header); 2654 const struct b43_fw_header *hdr; 2655 struct b43_firmware *fw = &dev->fw; 2656 const struct b43_iv *ivals; 2657 size_t count; 2658 int err; 2659 2660 hdr = (const struct b43_fw_header *)(fw->initvals.data->data); 2661 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); 2662 count = be32_to_cpu(hdr->size); 2663 err = b43_write_initvals(dev, ivals, count, 2664 fw->initvals.data->size - hdr_len); 2665 if (err) 2666 goto out; 2667 if (fw->initvals_band.data) { 2668 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); 2669 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); 2670 count = be32_to_cpu(hdr->size); 2671 err = b43_write_initvals(dev, ivals, count, 2672 fw->initvals_band.data->size - hdr_len); 2673 if (err) 2674 goto out; 2675 } 2676out: 2677 2678 return err; 2679} 2680 2681/* Initialize the GPIOs 2682 * http://bcm-specs.sipsolutions.net/GPIO 2683 */ 2684static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev) 2685{ 2686 struct ssb_bus *bus = dev->dev->sdev->bus; 2687 2688#ifdef CONFIG_SSB_DRIVER_PCICORE 2689 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev); 2690#else 2691 return bus->chipco.dev; 2692#endif 2693} 2694 2695static int b43_gpio_init(struct b43_wldev *dev) 2696{ 2697 struct ssb_device *gpiodev; 2698 u32 mask, set; 2699 2700 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2701 & ~B43_MACCTL_GPOUTSMSK); 2702 2703 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 2704 | 0x000F); 2705 2706 mask = 0x0000001F; 2707 set = 0x0000000F; 2708 if (dev->dev->chip_id == 0x4301) { 2709 mask |= 0x0060; 2710 set |= 0x0060; 2711 } 2712 if (0 /* FIXME: conditional unknown */ ) { 2713 b43_write16(dev, B43_MMIO_GPIO_MASK, 2714 b43_read16(dev, B43_MMIO_GPIO_MASK) 2715 | 0x0100); 2716 mask |= 0x0180; 2717 set |= 0x0180; 2718 } 2719 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) { 2720 b43_write16(dev, B43_MMIO_GPIO_MASK, 2721 b43_read16(dev, B43_MMIO_GPIO_MASK) 2722 | 0x0200); 2723 mask |= 0x0200; 2724 set |= 0x0200; 2725 } 2726 if (dev->dev->core_rev >= 2) 2727 mask |= 0x0010; /* FIXME: This is redundant. */ 2728 2729 switch (dev->dev->bus_type) { 2730#ifdef CONFIG_B43_BCMA 2731 case B43_BUS_BCMA: 2732 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL, 2733 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc, 2734 BCMA_CC_GPIOCTL) & mask) | set); 2735 break; 2736#endif 2737#ifdef CONFIG_B43_SSB 2738 case B43_BUS_SSB: 2739 gpiodev = b43_ssb_gpio_dev(dev); 2740 if (gpiodev) 2741 ssb_write32(gpiodev, B43_GPIO_CONTROL, 2742 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2743 & mask) | set); 2744 break; 2745#endif 2746 } 2747 2748 return 0; 2749} 2750 2751/* Turn off all GPIO stuff. Call this on module unload, for example. */ 2752static void b43_gpio_cleanup(struct b43_wldev *dev) 2753{ 2754 struct ssb_device *gpiodev; 2755 2756 switch (dev->dev->bus_type) { 2757#ifdef CONFIG_B43_BCMA 2758 case B43_BUS_BCMA: 2759 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL, 2760 0); 2761 break; 2762#endif 2763#ifdef CONFIG_B43_SSB 2764 case B43_BUS_SSB: 2765 gpiodev = b43_ssb_gpio_dev(dev); 2766 if (gpiodev) 2767 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2768 break; 2769#endif 2770 } 2771} 2772 2773/* http://bcm-specs.sipsolutions.net/EnableMac */ 2774void b43_mac_enable(struct b43_wldev *dev) 2775{ 2776 if (b43_debug(dev, B43_DBG_FIRMWARE)) { 2777 u16 fwstate; 2778 2779 fwstate = b43_shm_read16(dev, B43_SHM_SHARED, 2780 B43_SHM_SH_UCODESTAT); 2781 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) && 2782 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) { 2783 b43err(dev->wl, "b43_mac_enable(): The firmware " 2784 "should be suspended, but current state is %u\n", 2785 fwstate); 2786 } 2787 } 2788 2789 dev->mac_suspended--; 2790 B43_WARN_ON(dev->mac_suspended < 0); 2791 if (dev->mac_suspended == 0) { 2792 b43_write32(dev, B43_MMIO_MACCTL, 2793 b43_read32(dev, B43_MMIO_MACCTL) 2794 | B43_MACCTL_ENABLED); 2795 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2796 B43_IRQ_MAC_SUSPENDED); 2797 /* Commit writes */ 2798 b43_read32(dev, B43_MMIO_MACCTL); 2799 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2800 b43_power_saving_ctl_bits(dev, 0); 2801 } 2802} 2803 2804/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2805void b43_mac_suspend(struct b43_wldev *dev) 2806{ 2807 int i; 2808 u32 tmp; 2809 2810 might_sleep(); 2811 B43_WARN_ON(dev->mac_suspended < 0); 2812 2813 if (dev->mac_suspended == 0) { 2814 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2815 b43_write32(dev, B43_MMIO_MACCTL, 2816 b43_read32(dev, B43_MMIO_MACCTL) 2817 & ~B43_MACCTL_ENABLED); 2818 /* force pci to flush the write */ 2819 b43_read32(dev, B43_MMIO_MACCTL); 2820 for (i = 35; i; i--) { 2821 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2822 if (tmp & B43_IRQ_MAC_SUSPENDED) 2823 goto out; 2824 udelay(10); 2825 } 2826 /* Hm, it seems this will take some time. Use msleep(). */ 2827 for (i = 40; i; i--) { 2828 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2829 if (tmp & B43_IRQ_MAC_SUSPENDED) 2830 goto out; 2831 msleep(1); 2832 } 2833 b43err(dev->wl, "MAC suspend failed\n"); 2834 } 2835out: 2836 dev->mac_suspended++; 2837} 2838 2839/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 2840void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on) 2841{ 2842 u32 tmp; 2843 2844 switch (dev->dev->bus_type) { 2845#ifdef CONFIG_B43_BCMA 2846 case B43_BUS_BCMA: 2847 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 2848 if (on) 2849 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN; 2850 else 2851 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN; 2852 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); 2853 break; 2854#endif 2855#ifdef CONFIG_B43_SSB 2856 case B43_BUS_SSB: 2857 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 2858 if (on) 2859 tmp |= B43_TMSLOW_MACPHYCLKEN; 2860 else 2861 tmp &= ~B43_TMSLOW_MACPHYCLKEN; 2862 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 2863 break; 2864#endif 2865 } 2866} 2867 2868static void b43_adjust_opmode(struct b43_wldev *dev) 2869{ 2870 struct b43_wl *wl = dev->wl; 2871 u32 ctl; 2872 u16 cfp_pretbtt; 2873 2874 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2875 /* Reset status to STA infrastructure mode. */ 2876 ctl &= ~B43_MACCTL_AP; 2877 ctl &= ~B43_MACCTL_KEEP_CTL; 2878 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2879 ctl &= ~B43_MACCTL_KEEP_BAD; 2880 ctl &= ~B43_MACCTL_PROMISC; 2881 ctl &= ~B43_MACCTL_BEACPROMISC; 2882 ctl |= B43_MACCTL_INFRA; 2883 2884 if (b43_is_mode(wl, NL80211_IFTYPE_AP) || 2885 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 2886 ctl |= B43_MACCTL_AP; 2887 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 2888 ctl &= ~B43_MACCTL_INFRA; 2889 2890 if (wl->filter_flags & FIF_CONTROL) 2891 ctl |= B43_MACCTL_KEEP_CTL; 2892 if (wl->filter_flags & FIF_FCSFAIL) 2893 ctl |= B43_MACCTL_KEEP_BAD; 2894 if (wl->filter_flags & FIF_PLCPFAIL) 2895 ctl |= B43_MACCTL_KEEP_BADPLCP; 2896 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2897 ctl |= B43_MACCTL_PROMISC; 2898 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2899 ctl |= B43_MACCTL_BEACPROMISC; 2900 2901 /* Workaround: On old hardware the HW-MAC-address-filter 2902 * doesn't work properly, so always run promisc in filter 2903 * it in software. */ 2904 if (dev->dev->core_rev <= 4) 2905 ctl |= B43_MACCTL_PROMISC; 2906 2907 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2908 2909 cfp_pretbtt = 2; 2910 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2911 if (dev->dev->chip_id == 0x4306 && 2912 dev->dev->chip_rev == 3) 2913 cfp_pretbtt = 100; 2914 else 2915 cfp_pretbtt = 50; 2916 } 2917 b43_write16(dev, 0x612, cfp_pretbtt); 2918 2919 /* FIXME: We don't currently implement the PMQ mechanism, 2920 * so always disable it. If we want to implement PMQ, 2921 * we need to enable it here (clear DISCPMQ) in AP mode. 2922 */ 2923 if (0 /* ctl & B43_MACCTL_AP */) { 2924 b43_write32(dev, B43_MMIO_MACCTL, 2925 b43_read32(dev, B43_MMIO_MACCTL) 2926 & ~B43_MACCTL_DISCPMQ); 2927 } else { 2928 b43_write32(dev, B43_MMIO_MACCTL, 2929 b43_read32(dev, B43_MMIO_MACCTL) 2930 | B43_MACCTL_DISCPMQ); 2931 } 2932} 2933 2934static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2935{ 2936 u16 offset; 2937 2938 if (is_ofdm) { 2939 offset = 0x480; 2940 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2941 } else { 2942 offset = 0x4C0; 2943 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2944 } 2945 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2946 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2947} 2948 2949static void b43_rate_memory_init(struct b43_wldev *dev) 2950{ 2951 switch (dev->phy.type) { 2952 case B43_PHYTYPE_A: 2953 case B43_PHYTYPE_G: 2954 case B43_PHYTYPE_N: 2955 case B43_PHYTYPE_LP: 2956 case B43_PHYTYPE_HT: 2957 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2958 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2959 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2960 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2961 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2962 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2963 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2964 if (dev->phy.type == B43_PHYTYPE_A) 2965 break; 2966 /* fallthrough */ 2967 case B43_PHYTYPE_B: 2968 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2969 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2970 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2971 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2972 break; 2973 default: 2974 B43_WARN_ON(1); 2975 } 2976} 2977 2978/* Set the default values for the PHY TX Control Words. */ 2979static void b43_set_phytxctl_defaults(struct b43_wldev *dev) 2980{ 2981 u16 ctl = 0; 2982 2983 ctl |= B43_TXH_PHY_ENC_CCK; 2984 ctl |= B43_TXH_PHY_ANT01AUTO; 2985 ctl |= B43_TXH_PHY_TXPWR; 2986 2987 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 2988 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); 2989 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); 2990} 2991 2992/* Set the TX-Antenna for management frames sent by firmware. */ 2993static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2994{ 2995 u16 ant; 2996 u16 tmp; 2997 2998 ant = b43_antenna_to_phyctl(antenna); 2999 3000 /* For ACK/CTS */ 3001 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 3002 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 3003 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 3004 /* For Probe Resposes */ 3005 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 3006 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 3007 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 3008} 3009 3010/* This is the opposite of b43_chip_init() */ 3011static void b43_chip_exit(struct b43_wldev *dev) 3012{ 3013 b43_phy_exit(dev); 3014 b43_gpio_cleanup(dev); 3015 /* firmware is released later */ 3016} 3017 3018/* Initialize the chip 3019 * http://bcm-specs.sipsolutions.net/ChipInit 3020 */ 3021static int b43_chip_init(struct b43_wldev *dev) 3022{ 3023 struct b43_phy *phy = &dev->phy; 3024 int err; 3025 u32 macctl; 3026 u16 value16; 3027 3028 /* Initialize the MAC control */ 3029 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; 3030 if (dev->phy.gmode) 3031 macctl |= B43_MACCTL_GMODE; 3032 macctl |= B43_MACCTL_INFRA; 3033 b43_write32(dev, B43_MMIO_MACCTL, macctl); 3034 3035 err = b43_request_firmware(dev); 3036 if (err) 3037 goto out; 3038 err = b43_upload_microcode(dev); 3039 if (err) 3040 goto out; /* firmware is released later */ 3041 3042 err = b43_gpio_init(dev); 3043 if (err) 3044 goto out; /* firmware is released later */ 3045 3046 err = b43_upload_initvals(dev); 3047 if (err) 3048 goto err_gpio_clean; 3049 3050 /* Turn the Analog on and initialize the PHY. */ 3051 phy->ops->switch_analog(dev, 1); 3052 err = b43_phy_init(dev); 3053 if (err) 3054 goto err_gpio_clean; 3055 3056 /* Disable Interference Mitigation. */ 3057 if (phy->ops->interf_mitigation) 3058 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); 3059 3060 /* Select the antennae */ 3061 if (phy->ops->set_rx_antenna) 3062 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 3063 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 3064 3065 if (phy->type == B43_PHYTYPE_B) { 3066 value16 = b43_read16(dev, 0x005E); 3067 value16 |= 0x0004; 3068 b43_write16(dev, 0x005E, value16); 3069 } 3070 b43_write32(dev, 0x0100, 0x01000000); 3071 if (dev->dev->core_rev < 5) 3072 b43_write32(dev, 0x010C, 0x01000000); 3073 3074 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 3075 & ~B43_MACCTL_INFRA); 3076 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 3077 | B43_MACCTL_INFRA); 3078 3079 /* Probe Response Timeout value */ 3080 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 3081 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 3082 3083 /* Initially set the wireless operation mode. */ 3084 b43_adjust_opmode(dev); 3085 3086 if (dev->dev->core_rev < 3) { 3087 b43_write16(dev, 0x060E, 0x0000); 3088 b43_write16(dev, 0x0610, 0x8000); 3089 b43_write16(dev, 0x0604, 0x0000); 3090 b43_write16(dev, 0x0606, 0x0200); 3091 } else { 3092 b43_write32(dev, 0x0188, 0x80000000); 3093 b43_write32(dev, 0x018C, 0x02000000); 3094 } 3095 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 3096 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 3097 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 3098 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 3099 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 3100 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 3101 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 3102 3103 b43_mac_phy_clock_set(dev, true); 3104 3105 switch (dev->dev->bus_type) { 3106#ifdef CONFIG_B43_BCMA 3107 case B43_BUS_BCMA: 3108 /* FIXME: 0xE74 is quite common, but should be read from CC */ 3109 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74); 3110 break; 3111#endif 3112#ifdef CONFIG_B43_SSB 3113 case B43_BUS_SSB: 3114 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 3115 dev->dev->sdev->bus->chipco.fast_pwrup_delay); 3116 break; 3117#endif 3118 } 3119 3120 err = 0; 3121 b43dbg(dev->wl, "Chip initialized\n"); 3122out: 3123 return err; 3124 3125err_gpio_clean: 3126 b43_gpio_cleanup(dev); 3127 return err; 3128} 3129 3130static void b43_periodic_every60sec(struct b43_wldev *dev) 3131{ 3132 const struct b43_phy_operations *ops = dev->phy.ops; 3133 3134 if (ops->pwork_60sec) 3135 ops->pwork_60sec(dev); 3136 3137 /* Force check the TX power emission now. */ 3138 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME); 3139} 3140 3141static void b43_periodic_every30sec(struct b43_wldev *dev) 3142{ 3143 /* Update device statistics. */ 3144 b43_calculate_link_quality(dev); 3145} 3146 3147static void b43_periodic_every15sec(struct b43_wldev *dev) 3148{ 3149 struct b43_phy *phy = &dev->phy; 3150 u16 wdr; 3151 3152 if (dev->fw.opensource) { 3153 /* Check if the firmware is still alive. 3154 * It will reset the watchdog counter to 0 in its idle loop. */ 3155 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG); 3156 if (unlikely(wdr)) { 3157 b43err(dev->wl, "Firmware watchdog: The firmware died!\n"); 3158 b43_controller_restart(dev, "Firmware watchdog"); 3159 return; 3160 } else { 3161 b43_shm_write16(dev, B43_SHM_SCRATCH, 3162 B43_WATCHDOG_REG, 1); 3163 } 3164 } 3165 3166 if (phy->ops->pwork_15sec) 3167 phy->ops->pwork_15sec(dev); 3168 3169 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3170 wmb(); 3171 3172#if B43_DEBUG 3173 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 3174 unsigned int i; 3175 3176 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n", 3177 dev->irq_count / 15, 3178 dev->tx_count / 15, 3179 dev->rx_count / 15); 3180 dev->irq_count = 0; 3181 dev->tx_count = 0; 3182 dev->rx_count = 0; 3183 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 3184 if (dev->irq_bit_count[i]) { 3185 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", 3186 dev->irq_bit_count[i] / 15, i, (1 << i)); 3187 dev->irq_bit_count[i] = 0; 3188 } 3189 } 3190 } 3191#endif 3192} 3193 3194static void do_periodic_work(struct b43_wldev *dev) 3195{ 3196 unsigned int state; 3197 3198 state = dev->periodic_state; 3199 if (state % 4 == 0) 3200 b43_periodic_every60sec(dev); 3201 if (state % 2 == 0) 3202 b43_periodic_every30sec(dev); 3203 b43_periodic_every15sec(dev); 3204} 3205 3206/* Periodic work locking policy: 3207 * The whole periodic work handler is protected by 3208 * wl->mutex. If another lock is needed somewhere in the 3209 * pwork callchain, it's acquired in-place, where it's needed. 3210 */ 3211static void b43_periodic_work_handler(struct work_struct *work) 3212{ 3213 struct b43_wldev *dev = container_of(work, struct b43_wldev, 3214 periodic_work.work); 3215 struct b43_wl *wl = dev->wl; 3216 unsigned long delay; 3217 3218 mutex_lock(&wl->mutex); 3219 3220 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 3221 goto out; 3222 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 3223 goto out_requeue; 3224 3225 do_periodic_work(dev); 3226 3227 dev->periodic_state++; 3228out_requeue: 3229 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 3230 delay = msecs_to_jiffies(50); 3231 else 3232 delay = round_jiffies_relative(HZ * 15); 3233 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); 3234out: 3235 mutex_unlock(&wl->mutex); 3236} 3237 3238static void b43_periodic_tasks_setup(struct b43_wldev *dev) 3239{ 3240 struct delayed_work *work = &dev->periodic_work; 3241 3242 dev->periodic_state = 0; 3243 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 3244 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); 3245} 3246 3247/* Check if communication with the device works correctly. */ 3248static int b43_validate_chipaccess(struct b43_wldev *dev) 3249{ 3250 u32 v, backup0, backup4; 3251 3252 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); 3253 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4); 3254 3255 /* Check for read/write and endianness problems. */ 3256 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 3257 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 3258 goto error; 3259 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 3260 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 3261 goto error; 3262 3263 /* Check if unaligned 32bit SHM_SHARED access works properly. 3264 * However, don't bail out on failure, because it's noncritical. */ 3265 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); 3266 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); 3267 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); 3268 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); 3269 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) 3270 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n"); 3271 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); 3272 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || 3273 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || 3274 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || 3275 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) 3276 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n"); 3277 3278 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); 3279 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); 3280 3281 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) { 3282 /* The 32bit register shadows the two 16bit registers 3283 * with update sideeffects. Validate this. */ 3284 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 3285 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 3286 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 3287 goto error; 3288 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 3289 goto error; 3290 } 3291 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 3292 3293 v = b43_read32(dev, B43_MMIO_MACCTL); 3294 v |= B43_MACCTL_GMODE; 3295 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 3296 goto error; 3297 3298 return 0; 3299error: 3300 b43err(dev->wl, "Failed to validate the chipaccess\n"); 3301 return -ENODEV; 3302} 3303 3304static void b43_security_init(struct b43_wldev *dev) 3305{ 3306 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 3307 /* KTP is a word address, but we address SHM bytewise. 3308 * So multiply by two. 3309 */ 3310 dev->ktp *= 2; 3311 /* Number of RCMTA address slots */ 3312 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS); 3313 /* Clear the key memory. */ 3314 b43_clear_keys(dev); 3315} 3316 3317#ifdef CONFIG_B43_HWRNG 3318static int b43_rng_read(struct hwrng *rng, u32 *data) 3319{ 3320 struct b43_wl *wl = (struct b43_wl *)rng->priv; 3321 struct b43_wldev *dev; 3322 int count = -ENODEV; 3323 3324 mutex_lock(&wl->mutex); 3325 dev = wl->current_dev; 3326 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) { 3327 *data = b43_read16(dev, B43_MMIO_RNG); 3328 count = sizeof(u16); 3329 } 3330 mutex_unlock(&wl->mutex); 3331 3332 return count; 3333} 3334#endif /* CONFIG_B43_HWRNG */ 3335 3336static void b43_rng_exit(struct b43_wl *wl) 3337{ 3338#ifdef CONFIG_B43_HWRNG 3339 if (wl->rng_initialized) 3340 hwrng_unregister(&wl->rng); 3341#endif /* CONFIG_B43_HWRNG */ 3342} 3343 3344static int b43_rng_init(struct b43_wl *wl) 3345{ 3346 int err = 0; 3347 3348#ifdef CONFIG_B43_HWRNG 3349 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 3350 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 3351 wl->rng.name = wl->rng_name; 3352 wl->rng.data_read = b43_rng_read; 3353 wl->rng.priv = (unsigned long)wl; 3354 wl->rng_initialized = 1; 3355 err = hwrng_register(&wl->rng); 3356 if (err) { 3357 wl->rng_initialized = 0; 3358 b43err(wl, "Failed to register the random " 3359 "number generator (%d)\n", err); 3360 } 3361#endif /* CONFIG_B43_HWRNG */ 3362 3363 return err; 3364} 3365 3366static void b43_tx_work(struct work_struct *work) 3367{ 3368 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work); 3369 struct b43_wldev *dev; 3370 struct sk_buff *skb; 3371 int err = 0; 3372 3373 mutex_lock(&wl->mutex); 3374 dev = wl->current_dev; 3375 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) { 3376 mutex_unlock(&wl->mutex); 3377 return; 3378 } 3379 3380 while (skb_queue_len(&wl->tx_queue)) { 3381 skb = skb_dequeue(&wl->tx_queue); 3382 3383 if (b43_using_pio_transfers(dev)) 3384 err = b43_pio_tx(dev, skb); 3385 else 3386 err = b43_dma_tx(dev, skb); 3387 if (unlikely(err)) 3388 dev_kfree_skb(skb); /* Drop it */ 3389 } 3390 3391#if B43_DEBUG 3392 dev->tx_count++; 3393#endif 3394 mutex_unlock(&wl->mutex); 3395} 3396 3397static void b43_op_tx(struct ieee80211_hw *hw, 3398 struct sk_buff *skb) 3399{ 3400 struct b43_wl *wl = hw_to_b43_wl(hw); 3401 3402 if (unlikely(skb->len < 2 + 2 + 6)) { 3403 /* Too short, this can't be a valid frame. */ 3404 dev_kfree_skb_any(skb); 3405 return; 3406 } 3407 B43_WARN_ON(skb_shinfo(skb)->nr_frags); 3408 3409 skb_queue_tail(&wl->tx_queue, skb); 3410 ieee80211_queue_work(wl->hw, &wl->tx_work); 3411} 3412 3413static void b43_qos_params_upload(struct b43_wldev *dev, 3414 const struct ieee80211_tx_queue_params *p, 3415 u16 shm_offset) 3416{ 3417 u16 params[B43_NR_QOSPARAMS]; 3418 int bslots, tmp; 3419 unsigned int i; 3420 3421 if (!dev->qos_enabled) 3422 return; 3423 3424 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min; 3425 3426 memset(¶ms, 0, sizeof(params)); 3427 3428 params[B43_QOSPARAM_TXOP] = p->txop * 32; 3429 params[B43_QOSPARAM_CWMIN] = p->cw_min; 3430 params[B43_QOSPARAM_CWMAX] = p->cw_max; 3431 params[B43_QOSPARAM_CWCUR] = p->cw_min; 3432 params[B43_QOSPARAM_AIFS] = p->aifs; 3433 params[B43_QOSPARAM_BSLOTS] = bslots; 3434 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs; 3435 3436 for (i = 0; i < ARRAY_SIZE(params); i++) { 3437 if (i == B43_QOSPARAM_STATUS) { 3438 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 3439 shm_offset + (i * 2)); 3440 /* Mark the parameters as updated. */ 3441 tmp |= 0x100; 3442 b43_shm_write16(dev, B43_SHM_SHARED, 3443 shm_offset + (i * 2), 3444 tmp); 3445 } else { 3446 b43_shm_write16(dev, B43_SHM_SHARED, 3447 shm_offset + (i * 2), 3448 params[i]); 3449 } 3450 } 3451} 3452 3453/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */ 3454static const u16 b43_qos_shm_offsets[] = { 3455 /* [mac80211-queue-nr] = SHM_OFFSET, */ 3456 [0] = B43_QOS_VOICE, 3457 [1] = B43_QOS_VIDEO, 3458 [2] = B43_QOS_BESTEFFORT, 3459 [3] = B43_QOS_BACKGROUND, 3460}; 3461 3462/* Update all QOS parameters in hardware. */ 3463static void b43_qos_upload_all(struct b43_wldev *dev) 3464{ 3465 struct b43_wl *wl = dev->wl; 3466 struct b43_qos_params *params; 3467 unsigned int i; 3468 3469 if (!dev->qos_enabled) 3470 return; 3471 3472 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3473 ARRAY_SIZE(wl->qos_params)); 3474 3475 b43_mac_suspend(dev); 3476 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3477 params = &(wl->qos_params[i]); 3478 b43_qos_params_upload(dev, &(params->p), 3479 b43_qos_shm_offsets[i]); 3480 } 3481 b43_mac_enable(dev); 3482} 3483 3484static void b43_qos_clear(struct b43_wl *wl) 3485{ 3486 struct b43_qos_params *params; 3487 unsigned int i; 3488 3489 /* Initialize QoS parameters to sane defaults. */ 3490 3491 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3492 ARRAY_SIZE(wl->qos_params)); 3493 3494 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3495 params = &(wl->qos_params[i]); 3496 3497 switch (b43_qos_shm_offsets[i]) { 3498 case B43_QOS_VOICE: 3499 params->p.txop = 0; 3500 params->p.aifs = 2; 3501 params->p.cw_min = 0x0001; 3502 params->p.cw_max = 0x0001; 3503 break; 3504 case B43_QOS_VIDEO: 3505 params->p.txop = 0; 3506 params->p.aifs = 2; 3507 params->p.cw_min = 0x0001; 3508 params->p.cw_max = 0x0001; 3509 break; 3510 case B43_QOS_BESTEFFORT: 3511 params->p.txop = 0; 3512 params->p.aifs = 3; 3513 params->p.cw_min = 0x0001; 3514 params->p.cw_max = 0x03FF; 3515 break; 3516 case B43_QOS_BACKGROUND: 3517 params->p.txop = 0; 3518 params->p.aifs = 7; 3519 params->p.cw_min = 0x0001; 3520 params->p.cw_max = 0x03FF; 3521 break; 3522 default: 3523 B43_WARN_ON(1); 3524 } 3525 } 3526} 3527 3528/* Initialize the core's QOS capabilities */ 3529static void b43_qos_init(struct b43_wldev *dev) 3530{ 3531 if (!dev->qos_enabled) { 3532 /* Disable QOS support. */ 3533 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF); 3534 b43_write16(dev, B43_MMIO_IFSCTL, 3535 b43_read16(dev, B43_MMIO_IFSCTL) 3536 & ~B43_MMIO_IFSCTL_USE_EDCF); 3537 b43dbg(dev->wl, "QoS disabled\n"); 3538 return; 3539 } 3540 3541 /* Upload the current QOS parameters. */ 3542 b43_qos_upload_all(dev); 3543 3544 /* Enable QOS support. */ 3545 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); 3546 b43_write16(dev, B43_MMIO_IFSCTL, 3547 b43_read16(dev, B43_MMIO_IFSCTL) 3548 | B43_MMIO_IFSCTL_USE_EDCF); 3549 b43dbg(dev->wl, "QoS enabled\n"); 3550} 3551 3552static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue, 3553 const struct ieee80211_tx_queue_params *params) 3554{ 3555 struct b43_wl *wl = hw_to_b43_wl(hw); 3556 struct b43_wldev *dev; 3557 unsigned int queue = (unsigned int)_queue; 3558 int err = -ENODEV; 3559 3560 if (queue >= ARRAY_SIZE(wl->qos_params)) { 3561 /* Queue not available or don't support setting 3562 * params on this queue. Return success to not 3563 * confuse mac80211. */ 3564 return 0; 3565 } 3566 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3567 ARRAY_SIZE(wl->qos_params)); 3568 3569 mutex_lock(&wl->mutex); 3570 dev = wl->current_dev; 3571 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) 3572 goto out_unlock; 3573 3574 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params)); 3575 b43_mac_suspend(dev); 3576 b43_qos_params_upload(dev, &(wl->qos_params[queue].p), 3577 b43_qos_shm_offsets[queue]); 3578 b43_mac_enable(dev); 3579 err = 0; 3580 3581out_unlock: 3582 mutex_unlock(&wl->mutex); 3583 3584 return err; 3585} 3586 3587static int b43_op_get_stats(struct ieee80211_hw *hw, 3588 struct ieee80211_low_level_stats *stats) 3589{ 3590 struct b43_wl *wl = hw_to_b43_wl(hw); 3591 3592 mutex_lock(&wl->mutex); 3593 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 3594 mutex_unlock(&wl->mutex); 3595 3596 return 0; 3597} 3598 3599static u64 b43_op_get_tsf(struct ieee80211_hw *hw) 3600{ 3601 struct b43_wl *wl = hw_to_b43_wl(hw); 3602 struct b43_wldev *dev; 3603 u64 tsf; 3604 3605 mutex_lock(&wl->mutex); 3606 dev = wl->current_dev; 3607 3608 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3609 b43_tsf_read(dev, &tsf); 3610 else 3611 tsf = 0; 3612 3613 mutex_unlock(&wl->mutex); 3614 3615 return tsf; 3616} 3617 3618static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3619{ 3620 struct b43_wl *wl = hw_to_b43_wl(hw); 3621 struct b43_wldev *dev; 3622 3623 mutex_lock(&wl->mutex); 3624 dev = wl->current_dev; 3625 3626 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3627 b43_tsf_write(dev, tsf); 3628 3629 mutex_unlock(&wl->mutex); 3630} 3631 3632static void b43_put_phy_into_reset(struct b43_wldev *dev) 3633{ 3634 u32 tmp; 3635 3636 switch (dev->dev->bus_type) { 3637#ifdef CONFIG_B43_BCMA 3638 case B43_BUS_BCMA: 3639 b43err(dev->wl, 3640 "Putting PHY into reset not supported on BCMA\n"); 3641 break; 3642#endif 3643#ifdef CONFIG_B43_SSB 3644 case B43_BUS_SSB: 3645 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 3646 tmp &= ~B43_TMSLOW_GMODE; 3647 tmp |= B43_TMSLOW_PHYRESET; 3648 tmp |= SSB_TMSLOW_FGC; 3649 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 3650 msleep(1); 3651 3652 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 3653 tmp &= ~SSB_TMSLOW_FGC; 3654 tmp |= B43_TMSLOW_PHYRESET; 3655 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 3656 msleep(1); 3657 3658 break; 3659#endif 3660 } 3661} 3662 3663static const char *band_to_string(enum ieee80211_band band) 3664{ 3665 switch (band) { 3666 case IEEE80211_BAND_5GHZ: 3667 return "5"; 3668 case IEEE80211_BAND_2GHZ: 3669 return "2.4"; 3670 default: 3671 break; 3672 } 3673 B43_WARN_ON(1); 3674 return ""; 3675} 3676 3677/* Expects wl->mutex locked */ 3678static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan) 3679{ 3680 struct b43_wldev *up_dev = NULL; 3681 struct b43_wldev *down_dev; 3682 struct b43_wldev *d; 3683 int err; 3684 bool uninitialized_var(gmode); 3685 int prev_status; 3686 3687 /* Find a device and PHY which supports the band. */ 3688 list_for_each_entry(d, &wl->devlist, list) { 3689 switch (chan->band) { 3690 case IEEE80211_BAND_5GHZ: 3691 if (d->phy.supports_5ghz) { 3692 up_dev = d; 3693 gmode = 0; 3694 } 3695 break; 3696 case IEEE80211_BAND_2GHZ: 3697 if (d->phy.supports_2ghz) { 3698 up_dev = d; 3699 gmode = 1; 3700 } 3701 break; 3702 default: 3703 B43_WARN_ON(1); 3704 return -EINVAL; 3705 } 3706 if (up_dev) 3707 break; 3708 } 3709 if (!up_dev) { 3710 b43err(wl, "Could not find a device for %s-GHz band operation\n", 3711 band_to_string(chan->band)); 3712 return -ENODEV; 3713 } 3714 if ((up_dev == wl->current_dev) && 3715 (!!wl->current_dev->phy.gmode == !!gmode)) { 3716 /* This device is already running. */ 3717 return 0; 3718 } 3719 b43dbg(wl, "Switching to %s-GHz band\n", 3720 band_to_string(chan->band)); 3721 down_dev = wl->current_dev; 3722 3723 prev_status = b43_status(down_dev); 3724 /* Shutdown the currently running core. */ 3725 if (prev_status >= B43_STAT_STARTED) 3726 down_dev = b43_wireless_core_stop(down_dev); 3727 if (prev_status >= B43_STAT_INITIALIZED) 3728 b43_wireless_core_exit(down_dev); 3729 3730 if (down_dev != up_dev) { 3731 /* We switch to a different core, so we put PHY into 3732 * RESET on the old core. */ 3733 b43_put_phy_into_reset(down_dev); 3734 } 3735 3736 /* Now start the new core. */ 3737 up_dev->phy.gmode = gmode; 3738 if (prev_status >= B43_STAT_INITIALIZED) { 3739 err = b43_wireless_core_init(up_dev); 3740 if (err) { 3741 b43err(wl, "Fatal: Could not initialize device for " 3742 "selected %s-GHz band\n", 3743 band_to_string(chan->band)); 3744 goto init_failure; 3745 } 3746 } 3747 if (prev_status >= B43_STAT_STARTED) { 3748 err = b43_wireless_core_start(up_dev); 3749 if (err) { 3750 b43err(wl, "Fatal: Coult not start device for " 3751 "selected %s-GHz band\n", 3752 band_to_string(chan->band)); 3753 b43_wireless_core_exit(up_dev); 3754 goto init_failure; 3755 } 3756 } 3757 B43_WARN_ON(b43_status(up_dev) != prev_status); 3758 3759 wl->current_dev = up_dev; 3760 3761 return 0; 3762init_failure: 3763 /* Whoops, failed to init the new core. No core is operating now. */ 3764 wl->current_dev = NULL; 3765 return err; 3766} 3767 3768/* Write the short and long frame retry limit values. */ 3769static void b43_set_retry_limits(struct b43_wldev *dev, 3770 unsigned int short_retry, 3771 unsigned int long_retry) 3772{ 3773 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3774 * the chip-internal counter. */ 3775 short_retry = min(short_retry, (unsigned int)0xF); 3776 long_retry = min(long_retry, (unsigned int)0xF); 3777 3778 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3779 short_retry); 3780 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3781 long_retry); 3782} 3783 3784static int b43_op_config(struct ieee80211_hw *hw, u32 changed) 3785{ 3786 struct b43_wl *wl = hw_to_b43_wl(hw); 3787 struct b43_wldev *dev; 3788 struct b43_phy *phy; 3789 struct ieee80211_conf *conf = &hw->conf; 3790 int antenna; 3791 int err = 0; 3792 bool reload_bss = false; 3793 3794 mutex_lock(&wl->mutex); 3795 3796 dev = wl->current_dev; 3797 3798 /* Switch the band (if necessary). This might change the active core. */ 3799 err = b43_switch_band(wl, conf->channel); 3800 if (err) 3801 goto out_unlock_mutex; 3802 3803 /* Need to reload all settings if the core changed */ 3804 if (dev != wl->current_dev) { 3805 dev = wl->current_dev; 3806 changed = ~0; 3807 reload_bss = true; 3808 } 3809 3810 phy = &dev->phy; 3811 3812 if (conf_is_ht(conf)) 3813 phy->is_40mhz = 3814 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf)); 3815 else 3816 phy->is_40mhz = false; 3817 3818 b43_mac_suspend(dev); 3819 3820 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 3821 b43_set_retry_limits(dev, conf->short_frame_max_tx_count, 3822 conf->long_frame_max_tx_count); 3823 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; 3824 if (!changed) 3825 goto out_mac_enable; 3826 3827 /* Switch to the requested channel. 3828 * The firmware takes care of races with the TX handler. */ 3829 if (conf->channel->hw_value != phy->channel) 3830 b43_switch_channel(dev, conf->channel->hw_value); 3831 3832 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 3833 3834 /* Adjust the desired TX power level. */ 3835 if (conf->power_level != 0) { 3836 if (conf->power_level != phy->desired_txpower) { 3837 phy->desired_txpower = conf->power_level; 3838 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME | 3839 B43_TXPWR_IGNORE_TSSI); 3840 } 3841 } 3842 3843 /* Antennas for RX and management frame TX. */ 3844 antenna = B43_ANTENNA_DEFAULT; 3845 b43_mgmtframe_txantenna(dev, antenna); 3846 antenna = B43_ANTENNA_DEFAULT; 3847 if (phy->ops->set_rx_antenna) 3848 phy->ops->set_rx_antenna(dev, antenna); 3849 3850 if (wl->radio_enabled != phy->radio_on) { 3851 if (wl->radio_enabled) { 3852 b43_software_rfkill(dev, false); 3853 b43info(dev->wl, "Radio turned on by software\n"); 3854 if (!dev->radio_hw_enable) { 3855 b43info(dev->wl, "The hardware RF-kill button " 3856 "still turns the radio physically off. " 3857 "Press the button to turn it on.\n"); 3858 } 3859 } else { 3860 b43_software_rfkill(dev, true); 3861 b43info(dev->wl, "Radio turned off by software\n"); 3862 } 3863 } 3864 3865out_mac_enable: 3866 b43_mac_enable(dev); 3867out_unlock_mutex: 3868 mutex_unlock(&wl->mutex); 3869 3870 if (wl->vif && reload_bss) 3871 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0); 3872 3873 return err; 3874} 3875 3876static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates) 3877{ 3878 struct ieee80211_supported_band *sband = 3879 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)]; 3880 struct ieee80211_rate *rate; 3881 int i; 3882 u16 basic, direct, offset, basic_offset, rateptr; 3883 3884 for (i = 0; i < sband->n_bitrates; i++) { 3885 rate = &sband->bitrates[i]; 3886 3887 if (b43_is_cck_rate(rate->hw_value)) { 3888 direct = B43_SHM_SH_CCKDIRECT; 3889 basic = B43_SHM_SH_CCKBASIC; 3890 offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3891 offset &= 0xF; 3892 } else { 3893 direct = B43_SHM_SH_OFDMDIRECT; 3894 basic = B43_SHM_SH_OFDMBASIC; 3895 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3896 offset &= 0xF; 3897 } 3898 3899 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); 3900 3901 if (b43_is_cck_rate(rate->hw_value)) { 3902 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3903 basic_offset &= 0xF; 3904 } else { 3905 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3906 basic_offset &= 0xF; 3907 } 3908 3909 /* 3910 * Get the pointer that we need to point to 3911 * from the direct map 3912 */ 3913 rateptr = b43_shm_read16(dev, B43_SHM_SHARED, 3914 direct + 2 * basic_offset); 3915 /* and write it to the basic map */ 3916 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset, 3917 rateptr); 3918 } 3919} 3920 3921static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 3922 struct ieee80211_vif *vif, 3923 struct ieee80211_bss_conf *conf, 3924 u32 changed) 3925{ 3926 struct b43_wl *wl = hw_to_b43_wl(hw); 3927 struct b43_wldev *dev; 3928 3929 mutex_lock(&wl->mutex); 3930 3931 dev = wl->current_dev; 3932 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3933 goto out_unlock_mutex; 3934 3935 B43_WARN_ON(wl->vif != vif); 3936 3937 if (changed & BSS_CHANGED_BSSID) { 3938 if (conf->bssid) 3939 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3940 else 3941 memset(wl->bssid, 0, ETH_ALEN); 3942 } 3943 3944 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3945 if (changed & BSS_CHANGED_BEACON && 3946 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3947 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3948 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3949 b43_update_templates(wl); 3950 3951 if (changed & BSS_CHANGED_BSSID) 3952 b43_write_mac_bssid_templates(dev); 3953 } 3954 3955 b43_mac_suspend(dev); 3956 3957 /* Update templates for AP/mesh mode. */ 3958 if (changed & BSS_CHANGED_BEACON_INT && 3959 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3960 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3961 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) && 3962 conf->beacon_int) 3963 b43_set_beacon_int(dev, conf->beacon_int); 3964 3965 if (changed & BSS_CHANGED_BASIC_RATES) 3966 b43_update_basic_rates(dev, conf->basic_rates); 3967 3968 if (changed & BSS_CHANGED_ERP_SLOT) { 3969 if (conf->use_short_slot) 3970 b43_short_slot_timing_enable(dev); 3971 else 3972 b43_short_slot_timing_disable(dev); 3973 } 3974 3975 b43_mac_enable(dev); 3976out_unlock_mutex: 3977 mutex_unlock(&wl->mutex); 3978} 3979 3980static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3981 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3982 struct ieee80211_key_conf *key) 3983{ 3984 struct b43_wl *wl = hw_to_b43_wl(hw); 3985 struct b43_wldev *dev; 3986 u8 algorithm; 3987 u8 index; 3988 int err; 3989 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3990 3991 if (modparam_nohwcrypt) 3992 return -ENOSPC; /* User disabled HW-crypto */ 3993 3994 mutex_lock(&wl->mutex); 3995 3996 dev = wl->current_dev; 3997 err = -ENODEV; 3998 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 3999 goto out_unlock; 4000 4001 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) { 4002 /* We don't have firmware for the crypto engine. 4003 * Must use software-crypto. */ 4004 err = -EOPNOTSUPP; 4005 goto out_unlock; 4006 } 4007 4008 err = -EINVAL; 4009 switch (key->cipher) { 4010 case WLAN_CIPHER_SUITE_WEP40: 4011 algorithm = B43_SEC_ALGO_WEP40; 4012 break; 4013 case WLAN_CIPHER_SUITE_WEP104: 4014 algorithm = B43_SEC_ALGO_WEP104; 4015 break; 4016 case WLAN_CIPHER_SUITE_TKIP: 4017 algorithm = B43_SEC_ALGO_TKIP; 4018 break; 4019 case WLAN_CIPHER_SUITE_CCMP: 4020 algorithm = B43_SEC_ALGO_AES; 4021 break; 4022 default: 4023 B43_WARN_ON(1); 4024 goto out_unlock; 4025 } 4026 index = (u8) (key->keyidx); 4027 if (index > 3) 4028 goto out_unlock; 4029 4030 switch (cmd) { 4031 case SET_KEY: 4032 if (algorithm == B43_SEC_ALGO_TKIP && 4033 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) || 4034 !modparam_hwtkip)) { 4035 /* We support only pairwise key */ 4036 err = -EOPNOTSUPP; 4037 goto out_unlock; 4038 } 4039 4040 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 4041 if (WARN_ON(!sta)) { 4042 err = -EOPNOTSUPP; 4043 goto out_unlock; 4044 } 4045 /* Pairwise key with an assigned MAC address. */ 4046 err = b43_key_write(dev, -1, algorithm, 4047 key->key, key->keylen, 4048 sta->addr, key); 4049 } else { 4050 /* Group key */ 4051 err = b43_key_write(dev, index, algorithm, 4052 key->key, key->keylen, NULL, key); 4053 } 4054 if (err) 4055 goto out_unlock; 4056 4057 if (algorithm == B43_SEC_ALGO_WEP40 || 4058 algorithm == B43_SEC_ALGO_WEP104) { 4059 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 4060 } else { 4061 b43_hf_write(dev, 4062 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 4063 } 4064 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 4065 if (algorithm == B43_SEC_ALGO_TKIP) 4066 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 4067 break; 4068 case DISABLE_KEY: { 4069 err = b43_key_clear(dev, key->hw_key_idx); 4070 if (err) 4071 goto out_unlock; 4072 break; 4073 } 4074 default: 4075 B43_WARN_ON(1); 4076 } 4077 4078out_unlock: 4079 if (!err) { 4080 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 4081 "mac: %pM\n", 4082 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 4083 sta ? sta->addr : bcast_addr); 4084 b43_dump_keymemory(dev); 4085 } 4086 mutex_unlock(&wl->mutex); 4087 4088 return err; 4089} 4090 4091static void b43_op_configure_filter(struct ieee80211_hw *hw, 4092 unsigned int changed, unsigned int *fflags, 4093 u64 multicast) 4094{ 4095 struct b43_wl *wl = hw_to_b43_wl(hw); 4096 struct b43_wldev *dev; 4097 4098 mutex_lock(&wl->mutex); 4099 dev = wl->current_dev; 4100 if (!dev) { 4101 *fflags = 0; 4102 goto out_unlock; 4103 } 4104 4105 *fflags &= FIF_PROMISC_IN_BSS | 4106 FIF_ALLMULTI | 4107 FIF_FCSFAIL | 4108 FIF_PLCPFAIL | 4109 FIF_CONTROL | 4110 FIF_OTHER_BSS | 4111 FIF_BCN_PRBRESP_PROMISC; 4112 4113 changed &= FIF_PROMISC_IN_BSS | 4114 FIF_ALLMULTI | 4115 FIF_FCSFAIL | 4116 FIF_PLCPFAIL | 4117 FIF_CONTROL | 4118 FIF_OTHER_BSS | 4119 FIF_BCN_PRBRESP_PROMISC; 4120 4121 wl->filter_flags = *fflags; 4122 4123 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 4124 b43_adjust_opmode(dev); 4125 4126out_unlock: 4127 mutex_unlock(&wl->mutex); 4128} 4129 4130/* Locking: wl->mutex 4131 * Returns the current dev. This might be different from the passed in dev, 4132 * because the core might be gone away while we unlocked the mutex. */ 4133static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev) 4134{ 4135 struct b43_wl *wl = dev->wl; 4136 struct b43_wldev *orig_dev; 4137 u32 mask; 4138 4139redo: 4140 if (!dev || b43_status(dev) < B43_STAT_STARTED) 4141 return dev; 4142 4143 /* Cancel work. Unlock to avoid deadlocks. */ 4144 mutex_unlock(&wl->mutex); 4145 cancel_delayed_work_sync(&dev->periodic_work); 4146 cancel_work_sync(&wl->tx_work); 4147 mutex_lock(&wl->mutex); 4148 dev = wl->current_dev; 4149 if (!dev || b43_status(dev) < B43_STAT_STARTED) { 4150 /* Whoops, aliens ate up the device while we were unlocked. */ 4151 return dev; 4152 } 4153 4154 /* Disable interrupts on the device. */ 4155 b43_set_status(dev, B43_STAT_INITIALIZED); 4156 if (b43_bus_host_is_sdio(dev->dev)) { 4157 /* wl->mutex is locked. That is enough. */ 4158 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4159 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4160 } else { 4161 spin_lock_irq(&wl->hardirq_lock); 4162 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4163 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4164 spin_unlock_irq(&wl->hardirq_lock); 4165 } 4166 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ 4167 orig_dev = dev; 4168 mutex_unlock(&wl->mutex); 4169 if (b43_bus_host_is_sdio(dev->dev)) { 4170 b43_sdio_free_irq(dev); 4171 } else { 4172 synchronize_irq(dev->dev->irq); 4173 free_irq(dev->dev->irq, dev); 4174 } 4175 mutex_lock(&wl->mutex); 4176 dev = wl->current_dev; 4177 if (!dev) 4178 return dev; 4179 if (dev != orig_dev) { 4180 if (b43_status(dev) >= B43_STAT_STARTED) 4181 goto redo; 4182 return dev; 4183 } 4184 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 4185 B43_WARN_ON(mask != 0xFFFFFFFF && mask); 4186 4187 /* Drain the TX queue */ 4188 while (skb_queue_len(&wl->tx_queue)) 4189 dev_kfree_skb(skb_dequeue(&wl->tx_queue)); 4190 4191 b43_mac_suspend(dev); 4192 b43_leds_exit(dev); 4193 b43dbg(wl, "Wireless interface stopped\n"); 4194 4195 return dev; 4196} 4197 4198/* Locking: wl->mutex */ 4199static int b43_wireless_core_start(struct b43_wldev *dev) 4200{ 4201 int err; 4202 4203 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 4204 4205 drain_txstatus_queue(dev); 4206 if (b43_bus_host_is_sdio(dev->dev)) { 4207 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); 4208 if (err) { 4209 b43err(dev->wl, "Cannot request SDIO IRQ\n"); 4210 goto out; 4211 } 4212 } else { 4213 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler, 4214 b43_interrupt_thread_handler, 4215 IRQF_SHARED, KBUILD_MODNAME, dev); 4216 if (err) { 4217 b43err(dev->wl, "Cannot request IRQ-%d\n", 4218 dev->dev->irq); 4219 goto out; 4220 } 4221 } 4222 4223 /* We are ready to run. */ 4224 ieee80211_wake_queues(dev->wl->hw); 4225 b43_set_status(dev, B43_STAT_STARTED); 4226 4227 /* Start data flow (TX/RX). */ 4228 b43_mac_enable(dev); 4229 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 4230 4231 /* Start maintenance work */ 4232 b43_periodic_tasks_setup(dev); 4233 4234 b43_leds_init(dev); 4235 4236 b43dbg(dev->wl, "Wireless interface started\n"); 4237out: 4238 return err; 4239} 4240 4241/* Get PHY and RADIO versioning numbers */ 4242static int b43_phy_versioning(struct b43_wldev *dev) 4243{ 4244 struct b43_phy *phy = &dev->phy; 4245 u32 tmp; 4246 u8 analog_type; 4247 u8 phy_type; 4248 u8 phy_rev; 4249 u16 radio_manuf; 4250 u16 radio_ver; 4251 u16 radio_rev; 4252 int unsupported = 0; 4253 4254 /* Get PHY versioning */ 4255 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 4256 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 4257 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 4258 phy_rev = (tmp & B43_PHYVER_VERSION); 4259 switch (phy_type) { 4260 case B43_PHYTYPE_A: 4261 if (phy_rev >= 4) 4262 unsupported = 1; 4263 break; 4264 case B43_PHYTYPE_B: 4265 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 4266 && phy_rev != 7) 4267 unsupported = 1; 4268 break; 4269 case B43_PHYTYPE_G: 4270 if (phy_rev > 9) 4271 unsupported = 1; 4272 break; 4273#ifdef CONFIG_B43_PHY_N 4274 case B43_PHYTYPE_N: 4275 if (phy_rev > 9) 4276 unsupported = 1; 4277 break; 4278#endif 4279#ifdef CONFIG_B43_PHY_LP 4280 case B43_PHYTYPE_LP: 4281 if (phy_rev > 2) 4282 unsupported = 1; 4283 break; 4284#endif 4285#ifdef CONFIG_B43_PHY_HT 4286 case B43_PHYTYPE_HT: 4287 if (phy_rev > 1) 4288 unsupported = 1; 4289 break; 4290#endif 4291#ifdef CONFIG_B43_PHY_LCN 4292 case B43_PHYTYPE_LCN: 4293 if (phy_rev > 1) 4294 unsupported = 1; 4295 break; 4296#endif 4297 default: 4298 unsupported = 1; 4299 } 4300 if (unsupported) { 4301 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 4302 "(Analog %u, Type %u, Revision %u)\n", 4303 analog_type, phy_type, phy_rev); 4304 return -EOPNOTSUPP; 4305 } 4306 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 4307 analog_type, phy_type, phy_rev); 4308 4309 /* Get RADIO versioning */ 4310 if (dev->dev->core_rev >= 24) { 4311 u16 radio24[3]; 4312 4313 for (tmp = 0; tmp < 3; tmp++) { 4314 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp); 4315 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4316 } 4317 4318 /* Broadcom uses "id" for our "ver" and has separated "ver" */ 4319 /* radio_ver = (radio24[0] & 0xF0) >> 4; */ 4320 4321 radio_manuf = 0x17F; 4322 radio_ver = (radio24[2] << 8) | radio24[1]; 4323 radio_rev = (radio24[0] & 0xF); 4324 } else { 4325 if (dev->dev->chip_id == 0x4317) { 4326 if (dev->dev->chip_rev == 0) 4327 tmp = 0x3205017F; 4328 else if (dev->dev->chip_rev == 1) 4329 tmp = 0x4205017F; 4330 else 4331 tmp = 0x5205017F; 4332 } else { 4333 b43_write16(dev, B43_MMIO_RADIO_CONTROL, 4334 B43_RADIOCTL_ID); 4335 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 4336 b43_write16(dev, B43_MMIO_RADIO_CONTROL, 4337 B43_RADIOCTL_ID); 4338 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) 4339 << 16; 4340 } 4341 radio_manuf = (tmp & 0x00000FFF); 4342 radio_ver = (tmp & 0x0FFFF000) >> 12; 4343 radio_rev = (tmp & 0xF0000000) >> 28; 4344 } 4345 4346 if (radio_manuf != 0x17F /* Broadcom */) 4347 unsupported = 1; 4348 switch (phy_type) { 4349 case B43_PHYTYPE_A: 4350 if (radio_ver != 0x2060) 4351 unsupported = 1; 4352 if (radio_rev != 1) 4353 unsupported = 1; 4354 if (radio_manuf != 0x17F) 4355 unsupported = 1; 4356 break; 4357 case B43_PHYTYPE_B: 4358 if ((radio_ver & 0xFFF0) != 0x2050) 4359 unsupported = 1; 4360 break; 4361 case B43_PHYTYPE_G: 4362 if (radio_ver != 0x2050) 4363 unsupported = 1; 4364 break; 4365 case B43_PHYTYPE_N: 4366 if (radio_ver != 0x2055 && radio_ver != 0x2056) 4367 unsupported = 1; 4368 break; 4369 case B43_PHYTYPE_LP: 4370 if (radio_ver != 0x2062 && radio_ver != 0x2063) 4371 unsupported = 1; 4372 break; 4373 case B43_PHYTYPE_HT: 4374 if (radio_ver != 0x2059) 4375 unsupported = 1; 4376 break; 4377 case B43_PHYTYPE_LCN: 4378 if (radio_ver != 0x2064) 4379 unsupported = 1; 4380 break; 4381 default: 4382 B43_WARN_ON(1); 4383 } 4384 if (unsupported) { 4385 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 4386 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 4387 radio_manuf, radio_ver, radio_rev); 4388 return -EOPNOTSUPP; 4389 } 4390 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 4391 radio_manuf, radio_ver, radio_rev); 4392 4393 phy->radio_manuf = radio_manuf; 4394 phy->radio_ver = radio_ver; 4395 phy->radio_rev = radio_rev; 4396 4397 phy->analog = analog_type; 4398 phy->type = phy_type; 4399 phy->rev = phy_rev; 4400 4401 return 0; 4402} 4403 4404static void setup_struct_phy_for_init(struct b43_wldev *dev, 4405 struct b43_phy *phy) 4406{ 4407 phy->hardware_power_control = !!modparam_hwpctl; 4408 phy->next_txpwr_check_time = jiffies; 4409 /* PHY TX errors counter. */ 4410 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 4411 4412#if B43_DEBUG 4413 phy->phy_locked = 0; 4414 phy->radio_locked = 0; 4415#endif 4416} 4417 4418static void setup_struct_wldev_for_init(struct b43_wldev *dev) 4419{ 4420 dev->dfq_valid = 0; 4421 4422 /* Assume the radio is enabled. If it's not enabled, the state will 4423 * immediately get fixed on the first periodic work run. */ 4424 dev->radio_hw_enable = 1; 4425 4426 /* Stats */ 4427 memset(&dev->stats, 0, sizeof(dev->stats)); 4428 4429 setup_struct_phy_for_init(dev, &dev->phy); 4430 4431 /* IRQ related flags */ 4432 dev->irq_reason = 0; 4433 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 4434 dev->irq_mask = B43_IRQ_MASKTEMPLATE; 4435 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 4436 dev->irq_mask &= ~B43_IRQ_PHY_TXERR; 4437 4438 dev->mac_suspended = 1; 4439 4440 /* Noise calculation context */ 4441 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 4442} 4443 4444static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 4445{ 4446 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4447 u64 hf; 4448 4449 if (!modparam_btcoex) 4450 return; 4451 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 4452 return; 4453 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 4454 return; 4455 4456 hf = b43_hf_read(dev); 4457 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 4458 hf |= B43_HF_BTCOEXALT; 4459 else 4460 hf |= B43_HF_BTCOEX; 4461 b43_hf_write(dev, hf); 4462} 4463 4464static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 4465{ 4466 if (!modparam_btcoex) 4467 return; 4468 //TODO 4469} 4470 4471static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 4472{ 4473 struct ssb_bus *bus; 4474 u32 tmp; 4475 4476 if (dev->dev->bus_type != B43_BUS_SSB) 4477 return; 4478 4479 bus = dev->dev->sdev->bus; 4480 4481 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || 4482 (bus->chip_id == 0x4312)) { 4483 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO); 4484 tmp &= ~SSB_IMCFGLO_REQTO; 4485 tmp &= ~SSB_IMCFGLO_SERTO; 4486 tmp |= 0x3; 4487 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp); 4488 ssb_commit_settings(bus); 4489 } 4490} 4491 4492static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) 4493{ 4494 u16 pu_delay; 4495 4496 /* The time value is in microseconds. */ 4497 if (dev->phy.type == B43_PHYTYPE_A) 4498 pu_delay = 3700; 4499 else 4500 pu_delay = 1050; 4501 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) 4502 pu_delay = 500; 4503 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) 4504 pu_delay = max(pu_delay, (u16)2400); 4505 4506 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); 4507} 4508 4509/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ 4510static void b43_set_pretbtt(struct b43_wldev *dev) 4511{ 4512 u16 pretbtt; 4513 4514 /* The time value is in microseconds. */ 4515 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) { 4516 pretbtt = 2; 4517 } else { 4518 if (dev->phy.type == B43_PHYTYPE_A) 4519 pretbtt = 120; 4520 else 4521 pretbtt = 250; 4522 } 4523 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); 4524 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); 4525} 4526 4527/* Shutdown a wireless core */ 4528/* Locking: wl->mutex */ 4529static void b43_wireless_core_exit(struct b43_wldev *dev) 4530{ 4531 u32 macctl; 4532 4533 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED); 4534 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED) 4535 return; 4536 4537 /* Unregister HW RNG driver */ 4538 b43_rng_exit(dev->wl); 4539 4540 b43_set_status(dev, B43_STAT_UNINIT); 4541 4542 /* Stop the microcode PSM. */ 4543 macctl = b43_read32(dev, B43_MMIO_MACCTL); 4544 macctl &= ~B43_MACCTL_PSM_RUN; 4545 macctl |= B43_MACCTL_PSM_JMP0; 4546 b43_write32(dev, B43_MMIO_MACCTL, macctl); 4547 4548 b43_dma_free(dev); 4549 b43_pio_free(dev); 4550 b43_chip_exit(dev); 4551 dev->phy.ops->switch_analog(dev, 0); 4552 if (dev->wl->current_beacon) { 4553 dev_kfree_skb_any(dev->wl->current_beacon); 4554 dev->wl->current_beacon = NULL; 4555 } 4556 4557 b43_device_disable(dev, 0); 4558 b43_bus_may_powerdown(dev); 4559} 4560 4561/* Initialize a wireless core */ 4562static int b43_wireless_core_init(struct b43_wldev *dev) 4563{ 4564 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4565 struct b43_phy *phy = &dev->phy; 4566 int err; 4567 u64 hf; 4568 4569 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4570 4571 err = b43_bus_powerup(dev, 0); 4572 if (err) 4573 goto out; 4574 if (!b43_device_is_enabled(dev)) 4575 b43_wireless_core_reset(dev, phy->gmode); 4576 4577 /* Reset all data structures. */ 4578 setup_struct_wldev_for_init(dev); 4579 phy->ops->prepare_structs(dev); 4580 4581 /* Enable IRQ routing to this device. */ 4582 switch (dev->dev->bus_type) { 4583#ifdef CONFIG_B43_BCMA 4584 case B43_BUS_BCMA: 4585 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci, 4586 dev->dev->bdev, true); 4587 break; 4588#endif 4589#ifdef CONFIG_B43_SSB 4590 case B43_BUS_SSB: 4591 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore, 4592 dev->dev->sdev); 4593 break; 4594#endif 4595 } 4596 4597 b43_imcfglo_timeouts_workaround(dev); 4598 b43_bluetooth_coext_disable(dev); 4599 if (phy->ops->prepare_hardware) { 4600 err = phy->ops->prepare_hardware(dev); 4601 if (err) 4602 goto err_busdown; 4603 } 4604 err = b43_chip_init(dev); 4605 if (err) 4606 goto err_busdown; 4607 b43_shm_write16(dev, B43_SHM_SHARED, 4608 B43_SHM_SH_WLCOREREV, dev->dev->core_rev); 4609 hf = b43_hf_read(dev); 4610 if (phy->type == B43_PHYTYPE_G) { 4611 hf |= B43_HF_SYMW; 4612 if (phy->rev == 1) 4613 hf |= B43_HF_GDCW; 4614 if (sprom->boardflags_lo & B43_BFL_PACTRL) 4615 hf |= B43_HF_OFDMPABOOST; 4616 } 4617 if (phy->radio_ver == 0x2050) { 4618 if (phy->radio_rev == 6) 4619 hf |= B43_HF_4318TSSI; 4620 if (phy->radio_rev < 6) 4621 hf |= B43_HF_VCORECALC; 4622 } 4623 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) 4624 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ 4625#ifdef CONFIG_SSB_DRIVER_PCICORE 4626 if (dev->dev->bus_type == B43_BUS_SSB && 4627 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI && 4628 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10) 4629 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ 4630#endif 4631 hf &= ~B43_HF_SKCFPUP; 4632 b43_hf_write(dev, hf); 4633 4634 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 4635 B43_DEFAULT_LONG_RETRY_LIMIT); 4636 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 4637 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 4638 4639 /* Disable sending probe responses from firmware. 4640 * Setting the MaxTime to one usec will always trigger 4641 * a timeout, so we never send any probe resp. 4642 * A timeout of zero is infinite. */ 4643 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 4644 4645 b43_rate_memory_init(dev); 4646 b43_set_phytxctl_defaults(dev); 4647 4648 /* Minimum Contention Window */ 4649 if (phy->type == B43_PHYTYPE_B) 4650 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 4651 else 4652 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 4653 /* Maximum Contention Window */ 4654 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 4655 4656 if (b43_bus_host_is_pcmcia(dev->dev) || 4657 b43_bus_host_is_sdio(dev->dev) || 4658 dev->use_pio) { 4659 dev->__using_pio_transfers = 1; 4660 err = b43_pio_init(dev); 4661 } else { 4662 dev->__using_pio_transfers = 0; 4663 err = b43_dma_init(dev); 4664 } 4665 if (err) 4666 goto err_chip_exit; 4667 b43_qos_init(dev); 4668 b43_set_synth_pu_delay(dev, 1); 4669 b43_bluetooth_coext_enable(dev); 4670 4671 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); 4672 b43_upload_card_macaddress(dev); 4673 b43_security_init(dev); 4674 4675 ieee80211_wake_queues(dev->wl->hw); 4676 4677 b43_set_status(dev, B43_STAT_INITIALIZED); 4678 4679 /* Register HW RNG driver */ 4680 b43_rng_init(dev->wl); 4681 4682out: 4683 return err; 4684 4685err_chip_exit: 4686 b43_chip_exit(dev); 4687err_busdown: 4688 b43_bus_may_powerdown(dev); 4689 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4690 return err; 4691} 4692 4693static int b43_op_add_interface(struct ieee80211_hw *hw, 4694 struct ieee80211_vif *vif) 4695{ 4696 struct b43_wl *wl = hw_to_b43_wl(hw); 4697 struct b43_wldev *dev; 4698 int err = -EOPNOTSUPP; 4699 4700 /* TODO: allow WDS/AP devices to coexist */ 4701 4702 if (vif->type != NL80211_IFTYPE_AP && 4703 vif->type != NL80211_IFTYPE_MESH_POINT && 4704 vif->type != NL80211_IFTYPE_STATION && 4705 vif->type != NL80211_IFTYPE_WDS && 4706 vif->type != NL80211_IFTYPE_ADHOC) 4707 return -EOPNOTSUPP; 4708 4709 mutex_lock(&wl->mutex); 4710 if (wl->operating) 4711 goto out_mutex_unlock; 4712 4713 b43dbg(wl, "Adding Interface type %d\n", vif->type); 4714 4715 dev = wl->current_dev; 4716 wl->operating = 1; 4717 wl->vif = vif; 4718 wl->if_type = vif->type; 4719 memcpy(wl->mac_addr, vif->addr, ETH_ALEN); 4720 4721 b43_adjust_opmode(dev); 4722 b43_set_pretbtt(dev); 4723 b43_set_synth_pu_delay(dev, 0); 4724 b43_upload_card_macaddress(dev); 4725 4726 err = 0; 4727 out_mutex_unlock: 4728 mutex_unlock(&wl->mutex); 4729 4730 if (err == 0) 4731 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0); 4732 4733 return err; 4734} 4735 4736static void b43_op_remove_interface(struct ieee80211_hw *hw, 4737 struct ieee80211_vif *vif) 4738{ 4739 struct b43_wl *wl = hw_to_b43_wl(hw); 4740 struct b43_wldev *dev = wl->current_dev; 4741 4742 b43dbg(wl, "Removing Interface type %d\n", vif->type); 4743 4744 mutex_lock(&wl->mutex); 4745 4746 B43_WARN_ON(!wl->operating); 4747 B43_WARN_ON(wl->vif != vif); 4748 wl->vif = NULL; 4749 4750 wl->operating = 0; 4751 4752 b43_adjust_opmode(dev); 4753 memset(wl->mac_addr, 0, ETH_ALEN); 4754 b43_upload_card_macaddress(dev); 4755 4756 mutex_unlock(&wl->mutex); 4757} 4758 4759static int b43_op_start(struct ieee80211_hw *hw) 4760{ 4761 struct b43_wl *wl = hw_to_b43_wl(hw); 4762 struct b43_wldev *dev = wl->current_dev; 4763 int did_init = 0; 4764 int err = 0; 4765 4766 /* Kill all old instance specific information to make sure 4767 * the card won't use it in the short timeframe between start 4768 * and mac80211 reconfiguring it. */ 4769 memset(wl->bssid, 0, ETH_ALEN); 4770 memset(wl->mac_addr, 0, ETH_ALEN); 4771 wl->filter_flags = 0; 4772 wl->radiotap_enabled = 0; 4773 b43_qos_clear(wl); 4774 wl->beacon0_uploaded = 0; 4775 wl->beacon1_uploaded = 0; 4776 wl->beacon_templates_virgin = 1; 4777 wl->radio_enabled = 1; 4778 4779 mutex_lock(&wl->mutex); 4780 4781 if (b43_status(dev) < B43_STAT_INITIALIZED) { 4782 err = b43_wireless_core_init(dev); 4783 if (err) 4784 goto out_mutex_unlock; 4785 did_init = 1; 4786 } 4787 4788 if (b43_status(dev) < B43_STAT_STARTED) { 4789 err = b43_wireless_core_start(dev); 4790 if (err) { 4791 if (did_init) 4792 b43_wireless_core_exit(dev); 4793 goto out_mutex_unlock; 4794 } 4795 } 4796 4797 /* XXX: only do if device doesn't support rfkill irq */ 4798 wiphy_rfkill_start_polling(hw->wiphy); 4799 4800 out_mutex_unlock: 4801 mutex_unlock(&wl->mutex); 4802 4803 /* reload configuration */ 4804 b43_op_config(hw, ~0); 4805 4806 return err; 4807} 4808 4809static void b43_op_stop(struct ieee80211_hw *hw) 4810{ 4811 struct b43_wl *wl = hw_to_b43_wl(hw); 4812 struct b43_wldev *dev = wl->current_dev; 4813 4814 cancel_work_sync(&(wl->beacon_update_trigger)); 4815 4816 mutex_lock(&wl->mutex); 4817 if (b43_status(dev) >= B43_STAT_STARTED) { 4818 dev = b43_wireless_core_stop(dev); 4819 if (!dev) 4820 goto out_unlock; 4821 } 4822 b43_wireless_core_exit(dev); 4823 wl->radio_enabled = 0; 4824 4825out_unlock: 4826 mutex_unlock(&wl->mutex); 4827 4828 cancel_work_sync(&(wl->txpower_adjust_work)); 4829} 4830 4831static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, 4832 struct ieee80211_sta *sta, bool set) 4833{ 4834 struct b43_wl *wl = hw_to_b43_wl(hw); 4835 4836 /* FIXME: add locking */ 4837 b43_update_templates(wl); 4838 4839 return 0; 4840} 4841 4842static void b43_op_sta_notify(struct ieee80211_hw *hw, 4843 struct ieee80211_vif *vif, 4844 enum sta_notify_cmd notify_cmd, 4845 struct ieee80211_sta *sta) 4846{ 4847 struct b43_wl *wl = hw_to_b43_wl(hw); 4848 4849 B43_WARN_ON(!vif || wl->vif != vif); 4850} 4851 4852static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw) 4853{ 4854 struct b43_wl *wl = hw_to_b43_wl(hw); 4855 struct b43_wldev *dev; 4856 4857 mutex_lock(&wl->mutex); 4858 dev = wl->current_dev; 4859 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4860 /* Disable CFP update during scan on other channels. */ 4861 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP); 4862 } 4863 mutex_unlock(&wl->mutex); 4864} 4865 4866static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw) 4867{ 4868 struct b43_wl *wl = hw_to_b43_wl(hw); 4869 struct b43_wldev *dev; 4870 4871 mutex_lock(&wl->mutex); 4872 dev = wl->current_dev; 4873 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4874 /* Re-enable CFP update. */ 4875 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP); 4876 } 4877 mutex_unlock(&wl->mutex); 4878} 4879 4880static int b43_op_get_survey(struct ieee80211_hw *hw, int idx, 4881 struct survey_info *survey) 4882{ 4883 struct b43_wl *wl = hw_to_b43_wl(hw); 4884 struct b43_wldev *dev = wl->current_dev; 4885 struct ieee80211_conf *conf = &hw->conf; 4886 4887 if (idx != 0) 4888 return -ENOENT; 4889 4890 survey->channel = conf->channel; 4891 survey->filled = SURVEY_INFO_NOISE_DBM; 4892 survey->noise = dev->stats.link_noise; 4893 4894 return 0; 4895} 4896 4897static const struct ieee80211_ops b43_hw_ops = { 4898 .tx = b43_op_tx, 4899 .conf_tx = b43_op_conf_tx, 4900 .add_interface = b43_op_add_interface, 4901 .remove_interface = b43_op_remove_interface, 4902 .config = b43_op_config, 4903 .bss_info_changed = b43_op_bss_info_changed, 4904 .configure_filter = b43_op_configure_filter, 4905 .set_key = b43_op_set_key, 4906 .update_tkip_key = b43_op_update_tkip_key, 4907 .get_stats = b43_op_get_stats, 4908 .get_tsf = b43_op_get_tsf, 4909 .set_tsf = b43_op_set_tsf, 4910 .start = b43_op_start, 4911 .stop = b43_op_stop, 4912 .set_tim = b43_op_beacon_set_tim, 4913 .sta_notify = b43_op_sta_notify, 4914 .sw_scan_start = b43_op_sw_scan_start_notifier, 4915 .sw_scan_complete = b43_op_sw_scan_complete_notifier, 4916 .get_survey = b43_op_get_survey, 4917 .rfkill_poll = b43_rfkill_poll, 4918}; 4919 4920/* Hard-reset the chip. Do not call this directly. 4921 * Use b43_controller_restart() 4922 */ 4923static void b43_chip_reset(struct work_struct *work) 4924{ 4925 struct b43_wldev *dev = 4926 container_of(work, struct b43_wldev, restart_work); 4927 struct b43_wl *wl = dev->wl; 4928 int err = 0; 4929 int prev_status; 4930 4931 mutex_lock(&wl->mutex); 4932 4933 prev_status = b43_status(dev); 4934 /* Bring the device down... */ 4935 if (prev_status >= B43_STAT_STARTED) { 4936 dev = b43_wireless_core_stop(dev); 4937 if (!dev) { 4938 err = -ENODEV; 4939 goto out; 4940 } 4941 } 4942 if (prev_status >= B43_STAT_INITIALIZED) 4943 b43_wireless_core_exit(dev); 4944 4945 /* ...and up again. */ 4946 if (prev_status >= B43_STAT_INITIALIZED) { 4947 err = b43_wireless_core_init(dev); 4948 if (err) 4949 goto out; 4950 } 4951 if (prev_status >= B43_STAT_STARTED) { 4952 err = b43_wireless_core_start(dev); 4953 if (err) { 4954 b43_wireless_core_exit(dev); 4955 goto out; 4956 } 4957 } 4958out: 4959 if (err) 4960 wl->current_dev = NULL; /* Failed to init the dev. */ 4961 mutex_unlock(&wl->mutex); 4962 4963 if (err) { 4964 b43err(wl, "Controller restart FAILED\n"); 4965 return; 4966 } 4967 4968 /* reload configuration */ 4969 b43_op_config(wl->hw, ~0); 4970 if (wl->vif) 4971 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0); 4972 4973 b43info(wl, "Controller restarted\n"); 4974} 4975 4976static int b43_setup_bands(struct b43_wldev *dev, 4977 bool have_2ghz_phy, bool have_5ghz_phy) 4978{ 4979 struct ieee80211_hw *hw = dev->wl->hw; 4980 4981 if (have_2ghz_phy) 4982 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz; 4983 if (dev->phy.type == B43_PHYTYPE_N) { 4984 if (have_5ghz_phy) 4985 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy; 4986 } else { 4987 if (have_5ghz_phy) 4988 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy; 4989 } 4990 4991 dev->phy.supports_2ghz = have_2ghz_phy; 4992 dev->phy.supports_5ghz = have_5ghz_phy; 4993 4994 return 0; 4995} 4996 4997static void b43_wireless_core_detach(struct b43_wldev *dev) 4998{ 4999 /* We release firmware that late to not be required to re-request 5000 * is all the time when we reinit the core. */ 5001 b43_release_firmware(dev); 5002 b43_phy_free(dev); 5003} 5004 5005static int b43_wireless_core_attach(struct b43_wldev *dev) 5006{ 5007 struct b43_wl *wl = dev->wl; 5008 struct pci_dev *pdev = NULL; 5009 int err; 5010 u32 tmp; 5011 bool have_2ghz_phy = 0, have_5ghz_phy = 0; 5012 5013 /* Do NOT do any device initialization here. 5014 * Do it in wireless_core_init() instead. 5015 * This function is for gathering basic information about the HW, only. 5016 * Also some structs may be set up here. But most likely you want to have 5017 * that in core_init(), too. 5018 */ 5019 5020#ifdef CONFIG_B43_SSB 5021 if (dev->dev->bus_type == B43_BUS_SSB && 5022 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) 5023 pdev = dev->dev->sdev->bus->host_pci; 5024#endif 5025 5026 err = b43_bus_powerup(dev, 0); 5027 if (err) { 5028 b43err(wl, "Bus powerup failed\n"); 5029 goto out; 5030 } 5031 5032 /* Get the PHY type. */ 5033 switch (dev->dev->bus_type) { 5034#ifdef CONFIG_B43_BCMA 5035 case B43_BUS_BCMA: 5036 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST); 5037 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY); 5038 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY); 5039 break; 5040#endif 5041#ifdef CONFIG_B43_SSB 5042 case B43_BUS_SSB: 5043 if (dev->dev->core_rev >= 5) { 5044 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 5045 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY); 5046 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY); 5047 } else 5048 B43_WARN_ON(1); 5049 break; 5050#endif 5051 } 5052 5053 dev->phy.gmode = have_2ghz_phy; 5054 dev->phy.radio_on = 1; 5055 b43_wireless_core_reset(dev, dev->phy.gmode); 5056 5057 err = b43_phy_versioning(dev); 5058 if (err) 5059 goto err_powerdown; 5060 /* Check if this device supports multiband. */ 5061 if (!pdev || 5062 (pdev->device != 0x4312 && 5063 pdev->device != 0x4319 && pdev->device != 0x4324)) { 5064 /* No multiband support. */ 5065 have_2ghz_phy = 0; 5066 have_5ghz_phy = 0; 5067 switch (dev->phy.type) { 5068 case B43_PHYTYPE_A: 5069 have_5ghz_phy = 1; 5070 break; 5071 case B43_PHYTYPE_LP: //FIXME not always! 5072#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference 5073 have_5ghz_phy = 1; 5074#endif 5075 case B43_PHYTYPE_G: 5076 case B43_PHYTYPE_N: 5077 case B43_PHYTYPE_HT: 5078 case B43_PHYTYPE_LCN: 5079 have_2ghz_phy = 1; 5080 break; 5081 default: 5082 B43_WARN_ON(1); 5083 } 5084 } 5085 if (dev->phy.type == B43_PHYTYPE_A) { 5086 /* FIXME */ 5087 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 5088 err = -EOPNOTSUPP; 5089 goto err_powerdown; 5090 } 5091 if (1 /* disable A-PHY */) { 5092 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */ 5093 if (dev->phy.type != B43_PHYTYPE_N && 5094 dev->phy.type != B43_PHYTYPE_LP) { 5095 have_2ghz_phy = 1; 5096 have_5ghz_phy = 0; 5097 } 5098 } 5099 5100 err = b43_phy_allocate(dev); 5101 if (err) 5102 goto err_powerdown; 5103 5104 dev->phy.gmode = have_2ghz_phy; 5105 b43_wireless_core_reset(dev, dev->phy.gmode); 5106 5107 err = b43_validate_chipaccess(dev); 5108 if (err) 5109 goto err_phy_free; 5110 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); 5111 if (err) 5112 goto err_phy_free; 5113 5114 /* Now set some default "current_dev" */ 5115 if (!wl->current_dev) 5116 wl->current_dev = dev; 5117 INIT_WORK(&dev->restart_work, b43_chip_reset); 5118 5119 dev->phy.ops->switch_analog(dev, 0); 5120 b43_device_disable(dev, 0); 5121 b43_bus_may_powerdown(dev); 5122 5123out: 5124 return err; 5125 5126err_phy_free: 5127 b43_phy_free(dev); 5128err_powerdown: 5129 b43_bus_may_powerdown(dev); 5130 return err; 5131} 5132 5133static void b43_one_core_detach(struct b43_bus_dev *dev) 5134{ 5135 struct b43_wldev *wldev; 5136 struct b43_wl *wl; 5137 5138 /* Do not cancel ieee80211-workqueue based work here. 5139 * See comment in b43_remove(). */ 5140 5141 wldev = b43_bus_get_wldev(dev); 5142 wl = wldev->wl; 5143 b43_debugfs_remove_device(wldev); 5144 b43_wireless_core_detach(wldev); 5145 list_del(&wldev->list); 5146 wl->nr_devs--; 5147 b43_bus_set_wldev(dev, NULL); 5148 kfree(wldev); 5149} 5150 5151static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl) 5152{ 5153 struct b43_wldev *wldev; 5154 int err = -ENOMEM; 5155 5156 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 5157 if (!wldev) 5158 goto out; 5159 5160 wldev->use_pio = b43_modparam_pio; 5161 wldev->dev = dev; 5162 wldev->wl = wl; 5163 b43_set_status(wldev, B43_STAT_UNINIT); 5164 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 5165 INIT_LIST_HEAD(&wldev->list); 5166 5167 err = b43_wireless_core_attach(wldev); 5168 if (err) 5169 goto err_kfree_wldev; 5170 5171 list_add(&wldev->list, &wl->devlist); 5172 wl->nr_devs++; 5173 b43_bus_set_wldev(dev, wldev); 5174 b43_debugfs_add_device(wldev); 5175 5176 out: 5177 return err; 5178 5179 err_kfree_wldev: 5180 kfree(wldev); 5181 return err; 5182} 5183 5184#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ 5185 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ 5186 (pdev->device == _device) && \ 5187 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ 5188 (pdev->subsystem_device == _subdevice) ) 5189 5190static void b43_sprom_fixup(struct ssb_bus *bus) 5191{ 5192 struct pci_dev *pdev; 5193 5194 /* boardflags workarounds */ 5195 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 5196 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 5197 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 5198 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 5199 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 5200 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 5201 if (bus->bustype == SSB_BUSTYPE_PCI) { 5202 pdev = bus->host_pci; 5203 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || 5204 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || 5205 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || 5206 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || 5207 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || 5208 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || 5209 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) 5210 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; 5211 } 5212} 5213 5214static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl) 5215{ 5216 struct ieee80211_hw *hw = wl->hw; 5217 5218 ssb_set_devtypedata(dev->sdev, NULL); 5219 ieee80211_free_hw(hw); 5220} 5221 5222static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev) 5223{ 5224 struct ssb_sprom *sprom = dev->bus_sprom; 5225 struct ieee80211_hw *hw; 5226 struct b43_wl *wl; 5227 char chip_name[6]; 5228 5229 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 5230 if (!hw) { 5231 b43err(NULL, "Could not allocate ieee80211 device\n"); 5232 return ERR_PTR(-ENOMEM); 5233 } 5234 wl = hw_to_b43_wl(hw); 5235 5236 /* fill hw info */ 5237 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 5238 IEEE80211_HW_SIGNAL_DBM; 5239 5240 hw->wiphy->interface_modes = 5241 BIT(NL80211_IFTYPE_AP) | 5242 BIT(NL80211_IFTYPE_MESH_POINT) | 5243 BIT(NL80211_IFTYPE_STATION) | 5244 BIT(NL80211_IFTYPE_WDS) | 5245 BIT(NL80211_IFTYPE_ADHOC); 5246 5247 hw->queues = modparam_qos ? 4 : 1; 5248 wl->mac80211_initially_registered_queues = hw->queues; 5249 hw->max_rates = 2; 5250 SET_IEEE80211_DEV(hw, dev->dev); 5251 if (is_valid_ether_addr(sprom->et1mac)) 5252 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 5253 else 5254 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 5255 5256 /* Initialize struct b43_wl */ 5257 wl->hw = hw; 5258 mutex_init(&wl->mutex); 5259 spin_lock_init(&wl->hardirq_lock); 5260 INIT_LIST_HEAD(&wl->devlist); 5261 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); 5262 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work); 5263 INIT_WORK(&wl->tx_work, b43_tx_work); 5264 skb_queue_head_init(&wl->tx_queue); 5265 5266 snprintf(chip_name, ARRAY_SIZE(chip_name), 5267 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id); 5268 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name, 5269 dev->core_rev); 5270 return wl; 5271} 5272 5273#ifdef CONFIG_B43_BCMA 5274static int b43_bcma_probe(struct bcma_device *core) 5275{ 5276 struct b43_bus_dev *dev; 5277 struct b43_wl *wl; 5278 int err; 5279 5280 dev = b43_bus_dev_bcma_init(core); 5281 if (!dev) 5282 return -ENODEV; 5283 5284 wl = b43_wireless_init(dev); 5285 if (IS_ERR(wl)) { 5286 err = PTR_ERR(wl); 5287 goto bcma_out; 5288 } 5289 5290 err = b43_one_core_attach(dev, wl); 5291 if (err) 5292 goto bcma_err_wireless_exit; 5293 5294 err = ieee80211_register_hw(wl->hw); 5295 if (err) 5296 goto bcma_err_one_core_detach; 5297 b43_leds_register(wl->current_dev); 5298 5299bcma_out: 5300 return err; 5301 5302bcma_err_one_core_detach: 5303 b43_one_core_detach(dev); 5304bcma_err_wireless_exit: 5305 ieee80211_free_hw(wl->hw); 5306 return err; 5307} 5308 5309static void b43_bcma_remove(struct bcma_device *core) 5310{ 5311 struct b43_wldev *wldev = bcma_get_drvdata(core); 5312 struct b43_wl *wl = wldev->wl; 5313 5314 /* We must cancel any work here before unregistering from ieee80211, 5315 * as the ieee80211 unreg will destroy the workqueue. */ 5316 cancel_work_sync(&wldev->restart_work); 5317 5318 /* Restore the queues count before unregistering, because firmware detect 5319 * might have modified it. Restoring is important, so the networking 5320 * stack can properly free resources. */ 5321 wl->hw->queues = wl->mac80211_initially_registered_queues; 5322 b43_leds_stop(wldev); 5323 ieee80211_unregister_hw(wl->hw); 5324 5325 b43_one_core_detach(wldev->dev); 5326 5327 b43_leds_unregister(wl); 5328 5329 ieee80211_free_hw(wl->hw); 5330} 5331 5332static struct bcma_driver b43_bcma_driver = { 5333 .name = KBUILD_MODNAME, 5334 .id_table = b43_bcma_tbl, 5335 .probe = b43_bcma_probe, 5336 .remove = b43_bcma_remove, 5337}; 5338#endif 5339 5340#ifdef CONFIG_B43_SSB 5341static 5342int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id) 5343{ 5344 struct b43_bus_dev *dev; 5345 struct b43_wl *wl; 5346 int err; 5347 int first = 0; 5348 5349 dev = b43_bus_dev_ssb_init(sdev); 5350 if (!dev) 5351 return -ENOMEM; 5352 5353 wl = ssb_get_devtypedata(sdev); 5354 if (!wl) { 5355 /* Probing the first core. Must setup common struct b43_wl */ 5356 first = 1; 5357 b43_sprom_fixup(sdev->bus); 5358 wl = b43_wireless_init(dev); 5359 if (IS_ERR(wl)) { 5360 err = PTR_ERR(wl); 5361 goto out; 5362 } 5363 ssb_set_devtypedata(sdev, wl); 5364 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl); 5365 } 5366 err = b43_one_core_attach(dev, wl); 5367 if (err) 5368 goto err_wireless_exit; 5369 5370 if (first) { 5371 err = ieee80211_register_hw(wl->hw); 5372 if (err) 5373 goto err_one_core_detach; 5374 b43_leds_register(wl->current_dev); 5375 } 5376 5377 out: 5378 return err; 5379 5380 err_one_core_detach: 5381 b43_one_core_detach(dev); 5382 err_wireless_exit: 5383 if (first) 5384 b43_wireless_exit(dev, wl); 5385 return err; 5386} 5387 5388static void b43_ssb_remove(struct ssb_device *sdev) 5389{ 5390 struct b43_wl *wl = ssb_get_devtypedata(sdev); 5391 struct b43_wldev *wldev = ssb_get_drvdata(sdev); 5392 struct b43_bus_dev *dev = wldev->dev; 5393 5394 /* We must cancel any work here before unregistering from ieee80211, 5395 * as the ieee80211 unreg will destroy the workqueue. */ 5396 cancel_work_sync(&wldev->restart_work); 5397 5398 B43_WARN_ON(!wl); 5399 if (wl->current_dev == wldev) { 5400 /* Restore the queues count before unregistering, because firmware detect 5401 * might have modified it. Restoring is important, so the networking 5402 * stack can properly free resources. */ 5403 wl->hw->queues = wl->mac80211_initially_registered_queues; 5404 b43_leds_stop(wldev); 5405 ieee80211_unregister_hw(wl->hw); 5406 } 5407 5408 b43_one_core_detach(dev); 5409 5410 if (list_empty(&wl->devlist)) { 5411 b43_leds_unregister(wl); 5412 /* Last core on the chip unregistered. 5413 * We can destroy common struct b43_wl. 5414 */ 5415 b43_wireless_exit(dev, wl); 5416 } 5417} 5418 5419static struct ssb_driver b43_ssb_driver = { 5420 .name = KBUILD_MODNAME, 5421 .id_table = b43_ssb_tbl, 5422 .probe = b43_ssb_probe, 5423 .remove = b43_ssb_remove, 5424}; 5425#endif /* CONFIG_B43_SSB */ 5426 5427/* Perform a hardware reset. This can be called from any context. */ 5428void b43_controller_restart(struct b43_wldev *dev, const char *reason) 5429{ 5430 /* Must avoid requeueing, if we are in shutdown. */ 5431 if (b43_status(dev) < B43_STAT_INITIALIZED) 5432 return; 5433 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 5434 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 5435} 5436 5437static void b43_print_driverinfo(void) 5438{ 5439 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", 5440 *feat_leds = "", *feat_sdio = ""; 5441 5442#ifdef CONFIG_B43_PCI_AUTOSELECT 5443 feat_pci = "P"; 5444#endif 5445#ifdef CONFIG_B43_PCMCIA 5446 feat_pcmcia = "M"; 5447#endif 5448#ifdef CONFIG_B43_PHY_N 5449 feat_nphy = "N"; 5450#endif 5451#ifdef CONFIG_B43_LEDS 5452 feat_leds = "L"; 5453#endif 5454#ifdef CONFIG_B43_SDIO 5455 feat_sdio = "S"; 5456#endif 5457 printk(KERN_INFO "Broadcom 43xx driver loaded " 5458 "[ Features: %s%s%s%s%s, Firmware-ID: " 5459 B43_SUPPORTED_FIRMWARE_ID " ]\n", 5460 feat_pci, feat_pcmcia, feat_nphy, 5461 feat_leds, feat_sdio); 5462} 5463 5464static int __init b43_init(void) 5465{ 5466 int err; 5467 5468 b43_debugfs_init(); 5469 err = b43_pcmcia_init(); 5470 if (err) 5471 goto err_dfs_exit; 5472 err = b43_sdio_init(); 5473 if (err) 5474 goto err_pcmcia_exit; 5475#ifdef CONFIG_B43_BCMA 5476 err = bcma_driver_register(&b43_bcma_driver); 5477 if (err) 5478 goto err_sdio_exit; 5479#endif 5480#ifdef CONFIG_B43_SSB 5481 err = ssb_driver_register(&b43_ssb_driver); 5482 if (err) 5483 goto err_bcma_driver_exit; 5484#endif 5485 b43_print_driverinfo(); 5486 5487 return err; 5488 5489#ifdef CONFIG_B43_SSB 5490err_bcma_driver_exit: 5491#endif 5492#ifdef CONFIG_B43_BCMA 5493 bcma_driver_unregister(&b43_bcma_driver); 5494err_sdio_exit: 5495#endif 5496 b43_sdio_exit(); 5497err_pcmcia_exit: 5498 b43_pcmcia_exit(); 5499err_dfs_exit: 5500 b43_debugfs_exit(); 5501 return err; 5502} 5503 5504static void __exit b43_exit(void) 5505{ 5506#ifdef CONFIG_B43_SSB 5507 ssb_driver_unregister(&b43_ssb_driver); 5508#endif 5509#ifdef CONFIG_B43_BCMA 5510 bcma_driver_unregister(&b43_bcma_driver); 5511#endif 5512 b43_sdio_exit(); 5513 b43_pcmcia_exit(); 5514 b43_debugfs_exit(); 5515} 5516 5517module_init(b43_init) 5518module_exit(b43_exit) 5519