main.c revision 74cfdba7ce7b601559a4bcdc9054baf1bdc6948d
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net> 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 Some parts of the code in this file are derived from the ipw2200 12 driver Copyright(c) 2003 - 2004 Intel Corporation. 13 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; either version 2 of the License, or 17 (at your option) any later version. 18 19 This program is distributed in the hope that it will be useful, 20 but WITHOUT ANY WARRANTY; without even the implied warranty of 21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 GNU General Public License for more details. 23 24 You should have received a copy of the GNU General Public License 25 along with this program; see the file COPYING. If not, write to 26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 27 Boston, MA 02110-1301, USA. 28 29*/ 30 31#include <linux/delay.h> 32#include <linux/init.h> 33#include <linux/moduleparam.h> 34#include <linux/if_arp.h> 35#include <linux/etherdevice.h> 36#include <linux/version.h> 37#include <linux/firmware.h> 38#include <linux/wireless.h> 39#include <linux/workqueue.h> 40#include <linux/skbuff.h> 41#include <linux/dma-mapping.h> 42#include <asm/unaligned.h> 43 44#include "b43.h" 45#include "main.h" 46#include "debugfs.h" 47#include "phy.h" 48#include "dma.h" 49#include "pio.h" 50#include "sysfs.h" 51#include "xmit.h" 52#include "lo.h" 53#include "pcmcia.h" 54 55MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 56MODULE_AUTHOR("Martin Langer"); 57MODULE_AUTHOR("Stefano Brivio"); 58MODULE_AUTHOR("Michael Buesch"); 59MODULE_LICENSE("GPL"); 60 61extern char *nvram_get(char *name); 62 63#if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO) 64static int modparam_pio; 65module_param_named(pio, modparam_pio, int, 0444); 66MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode"); 67#elif defined(CONFIG_B43_DMA) 68# define modparam_pio 0 69#elif defined(CONFIG_B43_PIO) 70# define modparam_pio 1 71#endif 72 73static int modparam_bad_frames_preempt; 74module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 75MODULE_PARM_DESC(bad_frames_preempt, 76 "enable(1) / disable(0) Bad Frames Preemption"); 77 78static char modparam_fwpostfix[16]; 79module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 80MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 81 82static int modparam_hwpctl; 83module_param_named(hwpctl, modparam_hwpctl, int, 0444); 84MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 85 86static int modparam_nohwcrypt; 87module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 88MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 89 90static const struct ssb_device_id b43_ssb_tbl[] = { 91 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 92 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 96 SSB_DEVTABLE_END 97}; 98 99MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 100 101/* Channel and ratetables are shared for all devices. 102 * They can't be const, because ieee80211 puts some precalculated 103 * data in there. This data is the same for all devices, so we don't 104 * get concurrency issues */ 105#define RATETAB_ENT(_rateid, _flags) \ 106 { \ 107 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \ 108 .val = (_rateid), \ 109 .val2 = (_rateid), \ 110 .flags = (_flags), \ 111 } 112static struct ieee80211_rate __b43_ratetable[] = { 113 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK), 114 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2), 115 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2), 116 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2), 117 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM), 118 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM), 119 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM), 120 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM), 121 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM), 122 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM), 123 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM), 124 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM), 125}; 126 127#define b43_a_ratetable (__b43_ratetable + 4) 128#define b43_a_ratetable_size 8 129#define b43_b_ratetable (__b43_ratetable + 0) 130#define b43_b_ratetable_size 4 131#define b43_g_ratetable (__b43_ratetable + 0) 132#define b43_g_ratetable_size 12 133 134#define CHANTAB_ENT(_chanid, _freq) \ 135 { \ 136 .chan = (_chanid), \ 137 .freq = (_freq), \ 138 .val = (_chanid), \ 139 .flag = IEEE80211_CHAN_W_SCAN | \ 140 IEEE80211_CHAN_W_ACTIVE_SCAN | \ 141 IEEE80211_CHAN_W_IBSS, \ 142 .power_level = 0xFF, \ 143 .antenna_max = 0xFF, \ 144 } 145static struct ieee80211_channel b43_bg_chantable[] = { 146 CHANTAB_ENT(1, 2412), 147 CHANTAB_ENT(2, 2417), 148 CHANTAB_ENT(3, 2422), 149 CHANTAB_ENT(4, 2427), 150 CHANTAB_ENT(5, 2432), 151 CHANTAB_ENT(6, 2437), 152 CHANTAB_ENT(7, 2442), 153 CHANTAB_ENT(8, 2447), 154 CHANTAB_ENT(9, 2452), 155 CHANTAB_ENT(10, 2457), 156 CHANTAB_ENT(11, 2462), 157 CHANTAB_ENT(12, 2467), 158 CHANTAB_ENT(13, 2472), 159 CHANTAB_ENT(14, 2484), 160}; 161 162#define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable) 163static struct ieee80211_channel b43_a_chantable[] = { 164 CHANTAB_ENT(36, 5180), 165 CHANTAB_ENT(40, 5200), 166 CHANTAB_ENT(44, 5220), 167 CHANTAB_ENT(48, 5240), 168 CHANTAB_ENT(52, 5260), 169 CHANTAB_ENT(56, 5280), 170 CHANTAB_ENT(60, 5300), 171 CHANTAB_ENT(64, 5320), 172 CHANTAB_ENT(149, 5745), 173 CHANTAB_ENT(153, 5765), 174 CHANTAB_ENT(157, 5785), 175 CHANTAB_ENT(161, 5805), 176 CHANTAB_ENT(165, 5825), 177}; 178 179#define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable) 180 181static void b43_wireless_core_exit(struct b43_wldev *dev); 182static int b43_wireless_core_init(struct b43_wldev *dev); 183static void b43_wireless_core_stop(struct b43_wldev *dev); 184static int b43_wireless_core_start(struct b43_wldev *dev); 185 186static int b43_ratelimit(struct b43_wl *wl) 187{ 188 if (!wl || !wl->current_dev) 189 return 1; 190 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 191 return 1; 192 /* We are up and running. 193 * Ratelimit the messages to avoid DoS over the net. */ 194 return net_ratelimit(); 195} 196 197void b43info(struct b43_wl *wl, const char *fmt, ...) 198{ 199 va_list args; 200 201 if (!b43_ratelimit(wl)) 202 return; 203 va_start(args, fmt); 204 printk(KERN_INFO "b43-%s: ", 205 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 206 vprintk(fmt, args); 207 va_end(args); 208} 209 210void b43err(struct b43_wl *wl, const char *fmt, ...) 211{ 212 va_list args; 213 214 if (!b43_ratelimit(wl)) 215 return; 216 va_start(args, fmt); 217 printk(KERN_ERR "b43-%s ERROR: ", 218 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 219 vprintk(fmt, args); 220 va_end(args); 221} 222 223void b43warn(struct b43_wl *wl, const char *fmt, ...) 224{ 225 va_list args; 226 227 if (!b43_ratelimit(wl)) 228 return; 229 va_start(args, fmt); 230 printk(KERN_WARNING "b43-%s warning: ", 231 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 232 vprintk(fmt, args); 233 va_end(args); 234} 235 236#if B43_DEBUG 237void b43dbg(struct b43_wl *wl, const char *fmt, ...) 238{ 239 va_list args; 240 241 va_start(args, fmt); 242 printk(KERN_DEBUG "b43-%s debug: ", 243 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 244 vprintk(fmt, args); 245 va_end(args); 246} 247#endif /* DEBUG */ 248 249static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 250{ 251 u32 macctl; 252 253 B43_WARN_ON(offset % 4 != 0); 254 255 macctl = b43_read32(dev, B43_MMIO_MACCTL); 256 if (macctl & B43_MACCTL_BE) 257 val = swab32(val); 258 259 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 260 mmiowb(); 261 b43_write32(dev, B43_MMIO_RAM_DATA, val); 262} 263 264static inline 265 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset) 266{ 267 u32 control; 268 269 /* "offset" is the WORD offset. */ 270 271 control = routing; 272 control <<= 16; 273 control |= offset; 274 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 275} 276 277u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 278{ 279 u32 ret; 280 281 if (routing == B43_SHM_SHARED) { 282 B43_WARN_ON(offset & 0x0001); 283 if (offset & 0x0003) { 284 /* Unaligned access */ 285 b43_shm_control_word(dev, routing, offset >> 2); 286 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 287 ret <<= 16; 288 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 289 ret |= b43_read16(dev, B43_MMIO_SHM_DATA); 290 291 return ret; 292 } 293 offset >>= 2; 294 } 295 b43_shm_control_word(dev, routing, offset); 296 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 297 298 return ret; 299} 300 301u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset) 302{ 303 u16 ret; 304 305 if (routing == B43_SHM_SHARED) { 306 B43_WARN_ON(offset & 0x0001); 307 if (offset & 0x0003) { 308 /* Unaligned access */ 309 b43_shm_control_word(dev, routing, offset >> 2); 310 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 311 312 return ret; 313 } 314 offset >>= 2; 315 } 316 b43_shm_control_word(dev, routing, offset); 317 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 318 319 return ret; 320} 321 322void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 323{ 324 if (routing == B43_SHM_SHARED) { 325 B43_WARN_ON(offset & 0x0001); 326 if (offset & 0x0003) { 327 /* Unaligned access */ 328 b43_shm_control_word(dev, routing, offset >> 2); 329 mmiowb(); 330 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 331 (value >> 16) & 0xffff); 332 mmiowb(); 333 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 334 mmiowb(); 335 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff); 336 return; 337 } 338 offset >>= 2; 339 } 340 b43_shm_control_word(dev, routing, offset); 341 mmiowb(); 342 b43_write32(dev, B43_MMIO_SHM_DATA, value); 343} 344 345void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 346{ 347 if (routing == B43_SHM_SHARED) { 348 B43_WARN_ON(offset & 0x0001); 349 if (offset & 0x0003) { 350 /* Unaligned access */ 351 b43_shm_control_word(dev, routing, offset >> 2); 352 mmiowb(); 353 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 354 return; 355 } 356 offset >>= 2; 357 } 358 b43_shm_control_word(dev, routing, offset); 359 mmiowb(); 360 b43_write16(dev, B43_MMIO_SHM_DATA, value); 361} 362 363/* Read HostFlags */ 364u32 b43_hf_read(struct b43_wldev * dev) 365{ 366 u32 ret; 367 368 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 369 ret <<= 16; 370 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 371 372 return ret; 373} 374 375/* Write HostFlags */ 376void b43_hf_write(struct b43_wldev *dev, u32 value) 377{ 378 b43_shm_write16(dev, B43_SHM_SHARED, 379 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF)); 380 b43_shm_write16(dev, B43_SHM_SHARED, 381 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16)); 382} 383 384void b43_tsf_read(struct b43_wldev *dev, u64 * tsf) 385{ 386 /* We need to be careful. As we read the TSF from multiple 387 * registers, we should take care of register overflows. 388 * In theory, the whole tsf read process should be atomic. 389 * We try to be atomic here, by restaring the read process, 390 * if any of the high registers changed (overflew). 391 */ 392 if (dev->dev->id.revision >= 3) { 393 u32 low, high, high2; 394 395 do { 396 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 397 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 398 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 399 } while (unlikely(high != high2)); 400 401 *tsf = high; 402 *tsf <<= 32; 403 *tsf |= low; 404 } else { 405 u64 tmp; 406 u16 v0, v1, v2, v3; 407 u16 test1, test2, test3; 408 409 do { 410 v3 = b43_read16(dev, B43_MMIO_TSF_3); 411 v2 = b43_read16(dev, B43_MMIO_TSF_2); 412 v1 = b43_read16(dev, B43_MMIO_TSF_1); 413 v0 = b43_read16(dev, B43_MMIO_TSF_0); 414 415 test3 = b43_read16(dev, B43_MMIO_TSF_3); 416 test2 = b43_read16(dev, B43_MMIO_TSF_2); 417 test1 = b43_read16(dev, B43_MMIO_TSF_1); 418 } while (v3 != test3 || v2 != test2 || v1 != test1); 419 420 *tsf = v3; 421 *tsf <<= 48; 422 tmp = v2; 423 tmp <<= 32; 424 *tsf |= tmp; 425 tmp = v1; 426 tmp <<= 16; 427 *tsf |= tmp; 428 *tsf |= v0; 429 } 430} 431 432static void b43_time_lock(struct b43_wldev *dev) 433{ 434 u32 macctl; 435 436 macctl = b43_read32(dev, B43_MMIO_MACCTL); 437 macctl |= B43_MACCTL_TBTTHOLD; 438 b43_write32(dev, B43_MMIO_MACCTL, macctl); 439 /* Commit the write */ 440 b43_read32(dev, B43_MMIO_MACCTL); 441} 442 443static void b43_time_unlock(struct b43_wldev *dev) 444{ 445 u32 macctl; 446 447 macctl = b43_read32(dev, B43_MMIO_MACCTL); 448 macctl &= ~B43_MACCTL_TBTTHOLD; 449 b43_write32(dev, B43_MMIO_MACCTL, macctl); 450 /* Commit the write */ 451 b43_read32(dev, B43_MMIO_MACCTL); 452} 453 454static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 455{ 456 /* Be careful with the in-progress timer. 457 * First zero out the low register, so we have a full 458 * register-overflow duration to complete the operation. 459 */ 460 if (dev->dev->id.revision >= 3) { 461 u32 lo = (tsf & 0x00000000FFFFFFFFULL); 462 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32; 463 464 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0); 465 mmiowb(); 466 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi); 467 mmiowb(); 468 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo); 469 } else { 470 u16 v0 = (tsf & 0x000000000000FFFFULL); 471 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16; 472 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32; 473 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; 474 475 b43_write16(dev, B43_MMIO_TSF_0, 0); 476 mmiowb(); 477 b43_write16(dev, B43_MMIO_TSF_3, v3); 478 mmiowb(); 479 b43_write16(dev, B43_MMIO_TSF_2, v2); 480 mmiowb(); 481 b43_write16(dev, B43_MMIO_TSF_1, v1); 482 mmiowb(); 483 b43_write16(dev, B43_MMIO_TSF_0, v0); 484 } 485} 486 487void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 488{ 489 b43_time_lock(dev); 490 b43_tsf_write_locked(dev, tsf); 491 b43_time_unlock(dev); 492} 493 494static 495void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac) 496{ 497 static const u8 zero_addr[ETH_ALEN] = { 0 }; 498 u16 data; 499 500 if (!mac) 501 mac = zero_addr; 502 503 offset |= 0x0020; 504 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 505 506 data = mac[0]; 507 data |= mac[1] << 8; 508 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 509 data = mac[2]; 510 data |= mac[3] << 8; 511 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 512 data = mac[4]; 513 data |= mac[5] << 8; 514 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 515} 516 517static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 518{ 519 const u8 *mac; 520 const u8 *bssid; 521 u8 mac_bssid[ETH_ALEN * 2]; 522 int i; 523 u32 tmp; 524 525 bssid = dev->wl->bssid; 526 mac = dev->wl->mac_addr; 527 528 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 529 530 memcpy(mac_bssid, mac, ETH_ALEN); 531 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 532 533 /* Write our MAC address and BSSID to template ram */ 534 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 535 tmp = (u32) (mac_bssid[i + 0]); 536 tmp |= (u32) (mac_bssid[i + 1]) << 8; 537 tmp |= (u32) (mac_bssid[i + 2]) << 16; 538 tmp |= (u32) (mac_bssid[i + 3]) << 24; 539 b43_ram_write(dev, 0x20 + i, tmp); 540 } 541} 542 543static void b43_upload_card_macaddress(struct b43_wldev *dev) 544{ 545 b43_write_mac_bssid_templates(dev); 546 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 547} 548 549static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 550{ 551 /* slot_time is in usec. */ 552 if (dev->phy.type != B43_PHYTYPE_G) 553 return; 554 b43_write16(dev, 0x684, 510 + slot_time); 555 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 556} 557 558static void b43_short_slot_timing_enable(struct b43_wldev *dev) 559{ 560 b43_set_slot_time(dev, 9); 561 dev->short_slot = 1; 562} 563 564static void b43_short_slot_timing_disable(struct b43_wldev *dev) 565{ 566 b43_set_slot_time(dev, 20); 567 dev->short_slot = 0; 568} 569 570/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable. 571 * Returns the _previously_ enabled IRQ mask. 572 */ 573static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask) 574{ 575 u32 old_mask; 576 577 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 578 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask); 579 580 return old_mask; 581} 582 583/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable. 584 * Returns the _previously_ enabled IRQ mask. 585 */ 586static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask) 587{ 588 u32 old_mask; 589 590 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 591 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask); 592 593 return old_mask; 594} 595 596/* Synchronize IRQ top- and bottom-half. 597 * IRQs must be masked before calling this. 598 * This must not be called with the irq_lock held. 599 */ 600static void b43_synchronize_irq(struct b43_wldev *dev) 601{ 602 synchronize_irq(dev->dev->irq); 603 tasklet_kill(&dev->isr_tasklet); 604} 605 606/* DummyTransmission function, as documented on 607 * http://bcm-specs.sipsolutions.net/DummyTransmission 608 */ 609void b43_dummy_transmission(struct b43_wldev *dev) 610{ 611 struct b43_phy *phy = &dev->phy; 612 unsigned int i, max_loop; 613 u16 value; 614 u32 buffer[5] = { 615 0x00000000, 616 0x00D40000, 617 0x00000000, 618 0x01000000, 619 0x00000000, 620 }; 621 622 switch (phy->type) { 623 case B43_PHYTYPE_A: 624 max_loop = 0x1E; 625 buffer[0] = 0x000201CC; 626 break; 627 case B43_PHYTYPE_B: 628 case B43_PHYTYPE_G: 629 max_loop = 0xFA; 630 buffer[0] = 0x000B846E; 631 break; 632 default: 633 B43_WARN_ON(1); 634 return; 635 } 636 637 for (i = 0; i < 5; i++) 638 b43_ram_write(dev, i * 4, buffer[i]); 639 640 /* Commit writes */ 641 b43_read32(dev, B43_MMIO_MACCTL); 642 643 b43_write16(dev, 0x0568, 0x0000); 644 b43_write16(dev, 0x07C0, 0x0000); 645 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0); 646 b43_write16(dev, 0x050C, value); 647 b43_write16(dev, 0x0508, 0x0000); 648 b43_write16(dev, 0x050A, 0x0000); 649 b43_write16(dev, 0x054C, 0x0000); 650 b43_write16(dev, 0x056A, 0x0014); 651 b43_write16(dev, 0x0568, 0x0826); 652 b43_write16(dev, 0x0500, 0x0000); 653 b43_write16(dev, 0x0502, 0x0030); 654 655 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 656 b43_radio_write16(dev, 0x0051, 0x0017); 657 for (i = 0x00; i < max_loop; i++) { 658 value = b43_read16(dev, 0x050E); 659 if (value & 0x0080) 660 break; 661 udelay(10); 662 } 663 for (i = 0x00; i < 0x0A; i++) { 664 value = b43_read16(dev, 0x050E); 665 if (value & 0x0400) 666 break; 667 udelay(10); 668 } 669 for (i = 0x00; i < 0x0A; i++) { 670 value = b43_read16(dev, 0x0690); 671 if (!(value & 0x0100)) 672 break; 673 udelay(10); 674 } 675 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 676 b43_radio_write16(dev, 0x0051, 0x0037); 677} 678 679static void key_write(struct b43_wldev *dev, 680 u8 index, u8 algorithm, const u8 * key) 681{ 682 unsigned int i; 683 u32 offset; 684 u16 value; 685 u16 kidx; 686 687 /* Key index/algo block */ 688 kidx = b43_kidx_to_fw(dev, index); 689 value = ((kidx << 4) | algorithm); 690 b43_shm_write16(dev, B43_SHM_SHARED, 691 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 692 693 /* Write the key to the Key Table Pointer offset */ 694 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 695 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 696 value = key[i]; 697 value |= (u16) (key[i + 1]) << 8; 698 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 699 } 700} 701 702static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr) 703{ 704 u32 addrtmp[2] = { 0, 0, }; 705 u8 per_sta_keys_start = 8; 706 707 if (b43_new_kidx_api(dev)) 708 per_sta_keys_start = 4; 709 710 B43_WARN_ON(index < per_sta_keys_start); 711 /* We have two default TX keys and possibly two default RX keys. 712 * Physical mac 0 is mapped to physical key 4 or 8, depending 713 * on the firmware version. 714 * So we must adjust the index here. 715 */ 716 index -= per_sta_keys_start; 717 718 if (addr) { 719 addrtmp[0] = addr[0]; 720 addrtmp[0] |= ((u32) (addr[1]) << 8); 721 addrtmp[0] |= ((u32) (addr[2]) << 16); 722 addrtmp[0] |= ((u32) (addr[3]) << 24); 723 addrtmp[1] = addr[4]; 724 addrtmp[1] |= ((u32) (addr[5]) << 8); 725 } 726 727 if (dev->dev->id.revision >= 5) { 728 /* Receive match transmitter address mechanism */ 729 b43_shm_write32(dev, B43_SHM_RCMTA, 730 (index * 2) + 0, addrtmp[0]); 731 b43_shm_write16(dev, B43_SHM_RCMTA, 732 (index * 2) + 1, addrtmp[1]); 733 } else { 734 /* RXE (Receive Engine) and 735 * PSM (Programmable State Machine) mechanism 736 */ 737 if (index < 8) { 738 /* TODO write to RCM 16, 19, 22 and 25 */ 739 } else { 740 b43_shm_write32(dev, B43_SHM_SHARED, 741 B43_SHM_SH_PSM + (index * 6) + 0, 742 addrtmp[0]); 743 b43_shm_write16(dev, B43_SHM_SHARED, 744 B43_SHM_SH_PSM + (index * 6) + 4, 745 addrtmp[1]); 746 } 747 } 748} 749 750static void do_key_write(struct b43_wldev *dev, 751 u8 index, u8 algorithm, 752 const u8 * key, size_t key_len, const u8 * mac_addr) 753{ 754 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 755 u8 per_sta_keys_start = 8; 756 757 if (b43_new_kidx_api(dev)) 758 per_sta_keys_start = 4; 759 760 B43_WARN_ON(index >= dev->max_nr_keys); 761 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 762 763 if (index >= per_sta_keys_start) 764 keymac_write(dev, index, NULL); /* First zero out mac. */ 765 if (key) 766 memcpy(buf, key, key_len); 767 key_write(dev, index, algorithm, buf); 768 if (index >= per_sta_keys_start) 769 keymac_write(dev, index, mac_addr); 770 771 dev->key[index].algorithm = algorithm; 772} 773 774static int b43_key_write(struct b43_wldev *dev, 775 int index, u8 algorithm, 776 const u8 * key, size_t key_len, 777 const u8 * mac_addr, 778 struct ieee80211_key_conf *keyconf) 779{ 780 int i; 781 int sta_keys_start; 782 783 if (key_len > B43_SEC_KEYSIZE) 784 return -EINVAL; 785 for (i = 0; i < dev->max_nr_keys; i++) { 786 /* Check that we don't already have this key. */ 787 B43_WARN_ON(dev->key[i].keyconf == keyconf); 788 } 789 if (index < 0) { 790 /* Either pairwise key or address is 00:00:00:00:00:00 791 * for transmit-only keys. Search the index. */ 792 if (b43_new_kidx_api(dev)) 793 sta_keys_start = 4; 794 else 795 sta_keys_start = 8; 796 for (i = sta_keys_start; i < dev->max_nr_keys; i++) { 797 if (!dev->key[i].keyconf) { 798 /* found empty */ 799 index = i; 800 break; 801 } 802 } 803 if (index < 0) { 804 b43err(dev->wl, "Out of hardware key memory\n"); 805 return -ENOSPC; 806 } 807 } else 808 B43_WARN_ON(index > 3); 809 810 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 811 if ((index <= 3) && !b43_new_kidx_api(dev)) { 812 /* Default RX key */ 813 B43_WARN_ON(mac_addr); 814 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 815 } 816 keyconf->hw_key_idx = index; 817 dev->key[index].keyconf = keyconf; 818 819 return 0; 820} 821 822static int b43_key_clear(struct b43_wldev *dev, int index) 823{ 824 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys))) 825 return -EINVAL; 826 do_key_write(dev, index, B43_SEC_ALGO_NONE, 827 NULL, B43_SEC_KEYSIZE, NULL); 828 if ((index <= 3) && !b43_new_kidx_api(dev)) { 829 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 830 NULL, B43_SEC_KEYSIZE, NULL); 831 } 832 dev->key[index].keyconf = NULL; 833 834 return 0; 835} 836 837static void b43_clear_keys(struct b43_wldev *dev) 838{ 839 int i; 840 841 for (i = 0; i < dev->max_nr_keys; i++) 842 b43_key_clear(dev, i); 843} 844 845void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 846{ 847 u32 macctl; 848 u16 ucstat; 849 bool hwps; 850 bool awake; 851 int i; 852 853 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 854 (ps_flags & B43_PS_DISABLED)); 855 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 856 857 if (ps_flags & B43_PS_ENABLED) { 858 hwps = 1; 859 } else if (ps_flags & B43_PS_DISABLED) { 860 hwps = 0; 861 } else { 862 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 863 // and thus is not an AP and we are associated, set bit 25 864 } 865 if (ps_flags & B43_PS_AWAKE) { 866 awake = 1; 867 } else if (ps_flags & B43_PS_ASLEEP) { 868 awake = 0; 869 } else { 870 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 871 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 872 // successful, set bit26 873 } 874 875/* FIXME: For now we force awake-on and hwps-off */ 876 hwps = 0; 877 awake = 1; 878 879 macctl = b43_read32(dev, B43_MMIO_MACCTL); 880 if (hwps) 881 macctl |= B43_MACCTL_HWPS; 882 else 883 macctl &= ~B43_MACCTL_HWPS; 884 if (awake) 885 macctl |= B43_MACCTL_AWAKE; 886 else 887 macctl &= ~B43_MACCTL_AWAKE; 888 b43_write32(dev, B43_MMIO_MACCTL, macctl); 889 /* Commit write */ 890 b43_read32(dev, B43_MMIO_MACCTL); 891 if (awake && dev->dev->id.revision >= 5) { 892 /* Wait for the microcode to wake up. */ 893 for (i = 0; i < 100; i++) { 894 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 895 B43_SHM_SH_UCODESTAT); 896 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 897 break; 898 udelay(10); 899 } 900 } 901} 902 903/* Turn the Analog ON/OFF */ 904static void b43_switch_analog(struct b43_wldev *dev, int on) 905{ 906 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); 907} 908 909void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 910{ 911 u32 tmslow; 912 u32 macctl; 913 914 flags |= B43_TMSLOW_PHYCLKEN; 915 flags |= B43_TMSLOW_PHYRESET; 916 ssb_device_enable(dev->dev, flags); 917 msleep(2); /* Wait for the PLL to turn on. */ 918 919 /* Now take the PHY out of Reset again */ 920 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 921 tmslow |= SSB_TMSLOW_FGC; 922 tmslow &= ~B43_TMSLOW_PHYRESET; 923 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 924 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 925 msleep(1); 926 tmslow &= ~SSB_TMSLOW_FGC; 927 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 928 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 929 msleep(1); 930 931 /* Turn Analog ON */ 932 b43_switch_analog(dev, 1); 933 934 macctl = b43_read32(dev, B43_MMIO_MACCTL); 935 macctl &= ~B43_MACCTL_GMODE; 936 if (flags & B43_TMSLOW_GMODE) 937 macctl |= B43_MACCTL_GMODE; 938 macctl |= B43_MACCTL_IHR_ENABLED; 939 b43_write32(dev, B43_MMIO_MACCTL, macctl); 940} 941 942static void handle_irq_transmit_status(struct b43_wldev *dev) 943{ 944 u32 v0, v1; 945 u16 tmp; 946 struct b43_txstatus stat; 947 948 while (1) { 949 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 950 if (!(v0 & 0x00000001)) 951 break; 952 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 953 954 stat.cookie = (v0 >> 16); 955 stat.seq = (v1 & 0x0000FFFF); 956 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 957 tmp = (v0 & 0x0000FFFF); 958 stat.frame_count = ((tmp & 0xF000) >> 12); 959 stat.rts_count = ((tmp & 0x0F00) >> 8); 960 stat.supp_reason = ((tmp & 0x001C) >> 2); 961 stat.pm_indicated = !!(tmp & 0x0080); 962 stat.intermediate = !!(tmp & 0x0040); 963 stat.for_ampdu = !!(tmp & 0x0020); 964 stat.acked = !!(tmp & 0x0002); 965 966 b43_handle_txstatus(dev, &stat); 967 } 968} 969 970static void drain_txstatus_queue(struct b43_wldev *dev) 971{ 972 u32 dummy; 973 974 if (dev->dev->id.revision < 5) 975 return; 976 /* Read all entries from the microcode TXstatus FIFO 977 * and throw them away. 978 */ 979 while (1) { 980 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 981 if (!(dummy & 0x00000001)) 982 break; 983 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 984 } 985} 986 987static u32 b43_jssi_read(struct b43_wldev *dev) 988{ 989 u32 val = 0; 990 991 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 992 val <<= 16; 993 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 994 995 return val; 996} 997 998static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 999{ 1000 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1001 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1002} 1003 1004static void b43_generate_noise_sample(struct b43_wldev *dev) 1005{ 1006 b43_jssi_write(dev, 0x7F7F7F7F); 1007 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, 1008 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD) 1009 | (1 << 4)); 1010 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel); 1011} 1012 1013static void b43_calculate_link_quality(struct b43_wldev *dev) 1014{ 1015 /* Top half of Link Quality calculation. */ 1016 1017 if (dev->noisecalc.calculation_running) 1018 return; 1019 dev->noisecalc.channel_at_start = dev->phy.channel; 1020 dev->noisecalc.calculation_running = 1; 1021 dev->noisecalc.nr_samples = 0; 1022 1023 b43_generate_noise_sample(dev); 1024} 1025 1026static void handle_irq_noise(struct b43_wldev *dev) 1027{ 1028 struct b43_phy *phy = &dev->phy; 1029 u16 tmp; 1030 u8 noise[4]; 1031 u8 i, j; 1032 s32 average; 1033 1034 /* Bottom half of Link Quality calculation. */ 1035 1036 B43_WARN_ON(!dev->noisecalc.calculation_running); 1037 if (dev->noisecalc.channel_at_start != phy->channel) 1038 goto drop_calculation; 1039 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1040 if (noise[0] == 0x7F || noise[1] == 0x7F || 1041 noise[2] == 0x7F || noise[3] == 0x7F) 1042 goto generate_new; 1043 1044 /* Get the noise samples. */ 1045 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1046 i = dev->noisecalc.nr_samples; 1047 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1048 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1049 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1050 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1051 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1052 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1053 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1054 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1055 dev->noisecalc.nr_samples++; 1056 if (dev->noisecalc.nr_samples == 8) { 1057 /* Calculate the Link Quality by the noise samples. */ 1058 average = 0; 1059 for (i = 0; i < 8; i++) { 1060 for (j = 0; j < 4; j++) 1061 average += dev->noisecalc.samples[i][j]; 1062 } 1063 average /= (8 * 4); 1064 average *= 125; 1065 average += 64; 1066 average /= 128; 1067 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1068 tmp = (tmp / 128) & 0x1F; 1069 if (tmp >= 8) 1070 average += 2; 1071 else 1072 average -= 25; 1073 if (tmp == 8) 1074 average -= 72; 1075 else 1076 average -= 48; 1077 1078 dev->stats.link_noise = average; 1079 drop_calculation: 1080 dev->noisecalc.calculation_running = 0; 1081 return; 1082 } 1083 generate_new: 1084 b43_generate_noise_sample(dev); 1085} 1086 1087static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1088{ 1089 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) { 1090 ///TODO: PS TBTT 1091 } else { 1092 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1093 b43_power_saving_ctl_bits(dev, 0); 1094 } 1095 dev->reg124_set_0x4 = 0; 1096 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) 1097 dev->reg124_set_0x4 = 1; 1098} 1099 1100static void handle_irq_atim_end(struct b43_wldev *dev) 1101{ 1102 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ ) 1103 return; 1104 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, 1105 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD) 1106 | 0x4); 1107} 1108 1109static void handle_irq_pmq(struct b43_wldev *dev) 1110{ 1111 u32 tmp; 1112 1113 //TODO: AP mode. 1114 1115 while (1) { 1116 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1117 if (!(tmp & 0x00000008)) 1118 break; 1119 } 1120 /* 16bit write is odd, but correct. */ 1121 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1122} 1123 1124static void b43_write_template_common(struct b43_wldev *dev, 1125 const u8 * data, u16 size, 1126 u16 ram_offset, 1127 u16 shm_size_offset, u8 rate) 1128{ 1129 u32 i, tmp; 1130 struct b43_plcp_hdr4 plcp; 1131 1132 plcp.data = 0; 1133 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1134 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1135 ram_offset += sizeof(u32); 1136 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1137 * So leave the first two bytes of the next write blank. 1138 */ 1139 tmp = (u32) (data[0]) << 16; 1140 tmp |= (u32) (data[1]) << 24; 1141 b43_ram_write(dev, ram_offset, tmp); 1142 ram_offset += sizeof(u32); 1143 for (i = 2; i < size; i += sizeof(u32)) { 1144 tmp = (u32) (data[i + 0]); 1145 if (i + 1 < size) 1146 tmp |= (u32) (data[i + 1]) << 8; 1147 if (i + 2 < size) 1148 tmp |= (u32) (data[i + 2]) << 16; 1149 if (i + 3 < size) 1150 tmp |= (u32) (data[i + 3]) << 24; 1151 b43_ram_write(dev, ram_offset + i - 2, tmp); 1152 } 1153 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1154 size + sizeof(struct b43_plcp_hdr6)); 1155} 1156 1157static void b43_write_beacon_template(struct b43_wldev *dev, 1158 u16 ram_offset, 1159 u16 shm_size_offset, u8 rate) 1160{ 1161 int len; 1162 const u8 *data; 1163 1164 B43_WARN_ON(!dev->cached_beacon); 1165 len = min((size_t) dev->cached_beacon->len, 1166 0x200 - sizeof(struct b43_plcp_hdr6)); 1167 data = (const u8 *)(dev->cached_beacon->data); 1168 b43_write_template_common(dev, data, 1169 len, ram_offset, shm_size_offset, rate); 1170} 1171 1172static void b43_write_probe_resp_plcp(struct b43_wldev *dev, 1173 u16 shm_offset, u16 size, u8 rate) 1174{ 1175 struct b43_plcp_hdr4 plcp; 1176 u32 tmp; 1177 __le16 dur; 1178 1179 plcp.data = 0; 1180 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1181 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1182 dev->wl->if_id, size, 1183 B43_RATE_TO_BASE100KBPS(rate)); 1184 /* Write PLCP in two parts and timing for packet transfer */ 1185 tmp = le32_to_cpu(plcp.data); 1186 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF); 1187 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16); 1188 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur)); 1189} 1190 1191/* Instead of using custom probe response template, this function 1192 * just patches custom beacon template by: 1193 * 1) Changing packet type 1194 * 2) Patching duration field 1195 * 3) Stripping TIM 1196 */ 1197static u8 *b43_generate_probe_resp(struct b43_wldev *dev, 1198 u16 * dest_size, u8 rate) 1199{ 1200 const u8 *src_data; 1201 u8 *dest_data; 1202 u16 src_size, elem_size, src_pos, dest_pos; 1203 __le16 dur; 1204 struct ieee80211_hdr *hdr; 1205 1206 B43_WARN_ON(!dev->cached_beacon); 1207 src_size = dev->cached_beacon->len; 1208 src_data = (const u8 *)dev->cached_beacon->data; 1209 1210 if (unlikely(src_size < 0x24)) { 1211 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n"); 1212 return NULL; 1213 } 1214 1215 dest_data = kmalloc(src_size, GFP_ATOMIC); 1216 if (unlikely(!dest_data)) 1217 return NULL; 1218 1219 /* 0x24 is offset of first variable-len Information-Element 1220 * in beacon frame. 1221 */ 1222 memcpy(dest_data, src_data, 0x24); 1223 src_pos = dest_pos = 0x24; 1224 for (; src_pos < src_size - 2; src_pos += elem_size) { 1225 elem_size = src_data[src_pos + 1] + 2; 1226 if (src_data[src_pos] != 0x05) { /* TIM */ 1227 memcpy(dest_data + dest_pos, src_data + src_pos, 1228 elem_size); 1229 dest_pos += elem_size; 1230 } 1231 } 1232 *dest_size = dest_pos; 1233 hdr = (struct ieee80211_hdr *)dest_data; 1234 1235 /* Set the frame control. */ 1236 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | 1237 IEEE80211_STYPE_PROBE_RESP); 1238 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1239 dev->wl->if_id, *dest_size, 1240 B43_RATE_TO_BASE100KBPS(rate)); 1241 hdr->duration_id = dur; 1242 1243 return dest_data; 1244} 1245 1246static void b43_write_probe_resp_template(struct b43_wldev *dev, 1247 u16 ram_offset, 1248 u16 shm_size_offset, u8 rate) 1249{ 1250 u8 *probe_resp_data; 1251 u16 size; 1252 1253 B43_WARN_ON(!dev->cached_beacon); 1254 size = dev->cached_beacon->len; 1255 probe_resp_data = b43_generate_probe_resp(dev, &size, rate); 1256 if (unlikely(!probe_resp_data)) 1257 return; 1258 1259 /* Looks like PLCP headers plus packet timings are stored for 1260 * all possible basic rates 1261 */ 1262 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB); 1263 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB); 1264 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB); 1265 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB); 1266 1267 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6)); 1268 b43_write_template_common(dev, probe_resp_data, 1269 size, ram_offset, shm_size_offset, rate); 1270 kfree(probe_resp_data); 1271} 1272 1273static int b43_refresh_cached_beacon(struct b43_wldev *dev, 1274 struct sk_buff *beacon) 1275{ 1276 if (dev->cached_beacon) 1277 kfree_skb(dev->cached_beacon); 1278 dev->cached_beacon = beacon; 1279 1280 return 0; 1281} 1282 1283static void b43_update_templates(struct b43_wldev *dev) 1284{ 1285 u32 status; 1286 1287 B43_WARN_ON(!dev->cached_beacon); 1288 1289 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB); 1290 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB); 1291 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB); 1292 1293 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD); 1294 status |= 0x03; 1295 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1296} 1297 1298static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon) 1299{ 1300 int err; 1301 1302 err = b43_refresh_cached_beacon(dev, beacon); 1303 if (unlikely(err)) 1304 return; 1305 b43_update_templates(dev); 1306} 1307 1308static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len) 1309{ 1310 u32 tmp; 1311 u16 i, len; 1312 1313 len = min((u16) ssid_len, (u16) 0x100); 1314 for (i = 0; i < len; i += sizeof(u32)) { 1315 tmp = (u32) (ssid[i + 0]); 1316 if (i + 1 < len) 1317 tmp |= (u32) (ssid[i + 1]) << 8; 1318 if (i + 2 < len) 1319 tmp |= (u32) (ssid[i + 2]) << 16; 1320 if (i + 3 < len) 1321 tmp |= (u32) (ssid[i + 3]) << 24; 1322 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp); 1323 } 1324 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len); 1325} 1326 1327static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1328{ 1329 b43_time_lock(dev); 1330 if (dev->dev->id.revision >= 3) { 1331 b43_write32(dev, 0x188, (beacon_int << 16)); 1332 } else { 1333 b43_write16(dev, 0x606, (beacon_int >> 6)); 1334 b43_write16(dev, 0x610, beacon_int); 1335 } 1336 b43_time_unlock(dev); 1337} 1338 1339static void handle_irq_beacon(struct b43_wldev *dev) 1340{ 1341 u32 status; 1342 1343 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) 1344 return; 1345 1346 dev->irq_savedstate &= ~B43_IRQ_BEACON; 1347 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD); 1348 1349 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) { 1350 /* ACK beacon IRQ. */ 1351 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1352 dev->irq_savedstate |= B43_IRQ_BEACON; 1353 if (dev->cached_beacon) 1354 kfree_skb(dev->cached_beacon); 1355 dev->cached_beacon = NULL; 1356 return; 1357 } 1358 if (!(status & 0x1)) { 1359 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB); 1360 status |= 0x1; 1361 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1362 } 1363 if (!(status & 0x2)) { 1364 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB); 1365 status |= 0x2; 1366 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status); 1367 } 1368} 1369 1370static void handle_irq_ucode_debug(struct b43_wldev *dev) 1371{ 1372 //TODO 1373} 1374 1375/* Interrupt handler bottom-half */ 1376static void b43_interrupt_tasklet(struct b43_wldev *dev) 1377{ 1378 u32 reason; 1379 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1380 u32 merged_dma_reason = 0; 1381 int i; 1382 unsigned long flags; 1383 1384 spin_lock_irqsave(&dev->wl->irq_lock, flags); 1385 1386 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED); 1387 1388 reason = dev->irq_reason; 1389 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1390 dma_reason[i] = dev->dma_reason[i]; 1391 merged_dma_reason |= dma_reason[i]; 1392 } 1393 1394 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1395 b43err(dev->wl, "MAC transmission error\n"); 1396 1397 if (unlikely(reason & B43_IRQ_PHY_TXERR)) 1398 b43err(dev->wl, "PHY transmission error\n"); 1399 1400 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1401 B43_DMAIRQ_NONFATALMASK))) { 1402 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1403 b43err(dev->wl, "Fatal DMA error: " 1404 "0x%08X, 0x%08X, 0x%08X, " 1405 "0x%08X, 0x%08X, 0x%08X\n", 1406 dma_reason[0], dma_reason[1], 1407 dma_reason[2], dma_reason[3], 1408 dma_reason[4], dma_reason[5]); 1409 b43_controller_restart(dev, "DMA error"); 1410 mmiowb(); 1411 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1412 return; 1413 } 1414 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1415 b43err(dev->wl, "DMA error: " 1416 "0x%08X, 0x%08X, 0x%08X, " 1417 "0x%08X, 0x%08X, 0x%08X\n", 1418 dma_reason[0], dma_reason[1], 1419 dma_reason[2], dma_reason[3], 1420 dma_reason[4], dma_reason[5]); 1421 } 1422 } 1423 1424 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1425 handle_irq_ucode_debug(dev); 1426 if (reason & B43_IRQ_TBTT_INDI) 1427 handle_irq_tbtt_indication(dev); 1428 if (reason & B43_IRQ_ATIM_END) 1429 handle_irq_atim_end(dev); 1430 if (reason & B43_IRQ_BEACON) 1431 handle_irq_beacon(dev); 1432 if (reason & B43_IRQ_PMQ) 1433 handle_irq_pmq(dev); 1434 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1435 ;/* TODO */ 1436 if (reason & B43_IRQ_NOISESAMPLE_OK) 1437 handle_irq_noise(dev); 1438 1439 /* Check the DMA reason registers for received data. */ 1440 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 1441 if (b43_using_pio(dev)) 1442 b43_pio_rx(dev->pio.queue0); 1443 else 1444 b43_dma_rx(dev->dma.rx_ring0); 1445 } 1446 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1447 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1448 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) { 1449 if (b43_using_pio(dev)) 1450 b43_pio_rx(dev->pio.queue3); 1451 else 1452 b43_dma_rx(dev->dma.rx_ring3); 1453 } 1454 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1455 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1456 1457 if (reason & B43_IRQ_TX_OK) 1458 handle_irq_transmit_status(dev); 1459 1460 b43_interrupt_enable(dev, dev->irq_savedstate); 1461 mmiowb(); 1462 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1463} 1464 1465static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx) 1466{ 1467 u16 rxctl; 1468 1469 rxctl = b43_read16(dev, base + B43_PIO_RXCTL); 1470 if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE) 1471 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE; 1472 else 1473 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE; 1474} 1475 1476static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason) 1477{ 1478 if (b43_using_pio(dev) && 1479 (dev->dev->id.revision < 3) && 1480 (!(reason & B43_IRQ_PIO_WORKAROUND))) { 1481 /* Apply a PIO specific workaround to the dma_reasons */ 1482 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0); 1483 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1); 1484 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2); 1485 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3); 1486 } 1487 1488 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1489 1490 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1491 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1492 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1493 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1494 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1495 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1496} 1497 1498/* Interrupt handler top-half */ 1499static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1500{ 1501 irqreturn_t ret = IRQ_NONE; 1502 struct b43_wldev *dev = dev_id; 1503 u32 reason; 1504 1505 if (!dev) 1506 return IRQ_NONE; 1507 1508 spin_lock(&dev->wl->irq_lock); 1509 1510 if (b43_status(dev) < B43_STAT_STARTED) 1511 goto out; 1512 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1513 if (reason == 0xffffffff) /* shared IRQ */ 1514 goto out; 1515 ret = IRQ_HANDLED; 1516 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 1517 if (!reason) 1518 goto out; 1519 1520 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1521 & 0x0001DC00; 1522 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1523 & 0x0000DC00; 1524 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1525 & 0x0000DC00; 1526 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1527 & 0x0001DC00; 1528 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1529 & 0x0000DC00; 1530 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1531 & 0x0000DC00; 1532 1533 b43_interrupt_ack(dev, reason); 1534 /* disable all IRQs. They are enabled again in the bottom half. */ 1535 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 1536 /* save the reason code and call our bottom half. */ 1537 dev->irq_reason = reason; 1538 tasklet_schedule(&dev->isr_tasklet); 1539 out: 1540 mmiowb(); 1541 spin_unlock(&dev->wl->irq_lock); 1542 1543 return ret; 1544} 1545 1546static void b43_release_firmware(struct b43_wldev *dev) 1547{ 1548 release_firmware(dev->fw.ucode); 1549 dev->fw.ucode = NULL; 1550 release_firmware(dev->fw.pcm); 1551 dev->fw.pcm = NULL; 1552 release_firmware(dev->fw.initvals); 1553 dev->fw.initvals = NULL; 1554 release_firmware(dev->fw.initvals_band); 1555 dev->fw.initvals_band = NULL; 1556} 1557 1558static void b43_print_fw_helptext(struct b43_wl *wl) 1559{ 1560 b43err(wl, "You must go to " 1561 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware " 1562 "and download the correct firmware (version 4).\n"); 1563} 1564 1565static int do_request_fw(struct b43_wldev *dev, 1566 const char *name, 1567 const struct firmware **fw) 1568{ 1569 char path[sizeof(modparam_fwpostfix) + 32]; 1570 struct b43_fw_header *hdr; 1571 u32 size; 1572 int err; 1573 1574 if (!name) 1575 return 0; 1576 1577 snprintf(path, ARRAY_SIZE(path), 1578 "b43%s/%s.fw", 1579 modparam_fwpostfix, name); 1580 err = request_firmware(fw, path, dev->dev->dev); 1581 if (err) { 1582 b43err(dev->wl, "Firmware file \"%s\" not found " 1583 "or load failed.\n", path); 1584 return err; 1585 } 1586 if ((*fw)->size < sizeof(struct b43_fw_header)) 1587 goto err_format; 1588 hdr = (struct b43_fw_header *)((*fw)->data); 1589 switch (hdr->type) { 1590 case B43_FW_TYPE_UCODE: 1591 case B43_FW_TYPE_PCM: 1592 size = be32_to_cpu(hdr->size); 1593 if (size != (*fw)->size - sizeof(struct b43_fw_header)) 1594 goto err_format; 1595 /* fallthrough */ 1596 case B43_FW_TYPE_IV: 1597 if (hdr->ver != 1) 1598 goto err_format; 1599 break; 1600 default: 1601 goto err_format; 1602 } 1603 1604 return err; 1605 1606err_format: 1607 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path); 1608 return -EPROTO; 1609} 1610 1611static int b43_request_firmware(struct b43_wldev *dev) 1612{ 1613 struct b43_firmware *fw = &dev->fw; 1614 const u8 rev = dev->dev->id.revision; 1615 const char *filename; 1616 u32 tmshigh; 1617 int err; 1618 1619 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 1620 if (!fw->ucode) { 1621 if ((rev >= 5) && (rev <= 10)) 1622 filename = "ucode5"; 1623 else if ((rev >= 11) && (rev <= 12)) 1624 filename = "ucode11"; 1625 else if (rev >= 13) 1626 filename = "ucode13"; 1627 else 1628 goto err_no_ucode; 1629 err = do_request_fw(dev, filename, &fw->ucode); 1630 if (err) 1631 goto err_load; 1632 } 1633 if (!fw->pcm) { 1634 if ((rev >= 5) && (rev <= 10)) 1635 filename = "pcm5"; 1636 else if (rev >= 11) 1637 filename = NULL; 1638 else 1639 goto err_no_pcm; 1640 err = do_request_fw(dev, filename, &fw->pcm); 1641 if (err) 1642 goto err_load; 1643 } 1644 if (!fw->initvals) { 1645 switch (dev->phy.type) { 1646 case B43_PHYTYPE_A: 1647 if ((rev >= 5) && (rev <= 10)) { 1648 if (tmshigh & B43_TMSHIGH_GPHY) 1649 filename = "a0g1initvals5"; 1650 else 1651 filename = "a0g0initvals5"; 1652 } else 1653 goto err_no_initvals; 1654 break; 1655 case B43_PHYTYPE_G: 1656 if ((rev >= 5) && (rev <= 10)) 1657 filename = "b0g0initvals5"; 1658 else if (rev >= 13) 1659 filename = "lp0initvals13"; 1660 else 1661 goto err_no_initvals; 1662 break; 1663 default: 1664 goto err_no_initvals; 1665 } 1666 err = do_request_fw(dev, filename, &fw->initvals); 1667 if (err) 1668 goto err_load; 1669 } 1670 if (!fw->initvals_band) { 1671 switch (dev->phy.type) { 1672 case B43_PHYTYPE_A: 1673 if ((rev >= 5) && (rev <= 10)) { 1674 if (tmshigh & B43_TMSHIGH_GPHY) 1675 filename = "a0g1bsinitvals5"; 1676 else 1677 filename = "a0g0bsinitvals5"; 1678 } else if (rev >= 11) 1679 filename = NULL; 1680 else 1681 goto err_no_initvals; 1682 break; 1683 case B43_PHYTYPE_G: 1684 if ((rev >= 5) && (rev <= 10)) 1685 filename = "b0g0bsinitvals5"; 1686 else if (rev >= 11) 1687 filename = NULL; 1688 else 1689 goto err_no_initvals; 1690 break; 1691 default: 1692 goto err_no_initvals; 1693 } 1694 err = do_request_fw(dev, filename, &fw->initvals_band); 1695 if (err) 1696 goto err_load; 1697 } 1698 1699 return 0; 1700 1701err_load: 1702 b43_print_fw_helptext(dev->wl); 1703 goto error; 1704 1705err_no_ucode: 1706 err = -ENODEV; 1707 b43err(dev->wl, "No microcode available for core rev %u\n", rev); 1708 goto error; 1709 1710err_no_pcm: 1711 err = -ENODEV; 1712 b43err(dev->wl, "No PCM available for core rev %u\n", rev); 1713 goto error; 1714 1715err_no_initvals: 1716 err = -ENODEV; 1717 b43err(dev->wl, "No Initial Values firmware file for PHY %u, " 1718 "core rev %u\n", dev->phy.type, rev); 1719 goto error; 1720 1721error: 1722 b43_release_firmware(dev); 1723 return err; 1724} 1725 1726static int b43_upload_microcode(struct b43_wldev *dev) 1727{ 1728 const size_t hdr_len = sizeof(struct b43_fw_header); 1729 const __be32 *data; 1730 unsigned int i, len; 1731 u16 fwrev, fwpatch, fwdate, fwtime; 1732 u32 tmp; 1733 int err = 0; 1734 1735 /* Upload Microcode. */ 1736 data = (__be32 *) (dev->fw.ucode->data + hdr_len); 1737 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32); 1738 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 1739 for (i = 0; i < len; i++) { 1740 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1741 udelay(10); 1742 } 1743 1744 if (dev->fw.pcm) { 1745 /* Upload PCM data. */ 1746 data = (__be32 *) (dev->fw.pcm->data + hdr_len); 1747 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32); 1748 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 1749 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 1750 /* No need for autoinc bit in SHM_HW */ 1751 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 1752 for (i = 0; i < len; i++) { 1753 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1754 udelay(10); 1755 } 1756 } 1757 1758 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 1759 b43_write32(dev, B43_MMIO_MACCTL, 1760 B43_MACCTL_PSM_RUN | 1761 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA); 1762 1763 /* Wait for the microcode to load and respond */ 1764 i = 0; 1765 while (1) { 1766 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1767 if (tmp == B43_IRQ_MAC_SUSPENDED) 1768 break; 1769 i++; 1770 if (i >= 50) { 1771 b43err(dev->wl, "Microcode not responding\n"); 1772 b43_print_fw_helptext(dev->wl); 1773 err = -ENODEV; 1774 goto out; 1775 } 1776 udelay(10); 1777 } 1778 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 1779 1780 /* Get and check the revisions. */ 1781 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 1782 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 1783 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 1784 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 1785 1786 if (fwrev <= 0x128) { 1787 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 1788 "binary drivers older than version 4.x is unsupported. " 1789 "You must upgrade your firmware files.\n"); 1790 b43_print_fw_helptext(dev->wl); 1791 b43_write32(dev, B43_MMIO_MACCTL, 0); 1792 err = -EOPNOTSUPP; 1793 goto out; 1794 } 1795 b43dbg(dev->wl, "Loading firmware version %u.%u " 1796 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 1797 fwrev, fwpatch, 1798 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 1799 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 1800 1801 dev->fw.rev = fwrev; 1802 dev->fw.patch = fwpatch; 1803 1804 out: 1805 return err; 1806} 1807 1808static int b43_write_initvals(struct b43_wldev *dev, 1809 const struct b43_iv *ivals, 1810 size_t count, 1811 size_t array_size) 1812{ 1813 const struct b43_iv *iv; 1814 u16 offset; 1815 size_t i; 1816 bool bit32; 1817 1818 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 1819 iv = ivals; 1820 for (i = 0; i < count; i++) { 1821 if (array_size < sizeof(iv->offset_size)) 1822 goto err_format; 1823 array_size -= sizeof(iv->offset_size); 1824 offset = be16_to_cpu(iv->offset_size); 1825 bit32 = !!(offset & B43_IV_32BIT); 1826 offset &= B43_IV_OFFSET_MASK; 1827 if (offset >= 0x1000) 1828 goto err_format; 1829 if (bit32) { 1830 u32 value; 1831 1832 if (array_size < sizeof(iv->data.d32)) 1833 goto err_format; 1834 array_size -= sizeof(iv->data.d32); 1835 1836 value = be32_to_cpu(get_unaligned(&iv->data.d32)); 1837 b43_write32(dev, offset, value); 1838 1839 iv = (const struct b43_iv *)((const uint8_t *)iv + 1840 sizeof(__be16) + 1841 sizeof(__be32)); 1842 } else { 1843 u16 value; 1844 1845 if (array_size < sizeof(iv->data.d16)) 1846 goto err_format; 1847 array_size -= sizeof(iv->data.d16); 1848 1849 value = be16_to_cpu(iv->data.d16); 1850 b43_write16(dev, offset, value); 1851 1852 iv = (const struct b43_iv *)((const uint8_t *)iv + 1853 sizeof(__be16) + 1854 sizeof(__be16)); 1855 } 1856 } 1857 if (array_size) 1858 goto err_format; 1859 1860 return 0; 1861 1862err_format: 1863 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 1864 b43_print_fw_helptext(dev->wl); 1865 1866 return -EPROTO; 1867} 1868 1869static int b43_upload_initvals(struct b43_wldev *dev) 1870{ 1871 const size_t hdr_len = sizeof(struct b43_fw_header); 1872 const struct b43_fw_header *hdr; 1873 struct b43_firmware *fw = &dev->fw; 1874 const struct b43_iv *ivals; 1875 size_t count; 1876 int err; 1877 1878 hdr = (const struct b43_fw_header *)(fw->initvals->data); 1879 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len); 1880 count = be32_to_cpu(hdr->size); 1881 err = b43_write_initvals(dev, ivals, count, 1882 fw->initvals->size - hdr_len); 1883 if (err) 1884 goto out; 1885 if (fw->initvals_band) { 1886 hdr = (const struct b43_fw_header *)(fw->initvals_band->data); 1887 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len); 1888 count = be32_to_cpu(hdr->size); 1889 err = b43_write_initvals(dev, ivals, count, 1890 fw->initvals_band->size - hdr_len); 1891 if (err) 1892 goto out; 1893 } 1894out: 1895 1896 return err; 1897} 1898 1899/* Initialize the GPIOs 1900 * http://bcm-specs.sipsolutions.net/GPIO 1901 */ 1902static int b43_gpio_init(struct b43_wldev *dev) 1903{ 1904 struct ssb_bus *bus = dev->dev->bus; 1905 struct ssb_device *gpiodev, *pcidev = NULL; 1906 u32 mask, set; 1907 1908 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 1909 & ~B43_MACCTL_GPOUTSMSK); 1910 1911 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 1912 | 0x000F); 1913 1914 mask = 0x0000001F; 1915 set = 0x0000000F; 1916 if (dev->dev->bus->chip_id == 0x4301) { 1917 mask |= 0x0060; 1918 set |= 0x0060; 1919 } 1920 if (0 /* FIXME: conditional unknown */ ) { 1921 b43_write16(dev, B43_MMIO_GPIO_MASK, 1922 b43_read16(dev, B43_MMIO_GPIO_MASK) 1923 | 0x0100); 1924 mask |= 0x0180; 1925 set |= 0x0180; 1926 } 1927 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) { 1928 b43_write16(dev, B43_MMIO_GPIO_MASK, 1929 b43_read16(dev, B43_MMIO_GPIO_MASK) 1930 | 0x0200); 1931 mask |= 0x0200; 1932 set |= 0x0200; 1933 } 1934 if (dev->dev->id.revision >= 2) 1935 mask |= 0x0010; /* FIXME: This is redundant. */ 1936 1937#ifdef CONFIG_SSB_DRIVER_PCICORE 1938 pcidev = bus->pcicore.dev; 1939#endif 1940 gpiodev = bus->chipco.dev ? : pcidev; 1941 if (!gpiodev) 1942 return 0; 1943 ssb_write32(gpiodev, B43_GPIO_CONTROL, 1944 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 1945 & mask) | set); 1946 1947 return 0; 1948} 1949 1950/* Turn off all GPIO stuff. Call this on module unload, for example. */ 1951static void b43_gpio_cleanup(struct b43_wldev *dev) 1952{ 1953 struct ssb_bus *bus = dev->dev->bus; 1954 struct ssb_device *gpiodev, *pcidev = NULL; 1955 1956#ifdef CONFIG_SSB_DRIVER_PCICORE 1957 pcidev = bus->pcicore.dev; 1958#endif 1959 gpiodev = bus->chipco.dev ? : pcidev; 1960 if (!gpiodev) 1961 return; 1962 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 1963} 1964 1965/* http://bcm-specs.sipsolutions.net/EnableMac */ 1966void b43_mac_enable(struct b43_wldev *dev) 1967{ 1968 dev->mac_suspended--; 1969 B43_WARN_ON(dev->mac_suspended < 0); 1970 B43_WARN_ON(irqs_disabled()); 1971 if (dev->mac_suspended == 0) { 1972 b43_write32(dev, B43_MMIO_MACCTL, 1973 b43_read32(dev, B43_MMIO_MACCTL) 1974 | B43_MACCTL_ENABLED); 1975 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 1976 B43_IRQ_MAC_SUSPENDED); 1977 /* Commit writes */ 1978 b43_read32(dev, B43_MMIO_MACCTL); 1979 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1980 b43_power_saving_ctl_bits(dev, 0); 1981 1982 /* Re-enable IRQs. */ 1983 spin_lock_irq(&dev->wl->irq_lock); 1984 b43_interrupt_enable(dev, dev->irq_savedstate); 1985 spin_unlock_irq(&dev->wl->irq_lock); 1986 } 1987} 1988 1989/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 1990void b43_mac_suspend(struct b43_wldev *dev) 1991{ 1992 int i; 1993 u32 tmp; 1994 1995 might_sleep(); 1996 B43_WARN_ON(irqs_disabled()); 1997 B43_WARN_ON(dev->mac_suspended < 0); 1998 1999 if (dev->mac_suspended == 0) { 2000 /* Mask IRQs before suspending MAC. Otherwise 2001 * the MAC stays busy and won't suspend. */ 2002 spin_lock_irq(&dev->wl->irq_lock); 2003 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL); 2004 spin_unlock_irq(&dev->wl->irq_lock); 2005 b43_synchronize_irq(dev); 2006 dev->irq_savedstate = tmp; 2007 2008 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2009 b43_write32(dev, B43_MMIO_MACCTL, 2010 b43_read32(dev, B43_MMIO_MACCTL) 2011 & ~B43_MACCTL_ENABLED); 2012 /* force pci to flush the write */ 2013 b43_read32(dev, B43_MMIO_MACCTL); 2014 for (i = 40; i; i--) { 2015 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2016 if (tmp & B43_IRQ_MAC_SUSPENDED) 2017 goto out; 2018 msleep(1); 2019 } 2020 b43err(dev->wl, "MAC suspend failed\n"); 2021 } 2022out: 2023 dev->mac_suspended++; 2024} 2025 2026static void b43_adjust_opmode(struct b43_wldev *dev) 2027{ 2028 struct b43_wl *wl = dev->wl; 2029 u32 ctl; 2030 u16 cfp_pretbtt; 2031 2032 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2033 /* Reset status to STA infrastructure mode. */ 2034 ctl &= ~B43_MACCTL_AP; 2035 ctl &= ~B43_MACCTL_KEEP_CTL; 2036 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2037 ctl &= ~B43_MACCTL_KEEP_BAD; 2038 ctl &= ~B43_MACCTL_PROMISC; 2039 ctl &= ~B43_MACCTL_BEACPROMISC; 2040 ctl |= B43_MACCTL_INFRA; 2041 2042 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2043 ctl |= B43_MACCTL_AP; 2044 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) 2045 ctl &= ~B43_MACCTL_INFRA; 2046 2047 if (wl->filter_flags & FIF_CONTROL) 2048 ctl |= B43_MACCTL_KEEP_CTL; 2049 if (wl->filter_flags & FIF_FCSFAIL) 2050 ctl |= B43_MACCTL_KEEP_BAD; 2051 if (wl->filter_flags & FIF_PLCPFAIL) 2052 ctl |= B43_MACCTL_KEEP_BADPLCP; 2053 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2054 ctl |= B43_MACCTL_PROMISC; 2055 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2056 ctl |= B43_MACCTL_BEACPROMISC; 2057 2058 /* Workaround: On old hardware the HW-MAC-address-filter 2059 * doesn't work properly, so always run promisc in filter 2060 * it in software. */ 2061 if (dev->dev->id.revision <= 4) 2062 ctl |= B43_MACCTL_PROMISC; 2063 2064 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2065 2066 cfp_pretbtt = 2; 2067 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2068 if (dev->dev->bus->chip_id == 0x4306 && 2069 dev->dev->bus->chip_rev == 3) 2070 cfp_pretbtt = 100; 2071 else 2072 cfp_pretbtt = 50; 2073 } 2074 b43_write16(dev, 0x612, cfp_pretbtt); 2075} 2076 2077static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2078{ 2079 u16 offset; 2080 2081 if (is_ofdm) { 2082 offset = 0x480; 2083 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2084 } else { 2085 offset = 0x4C0; 2086 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2087 } 2088 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2089 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2090} 2091 2092static void b43_rate_memory_init(struct b43_wldev *dev) 2093{ 2094 switch (dev->phy.type) { 2095 case B43_PHYTYPE_A: 2096 case B43_PHYTYPE_G: 2097 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2098 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2099 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2100 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2101 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2102 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2103 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2104 if (dev->phy.type == B43_PHYTYPE_A) 2105 break; 2106 /* fallthrough */ 2107 case B43_PHYTYPE_B: 2108 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2109 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2110 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2111 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2112 break; 2113 default: 2114 B43_WARN_ON(1); 2115 } 2116} 2117 2118/* Set the TX-Antenna for management frames sent by firmware. */ 2119static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2120{ 2121 u16 ant = 0; 2122 u16 tmp; 2123 2124 switch (antenna) { 2125 case B43_ANTENNA0: 2126 ant |= B43_TX4_PHY_ANT0; 2127 break; 2128 case B43_ANTENNA1: 2129 ant |= B43_TX4_PHY_ANT1; 2130 break; 2131 case B43_ANTENNA_AUTO: 2132 ant |= B43_TX4_PHY_ANTLAST; 2133 break; 2134 default: 2135 B43_WARN_ON(1); 2136 } 2137 2138 /* FIXME We also need to set the other flags of the PHY control field somewhere. */ 2139 2140 /* For Beacons */ 2141 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 2142 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2143 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp); 2144 /* For ACK/CTS */ 2145 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2146 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2147 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2148 /* For Probe Resposes */ 2149 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2150 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2151 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2152} 2153 2154/* This is the opposite of b43_chip_init() */ 2155static void b43_chip_exit(struct b43_wldev *dev) 2156{ 2157 b43_radio_turn_off(dev, 1); 2158 b43_gpio_cleanup(dev); 2159 /* firmware is released later */ 2160} 2161 2162/* Initialize the chip 2163 * http://bcm-specs.sipsolutions.net/ChipInit 2164 */ 2165static int b43_chip_init(struct b43_wldev *dev) 2166{ 2167 struct b43_phy *phy = &dev->phy; 2168 int err, tmp; 2169 u32 value32; 2170 u16 value16; 2171 2172 b43_write32(dev, B43_MMIO_MACCTL, 2173 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED); 2174 2175 err = b43_request_firmware(dev); 2176 if (err) 2177 goto out; 2178 err = b43_upload_microcode(dev); 2179 if (err) 2180 goto out; /* firmware is released later */ 2181 2182 err = b43_gpio_init(dev); 2183 if (err) 2184 goto out; /* firmware is released later */ 2185 2186 err = b43_upload_initvals(dev); 2187 if (err) 2188 goto err_gpio_clean; 2189 b43_radio_turn_on(dev); 2190 2191 b43_write16(dev, 0x03E6, 0x0000); 2192 err = b43_phy_init(dev); 2193 if (err) 2194 goto err_radio_off; 2195 2196 /* Select initial Interference Mitigation. */ 2197 tmp = phy->interfmode; 2198 phy->interfmode = B43_INTERFMODE_NONE; 2199 b43_radio_set_interference_mitigation(dev, tmp); 2200 2201 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2202 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2203 2204 if (phy->type == B43_PHYTYPE_B) { 2205 value16 = b43_read16(dev, 0x005E); 2206 value16 |= 0x0004; 2207 b43_write16(dev, 0x005E, value16); 2208 } 2209 b43_write32(dev, 0x0100, 0x01000000); 2210 if (dev->dev->id.revision < 5) 2211 b43_write32(dev, 0x010C, 0x01000000); 2212 2213 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2214 & ~B43_MACCTL_INFRA); 2215 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2216 | B43_MACCTL_INFRA); 2217 2218 if (b43_using_pio(dev)) { 2219 b43_write32(dev, 0x0210, 0x00000100); 2220 b43_write32(dev, 0x0230, 0x00000100); 2221 b43_write32(dev, 0x0250, 0x00000100); 2222 b43_write32(dev, 0x0270, 0x00000100); 2223 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000); 2224 } 2225 2226 /* Probe Response Timeout value */ 2227 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2228 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2229 2230 /* Initially set the wireless operation mode. */ 2231 b43_adjust_opmode(dev); 2232 2233 if (dev->dev->id.revision < 3) { 2234 b43_write16(dev, 0x060E, 0x0000); 2235 b43_write16(dev, 0x0610, 0x8000); 2236 b43_write16(dev, 0x0604, 0x0000); 2237 b43_write16(dev, 0x0606, 0x0200); 2238 } else { 2239 b43_write32(dev, 0x0188, 0x80000000); 2240 b43_write32(dev, 0x018C, 0x02000000); 2241 } 2242 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2243 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2244 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2245 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2246 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2247 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2248 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2249 2250 value32 = ssb_read32(dev->dev, SSB_TMSLOW); 2251 value32 |= 0x00100000; 2252 ssb_write32(dev->dev, SSB_TMSLOW, value32); 2253 2254 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2255 dev->dev->bus->chipco.fast_pwrup_delay); 2256 2257 err = 0; 2258 b43dbg(dev->wl, "Chip initialized\n"); 2259out: 2260 return err; 2261 2262err_radio_off: 2263 b43_radio_turn_off(dev, 1); 2264err_gpio_clean: 2265 b43_gpio_cleanup(dev); 2266 return err; 2267} 2268 2269static void b43_periodic_every120sec(struct b43_wldev *dev) 2270{ 2271 struct b43_phy *phy = &dev->phy; 2272 2273 if (phy->type != B43_PHYTYPE_G || phy->rev < 2) 2274 return; 2275 2276 b43_mac_suspend(dev); 2277 b43_lo_g_measure(dev); 2278 b43_mac_enable(dev); 2279 if (b43_has_hardware_pctl(phy)) 2280 b43_lo_g_ctl_mark_all_unused(dev); 2281} 2282 2283static void b43_periodic_every60sec(struct b43_wldev *dev) 2284{ 2285 struct b43_phy *phy = &dev->phy; 2286 2287 if (!b43_has_hardware_pctl(phy)) 2288 b43_lo_g_ctl_mark_all_unused(dev); 2289 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) { 2290 b43_mac_suspend(dev); 2291 b43_calc_nrssi_slope(dev); 2292 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { 2293 u8 old_chan = phy->channel; 2294 2295 /* VCO Calibration */ 2296 if (old_chan >= 8) 2297 b43_radio_selectchannel(dev, 1, 0); 2298 else 2299 b43_radio_selectchannel(dev, 13, 0); 2300 b43_radio_selectchannel(dev, old_chan, 0); 2301 } 2302 b43_mac_enable(dev); 2303 } 2304} 2305 2306static void b43_periodic_every30sec(struct b43_wldev *dev) 2307{ 2308 /* Update device statistics. */ 2309 b43_calculate_link_quality(dev); 2310} 2311 2312static void b43_periodic_every15sec(struct b43_wldev *dev) 2313{ 2314 struct b43_phy *phy = &dev->phy; 2315 2316 if (phy->type == B43_PHYTYPE_G) { 2317 //TODO: update_aci_moving_average 2318 if (phy->aci_enable && phy->aci_wlan_automatic) { 2319 b43_mac_suspend(dev); 2320 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) { 2321 if (0 /*TODO: bunch of conditions */ ) { 2322 b43_radio_set_interference_mitigation 2323 (dev, B43_INTERFMODE_MANUALWLAN); 2324 } 2325 } else if (1 /*TODO*/) { 2326 /* 2327 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) { 2328 b43_radio_set_interference_mitigation(dev, 2329 B43_INTERFMODE_NONE); 2330 } 2331 */ 2332 } 2333 b43_mac_enable(dev); 2334 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN && 2335 phy->rev == 1) { 2336 //TODO: implement rev1 workaround 2337 } 2338 } 2339 b43_phy_xmitpower(dev); //FIXME: unless scanning? 2340 //TODO for APHY (temperature?) 2341} 2342 2343static void do_periodic_work(struct b43_wldev *dev) 2344{ 2345 unsigned int state; 2346 2347 state = dev->periodic_state; 2348 if (state % 8 == 0) 2349 b43_periodic_every120sec(dev); 2350 if (state % 4 == 0) 2351 b43_periodic_every60sec(dev); 2352 if (state % 2 == 0) 2353 b43_periodic_every30sec(dev); 2354 b43_periodic_every15sec(dev); 2355} 2356 2357/* Periodic work locking policy: 2358 * The whole periodic work handler is protected by 2359 * wl->mutex. If another lock is needed somewhere in the 2360 * pwork callchain, it's aquired in-place, where it's needed. 2361 */ 2362static void b43_periodic_work_handler(struct work_struct *work) 2363{ 2364 struct b43_wldev *dev = container_of(work, struct b43_wldev, 2365 periodic_work.work); 2366 struct b43_wl *wl = dev->wl; 2367 unsigned long delay; 2368 2369 mutex_lock(&wl->mutex); 2370 2371 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 2372 goto out; 2373 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 2374 goto out_requeue; 2375 2376 do_periodic_work(dev); 2377 2378 dev->periodic_state++; 2379out_requeue: 2380 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 2381 delay = msecs_to_jiffies(50); 2382 else 2383 delay = round_jiffies_relative(HZ * 15); 2384 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay); 2385out: 2386 mutex_unlock(&wl->mutex); 2387} 2388 2389static void b43_periodic_tasks_setup(struct b43_wldev *dev) 2390{ 2391 struct delayed_work *work = &dev->periodic_work; 2392 2393 dev->periodic_state = 0; 2394 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 2395 queue_delayed_work(dev->wl->hw->workqueue, work, 0); 2396} 2397 2398/* Validate access to the chip (SHM) */ 2399static int b43_validate_chipaccess(struct b43_wldev *dev) 2400{ 2401 u32 value; 2402 u32 shm_backup; 2403 2404 shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0); 2405 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 2406 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 2407 goto error; 2408 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 2409 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 2410 goto error; 2411 b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup); 2412 2413 value = b43_read32(dev, B43_MMIO_MACCTL); 2414 if ((value | B43_MACCTL_GMODE) != 2415 (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 2416 goto error; 2417 2418 value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2419 if (value) 2420 goto error; 2421 2422 return 0; 2423 error: 2424 b43err(dev->wl, "Failed to validate the chipaccess\n"); 2425 return -ENODEV; 2426} 2427 2428static void b43_security_init(struct b43_wldev *dev) 2429{ 2430 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20; 2431 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key)); 2432 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 2433 /* KTP is a word address, but we address SHM bytewise. 2434 * So multiply by two. 2435 */ 2436 dev->ktp *= 2; 2437 if (dev->dev->id.revision >= 5) { 2438 /* Number of RCMTA address slots */ 2439 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8); 2440 } 2441 b43_clear_keys(dev); 2442} 2443 2444static int b43_rng_read(struct hwrng *rng, u32 * data) 2445{ 2446 struct b43_wl *wl = (struct b43_wl *)rng->priv; 2447 unsigned long flags; 2448 2449 /* Don't take wl->mutex here, as it could deadlock with 2450 * hwrng internal locking. It's not needed to take 2451 * wl->mutex here, anyway. */ 2452 2453 spin_lock_irqsave(&wl->irq_lock, flags); 2454 *data = b43_read16(wl->current_dev, B43_MMIO_RNG); 2455 spin_unlock_irqrestore(&wl->irq_lock, flags); 2456 2457 return (sizeof(u16)); 2458} 2459 2460static void b43_rng_exit(struct b43_wl *wl) 2461{ 2462 if (wl->rng_initialized) 2463 hwrng_unregister(&wl->rng); 2464} 2465 2466static int b43_rng_init(struct b43_wl *wl) 2467{ 2468 int err; 2469 2470 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 2471 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 2472 wl->rng.name = wl->rng_name; 2473 wl->rng.data_read = b43_rng_read; 2474 wl->rng.priv = (unsigned long)wl; 2475 wl->rng_initialized = 1; 2476 err = hwrng_register(&wl->rng); 2477 if (err) { 2478 wl->rng_initialized = 0; 2479 b43err(wl, "Failed to register the random " 2480 "number generator (%d)\n", err); 2481 } 2482 2483 return err; 2484} 2485 2486static int b43_tx(struct ieee80211_hw *hw, 2487 struct sk_buff *skb, struct ieee80211_tx_control *ctl) 2488{ 2489 struct b43_wl *wl = hw_to_b43_wl(hw); 2490 struct b43_wldev *dev = wl->current_dev; 2491 int err = -ENODEV; 2492 unsigned long flags; 2493 2494 if (unlikely(!dev)) 2495 goto out; 2496 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2497 goto out; 2498 /* DMA-TX is done without a global lock. */ 2499 if (b43_using_pio(dev)) { 2500 spin_lock_irqsave(&wl->irq_lock, flags); 2501 err = b43_pio_tx(dev, skb, ctl); 2502 spin_unlock_irqrestore(&wl->irq_lock, flags); 2503 } else 2504 err = b43_dma_tx(dev, skb, ctl); 2505 out: 2506 if (unlikely(err)) 2507 return NETDEV_TX_BUSY; 2508 return NETDEV_TX_OK; 2509} 2510 2511static int b43_conf_tx(struct ieee80211_hw *hw, 2512 int queue, 2513 const struct ieee80211_tx_queue_params *params) 2514{ 2515 return 0; 2516} 2517 2518static int b43_get_tx_stats(struct ieee80211_hw *hw, 2519 struct ieee80211_tx_queue_stats *stats) 2520{ 2521 struct b43_wl *wl = hw_to_b43_wl(hw); 2522 struct b43_wldev *dev = wl->current_dev; 2523 unsigned long flags; 2524 int err = -ENODEV; 2525 2526 if (!dev) 2527 goto out; 2528 spin_lock_irqsave(&wl->irq_lock, flags); 2529 if (likely(b43_status(dev) >= B43_STAT_STARTED)) { 2530 if (b43_using_pio(dev)) 2531 b43_pio_get_tx_stats(dev, stats); 2532 else 2533 b43_dma_get_tx_stats(dev, stats); 2534 err = 0; 2535 } 2536 spin_unlock_irqrestore(&wl->irq_lock, flags); 2537 out: 2538 return err; 2539} 2540 2541static int b43_get_stats(struct ieee80211_hw *hw, 2542 struct ieee80211_low_level_stats *stats) 2543{ 2544 struct b43_wl *wl = hw_to_b43_wl(hw); 2545 unsigned long flags; 2546 2547 spin_lock_irqsave(&wl->irq_lock, flags); 2548 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 2549 spin_unlock_irqrestore(&wl->irq_lock, flags); 2550 2551 return 0; 2552} 2553 2554static const char *phymode_to_string(unsigned int phymode) 2555{ 2556 switch (phymode) { 2557 case B43_PHYMODE_A: 2558 return "A"; 2559 case B43_PHYMODE_B: 2560 return "B"; 2561 case B43_PHYMODE_G: 2562 return "G"; 2563 default: 2564 B43_WARN_ON(1); 2565 } 2566 return ""; 2567} 2568 2569static int find_wldev_for_phymode(struct b43_wl *wl, 2570 unsigned int phymode, 2571 struct b43_wldev **dev, bool * gmode) 2572{ 2573 struct b43_wldev *d; 2574 2575 list_for_each_entry(d, &wl->devlist, list) { 2576 if (d->phy.possible_phymodes & phymode) { 2577 /* Ok, this device supports the PHY-mode. 2578 * Now figure out how the gmode bit has to be 2579 * set to support it. */ 2580 if (phymode == B43_PHYMODE_A) 2581 *gmode = 0; 2582 else 2583 *gmode = 1; 2584 *dev = d; 2585 2586 return 0; 2587 } 2588 } 2589 2590 return -ESRCH; 2591} 2592 2593static void b43_put_phy_into_reset(struct b43_wldev *dev) 2594{ 2595 struct ssb_device *sdev = dev->dev; 2596 u32 tmslow; 2597 2598 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2599 tmslow &= ~B43_TMSLOW_GMODE; 2600 tmslow |= B43_TMSLOW_PHYRESET; 2601 tmslow |= SSB_TMSLOW_FGC; 2602 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2603 msleep(1); 2604 2605 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2606 tmslow &= ~SSB_TMSLOW_FGC; 2607 tmslow |= B43_TMSLOW_PHYRESET; 2608 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2609 msleep(1); 2610} 2611 2612/* Expects wl->mutex locked */ 2613static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode) 2614{ 2615 struct b43_wldev *up_dev; 2616 struct b43_wldev *down_dev; 2617 int err; 2618 bool gmode = 0; 2619 int prev_status; 2620 2621 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode); 2622 if (err) { 2623 b43err(wl, "Could not find a device for %s-PHY mode\n", 2624 phymode_to_string(new_mode)); 2625 return err; 2626 } 2627 if ((up_dev == wl->current_dev) && 2628 (!!wl->current_dev->phy.gmode == !!gmode)) { 2629 /* This device is already running. */ 2630 return 0; 2631 } 2632 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n", 2633 phymode_to_string(new_mode)); 2634 down_dev = wl->current_dev; 2635 2636 prev_status = b43_status(down_dev); 2637 /* Shutdown the currently running core. */ 2638 if (prev_status >= B43_STAT_STARTED) 2639 b43_wireless_core_stop(down_dev); 2640 if (prev_status >= B43_STAT_INITIALIZED) 2641 b43_wireless_core_exit(down_dev); 2642 2643 if (down_dev != up_dev) { 2644 /* We switch to a different core, so we put PHY into 2645 * RESET on the old core. */ 2646 b43_put_phy_into_reset(down_dev); 2647 } 2648 2649 /* Now start the new core. */ 2650 up_dev->phy.gmode = gmode; 2651 if (prev_status >= B43_STAT_INITIALIZED) { 2652 err = b43_wireless_core_init(up_dev); 2653 if (err) { 2654 b43err(wl, "Fatal: Could not initialize device for " 2655 "newly selected %s-PHY mode\n", 2656 phymode_to_string(new_mode)); 2657 goto init_failure; 2658 } 2659 } 2660 if (prev_status >= B43_STAT_STARTED) { 2661 err = b43_wireless_core_start(up_dev); 2662 if (err) { 2663 b43err(wl, "Fatal: Coult not start device for " 2664 "newly selected %s-PHY mode\n", 2665 phymode_to_string(new_mode)); 2666 b43_wireless_core_exit(up_dev); 2667 goto init_failure; 2668 } 2669 } 2670 B43_WARN_ON(b43_status(up_dev) != prev_status); 2671 2672 wl->current_dev = up_dev; 2673 2674 return 0; 2675 init_failure: 2676 /* Whoops, failed to init the new core. No core is operating now. */ 2677 wl->current_dev = NULL; 2678 return err; 2679} 2680 2681static int b43_antenna_from_ieee80211(u8 antenna) 2682{ 2683 switch (antenna) { 2684 case 0: /* default/diversity */ 2685 return B43_ANTENNA_DEFAULT; 2686 case 1: /* Antenna 0 */ 2687 return B43_ANTENNA0; 2688 case 2: /* Antenna 1 */ 2689 return B43_ANTENNA1; 2690 default: 2691 return B43_ANTENNA_DEFAULT; 2692 } 2693} 2694 2695static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) 2696{ 2697 struct b43_wl *wl = hw_to_b43_wl(hw); 2698 struct b43_wldev *dev; 2699 struct b43_phy *phy; 2700 unsigned long flags; 2701 unsigned int new_phymode = 0xFFFF; 2702 int antenna_tx; 2703 int antenna_rx; 2704 int err = 0; 2705 u32 savedirqs; 2706 2707 antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx); 2708 antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx); 2709 2710 mutex_lock(&wl->mutex); 2711 2712 /* Switch the PHY mode (if necessary). */ 2713 switch (conf->phymode) { 2714 case MODE_IEEE80211A: 2715 new_phymode = B43_PHYMODE_A; 2716 break; 2717 case MODE_IEEE80211B: 2718 new_phymode = B43_PHYMODE_B; 2719 break; 2720 case MODE_IEEE80211G: 2721 new_phymode = B43_PHYMODE_G; 2722 break; 2723 default: 2724 B43_WARN_ON(1); 2725 } 2726 err = b43_switch_phymode(wl, new_phymode); 2727 if (err) 2728 goto out_unlock_mutex; 2729 dev = wl->current_dev; 2730 phy = &dev->phy; 2731 2732 /* Disable IRQs while reconfiguring the device. 2733 * This makes it possible to drop the spinlock throughout 2734 * the reconfiguration process. */ 2735 spin_lock_irqsave(&wl->irq_lock, flags); 2736 if (b43_status(dev) < B43_STAT_STARTED) { 2737 spin_unlock_irqrestore(&wl->irq_lock, flags); 2738 goto out_unlock_mutex; 2739 } 2740 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL); 2741 spin_unlock_irqrestore(&wl->irq_lock, flags); 2742 b43_synchronize_irq(dev); 2743 2744 /* Switch to the requested channel. 2745 * The firmware takes care of races with the TX handler. */ 2746 if (conf->channel_val != phy->channel) 2747 b43_radio_selectchannel(dev, conf->channel_val, 0); 2748 2749 /* Enable/Disable ShortSlot timing. */ 2750 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != 2751 dev->short_slot) { 2752 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2753 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) 2754 b43_short_slot_timing_enable(dev); 2755 else 2756 b43_short_slot_timing_disable(dev); 2757 } 2758 2759 /* Adjust the desired TX power level. */ 2760 if (conf->power_level != 0) { 2761 if (conf->power_level != phy->power_level) { 2762 phy->power_level = conf->power_level; 2763 b43_phy_xmitpower(dev); 2764 } 2765 } 2766 2767 /* Antennas for RX and management frame TX. */ 2768 b43_mgmtframe_txantenna(dev, antenna_tx); 2769 b43_set_rx_antenna(dev, antenna_rx); 2770 2771 /* Update templates for AP mode. */ 2772 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2773 b43_set_beacon_int(dev, conf->beacon_int); 2774 2775 if (!!conf->radio_enabled != phy->radio_on) { 2776 if (conf->radio_enabled) { 2777 b43_radio_turn_on(dev); 2778 b43info(dev->wl, "Radio turned on by software\n"); 2779 if (!dev->radio_hw_enable) { 2780 b43info(dev->wl, "The hardware RF-kill button " 2781 "still turns the radio physically off. " 2782 "Press the button to turn it on.\n"); 2783 } 2784 } else { 2785 b43_radio_turn_off(dev, 0); 2786 b43info(dev->wl, "Radio turned off by software\n"); 2787 } 2788 } 2789 2790 spin_lock_irqsave(&wl->irq_lock, flags); 2791 b43_interrupt_enable(dev, savedirqs); 2792 mmiowb(); 2793 spin_unlock_irqrestore(&wl->irq_lock, flags); 2794 out_unlock_mutex: 2795 mutex_unlock(&wl->mutex); 2796 2797 return err; 2798} 2799 2800static int b43_dev_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 2801 const u8 *local_addr, const u8 *addr, 2802 struct ieee80211_key_conf *key) 2803{ 2804 struct b43_wl *wl = hw_to_b43_wl(hw); 2805 struct b43_wldev *dev; 2806 unsigned long flags; 2807 u8 algorithm; 2808 u8 index; 2809 int err; 2810 DECLARE_MAC_BUF(mac); 2811 2812 if (modparam_nohwcrypt) 2813 return -ENOSPC; /* User disabled HW-crypto */ 2814 2815 mutex_lock(&wl->mutex); 2816 spin_lock_irqsave(&wl->irq_lock, flags); 2817 2818 dev = wl->current_dev; 2819 err = -ENODEV; 2820 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 2821 goto out_unlock; 2822 2823 err = -EINVAL; 2824 switch (key->alg) { 2825 case ALG_WEP: 2826 if (key->keylen == 5) 2827 algorithm = B43_SEC_ALGO_WEP40; 2828 else 2829 algorithm = B43_SEC_ALGO_WEP104; 2830 break; 2831 case ALG_TKIP: 2832 algorithm = B43_SEC_ALGO_TKIP; 2833 break; 2834 case ALG_CCMP: 2835 algorithm = B43_SEC_ALGO_AES; 2836 break; 2837 default: 2838 B43_WARN_ON(1); 2839 goto out_unlock; 2840 } 2841 index = (u8) (key->keyidx); 2842 if (index > 3) 2843 goto out_unlock; 2844 2845 switch (cmd) { 2846 case SET_KEY: 2847 if (algorithm == B43_SEC_ALGO_TKIP) { 2848 /* FIXME: No TKIP hardware encryption for now. */ 2849 err = -EOPNOTSUPP; 2850 goto out_unlock; 2851 } 2852 2853 if (is_broadcast_ether_addr(addr)) { 2854 /* addr is FF:FF:FF:FF:FF:FF for default keys */ 2855 err = b43_key_write(dev, index, algorithm, 2856 key->key, key->keylen, NULL, key); 2857 } else { 2858 /* 2859 * either pairwise key or address is 00:00:00:00:00:00 2860 * for transmit-only keys 2861 */ 2862 err = b43_key_write(dev, -1, algorithm, 2863 key->key, key->keylen, addr, key); 2864 } 2865 if (err) 2866 goto out_unlock; 2867 2868 if (algorithm == B43_SEC_ALGO_WEP40 || 2869 algorithm == B43_SEC_ALGO_WEP104) { 2870 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 2871 } else { 2872 b43_hf_write(dev, 2873 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 2874 } 2875 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 2876 break; 2877 case DISABLE_KEY: { 2878 err = b43_key_clear(dev, key->hw_key_idx); 2879 if (err) 2880 goto out_unlock; 2881 break; 2882 } 2883 default: 2884 B43_WARN_ON(1); 2885 } 2886out_unlock: 2887 spin_unlock_irqrestore(&wl->irq_lock, flags); 2888 mutex_unlock(&wl->mutex); 2889out: 2890 if (!err) { 2891 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 2892 "mac: %s\n", 2893 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 2894 print_mac(mac, addr)); 2895 } 2896 return err; 2897} 2898 2899static void b43_configure_filter(struct ieee80211_hw *hw, 2900 unsigned int changed, unsigned int *fflags, 2901 int mc_count, struct dev_addr_list *mc_list) 2902{ 2903 struct b43_wl *wl = hw_to_b43_wl(hw); 2904 struct b43_wldev *dev = wl->current_dev; 2905 unsigned long flags; 2906 2907 if (!dev) { 2908 *fflags = 0; 2909 return; 2910 } 2911 2912 spin_lock_irqsave(&wl->irq_lock, flags); 2913 *fflags &= FIF_PROMISC_IN_BSS | 2914 FIF_ALLMULTI | 2915 FIF_FCSFAIL | 2916 FIF_PLCPFAIL | 2917 FIF_CONTROL | 2918 FIF_OTHER_BSS | 2919 FIF_BCN_PRBRESP_PROMISC; 2920 2921 changed &= FIF_PROMISC_IN_BSS | 2922 FIF_ALLMULTI | 2923 FIF_FCSFAIL | 2924 FIF_PLCPFAIL | 2925 FIF_CONTROL | 2926 FIF_OTHER_BSS | 2927 FIF_BCN_PRBRESP_PROMISC; 2928 2929 wl->filter_flags = *fflags; 2930 2931 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 2932 b43_adjust_opmode(dev); 2933 spin_unlock_irqrestore(&wl->irq_lock, flags); 2934} 2935 2936static int b43_config_interface(struct ieee80211_hw *hw, 2937 int if_id, struct ieee80211_if_conf *conf) 2938{ 2939 struct b43_wl *wl = hw_to_b43_wl(hw); 2940 struct b43_wldev *dev = wl->current_dev; 2941 unsigned long flags; 2942 2943 if (!dev) 2944 return -ENODEV; 2945 mutex_lock(&wl->mutex); 2946 spin_lock_irqsave(&wl->irq_lock, flags); 2947 B43_WARN_ON(wl->if_id != if_id); 2948 if (conf->bssid) 2949 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 2950 else 2951 memset(wl->bssid, 0, ETH_ALEN); 2952 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 2953 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) { 2954 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); 2955 b43_set_ssid(dev, conf->ssid, conf->ssid_len); 2956 if (conf->beacon) 2957 b43_refresh_templates(dev, conf->beacon); 2958 } 2959 b43_write_mac_bssid_templates(dev); 2960 } 2961 spin_unlock_irqrestore(&wl->irq_lock, flags); 2962 mutex_unlock(&wl->mutex); 2963 2964 return 0; 2965} 2966 2967/* Locking: wl->mutex */ 2968static void b43_wireless_core_stop(struct b43_wldev *dev) 2969{ 2970 struct b43_wl *wl = dev->wl; 2971 unsigned long flags; 2972 2973 if (b43_status(dev) < B43_STAT_STARTED) 2974 return; 2975 2976 /* Disable and sync interrupts. We must do this before than 2977 * setting the status to INITIALIZED, as the interrupt handler 2978 * won't care about IRQs then. */ 2979 spin_lock_irqsave(&wl->irq_lock, flags); 2980 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 2981 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */ 2982 spin_unlock_irqrestore(&wl->irq_lock, flags); 2983 b43_synchronize_irq(dev); 2984 2985 b43_set_status(dev, B43_STAT_INITIALIZED); 2986 2987 mutex_unlock(&wl->mutex); 2988 /* Must unlock as it would otherwise deadlock. No races here. 2989 * Cancel the possibly running self-rearming periodic work. */ 2990 cancel_delayed_work_sync(&dev->periodic_work); 2991 mutex_lock(&wl->mutex); 2992 2993 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy. 2994 2995 b43_mac_suspend(dev); 2996 free_irq(dev->dev->irq, dev); 2997 b43dbg(wl, "Wireless interface stopped\n"); 2998} 2999 3000/* Locking: wl->mutex */ 3001static int b43_wireless_core_start(struct b43_wldev *dev) 3002{ 3003 int err; 3004 3005 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 3006 3007 drain_txstatus_queue(dev); 3008 err = request_irq(dev->dev->irq, b43_interrupt_handler, 3009 IRQF_SHARED, KBUILD_MODNAME, dev); 3010 if (err) { 3011 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); 3012 goto out; 3013 } 3014 3015 /* We are ready to run. */ 3016 b43_set_status(dev, B43_STAT_STARTED); 3017 3018 /* Start data flow (TX/RX). */ 3019 b43_mac_enable(dev); 3020 b43_interrupt_enable(dev, dev->irq_savedstate); 3021 ieee80211_start_queues(dev->wl->hw); 3022 3023 /* Start maintainance work */ 3024 b43_periodic_tasks_setup(dev); 3025 3026 b43dbg(dev->wl, "Wireless interface started\n"); 3027 out: 3028 return err; 3029} 3030 3031/* Get PHY and RADIO versioning numbers */ 3032static int b43_phy_versioning(struct b43_wldev *dev) 3033{ 3034 struct b43_phy *phy = &dev->phy; 3035 u32 tmp; 3036 u8 analog_type; 3037 u8 phy_type; 3038 u8 phy_rev; 3039 u16 radio_manuf; 3040 u16 radio_ver; 3041 u16 radio_rev; 3042 int unsupported = 0; 3043 3044 /* Get PHY versioning */ 3045 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 3046 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 3047 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 3048 phy_rev = (tmp & B43_PHYVER_VERSION); 3049 switch (phy_type) { 3050 case B43_PHYTYPE_A: 3051 if (phy_rev >= 4) 3052 unsupported = 1; 3053 break; 3054 case B43_PHYTYPE_B: 3055 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 3056 && phy_rev != 7) 3057 unsupported = 1; 3058 break; 3059 case B43_PHYTYPE_G: 3060 if (phy_rev > 8) 3061 unsupported = 1; 3062 break; 3063 default: 3064 unsupported = 1; 3065 }; 3066 if (unsupported) { 3067 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 3068 "(Analog %u, Type %u, Revision %u)\n", 3069 analog_type, phy_type, phy_rev); 3070 return -EOPNOTSUPP; 3071 } 3072 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 3073 analog_type, phy_type, phy_rev); 3074 3075 /* Get RADIO versioning */ 3076 if (dev->dev->bus->chip_id == 0x4317) { 3077 if (dev->dev->bus->chip_rev == 0) 3078 tmp = 0x3205017F; 3079 else if (dev->dev->bus->chip_rev == 1) 3080 tmp = 0x4205017F; 3081 else 3082 tmp = 0x5205017F; 3083 } else { 3084 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3085 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH); 3086 tmp <<= 16; 3087 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3088 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3089 } 3090 radio_manuf = (tmp & 0x00000FFF); 3091 radio_ver = (tmp & 0x0FFFF000) >> 12; 3092 radio_rev = (tmp & 0xF0000000) >> 28; 3093 switch (phy_type) { 3094 case B43_PHYTYPE_A: 3095 if (radio_ver != 0x2060) 3096 unsupported = 1; 3097 if (radio_rev != 1) 3098 unsupported = 1; 3099 if (radio_manuf != 0x17F) 3100 unsupported = 1; 3101 break; 3102 case B43_PHYTYPE_B: 3103 if ((radio_ver & 0xFFF0) != 0x2050) 3104 unsupported = 1; 3105 break; 3106 case B43_PHYTYPE_G: 3107 if (radio_ver != 0x2050) 3108 unsupported = 1; 3109 break; 3110 default: 3111 B43_WARN_ON(1); 3112 } 3113 if (unsupported) { 3114 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 3115 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 3116 radio_manuf, radio_ver, radio_rev); 3117 return -EOPNOTSUPP; 3118 } 3119 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 3120 radio_manuf, radio_ver, radio_rev); 3121 3122 phy->radio_manuf = radio_manuf; 3123 phy->radio_ver = radio_ver; 3124 phy->radio_rev = radio_rev; 3125 3126 phy->analog = analog_type; 3127 phy->type = phy_type; 3128 phy->rev = phy_rev; 3129 3130 return 0; 3131} 3132 3133static void setup_struct_phy_for_init(struct b43_wldev *dev, 3134 struct b43_phy *phy) 3135{ 3136 struct b43_txpower_lo_control *lo; 3137 int i; 3138 3139 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); 3140 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); 3141 3142 /* Flags */ 3143 phy->locked = 0; 3144 3145 phy->aci_enable = 0; 3146 phy->aci_wlan_automatic = 0; 3147 phy->aci_hw_rssi = 0; 3148 3149 phy->radio_off_context.valid = 0; 3150 3151 lo = phy->lo_control; 3152 if (lo) { 3153 memset(lo, 0, sizeof(*(phy->lo_control))); 3154 lo->rebuild = 1; 3155 lo->tx_bias = 0xFF; 3156 } 3157 phy->max_lb_gain = 0; 3158 phy->trsw_rx_gain = 0; 3159 phy->txpwr_offset = 0; 3160 3161 /* NRSSI */ 3162 phy->nrssislope = 0; 3163 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) 3164 phy->nrssi[i] = -1000; 3165 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) 3166 phy->nrssi_lt[i] = i; 3167 3168 phy->lofcal = 0xFFFF; 3169 phy->initval = 0xFFFF; 3170 3171 spin_lock_init(&phy->lock); 3172 phy->interfmode = B43_INTERFMODE_NONE; 3173 phy->channel = 0xFF; 3174 3175 phy->hardware_power_control = !!modparam_hwpctl; 3176} 3177 3178static void setup_struct_wldev_for_init(struct b43_wldev *dev) 3179{ 3180 /* Flags */ 3181 dev->reg124_set_0x4 = 0; 3182 /* Assume the radio is enabled. If it's not enabled, the state will 3183 * immediately get fixed on the first periodic work run. */ 3184 dev->radio_hw_enable = 1; 3185 3186 /* Stats */ 3187 memset(&dev->stats, 0, sizeof(dev->stats)); 3188 3189 setup_struct_phy_for_init(dev, &dev->phy); 3190 3191 /* IRQ related flags */ 3192 dev->irq_reason = 0; 3193 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 3194 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE; 3195 3196 dev->mac_suspended = 1; 3197 3198 /* Noise calculation context */ 3199 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 3200} 3201 3202static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 3203{ 3204 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 3205 u32 hf; 3206 3207 if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST)) 3208 return; 3209 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 3210 return; 3211 3212 hf = b43_hf_read(dev); 3213 if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD) 3214 hf |= B43_HF_BTCOEXALT; 3215 else 3216 hf |= B43_HF_BTCOEX; 3217 b43_hf_write(dev, hf); 3218 //TODO 3219} 3220 3221static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 3222{ //TODO 3223} 3224 3225static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 3226{ 3227#ifdef CONFIG_SSB_DRIVER_PCICORE 3228 struct ssb_bus *bus = dev->dev->bus; 3229 u32 tmp; 3230 3231 if (bus->pcicore.dev && 3232 bus->pcicore.dev->id.coreid == SSB_DEV_PCI && 3233 bus->pcicore.dev->id.revision <= 5) { 3234 /* IMCFGLO timeouts workaround. */ 3235 tmp = ssb_read32(dev->dev, SSB_IMCFGLO); 3236 tmp &= ~SSB_IMCFGLO_REQTO; 3237 tmp &= ~SSB_IMCFGLO_SERTO; 3238 switch (bus->bustype) { 3239 case SSB_BUSTYPE_PCI: 3240 case SSB_BUSTYPE_PCMCIA: 3241 tmp |= 0x32; 3242 break; 3243 case SSB_BUSTYPE_SSB: 3244 tmp |= 0x53; 3245 break; 3246 } 3247 ssb_write32(dev->dev, SSB_IMCFGLO, tmp); 3248 } 3249#endif /* CONFIG_SSB_DRIVER_PCICORE */ 3250} 3251 3252/* Write the short and long frame retry limit values. */ 3253static void b43_set_retry_limits(struct b43_wldev *dev, 3254 unsigned int short_retry, 3255 unsigned int long_retry) 3256{ 3257 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3258 * the chip-internal counter. */ 3259 short_retry = min(short_retry, (unsigned int)0xF); 3260 long_retry = min(long_retry, (unsigned int)0xF); 3261 3262 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3263 short_retry); 3264 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3265 long_retry); 3266} 3267 3268/* Shutdown a wireless core */ 3269/* Locking: wl->mutex */ 3270static void b43_wireless_core_exit(struct b43_wldev *dev) 3271{ 3272 struct b43_phy *phy = &dev->phy; 3273 3274 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED); 3275 if (b43_status(dev) != B43_STAT_INITIALIZED) 3276 return; 3277 b43_set_status(dev, B43_STAT_UNINIT); 3278 3279 b43_leds_exit(dev); 3280 b43_rng_exit(dev->wl); 3281 b43_pio_free(dev); 3282 b43_dma_free(dev); 3283 b43_chip_exit(dev); 3284 b43_radio_turn_off(dev, 1); 3285 b43_switch_analog(dev, 0); 3286 if (phy->dyn_tssi_tbl) 3287 kfree(phy->tssi2dbm); 3288 kfree(phy->lo_control); 3289 phy->lo_control = NULL; 3290 ssb_device_disable(dev->dev, 0); 3291 ssb_bus_may_powerdown(dev->dev->bus); 3292} 3293 3294/* Initialize a wireless core */ 3295static int b43_wireless_core_init(struct b43_wldev *dev) 3296{ 3297 struct b43_wl *wl = dev->wl; 3298 struct ssb_bus *bus = dev->dev->bus; 3299 struct ssb_sprom *sprom = &bus->sprom; 3300 struct b43_phy *phy = &dev->phy; 3301 int err; 3302 u32 hf, tmp; 3303 3304 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3305 3306 err = ssb_bus_powerup(bus, 0); 3307 if (err) 3308 goto out; 3309 if (!ssb_device_is_enabled(dev->dev)) { 3310 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 3311 b43_wireless_core_reset(dev, tmp); 3312 } 3313 3314 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) { 3315 phy->lo_control = 3316 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL); 3317 if (!phy->lo_control) { 3318 err = -ENOMEM; 3319 goto err_busdown; 3320 } 3321 } 3322 setup_struct_wldev_for_init(dev); 3323 3324 err = b43_phy_init_tssi2dbm_table(dev); 3325 if (err) 3326 goto err_kfree_lo_control; 3327 3328 /* Enable IRQ routing to this device. */ 3329 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 3330 3331 b43_imcfglo_timeouts_workaround(dev); 3332 b43_bluetooth_coext_disable(dev); 3333 b43_phy_early_init(dev); 3334 err = b43_chip_init(dev); 3335 if (err) 3336 goto err_kfree_tssitbl; 3337 b43_shm_write16(dev, B43_SHM_SHARED, 3338 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 3339 hf = b43_hf_read(dev); 3340 if (phy->type == B43_PHYTYPE_G) { 3341 hf |= B43_HF_SYMW; 3342 if (phy->rev == 1) 3343 hf |= B43_HF_GDCW; 3344 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL) 3345 hf |= B43_HF_OFDMPABOOST; 3346 } else if (phy->type == B43_PHYTYPE_B) { 3347 hf |= B43_HF_SYMW; 3348 if (phy->rev >= 2 && phy->radio_ver == 0x2050) 3349 hf &= ~B43_HF_GDCW; 3350 } 3351 b43_hf_write(dev, hf); 3352 3353 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 3354 B43_DEFAULT_LONG_RETRY_LIMIT); 3355 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 3356 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 3357 3358 /* Disable sending probe responses from firmware. 3359 * Setting the MaxTime to one usec will always trigger 3360 * a timeout, so we never send any probe resp. 3361 * A timeout of zero is infinite. */ 3362 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 3363 3364 b43_rate_memory_init(dev); 3365 3366 /* Minimum Contention Window */ 3367 if (phy->type == B43_PHYTYPE_B) { 3368 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 3369 } else { 3370 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 3371 } 3372 /* Maximum Contention Window */ 3373 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 3374 3375 do { 3376 if (b43_using_pio(dev)) { 3377 err = b43_pio_init(dev); 3378 } else { 3379 err = b43_dma_init(dev); 3380 if (!err) 3381 b43_qos_init(dev); 3382 } 3383 } while (err == -EAGAIN); 3384 if (err) 3385 goto err_chip_exit; 3386 3387//FIXME 3388#if 1 3389 b43_write16(dev, 0x0612, 0x0050); 3390 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050); 3391 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4); 3392#endif 3393 3394 b43_bluetooth_coext_enable(dev); 3395 3396 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */ 3397 memset(wl->bssid, 0, ETH_ALEN); 3398 memset(wl->mac_addr, 0, ETH_ALEN); 3399 b43_upload_card_macaddress(dev); 3400 b43_security_init(dev); 3401 b43_rng_init(wl); 3402 3403 b43_set_status(dev, B43_STAT_INITIALIZED); 3404 3405 b43_leds_init(dev); 3406out: 3407 return err; 3408 3409 err_chip_exit: 3410 b43_chip_exit(dev); 3411 err_kfree_tssitbl: 3412 if (phy->dyn_tssi_tbl) 3413 kfree(phy->tssi2dbm); 3414 err_kfree_lo_control: 3415 kfree(phy->lo_control); 3416 phy->lo_control = NULL; 3417 err_busdown: 3418 ssb_bus_may_powerdown(bus); 3419 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3420 return err; 3421} 3422 3423static int b43_add_interface(struct ieee80211_hw *hw, 3424 struct ieee80211_if_init_conf *conf) 3425{ 3426 struct b43_wl *wl = hw_to_b43_wl(hw); 3427 struct b43_wldev *dev; 3428 unsigned long flags; 3429 int err = -EOPNOTSUPP; 3430 3431 /* TODO: allow WDS/AP devices to coexist */ 3432 3433 if (conf->type != IEEE80211_IF_TYPE_AP && 3434 conf->type != IEEE80211_IF_TYPE_STA && 3435 conf->type != IEEE80211_IF_TYPE_WDS && 3436 conf->type != IEEE80211_IF_TYPE_IBSS) 3437 return -EOPNOTSUPP; 3438 3439 mutex_lock(&wl->mutex); 3440 if (wl->operating) 3441 goto out_mutex_unlock; 3442 3443 b43dbg(wl, "Adding Interface type %d\n", conf->type); 3444 3445 dev = wl->current_dev; 3446 wl->operating = 1; 3447 wl->if_id = conf->if_id; 3448 wl->if_type = conf->type; 3449 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN); 3450 3451 spin_lock_irqsave(&wl->irq_lock, flags); 3452 b43_adjust_opmode(dev); 3453 b43_upload_card_macaddress(dev); 3454 spin_unlock_irqrestore(&wl->irq_lock, flags); 3455 3456 err = 0; 3457 out_mutex_unlock: 3458 mutex_unlock(&wl->mutex); 3459 3460 return err; 3461} 3462 3463static void b43_remove_interface(struct ieee80211_hw *hw, 3464 struct ieee80211_if_init_conf *conf) 3465{ 3466 struct b43_wl *wl = hw_to_b43_wl(hw); 3467 struct b43_wldev *dev = wl->current_dev; 3468 unsigned long flags; 3469 3470 b43dbg(wl, "Removing Interface type %d\n", conf->type); 3471 3472 mutex_lock(&wl->mutex); 3473 3474 B43_WARN_ON(!wl->operating); 3475 B43_WARN_ON(wl->if_id != conf->if_id); 3476 3477 wl->operating = 0; 3478 3479 spin_lock_irqsave(&wl->irq_lock, flags); 3480 b43_adjust_opmode(dev); 3481 memset(wl->mac_addr, 0, ETH_ALEN); 3482 b43_upload_card_macaddress(dev); 3483 spin_unlock_irqrestore(&wl->irq_lock, flags); 3484 3485 mutex_unlock(&wl->mutex); 3486} 3487 3488static int b43_start(struct ieee80211_hw *hw) 3489{ 3490 struct b43_wl *wl = hw_to_b43_wl(hw); 3491 struct b43_wldev *dev = wl->current_dev; 3492 int did_init = 0; 3493 int err = 0; 3494 3495 /* First register RFkill. 3496 * LEDs that are registered later depend on it. */ 3497 b43_rfkill_init(dev); 3498 3499 mutex_lock(&wl->mutex); 3500 3501 if (b43_status(dev) < B43_STAT_INITIALIZED) { 3502 err = b43_wireless_core_init(dev); 3503 if (err) 3504 goto out_mutex_unlock; 3505 did_init = 1; 3506 } 3507 3508 if (b43_status(dev) < B43_STAT_STARTED) { 3509 err = b43_wireless_core_start(dev); 3510 if (err) { 3511 if (did_init) 3512 b43_wireless_core_exit(dev); 3513 goto out_mutex_unlock; 3514 } 3515 } 3516 3517 out_mutex_unlock: 3518 mutex_unlock(&wl->mutex); 3519 3520 return err; 3521} 3522 3523static void b43_stop(struct ieee80211_hw *hw) 3524{ 3525 struct b43_wl *wl = hw_to_b43_wl(hw); 3526 struct b43_wldev *dev = wl->current_dev; 3527 3528 b43_rfkill_exit(dev); 3529 3530 mutex_lock(&wl->mutex); 3531 if (b43_status(dev) >= B43_STAT_STARTED) 3532 b43_wireless_core_stop(dev); 3533 b43_wireless_core_exit(dev); 3534 mutex_unlock(&wl->mutex); 3535} 3536 3537static int b43_op_set_retry_limit(struct ieee80211_hw *hw, 3538 u32 short_retry_limit, u32 long_retry_limit) 3539{ 3540 struct b43_wl *wl = hw_to_b43_wl(hw); 3541 struct b43_wldev *dev; 3542 int err = 0; 3543 3544 mutex_lock(&wl->mutex); 3545 dev = wl->current_dev; 3546 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) { 3547 err = -ENODEV; 3548 goto out_unlock; 3549 } 3550 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit); 3551out_unlock: 3552 mutex_unlock(&wl->mutex); 3553 3554 return err; 3555} 3556 3557static const struct ieee80211_ops b43_hw_ops = { 3558 .tx = b43_tx, 3559 .conf_tx = b43_conf_tx, 3560 .add_interface = b43_add_interface, 3561 .remove_interface = b43_remove_interface, 3562 .config = b43_dev_config, 3563 .config_interface = b43_config_interface, 3564 .configure_filter = b43_configure_filter, 3565 .set_key = b43_dev_set_key, 3566 .get_stats = b43_get_stats, 3567 .get_tx_stats = b43_get_tx_stats, 3568 .start = b43_start, 3569 .stop = b43_stop, 3570 .set_retry_limit = b43_op_set_retry_limit, 3571}; 3572 3573/* Hard-reset the chip. Do not call this directly. 3574 * Use b43_controller_restart() 3575 */ 3576static void b43_chip_reset(struct work_struct *work) 3577{ 3578 struct b43_wldev *dev = 3579 container_of(work, struct b43_wldev, restart_work); 3580 struct b43_wl *wl = dev->wl; 3581 int err = 0; 3582 int prev_status; 3583 3584 mutex_lock(&wl->mutex); 3585 3586 prev_status = b43_status(dev); 3587 /* Bring the device down... */ 3588 if (prev_status >= B43_STAT_STARTED) 3589 b43_wireless_core_stop(dev); 3590 if (prev_status >= B43_STAT_INITIALIZED) 3591 b43_wireless_core_exit(dev); 3592 3593 /* ...and up again. */ 3594 if (prev_status >= B43_STAT_INITIALIZED) { 3595 err = b43_wireless_core_init(dev); 3596 if (err) 3597 goto out; 3598 } 3599 if (prev_status >= B43_STAT_STARTED) { 3600 err = b43_wireless_core_start(dev); 3601 if (err) { 3602 b43_wireless_core_exit(dev); 3603 goto out; 3604 } 3605 } 3606 out: 3607 mutex_unlock(&wl->mutex); 3608 if (err) 3609 b43err(wl, "Controller restart FAILED\n"); 3610 else 3611 b43info(wl, "Controller restarted\n"); 3612} 3613 3614static int b43_setup_modes(struct b43_wldev *dev, 3615 int have_aphy, int have_bphy, int have_gphy) 3616{ 3617 struct ieee80211_hw *hw = dev->wl->hw; 3618 struct ieee80211_hw_mode *mode; 3619 struct b43_phy *phy = &dev->phy; 3620 int cnt = 0; 3621 int err; 3622 3623/*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */ 3624 have_aphy = 0; 3625 3626 phy->possible_phymodes = 0; 3627 for (; 1; cnt++) { 3628 if (have_aphy) { 3629 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3630 mode = &phy->hwmodes[cnt]; 3631 3632 mode->mode = MODE_IEEE80211A; 3633 mode->num_channels = b43_a_chantable_size; 3634 mode->channels = b43_a_chantable; 3635 mode->num_rates = b43_a_ratetable_size; 3636 mode->rates = b43_a_ratetable; 3637 err = ieee80211_register_hwmode(hw, mode); 3638 if (err) 3639 return err; 3640 3641 phy->possible_phymodes |= B43_PHYMODE_A; 3642 have_aphy = 0; 3643 continue; 3644 } 3645 if (have_bphy) { 3646 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3647 mode = &phy->hwmodes[cnt]; 3648 3649 mode->mode = MODE_IEEE80211B; 3650 mode->num_channels = b43_bg_chantable_size; 3651 mode->channels = b43_bg_chantable; 3652 mode->num_rates = b43_b_ratetable_size; 3653 mode->rates = b43_b_ratetable; 3654 err = ieee80211_register_hwmode(hw, mode); 3655 if (err) 3656 return err; 3657 3658 phy->possible_phymodes |= B43_PHYMODE_B; 3659 have_bphy = 0; 3660 continue; 3661 } 3662 if (have_gphy) { 3663 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES); 3664 mode = &phy->hwmodes[cnt]; 3665 3666 mode->mode = MODE_IEEE80211G; 3667 mode->num_channels = b43_bg_chantable_size; 3668 mode->channels = b43_bg_chantable; 3669 mode->num_rates = b43_g_ratetable_size; 3670 mode->rates = b43_g_ratetable; 3671 err = ieee80211_register_hwmode(hw, mode); 3672 if (err) 3673 return err; 3674 3675 phy->possible_phymodes |= B43_PHYMODE_G; 3676 have_gphy = 0; 3677 continue; 3678 } 3679 break; 3680 } 3681 3682 return 0; 3683} 3684 3685static void b43_wireless_core_detach(struct b43_wldev *dev) 3686{ 3687 /* We release firmware that late to not be required to re-request 3688 * is all the time when we reinit the core. */ 3689 b43_release_firmware(dev); 3690} 3691 3692static int b43_wireless_core_attach(struct b43_wldev *dev) 3693{ 3694 struct b43_wl *wl = dev->wl; 3695 struct ssb_bus *bus = dev->dev->bus; 3696 struct pci_dev *pdev = bus->host_pci; 3697 int err; 3698 int have_aphy = 0, have_bphy = 0, have_gphy = 0; 3699 u32 tmp; 3700 3701 /* Do NOT do any device initialization here. 3702 * Do it in wireless_core_init() instead. 3703 * This function is for gathering basic information about the HW, only. 3704 * Also some structs may be set up here. But most likely you want to have 3705 * that in core_init(), too. 3706 */ 3707 3708 err = ssb_bus_powerup(bus, 0); 3709 if (err) { 3710 b43err(wl, "Bus powerup failed\n"); 3711 goto out; 3712 } 3713 /* Get the PHY type. */ 3714 if (dev->dev->id.revision >= 5) { 3715 u32 tmshigh; 3716 3717 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 3718 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY); 3719 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY); 3720 if (!have_aphy && !have_gphy) 3721 have_bphy = 1; 3722 } else if (dev->dev->id.revision == 4) { 3723 have_gphy = 1; 3724 have_aphy = 1; 3725 } else 3726 have_bphy = 1; 3727 3728 dev->phy.gmode = (have_gphy || have_bphy); 3729 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3730 b43_wireless_core_reset(dev, tmp); 3731 3732 err = b43_phy_versioning(dev); 3733 if (err) 3734 goto err_powerdown; 3735 /* Check if this device supports multiband. */ 3736 if (!pdev || 3737 (pdev->device != 0x4312 && 3738 pdev->device != 0x4319 && pdev->device != 0x4324)) { 3739 /* No multiband support. */ 3740 have_aphy = 0; 3741 have_bphy = 0; 3742 have_gphy = 0; 3743 switch (dev->phy.type) { 3744 case B43_PHYTYPE_A: 3745 have_aphy = 1; 3746 break; 3747 case B43_PHYTYPE_B: 3748 have_bphy = 1; 3749 break; 3750 case B43_PHYTYPE_G: 3751 have_gphy = 1; 3752 break; 3753 default: 3754 B43_WARN_ON(1); 3755 } 3756 } 3757 dev->phy.gmode = (have_gphy || have_bphy); 3758 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3759 b43_wireless_core_reset(dev, tmp); 3760 3761 err = b43_validate_chipaccess(dev); 3762 if (err) 3763 goto err_powerdown; 3764 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy); 3765 if (err) 3766 goto err_powerdown; 3767 3768 /* Now set some default "current_dev" */ 3769 if (!wl->current_dev) 3770 wl->current_dev = dev; 3771 INIT_WORK(&dev->restart_work, b43_chip_reset); 3772 3773 b43_radio_turn_off(dev, 1); 3774 b43_switch_analog(dev, 0); 3775 ssb_device_disable(dev->dev, 0); 3776 ssb_bus_may_powerdown(bus); 3777 3778out: 3779 return err; 3780 3781err_powerdown: 3782 ssb_bus_may_powerdown(bus); 3783 return err; 3784} 3785 3786static void b43_one_core_detach(struct ssb_device *dev) 3787{ 3788 struct b43_wldev *wldev; 3789 struct b43_wl *wl; 3790 3791 wldev = ssb_get_drvdata(dev); 3792 wl = wldev->wl; 3793 cancel_work_sync(&wldev->restart_work); 3794 b43_debugfs_remove_device(wldev); 3795 b43_wireless_core_detach(wldev); 3796 list_del(&wldev->list); 3797 wl->nr_devs--; 3798 ssb_set_drvdata(dev, NULL); 3799 kfree(wldev); 3800} 3801 3802static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 3803{ 3804 struct b43_wldev *wldev; 3805 struct pci_dev *pdev; 3806 int err = -ENOMEM; 3807 3808 if (!list_empty(&wl->devlist)) { 3809 /* We are not the first core on this chip. */ 3810 pdev = dev->bus->host_pci; 3811 /* Only special chips support more than one wireless 3812 * core, although some of the other chips have more than 3813 * one wireless core as well. Check for this and 3814 * bail out early. 3815 */ 3816 if (!pdev || 3817 ((pdev->device != 0x4321) && 3818 (pdev->device != 0x4313) && (pdev->device != 0x431A))) { 3819 b43dbg(wl, "Ignoring unconnected 802.11 core\n"); 3820 return -ENODEV; 3821 } 3822 } 3823 3824 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 3825 if (!wldev) 3826 goto out; 3827 3828 wldev->dev = dev; 3829 wldev->wl = wl; 3830 b43_set_status(wldev, B43_STAT_UNINIT); 3831 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 3832 tasklet_init(&wldev->isr_tasklet, 3833 (void (*)(unsigned long))b43_interrupt_tasklet, 3834 (unsigned long)wldev); 3835 if (modparam_pio) 3836 wldev->__using_pio = 1; 3837 INIT_LIST_HEAD(&wldev->list); 3838 3839 err = b43_wireless_core_attach(wldev); 3840 if (err) 3841 goto err_kfree_wldev; 3842 3843 list_add(&wldev->list, &wl->devlist); 3844 wl->nr_devs++; 3845 ssb_set_drvdata(dev, wldev); 3846 b43_debugfs_add_device(wldev); 3847 3848 out: 3849 return err; 3850 3851 err_kfree_wldev: 3852 kfree(wldev); 3853 return err; 3854} 3855 3856static void b43_sprom_fixup(struct ssb_bus *bus) 3857{ 3858 /* boardflags workarounds */ 3859 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 3860 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 3861 bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST; 3862 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3863 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 3864 bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL; 3865 3866 /* Handle case when gain is not set in sprom */ 3867 if (bus->sprom.r1.antenna_gain_a == 0xFF) 3868 bus->sprom.r1.antenna_gain_a = 2; 3869 if (bus->sprom.r1.antenna_gain_bg == 0xFF) 3870 bus->sprom.r1.antenna_gain_bg = 2; 3871 3872 /* Convert Antennagain values to Q5.2 */ 3873 bus->sprom.r1.antenna_gain_a <<= 2; 3874 bus->sprom.r1.antenna_gain_bg <<= 2; 3875} 3876 3877static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 3878{ 3879 struct ieee80211_hw *hw = wl->hw; 3880 3881 ssb_set_devtypedata(dev, NULL); 3882 ieee80211_free_hw(hw); 3883} 3884 3885static int b43_wireless_init(struct ssb_device *dev) 3886{ 3887 struct ssb_sprom *sprom = &dev->bus->sprom; 3888 struct ieee80211_hw *hw; 3889 struct b43_wl *wl; 3890 int err = -ENOMEM; 3891 3892 b43_sprom_fixup(dev->bus); 3893 3894 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 3895 if (!hw) { 3896 b43err(NULL, "Could not allocate ieee80211 device\n"); 3897 goto out; 3898 } 3899 3900 /* fill hw info */ 3901 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE; 3902 hw->max_signal = 100; 3903 hw->max_rssi = -110; 3904 hw->max_noise = -110; 3905 hw->queues = 1; /* FIXME: hardware has more queues */ 3906 SET_IEEE80211_DEV(hw, dev->dev); 3907 if (is_valid_ether_addr(sprom->r1.et1mac)) 3908 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac); 3909 else 3910 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac); 3911 3912 /* Get and initialize struct b43_wl */ 3913 wl = hw_to_b43_wl(hw); 3914 memset(wl, 0, sizeof(*wl)); 3915 wl->hw = hw; 3916 spin_lock_init(&wl->irq_lock); 3917 spin_lock_init(&wl->leds_lock); 3918 mutex_init(&wl->mutex); 3919 INIT_LIST_HEAD(&wl->devlist); 3920 3921 ssb_set_devtypedata(dev, wl); 3922 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id); 3923 err = 0; 3924 out: 3925 return err; 3926} 3927 3928static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id) 3929{ 3930 struct b43_wl *wl; 3931 int err; 3932 int first = 0; 3933 3934 wl = ssb_get_devtypedata(dev); 3935 if (!wl) { 3936 /* Probing the first core. Must setup common struct b43_wl */ 3937 first = 1; 3938 err = b43_wireless_init(dev); 3939 if (err) 3940 goto out; 3941 wl = ssb_get_devtypedata(dev); 3942 B43_WARN_ON(!wl); 3943 } 3944 err = b43_one_core_attach(dev, wl); 3945 if (err) 3946 goto err_wireless_exit; 3947 3948 if (first) { 3949 err = ieee80211_register_hw(wl->hw); 3950 if (err) 3951 goto err_one_core_detach; 3952 } 3953 3954 out: 3955 return err; 3956 3957 err_one_core_detach: 3958 b43_one_core_detach(dev); 3959 err_wireless_exit: 3960 if (first) 3961 b43_wireless_exit(dev, wl); 3962 return err; 3963} 3964 3965static void b43_remove(struct ssb_device *dev) 3966{ 3967 struct b43_wl *wl = ssb_get_devtypedata(dev); 3968 struct b43_wldev *wldev = ssb_get_drvdata(dev); 3969 3970 B43_WARN_ON(!wl); 3971 if (wl->current_dev == wldev) 3972 ieee80211_unregister_hw(wl->hw); 3973 3974 b43_one_core_detach(dev); 3975 3976 if (list_empty(&wl->devlist)) { 3977 /* Last core on the chip unregistered. 3978 * We can destroy common struct b43_wl. 3979 */ 3980 b43_wireless_exit(dev, wl); 3981 } 3982} 3983 3984/* Perform a hardware reset. This can be called from any context. */ 3985void b43_controller_restart(struct b43_wldev *dev, const char *reason) 3986{ 3987 /* Must avoid requeueing, if we are in shutdown. */ 3988 if (b43_status(dev) < B43_STAT_INITIALIZED) 3989 return; 3990 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 3991 queue_work(dev->wl->hw->workqueue, &dev->restart_work); 3992} 3993 3994#ifdef CONFIG_PM 3995 3996static int b43_suspend(struct ssb_device *dev, pm_message_t state) 3997{ 3998 struct b43_wldev *wldev = ssb_get_drvdata(dev); 3999 struct b43_wl *wl = wldev->wl; 4000 4001 b43dbg(wl, "Suspending...\n"); 4002 4003 mutex_lock(&wl->mutex); 4004 wldev->suspend_init_status = b43_status(wldev); 4005 if (wldev->suspend_init_status >= B43_STAT_STARTED) 4006 b43_wireless_core_stop(wldev); 4007 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) 4008 b43_wireless_core_exit(wldev); 4009 mutex_unlock(&wl->mutex); 4010 4011 b43dbg(wl, "Device suspended.\n"); 4012 4013 return 0; 4014} 4015 4016static int b43_resume(struct ssb_device *dev) 4017{ 4018 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4019 struct b43_wl *wl = wldev->wl; 4020 int err = 0; 4021 4022 b43dbg(wl, "Resuming...\n"); 4023 4024 mutex_lock(&wl->mutex); 4025 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) { 4026 err = b43_wireless_core_init(wldev); 4027 if (err) { 4028 b43err(wl, "Resume failed at core init\n"); 4029 goto out; 4030 } 4031 } 4032 if (wldev->suspend_init_status >= B43_STAT_STARTED) { 4033 err = b43_wireless_core_start(wldev); 4034 if (err) { 4035 b43_wireless_core_exit(wldev); 4036 b43err(wl, "Resume failed at core start\n"); 4037 goto out; 4038 } 4039 } 4040 mutex_unlock(&wl->mutex); 4041 4042 b43dbg(wl, "Device resumed.\n"); 4043 out: 4044 return err; 4045} 4046 4047#else /* CONFIG_PM */ 4048# define b43_suspend NULL 4049# define b43_resume NULL 4050#endif /* CONFIG_PM */ 4051 4052static struct ssb_driver b43_ssb_driver = { 4053 .name = KBUILD_MODNAME, 4054 .id_table = b43_ssb_tbl, 4055 .probe = b43_probe, 4056 .remove = b43_remove, 4057 .suspend = b43_suspend, 4058 .resume = b43_resume, 4059}; 4060 4061static int __init b43_init(void) 4062{ 4063 int err; 4064 4065 b43_debugfs_init(); 4066 err = b43_pcmcia_init(); 4067 if (err) 4068 goto err_dfs_exit; 4069 err = ssb_driver_register(&b43_ssb_driver); 4070 if (err) 4071 goto err_pcmcia_exit; 4072 4073 return err; 4074 4075err_pcmcia_exit: 4076 b43_pcmcia_exit(); 4077err_dfs_exit: 4078 b43_debugfs_exit(); 4079 return err; 4080} 4081 4082static void __exit b43_exit(void) 4083{ 4084 ssb_driver_unregister(&b43_ssb_driver); 4085 b43_pcmcia_exit(); 4086 b43_debugfs_exit(); 4087} 4088 4089module_init(b43_init) 4090module_exit(b43_exit) 4091