main.c revision 874239f51f8759f3955630fa5da5cf13cd6567d5
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com> 11 12 SDIO support 13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> 14 15 Some parts of the code in this file are derived from the ipw2200 16 driver Copyright(c) 2003 - 2004 Intel Corporation. 17 18 This program is free software; you can redistribute it and/or modify 19 it under the terms of the GNU General Public License as published by 20 the Free Software Foundation; either version 2 of the License, or 21 (at your option) any later version. 22 23 This program is distributed in the hope that it will be useful, 24 but WITHOUT ANY WARRANTY; without even the implied warranty of 25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 GNU General Public License for more details. 27 28 You should have received a copy of the GNU General Public License 29 along with this program; see the file COPYING. If not, write to 30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 31 Boston, MA 02110-1301, USA. 32 33*/ 34 35#include <linux/delay.h> 36#include <linux/init.h> 37#include <linux/module.h> 38#include <linux/if_arp.h> 39#include <linux/etherdevice.h> 40#include <linux/firmware.h> 41#include <linux/workqueue.h> 42#include <linux/skbuff.h> 43#include <linux/io.h> 44#include <linux/dma-mapping.h> 45#include <linux/slab.h> 46#include <asm/unaligned.h> 47 48#include "b43.h" 49#include "main.h" 50#include "debugfs.h" 51#include "phy_common.h" 52#include "phy_g.h" 53#include "phy_n.h" 54#include "dma.h" 55#include "pio.h" 56#include "sysfs.h" 57#include "xmit.h" 58#include "lo.h" 59#include "pcmcia.h" 60#include "sdio.h" 61#include <linux/mmc/sdio_func.h> 62 63MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 64MODULE_AUTHOR("Martin Langer"); 65MODULE_AUTHOR("Stefano Brivio"); 66MODULE_AUTHOR("Michael Buesch"); 67MODULE_AUTHOR("Gábor Stefanik"); 68MODULE_AUTHOR("Rafał Miłecki"); 69MODULE_LICENSE("GPL"); 70 71MODULE_FIRMWARE("b43/ucode11.fw"); 72MODULE_FIRMWARE("b43/ucode13.fw"); 73MODULE_FIRMWARE("b43/ucode14.fw"); 74MODULE_FIRMWARE("b43/ucode15.fw"); 75MODULE_FIRMWARE("b43/ucode16_mimo.fw"); 76MODULE_FIRMWARE("b43/ucode5.fw"); 77MODULE_FIRMWARE("b43/ucode9.fw"); 78 79static int modparam_bad_frames_preempt; 80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 81MODULE_PARM_DESC(bad_frames_preempt, 82 "enable(1) / disable(0) Bad Frames Preemption"); 83 84static char modparam_fwpostfix[16]; 85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 87 88static int modparam_hwpctl; 89module_param_named(hwpctl, modparam_hwpctl, int, 0444); 90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 91 92static int modparam_nohwcrypt; 93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 95 96static int modparam_hwtkip; 97module_param_named(hwtkip, modparam_hwtkip, int, 0444); 98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip."); 99 100static int modparam_qos = 1; 101module_param_named(qos, modparam_qos, int, 0444); 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); 103 104static int modparam_btcoex = 1; 105module_param_named(btcoex, modparam_btcoex, int, 0444); 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)"); 107 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT; 109module_param_named(verbose, b43_modparam_verbose, int, 0644); 110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug"); 111 112static int b43_modparam_pio = 0; 113module_param_named(pio, b43_modparam_pio, int, 0644); 114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO"); 115 116#ifdef CONFIG_B43_BCMA 117static const struct bcma_device_id b43_bcma_tbl[] = { 118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS), 119#ifdef CONFIG_B43_BCMA_EXTRA 120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS), 121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS), 122#endif 123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS), 124 BCMA_CORETABLE_END 125}; 126MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl); 127#endif 128 129#ifdef CONFIG_B43_SSB 130static const struct ssb_device_id b43_ssb_tbl[] = { 131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12), 138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15), 140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), 141 SSB_DEVTABLE_END 142}; 143MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 144#endif 145 146/* Channel and ratetables are shared for all devices. 147 * They can't be const, because ieee80211 puts some precalculated 148 * data in there. This data is the same for all devices, so we don't 149 * get concurrency issues */ 150#define RATETAB_ENT(_rateid, _flags) \ 151 { \ 152 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ 153 .hw_value = (_rateid), \ 154 .flags = (_flags), \ 155 } 156 157/* 158 * NOTE: When changing this, sync with xmit.c's 159 * b43_plcp_get_bitrate_idx_* functions! 160 */ 161static struct ieee80211_rate __b43_ratetable[] = { 162 RATETAB_ENT(B43_CCK_RATE_1MB, 0), 163 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), 164 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), 165 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), 166 RATETAB_ENT(B43_OFDM_RATE_6MB, 0), 167 RATETAB_ENT(B43_OFDM_RATE_9MB, 0), 168 RATETAB_ENT(B43_OFDM_RATE_12MB, 0), 169 RATETAB_ENT(B43_OFDM_RATE_18MB, 0), 170 RATETAB_ENT(B43_OFDM_RATE_24MB, 0), 171 RATETAB_ENT(B43_OFDM_RATE_36MB, 0), 172 RATETAB_ENT(B43_OFDM_RATE_48MB, 0), 173 RATETAB_ENT(B43_OFDM_RATE_54MB, 0), 174}; 175 176#define b43_a_ratetable (__b43_ratetable + 4) 177#define b43_a_ratetable_size 8 178#define b43_b_ratetable (__b43_ratetable + 0) 179#define b43_b_ratetable_size 4 180#define b43_g_ratetable (__b43_ratetable + 0) 181#define b43_g_ratetable_size 12 182 183#define CHAN4G(_channel, _freq, _flags) { \ 184 .band = IEEE80211_BAND_2GHZ, \ 185 .center_freq = (_freq), \ 186 .hw_value = (_channel), \ 187 .flags = (_flags), \ 188 .max_antenna_gain = 0, \ 189 .max_power = 30, \ 190} 191static struct ieee80211_channel b43_2ghz_chantable[] = { 192 CHAN4G(1, 2412, 0), 193 CHAN4G(2, 2417, 0), 194 CHAN4G(3, 2422, 0), 195 CHAN4G(4, 2427, 0), 196 CHAN4G(5, 2432, 0), 197 CHAN4G(6, 2437, 0), 198 CHAN4G(7, 2442, 0), 199 CHAN4G(8, 2447, 0), 200 CHAN4G(9, 2452, 0), 201 CHAN4G(10, 2457, 0), 202 CHAN4G(11, 2462, 0), 203 CHAN4G(12, 2467, 0), 204 CHAN4G(13, 2472, 0), 205 CHAN4G(14, 2484, 0), 206}; 207#undef CHAN4G 208 209#define CHAN5G(_channel, _flags) { \ 210 .band = IEEE80211_BAND_5GHZ, \ 211 .center_freq = 5000 + (5 * (_channel)), \ 212 .hw_value = (_channel), \ 213 .flags = (_flags), \ 214 .max_antenna_gain = 0, \ 215 .max_power = 30, \ 216} 217static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { 218 CHAN5G(32, 0), CHAN5G(34, 0), 219 CHAN5G(36, 0), CHAN5G(38, 0), 220 CHAN5G(40, 0), CHAN5G(42, 0), 221 CHAN5G(44, 0), CHAN5G(46, 0), 222 CHAN5G(48, 0), CHAN5G(50, 0), 223 CHAN5G(52, 0), CHAN5G(54, 0), 224 CHAN5G(56, 0), CHAN5G(58, 0), 225 CHAN5G(60, 0), CHAN5G(62, 0), 226 CHAN5G(64, 0), CHAN5G(66, 0), 227 CHAN5G(68, 0), CHAN5G(70, 0), 228 CHAN5G(72, 0), CHAN5G(74, 0), 229 CHAN5G(76, 0), CHAN5G(78, 0), 230 CHAN5G(80, 0), CHAN5G(82, 0), 231 CHAN5G(84, 0), CHAN5G(86, 0), 232 CHAN5G(88, 0), CHAN5G(90, 0), 233 CHAN5G(92, 0), CHAN5G(94, 0), 234 CHAN5G(96, 0), CHAN5G(98, 0), 235 CHAN5G(100, 0), CHAN5G(102, 0), 236 CHAN5G(104, 0), CHAN5G(106, 0), 237 CHAN5G(108, 0), CHAN5G(110, 0), 238 CHAN5G(112, 0), CHAN5G(114, 0), 239 CHAN5G(116, 0), CHAN5G(118, 0), 240 CHAN5G(120, 0), CHAN5G(122, 0), 241 CHAN5G(124, 0), CHAN5G(126, 0), 242 CHAN5G(128, 0), CHAN5G(130, 0), 243 CHAN5G(132, 0), CHAN5G(134, 0), 244 CHAN5G(136, 0), CHAN5G(138, 0), 245 CHAN5G(140, 0), CHAN5G(142, 0), 246 CHAN5G(144, 0), CHAN5G(145, 0), 247 CHAN5G(146, 0), CHAN5G(147, 0), 248 CHAN5G(148, 0), CHAN5G(149, 0), 249 CHAN5G(150, 0), CHAN5G(151, 0), 250 CHAN5G(152, 0), CHAN5G(153, 0), 251 CHAN5G(154, 0), CHAN5G(155, 0), 252 CHAN5G(156, 0), CHAN5G(157, 0), 253 CHAN5G(158, 0), CHAN5G(159, 0), 254 CHAN5G(160, 0), CHAN5G(161, 0), 255 CHAN5G(162, 0), CHAN5G(163, 0), 256 CHAN5G(164, 0), CHAN5G(165, 0), 257 CHAN5G(166, 0), CHAN5G(168, 0), 258 CHAN5G(170, 0), CHAN5G(172, 0), 259 CHAN5G(174, 0), CHAN5G(176, 0), 260 CHAN5G(178, 0), CHAN5G(180, 0), 261 CHAN5G(182, 0), CHAN5G(184, 0), 262 CHAN5G(186, 0), CHAN5G(188, 0), 263 CHAN5G(190, 0), CHAN5G(192, 0), 264 CHAN5G(194, 0), CHAN5G(196, 0), 265 CHAN5G(198, 0), CHAN5G(200, 0), 266 CHAN5G(202, 0), CHAN5G(204, 0), 267 CHAN5G(206, 0), CHAN5G(208, 0), 268 CHAN5G(210, 0), CHAN5G(212, 0), 269 CHAN5G(214, 0), CHAN5G(216, 0), 270 CHAN5G(218, 0), CHAN5G(220, 0), 271 CHAN5G(222, 0), CHAN5G(224, 0), 272 CHAN5G(226, 0), CHAN5G(228, 0), 273}; 274 275static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { 276 CHAN5G(34, 0), CHAN5G(36, 0), 277 CHAN5G(38, 0), CHAN5G(40, 0), 278 CHAN5G(42, 0), CHAN5G(44, 0), 279 CHAN5G(46, 0), CHAN5G(48, 0), 280 CHAN5G(52, 0), CHAN5G(56, 0), 281 CHAN5G(60, 0), CHAN5G(64, 0), 282 CHAN5G(100, 0), CHAN5G(104, 0), 283 CHAN5G(108, 0), CHAN5G(112, 0), 284 CHAN5G(116, 0), CHAN5G(120, 0), 285 CHAN5G(124, 0), CHAN5G(128, 0), 286 CHAN5G(132, 0), CHAN5G(136, 0), 287 CHAN5G(140, 0), CHAN5G(149, 0), 288 CHAN5G(153, 0), CHAN5G(157, 0), 289 CHAN5G(161, 0), CHAN5G(165, 0), 290 CHAN5G(184, 0), CHAN5G(188, 0), 291 CHAN5G(192, 0), CHAN5G(196, 0), 292 CHAN5G(200, 0), CHAN5G(204, 0), 293 CHAN5G(208, 0), CHAN5G(212, 0), 294 CHAN5G(216, 0), 295}; 296#undef CHAN5G 297 298static struct ieee80211_supported_band b43_band_5GHz_nphy = { 299 .band = IEEE80211_BAND_5GHZ, 300 .channels = b43_5ghz_nphy_chantable, 301 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), 302 .bitrates = b43_a_ratetable, 303 .n_bitrates = b43_a_ratetable_size, 304}; 305 306static struct ieee80211_supported_band b43_band_5GHz_aphy = { 307 .band = IEEE80211_BAND_5GHZ, 308 .channels = b43_5ghz_aphy_chantable, 309 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), 310 .bitrates = b43_a_ratetable, 311 .n_bitrates = b43_a_ratetable_size, 312}; 313 314static struct ieee80211_supported_band b43_band_2GHz = { 315 .band = IEEE80211_BAND_2GHZ, 316 .channels = b43_2ghz_chantable, 317 .n_channels = ARRAY_SIZE(b43_2ghz_chantable), 318 .bitrates = b43_g_ratetable, 319 .n_bitrates = b43_g_ratetable_size, 320}; 321 322static void b43_wireless_core_exit(struct b43_wldev *dev); 323static int b43_wireless_core_init(struct b43_wldev *dev); 324static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev); 325static int b43_wireless_core_start(struct b43_wldev *dev); 326static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 327 struct ieee80211_vif *vif, 328 struct ieee80211_bss_conf *conf, 329 u32 changed); 330 331static int b43_ratelimit(struct b43_wl *wl) 332{ 333 if (!wl || !wl->current_dev) 334 return 1; 335 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 336 return 1; 337 /* We are up and running. 338 * Ratelimit the messages to avoid DoS over the net. */ 339 return net_ratelimit(); 340} 341 342void b43info(struct b43_wl *wl, const char *fmt, ...) 343{ 344 struct va_format vaf; 345 va_list args; 346 347 if (b43_modparam_verbose < B43_VERBOSITY_INFO) 348 return; 349 if (!b43_ratelimit(wl)) 350 return; 351 352 va_start(args, fmt); 353 354 vaf.fmt = fmt; 355 vaf.va = &args; 356 357 printk(KERN_INFO "b43-%s: %pV", 358 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 359 360 va_end(args); 361} 362 363void b43err(struct b43_wl *wl, const char *fmt, ...) 364{ 365 struct va_format vaf; 366 va_list args; 367 368 if (b43_modparam_verbose < B43_VERBOSITY_ERROR) 369 return; 370 if (!b43_ratelimit(wl)) 371 return; 372 373 va_start(args, fmt); 374 375 vaf.fmt = fmt; 376 vaf.va = &args; 377 378 printk(KERN_ERR "b43-%s ERROR: %pV", 379 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 380 381 va_end(args); 382} 383 384void b43warn(struct b43_wl *wl, const char *fmt, ...) 385{ 386 struct va_format vaf; 387 va_list args; 388 389 if (b43_modparam_verbose < B43_VERBOSITY_WARN) 390 return; 391 if (!b43_ratelimit(wl)) 392 return; 393 394 va_start(args, fmt); 395 396 vaf.fmt = fmt; 397 vaf.va = &args; 398 399 printk(KERN_WARNING "b43-%s warning: %pV", 400 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 401 402 va_end(args); 403} 404 405void b43dbg(struct b43_wl *wl, const char *fmt, ...) 406{ 407 struct va_format vaf; 408 va_list args; 409 410 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 411 return; 412 413 va_start(args, fmt); 414 415 vaf.fmt = fmt; 416 vaf.va = &args; 417 418 printk(KERN_DEBUG "b43-%s debug: %pV", 419 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 420 421 va_end(args); 422} 423 424static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 425{ 426 u32 macctl; 427 428 B43_WARN_ON(offset % 4 != 0); 429 430 macctl = b43_read32(dev, B43_MMIO_MACCTL); 431 if (macctl & B43_MACCTL_BE) 432 val = swab32(val); 433 434 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 435 mmiowb(); 436 b43_write32(dev, B43_MMIO_RAM_DATA, val); 437} 438 439static inline void b43_shm_control_word(struct b43_wldev *dev, 440 u16 routing, u16 offset) 441{ 442 u32 control; 443 444 /* "offset" is the WORD offset. */ 445 control = routing; 446 control <<= 16; 447 control |= offset; 448 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 449} 450 451u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 452{ 453 u32 ret; 454 455 if (routing == B43_SHM_SHARED) { 456 B43_WARN_ON(offset & 0x0001); 457 if (offset & 0x0003) { 458 /* Unaligned access */ 459 b43_shm_control_word(dev, routing, offset >> 2); 460 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 461 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 462 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16; 463 464 goto out; 465 } 466 offset >>= 2; 467 } 468 b43_shm_control_word(dev, routing, offset); 469 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 470out: 471 return ret; 472} 473 474u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset) 475{ 476 u16 ret; 477 478 if (routing == B43_SHM_SHARED) { 479 B43_WARN_ON(offset & 0x0001); 480 if (offset & 0x0003) { 481 /* Unaligned access */ 482 b43_shm_control_word(dev, routing, offset >> 2); 483 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 484 485 goto out; 486 } 487 offset >>= 2; 488 } 489 b43_shm_control_word(dev, routing, offset); 490 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 491out: 492 return ret; 493} 494 495void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 496{ 497 if (routing == B43_SHM_SHARED) { 498 B43_WARN_ON(offset & 0x0001); 499 if (offset & 0x0003) { 500 /* Unaligned access */ 501 b43_shm_control_word(dev, routing, offset >> 2); 502 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 503 value & 0xFFFF); 504 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 505 b43_write16(dev, B43_MMIO_SHM_DATA, 506 (value >> 16) & 0xFFFF); 507 return; 508 } 509 offset >>= 2; 510 } 511 b43_shm_control_word(dev, routing, offset); 512 b43_write32(dev, B43_MMIO_SHM_DATA, value); 513} 514 515void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 516{ 517 if (routing == B43_SHM_SHARED) { 518 B43_WARN_ON(offset & 0x0001); 519 if (offset & 0x0003) { 520 /* Unaligned access */ 521 b43_shm_control_word(dev, routing, offset >> 2); 522 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 523 return; 524 } 525 offset >>= 2; 526 } 527 b43_shm_control_word(dev, routing, offset); 528 b43_write16(dev, B43_MMIO_SHM_DATA, value); 529} 530 531/* Read HostFlags */ 532u64 b43_hf_read(struct b43_wldev *dev) 533{ 534 u64 ret; 535 536 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 537 ret <<= 16; 538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI); 539 ret <<= 16; 540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 541 542 return ret; 543} 544 545/* Write HostFlags */ 546void b43_hf_write(struct b43_wldev *dev, u64 value) 547{ 548 u16 lo, mi, hi; 549 550 lo = (value & 0x00000000FFFFULL); 551 mi = (value & 0x0000FFFF0000ULL) >> 16; 552 hi = (value & 0xFFFF00000000ULL) >> 32; 553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo); 554 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi); 555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi); 556} 557 558/* Read the firmware capabilities bitmask (Opensource firmware only) */ 559static u16 b43_fwcapa_read(struct b43_wldev *dev) 560{ 561 B43_WARN_ON(!dev->fw.opensource); 562 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA); 563} 564 565void b43_tsf_read(struct b43_wldev *dev, u64 *tsf) 566{ 567 u32 low, high; 568 569 B43_WARN_ON(dev->dev->core_rev < 3); 570 571 /* The hardware guarantees us an atomic read, if we 572 * read the low register first. */ 573 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 574 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 575 576 *tsf = high; 577 *tsf <<= 32; 578 *tsf |= low; 579} 580 581static void b43_time_lock(struct b43_wldev *dev) 582{ 583 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD); 584 /* Commit the write */ 585 b43_read32(dev, B43_MMIO_MACCTL); 586} 587 588static void b43_time_unlock(struct b43_wldev *dev) 589{ 590 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0); 591 /* Commit the write */ 592 b43_read32(dev, B43_MMIO_MACCTL); 593} 594 595static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 596{ 597 u32 low, high; 598 599 B43_WARN_ON(dev->dev->core_rev < 3); 600 601 low = tsf; 602 high = (tsf >> 32); 603 /* The hardware guarantees us an atomic write, if we 604 * write the low register first. */ 605 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low); 606 mmiowb(); 607 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high); 608 mmiowb(); 609} 610 611void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 612{ 613 b43_time_lock(dev); 614 b43_tsf_write_locked(dev, tsf); 615 b43_time_unlock(dev); 616} 617 618static 619void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac) 620{ 621 static const u8 zero_addr[ETH_ALEN] = { 0 }; 622 u16 data; 623 624 if (!mac) 625 mac = zero_addr; 626 627 offset |= 0x0020; 628 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 629 630 data = mac[0]; 631 data |= mac[1] << 8; 632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 633 data = mac[2]; 634 data |= mac[3] << 8; 635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 636 data = mac[4]; 637 data |= mac[5] << 8; 638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 639} 640 641static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 642{ 643 const u8 *mac; 644 const u8 *bssid; 645 u8 mac_bssid[ETH_ALEN * 2]; 646 int i; 647 u32 tmp; 648 649 bssid = dev->wl->bssid; 650 mac = dev->wl->mac_addr; 651 652 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 653 654 memcpy(mac_bssid, mac, ETH_ALEN); 655 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 656 657 /* Write our MAC address and BSSID to template ram */ 658 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 659 tmp = (u32) (mac_bssid[i + 0]); 660 tmp |= (u32) (mac_bssid[i + 1]) << 8; 661 tmp |= (u32) (mac_bssid[i + 2]) << 16; 662 tmp |= (u32) (mac_bssid[i + 3]) << 24; 663 b43_ram_write(dev, 0x20 + i, tmp); 664 } 665} 666 667static void b43_upload_card_macaddress(struct b43_wldev *dev) 668{ 669 b43_write_mac_bssid_templates(dev); 670 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 671} 672 673static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 674{ 675 /* slot_time is in usec. */ 676 /* This test used to exit for all but a G PHY. */ 677 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 678 return; 679 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time); 680 /* Shared memory location 0x0010 is the slot time and should be 681 * set to slot_time; however, this register is initially 0 and changing 682 * the value adversely affects the transmit rate for BCM4311 683 * devices. Until this behavior is unterstood, delete this step 684 * 685 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 686 */ 687} 688 689static void b43_short_slot_timing_enable(struct b43_wldev *dev) 690{ 691 b43_set_slot_time(dev, 9); 692} 693 694static void b43_short_slot_timing_disable(struct b43_wldev *dev) 695{ 696 b43_set_slot_time(dev, 20); 697} 698 699/* DummyTransmission function, as documented on 700 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission 701 */ 702void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) 703{ 704 struct b43_phy *phy = &dev->phy; 705 unsigned int i, max_loop; 706 u16 value; 707 u32 buffer[5] = { 708 0x00000000, 709 0x00D40000, 710 0x00000000, 711 0x01000000, 712 0x00000000, 713 }; 714 715 if (ofdm) { 716 max_loop = 0x1E; 717 buffer[0] = 0x000201CC; 718 } else { 719 max_loop = 0xFA; 720 buffer[0] = 0x000B846E; 721 } 722 723 for (i = 0; i < 5; i++) 724 b43_ram_write(dev, i * 4, buffer[i]); 725 726 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000); 727 728 if (dev->dev->core_rev < 11) 729 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000); 730 else 731 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100); 732 733 value = (ofdm ? 0x41 : 0x40); 734 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value); 735 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP || 736 phy->type == B43_PHYTYPE_LCN) 737 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02); 738 739 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000); 740 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000); 741 742 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000); 743 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014); 744 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826); 745 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000); 746 747 if (!pa_on && phy->type == B43_PHYTYPE_N) 748 ; /*b43_nphy_pa_override(dev, false) */ 749 750 switch (phy->type) { 751 case B43_PHYTYPE_N: 752 case B43_PHYTYPE_LCN: 753 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0); 754 break; 755 case B43_PHYTYPE_LP: 756 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050); 757 break; 758 default: 759 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030); 760 } 761 b43_read16(dev, B43_MMIO_TXE0_AUX); 762 763 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 764 b43_radio_write16(dev, 0x0051, 0x0017); 765 for (i = 0x00; i < max_loop; i++) { 766 value = b43_read16(dev, B43_MMIO_TXE0_STATUS); 767 if (value & 0x0080) 768 break; 769 udelay(10); 770 } 771 for (i = 0x00; i < 0x0A; i++) { 772 value = b43_read16(dev, B43_MMIO_TXE0_STATUS); 773 if (value & 0x0400) 774 break; 775 udelay(10); 776 } 777 for (i = 0x00; i < 0x19; i++) { 778 value = b43_read16(dev, B43_MMIO_IFSSTAT); 779 if (!(value & 0x0100)) 780 break; 781 udelay(10); 782 } 783 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 784 b43_radio_write16(dev, 0x0051, 0x0037); 785} 786 787static void key_write(struct b43_wldev *dev, 788 u8 index, u8 algorithm, const u8 *key) 789{ 790 unsigned int i; 791 u32 offset; 792 u16 value; 793 u16 kidx; 794 795 /* Key index/algo block */ 796 kidx = b43_kidx_to_fw(dev, index); 797 value = ((kidx << 4) | algorithm); 798 b43_shm_write16(dev, B43_SHM_SHARED, 799 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 800 801 /* Write the key to the Key Table Pointer offset */ 802 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 803 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 804 value = key[i]; 805 value |= (u16) (key[i + 1]) << 8; 806 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 807 } 808} 809 810static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr) 811{ 812 u32 addrtmp[2] = { 0, 0, }; 813 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 814 815 if (b43_new_kidx_api(dev)) 816 pairwise_keys_start = B43_NR_GROUP_KEYS; 817 818 B43_WARN_ON(index < pairwise_keys_start); 819 /* We have four default TX keys and possibly four default RX keys. 820 * Physical mac 0 is mapped to physical key 4 or 8, depending 821 * on the firmware version. 822 * So we must adjust the index here. 823 */ 824 index -= pairwise_keys_start; 825 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 826 827 if (addr) { 828 addrtmp[0] = addr[0]; 829 addrtmp[0] |= ((u32) (addr[1]) << 8); 830 addrtmp[0] |= ((u32) (addr[2]) << 16); 831 addrtmp[0] |= ((u32) (addr[3]) << 24); 832 addrtmp[1] = addr[4]; 833 addrtmp[1] |= ((u32) (addr[5]) << 8); 834 } 835 836 /* Receive match transmitter address (RCMTA) mechanism */ 837 b43_shm_write32(dev, B43_SHM_RCMTA, 838 (index * 2) + 0, addrtmp[0]); 839 b43_shm_write16(dev, B43_SHM_RCMTA, 840 (index * 2) + 1, addrtmp[1]); 841} 842 843/* The ucode will use phase1 key with TEK key to decrypt rx packets. 844 * When a packet is received, the iv32 is checked. 845 * - if it doesn't the packet is returned without modification (and software 846 * decryption can be done). That's what happen when iv16 wrap. 847 * - if it does, the rc4 key is computed, and decryption is tried. 848 * Either it will success and B43_RX_MAC_DEC is returned, 849 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned 850 * and the packet is not usable (it got modified by the ucode). 851 * So in order to never have B43_RX_MAC_DECERR, we should provide 852 * a iv32 and phase1key that match. Because we drop packets in case of 853 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all 854 * packets will be lost without higher layer knowing (ie no resync possible 855 * until next wrap). 856 * 857 * NOTE : this should support 50 key like RCMTA because 858 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50 859 */ 860static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32, 861 u16 *phase1key) 862{ 863 unsigned int i; 864 u32 offset; 865 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 866 867 if (!modparam_hwtkip) 868 return; 869 870 if (b43_new_kidx_api(dev)) 871 pairwise_keys_start = B43_NR_GROUP_KEYS; 872 873 B43_WARN_ON(index < pairwise_keys_start); 874 /* We have four default TX keys and possibly four default RX keys. 875 * Physical mac 0 is mapped to physical key 4 or 8, depending 876 * on the firmware version. 877 * So we must adjust the index here. 878 */ 879 index -= pairwise_keys_start; 880 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 881 882 if (b43_debug(dev, B43_DBG_KEYS)) { 883 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", 884 index, iv32); 885 } 886 /* Write the key to the RX tkip shared mem */ 887 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4); 888 for (i = 0; i < 10; i += 2) { 889 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, 890 phase1key ? phase1key[i / 2] : 0); 891 } 892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32); 893 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16); 894} 895 896static void b43_op_update_tkip_key(struct ieee80211_hw *hw, 897 struct ieee80211_vif *vif, 898 struct ieee80211_key_conf *keyconf, 899 struct ieee80211_sta *sta, 900 u32 iv32, u16 *phase1key) 901{ 902 struct b43_wl *wl = hw_to_b43_wl(hw); 903 struct b43_wldev *dev; 904 int index = keyconf->hw_key_idx; 905 906 if (B43_WARN_ON(!modparam_hwtkip)) 907 return; 908 909 /* This is only called from the RX path through mac80211, where 910 * our mutex is already locked. */ 911 B43_WARN_ON(!mutex_is_locked(&wl->mutex)); 912 dev = wl->current_dev; 913 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED); 914 915 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */ 916 917 rx_tkip_phase1_write(dev, index, iv32, phase1key); 918 /* only pairwise TKIP keys are supported right now */ 919 if (WARN_ON(!sta)) 920 return; 921 keymac_write(dev, index, sta->addr); 922} 923 924static void do_key_write(struct b43_wldev *dev, 925 u8 index, u8 algorithm, 926 const u8 *key, size_t key_len, const u8 *mac_addr) 927{ 928 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 929 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 930 931 if (b43_new_kidx_api(dev)) 932 pairwise_keys_start = B43_NR_GROUP_KEYS; 933 934 B43_WARN_ON(index >= ARRAY_SIZE(dev->key)); 935 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 936 937 if (index >= pairwise_keys_start) 938 keymac_write(dev, index, NULL); /* First zero out mac. */ 939 if (algorithm == B43_SEC_ALGO_TKIP) { 940 /* 941 * We should provide an initial iv32, phase1key pair. 942 * We could start with iv32=0 and compute the corresponding 943 * phase1key, but this means calling ieee80211_get_tkip_key 944 * with a fake skb (or export other tkip function). 945 * Because we are lazy we hope iv32 won't start with 946 * 0xffffffff and let's b43_op_update_tkip_key provide a 947 * correct pair. 948 */ 949 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); 950 } else if (index >= pairwise_keys_start) /* clear it */ 951 rx_tkip_phase1_write(dev, index, 0, NULL); 952 if (key) 953 memcpy(buf, key, key_len); 954 key_write(dev, index, algorithm, buf); 955 if (index >= pairwise_keys_start) 956 keymac_write(dev, index, mac_addr); 957 958 dev->key[index].algorithm = algorithm; 959} 960 961static int b43_key_write(struct b43_wldev *dev, 962 int index, u8 algorithm, 963 const u8 *key, size_t key_len, 964 const u8 *mac_addr, 965 struct ieee80211_key_conf *keyconf) 966{ 967 int i; 968 int pairwise_keys_start; 969 970 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block: 971 * - Temporal Encryption Key (128 bits) 972 * - Temporal Authenticator Tx MIC Key (64 bits) 973 * - Temporal Authenticator Rx MIC Key (64 bits) 974 * 975 * Hardware only store TEK 976 */ 977 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32) 978 key_len = 16; 979 if (key_len > B43_SEC_KEYSIZE) 980 return -EINVAL; 981 for (i = 0; i < ARRAY_SIZE(dev->key); i++) { 982 /* Check that we don't already have this key. */ 983 B43_WARN_ON(dev->key[i].keyconf == keyconf); 984 } 985 if (index < 0) { 986 /* Pairwise key. Get an empty slot for the key. */ 987 if (b43_new_kidx_api(dev)) 988 pairwise_keys_start = B43_NR_GROUP_KEYS; 989 else 990 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 991 for (i = pairwise_keys_start; 992 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS; 993 i++) { 994 B43_WARN_ON(i >= ARRAY_SIZE(dev->key)); 995 if (!dev->key[i].keyconf) { 996 /* found empty */ 997 index = i; 998 break; 999 } 1000 } 1001 if (index < 0) { 1002 b43warn(dev->wl, "Out of hardware key memory\n"); 1003 return -ENOSPC; 1004 } 1005 } else 1006 B43_WARN_ON(index > 3); 1007 1008 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 1009 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1010 /* Default RX key */ 1011 B43_WARN_ON(mac_addr); 1012 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 1013 } 1014 keyconf->hw_key_idx = index; 1015 dev->key[index].keyconf = keyconf; 1016 1017 return 0; 1018} 1019 1020static int b43_key_clear(struct b43_wldev *dev, int index) 1021{ 1022 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) 1023 return -EINVAL; 1024 do_key_write(dev, index, B43_SEC_ALGO_NONE, 1025 NULL, B43_SEC_KEYSIZE, NULL); 1026 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1027 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 1028 NULL, B43_SEC_KEYSIZE, NULL); 1029 } 1030 dev->key[index].keyconf = NULL; 1031 1032 return 0; 1033} 1034 1035static void b43_clear_keys(struct b43_wldev *dev) 1036{ 1037 int i, count; 1038 1039 if (b43_new_kidx_api(dev)) 1040 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1041 else 1042 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1043 for (i = 0; i < count; i++) 1044 b43_key_clear(dev, i); 1045} 1046 1047static void b43_dump_keymemory(struct b43_wldev *dev) 1048{ 1049 unsigned int i, index, count, offset, pairwise_keys_start; 1050 u8 mac[ETH_ALEN]; 1051 u16 algo; 1052 u32 rcmta0; 1053 u16 rcmta1; 1054 u64 hf; 1055 struct b43_key *key; 1056 1057 if (!b43_debug(dev, B43_DBG_KEYS)) 1058 return; 1059 1060 hf = b43_hf_read(dev); 1061 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n", 1062 !!(hf & B43_HF_USEDEFKEYS)); 1063 if (b43_new_kidx_api(dev)) { 1064 pairwise_keys_start = B43_NR_GROUP_KEYS; 1065 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1066 } else { 1067 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 1068 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1069 } 1070 for (index = 0; index < count; index++) { 1071 key = &(dev->key[index]); 1072 printk(KERN_DEBUG "Key slot %02u: %s", 1073 index, (key->keyconf == NULL) ? " " : "*"); 1074 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 1075 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 1076 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1077 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1078 } 1079 1080 algo = b43_shm_read16(dev, B43_SHM_SHARED, 1081 B43_SHM_SH_KEYIDXBLOCK + (index * 2)); 1082 printk(" Algo: %04X/%02X", algo, key->algorithm); 1083 1084 if (index >= pairwise_keys_start) { 1085 if (key->algorithm == B43_SEC_ALGO_TKIP) { 1086 printk(" TKIP: "); 1087 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4); 1088 for (i = 0; i < 14; i += 2) { 1089 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1090 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1091 } 1092 } 1093 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA, 1094 ((index - pairwise_keys_start) * 2) + 0); 1095 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA, 1096 ((index - pairwise_keys_start) * 2) + 1); 1097 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); 1098 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1); 1099 printk(" MAC: %pM", mac); 1100 } else 1101 printk(" DEFAULT KEY"); 1102 printk("\n"); 1103 } 1104} 1105 1106void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 1107{ 1108 u32 macctl; 1109 u16 ucstat; 1110 bool hwps; 1111 bool awake; 1112 int i; 1113 1114 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 1115 (ps_flags & B43_PS_DISABLED)); 1116 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 1117 1118 if (ps_flags & B43_PS_ENABLED) { 1119 hwps = true; 1120 } else if (ps_flags & B43_PS_DISABLED) { 1121 hwps = false; 1122 } else { 1123 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 1124 // and thus is not an AP and we are associated, set bit 25 1125 } 1126 if (ps_flags & B43_PS_AWAKE) { 1127 awake = true; 1128 } else if (ps_flags & B43_PS_ASLEEP) { 1129 awake = false; 1130 } else { 1131 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 1132 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 1133 // successful, set bit26 1134 } 1135 1136/* FIXME: For now we force awake-on and hwps-off */ 1137 hwps = false; 1138 awake = true; 1139 1140 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1141 if (hwps) 1142 macctl |= B43_MACCTL_HWPS; 1143 else 1144 macctl &= ~B43_MACCTL_HWPS; 1145 if (awake) 1146 macctl |= B43_MACCTL_AWAKE; 1147 else 1148 macctl &= ~B43_MACCTL_AWAKE; 1149 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1150 /* Commit write */ 1151 b43_read32(dev, B43_MMIO_MACCTL); 1152 if (awake && dev->dev->core_rev >= 5) { 1153 /* Wait for the microcode to wake up. */ 1154 for (i = 0; i < 100; i++) { 1155 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 1156 B43_SHM_SH_UCODESTAT); 1157 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 1158 break; 1159 udelay(10); 1160 } 1161 } 1162} 1163 1164#ifdef CONFIG_B43_BCMA 1165static void b43_bcma_phy_reset(struct b43_wldev *dev) 1166{ 1167 u32 flags; 1168 1169 /* Put PHY into reset */ 1170 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1171 flags |= B43_BCMA_IOCTL_PHY_RESET; 1172 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */ 1173 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1174 udelay(2); 1175 1176 /* Take PHY out of reset */ 1177 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1178 flags &= ~B43_BCMA_IOCTL_PHY_RESET; 1179 flags |= BCMA_IOCTL_FGC; 1180 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1181 udelay(1); 1182 1183 /* Do not force clock anymore */ 1184 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1185 flags &= ~BCMA_IOCTL_FGC; 1186 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1187 udelay(1); 1188} 1189 1190static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1191{ 1192 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN); 1193 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST); 1194 b43_bcma_phy_reset(dev); 1195 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true); 1196} 1197#endif 1198 1199static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1200{ 1201 struct ssb_device *sdev = dev->dev->sdev; 1202 u32 tmslow; 1203 u32 flags = 0; 1204 1205 if (gmode) 1206 flags |= B43_TMSLOW_GMODE; 1207 flags |= B43_TMSLOW_PHYCLKEN; 1208 flags |= B43_TMSLOW_PHYRESET; 1209 if (dev->phy.type == B43_PHYTYPE_N) 1210 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */ 1211 b43_device_enable(dev, flags); 1212 msleep(2); /* Wait for the PLL to turn on. */ 1213 1214 /* Now take the PHY out of Reset again */ 1215 tmslow = ssb_read32(sdev, SSB_TMSLOW); 1216 tmslow |= SSB_TMSLOW_FGC; 1217 tmslow &= ~B43_TMSLOW_PHYRESET; 1218 ssb_write32(sdev, SSB_TMSLOW, tmslow); 1219 ssb_read32(sdev, SSB_TMSLOW); /* flush */ 1220 msleep(1); 1221 tmslow &= ~SSB_TMSLOW_FGC; 1222 ssb_write32(sdev, SSB_TMSLOW, tmslow); 1223 ssb_read32(sdev, SSB_TMSLOW); /* flush */ 1224 msleep(1); 1225} 1226 1227void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1228{ 1229 u32 macctl; 1230 1231 switch (dev->dev->bus_type) { 1232#ifdef CONFIG_B43_BCMA 1233 case B43_BUS_BCMA: 1234 b43_bcma_wireless_core_reset(dev, gmode); 1235 break; 1236#endif 1237#ifdef CONFIG_B43_SSB 1238 case B43_BUS_SSB: 1239 b43_ssb_wireless_core_reset(dev, gmode); 1240 break; 1241#endif 1242 } 1243 1244 /* Turn Analog ON, but only if we already know the PHY-type. 1245 * This protects against very early setup where we don't know the 1246 * PHY-type, yet. wireless_core_reset will be called once again later, 1247 * when we know the PHY-type. */ 1248 if (dev->phy.ops) 1249 dev->phy.ops->switch_analog(dev, 1); 1250 1251 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1252 macctl &= ~B43_MACCTL_GMODE; 1253 if (gmode) 1254 macctl |= B43_MACCTL_GMODE; 1255 macctl |= B43_MACCTL_IHR_ENABLED; 1256 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1257} 1258 1259static void handle_irq_transmit_status(struct b43_wldev *dev) 1260{ 1261 u32 v0, v1; 1262 u16 tmp; 1263 struct b43_txstatus stat; 1264 1265 while (1) { 1266 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1267 if (!(v0 & 0x00000001)) 1268 break; 1269 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1270 1271 stat.cookie = (v0 >> 16); 1272 stat.seq = (v1 & 0x0000FFFF); 1273 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 1274 tmp = (v0 & 0x0000FFFF); 1275 stat.frame_count = ((tmp & 0xF000) >> 12); 1276 stat.rts_count = ((tmp & 0x0F00) >> 8); 1277 stat.supp_reason = ((tmp & 0x001C) >> 2); 1278 stat.pm_indicated = !!(tmp & 0x0080); 1279 stat.intermediate = !!(tmp & 0x0040); 1280 stat.for_ampdu = !!(tmp & 0x0020); 1281 stat.acked = !!(tmp & 0x0002); 1282 1283 b43_handle_txstatus(dev, &stat); 1284 } 1285} 1286 1287static void drain_txstatus_queue(struct b43_wldev *dev) 1288{ 1289 u32 dummy; 1290 1291 if (dev->dev->core_rev < 5) 1292 return; 1293 /* Read all entries from the microcode TXstatus FIFO 1294 * and throw them away. 1295 */ 1296 while (1) { 1297 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1298 if (!(dummy & 0x00000001)) 1299 break; 1300 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1301 } 1302} 1303 1304static u32 b43_jssi_read(struct b43_wldev *dev) 1305{ 1306 u32 val = 0; 1307 1308 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 1309 val <<= 16; 1310 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1311 1312 return val; 1313} 1314 1315static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1316{ 1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1318 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1319} 1320 1321static void b43_generate_noise_sample(struct b43_wldev *dev) 1322{ 1323 b43_jssi_write(dev, 0x7F7F7F7F); 1324 b43_write32(dev, B43_MMIO_MACCMD, 1325 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1326} 1327 1328static void b43_calculate_link_quality(struct b43_wldev *dev) 1329{ 1330 /* Top half of Link Quality calculation. */ 1331 1332 if (dev->phy.type != B43_PHYTYPE_G) 1333 return; 1334 if (dev->noisecalc.calculation_running) 1335 return; 1336 dev->noisecalc.calculation_running = true; 1337 dev->noisecalc.nr_samples = 0; 1338 1339 b43_generate_noise_sample(dev); 1340} 1341 1342static void handle_irq_noise(struct b43_wldev *dev) 1343{ 1344 struct b43_phy_g *phy = dev->phy.g; 1345 u16 tmp; 1346 u8 noise[4]; 1347 u8 i, j; 1348 s32 average; 1349 1350 /* Bottom half of Link Quality calculation. */ 1351 1352 if (dev->phy.type != B43_PHYTYPE_G) 1353 return; 1354 1355 /* Possible race condition: It might be possible that the user 1356 * changed to a different channel in the meantime since we 1357 * started the calculation. We ignore that fact, since it's 1358 * not really that much of a problem. The background noise is 1359 * an estimation only anyway. Slightly wrong results will get damped 1360 * by the averaging of the 8 sample rounds. Additionally the 1361 * value is shortlived. So it will be replaced by the next noise 1362 * calculation round soon. */ 1363 1364 B43_WARN_ON(!dev->noisecalc.calculation_running); 1365 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1366 if (noise[0] == 0x7F || noise[1] == 0x7F || 1367 noise[2] == 0x7F || noise[3] == 0x7F) 1368 goto generate_new; 1369 1370 /* Get the noise samples. */ 1371 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1372 i = dev->noisecalc.nr_samples; 1373 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1374 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1375 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1376 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1377 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1378 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1379 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1380 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1381 dev->noisecalc.nr_samples++; 1382 if (dev->noisecalc.nr_samples == 8) { 1383 /* Calculate the Link Quality by the noise samples. */ 1384 average = 0; 1385 for (i = 0; i < 8; i++) { 1386 for (j = 0; j < 4; j++) 1387 average += dev->noisecalc.samples[i][j]; 1388 } 1389 average /= (8 * 4); 1390 average *= 125; 1391 average += 64; 1392 average /= 128; 1393 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1394 tmp = (tmp / 128) & 0x1F; 1395 if (tmp >= 8) 1396 average += 2; 1397 else 1398 average -= 25; 1399 if (tmp == 8) 1400 average -= 72; 1401 else 1402 average -= 48; 1403 1404 dev->stats.link_noise = average; 1405 dev->noisecalc.calculation_running = false; 1406 return; 1407 } 1408generate_new: 1409 b43_generate_noise_sample(dev); 1410} 1411 1412static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1413{ 1414 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) { 1415 ///TODO: PS TBTT 1416 } else { 1417 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1418 b43_power_saving_ctl_bits(dev, 0); 1419 } 1420 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 1421 dev->dfq_valid = true; 1422} 1423 1424static void handle_irq_atim_end(struct b43_wldev *dev) 1425{ 1426 if (dev->dfq_valid) { 1427 b43_write32(dev, B43_MMIO_MACCMD, 1428 b43_read32(dev, B43_MMIO_MACCMD) 1429 | B43_MACCMD_DFQ_VALID); 1430 dev->dfq_valid = false; 1431 } 1432} 1433 1434static void handle_irq_pmq(struct b43_wldev *dev) 1435{ 1436 u32 tmp; 1437 1438 //TODO: AP mode. 1439 1440 while (1) { 1441 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1442 if (!(tmp & 0x00000008)) 1443 break; 1444 } 1445 /* 16bit write is odd, but correct. */ 1446 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1447} 1448 1449static void b43_write_template_common(struct b43_wldev *dev, 1450 const u8 *data, u16 size, 1451 u16 ram_offset, 1452 u16 shm_size_offset, u8 rate) 1453{ 1454 u32 i, tmp; 1455 struct b43_plcp_hdr4 plcp; 1456 1457 plcp.data = 0; 1458 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1459 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1460 ram_offset += sizeof(u32); 1461 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1462 * So leave the first two bytes of the next write blank. 1463 */ 1464 tmp = (u32) (data[0]) << 16; 1465 tmp |= (u32) (data[1]) << 24; 1466 b43_ram_write(dev, ram_offset, tmp); 1467 ram_offset += sizeof(u32); 1468 for (i = 2; i < size; i += sizeof(u32)) { 1469 tmp = (u32) (data[i + 0]); 1470 if (i + 1 < size) 1471 tmp |= (u32) (data[i + 1]) << 8; 1472 if (i + 2 < size) 1473 tmp |= (u32) (data[i + 2]) << 16; 1474 if (i + 3 < size) 1475 tmp |= (u32) (data[i + 3]) << 24; 1476 b43_ram_write(dev, ram_offset + i - 2, tmp); 1477 } 1478 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1479 size + sizeof(struct b43_plcp_hdr6)); 1480} 1481 1482/* Check if the use of the antenna that ieee80211 told us to 1483 * use is possible. This will fall back to DEFAULT. 1484 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 1485u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 1486 u8 antenna_nr) 1487{ 1488 u8 antenna_mask; 1489 1490 if (antenna_nr == 0) { 1491 /* Zero means "use default antenna". That's always OK. */ 1492 return 0; 1493 } 1494 1495 /* Get the mask of available antennas. */ 1496 if (dev->phy.gmode) 1497 antenna_mask = dev->dev->bus_sprom->ant_available_bg; 1498 else 1499 antenna_mask = dev->dev->bus_sprom->ant_available_a; 1500 1501 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 1502 /* This antenna is not available. Fall back to default. */ 1503 return 0; 1504 } 1505 1506 return antenna_nr; 1507} 1508 1509/* Convert a b43 antenna number value to the PHY TX control value. */ 1510static u16 b43_antenna_to_phyctl(int antenna) 1511{ 1512 switch (antenna) { 1513 case B43_ANTENNA0: 1514 return B43_TXH_PHY_ANT0; 1515 case B43_ANTENNA1: 1516 return B43_TXH_PHY_ANT1; 1517 case B43_ANTENNA2: 1518 return B43_TXH_PHY_ANT2; 1519 case B43_ANTENNA3: 1520 return B43_TXH_PHY_ANT3; 1521 case B43_ANTENNA_AUTO0: 1522 case B43_ANTENNA_AUTO1: 1523 return B43_TXH_PHY_ANT01AUTO; 1524 } 1525 B43_WARN_ON(1); 1526 return 0; 1527} 1528 1529static void b43_write_beacon_template(struct b43_wldev *dev, 1530 u16 ram_offset, 1531 u16 shm_size_offset) 1532{ 1533 unsigned int i, len, variable_len; 1534 const struct ieee80211_mgmt *bcn; 1535 const u8 *ie; 1536 bool tim_found = false; 1537 unsigned int rate; 1538 u16 ctl; 1539 int antenna; 1540 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon); 1541 1542 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1543 len = min((size_t) dev->wl->current_beacon->len, 1544 0x200 - sizeof(struct b43_plcp_hdr6)); 1545 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; 1546 1547 b43_write_template_common(dev, (const u8 *)bcn, 1548 len, ram_offset, shm_size_offset, rate); 1549 1550 /* Write the PHY TX control parameters. */ 1551 antenna = B43_ANTENNA_DEFAULT; 1552 antenna = b43_antenna_to_phyctl(antenna); 1553 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 1554 /* We can't send beacons with short preamble. Would get PHY errors. */ 1555 ctl &= ~B43_TXH_PHY_SHORTPRMBL; 1556 ctl &= ~B43_TXH_PHY_ANT; 1557 ctl &= ~B43_TXH_PHY_ENC; 1558 ctl |= antenna; 1559 if (b43_is_cck_rate(rate)) 1560 ctl |= B43_TXH_PHY_ENC_CCK; 1561 else 1562 ctl |= B43_TXH_PHY_ENC_OFDM; 1563 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 1564 1565 /* Find the position of the TIM and the DTIM_period value 1566 * and write them to SHM. */ 1567 ie = bcn->u.beacon.variable; 1568 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1569 for (i = 0; i < variable_len - 2; ) { 1570 uint8_t ie_id, ie_len; 1571 1572 ie_id = ie[i]; 1573 ie_len = ie[i + 1]; 1574 if (ie_id == 5) { 1575 u16 tim_position; 1576 u16 dtim_period; 1577 /* This is the TIM Information Element */ 1578 1579 /* Check whether the ie_len is in the beacon data range. */ 1580 if (variable_len < ie_len + 2 + i) 1581 break; 1582 /* A valid TIM is at least 4 bytes long. */ 1583 if (ie_len < 4) 1584 break; 1585 tim_found = true; 1586 1587 tim_position = sizeof(struct b43_plcp_hdr6); 1588 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1589 tim_position += i; 1590 1591 dtim_period = ie[i + 3]; 1592 1593 b43_shm_write16(dev, B43_SHM_SHARED, 1594 B43_SHM_SH_TIMBPOS, tim_position); 1595 b43_shm_write16(dev, B43_SHM_SHARED, 1596 B43_SHM_SH_DTIMPER, dtim_period); 1597 break; 1598 } 1599 i += ie_len + 2; 1600 } 1601 if (!tim_found) { 1602 /* 1603 * If ucode wants to modify TIM do it behind the beacon, this 1604 * will happen, for example, when doing mesh networking. 1605 */ 1606 b43_shm_write16(dev, B43_SHM_SHARED, 1607 B43_SHM_SH_TIMBPOS, 1608 len + sizeof(struct b43_plcp_hdr6)); 1609 b43_shm_write16(dev, B43_SHM_SHARED, 1610 B43_SHM_SH_DTIMPER, 0); 1611 } 1612 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); 1613} 1614 1615static void b43_upload_beacon0(struct b43_wldev *dev) 1616{ 1617 struct b43_wl *wl = dev->wl; 1618 1619 if (wl->beacon0_uploaded) 1620 return; 1621 b43_write_beacon_template(dev, 0x68, 0x18); 1622 wl->beacon0_uploaded = true; 1623} 1624 1625static void b43_upload_beacon1(struct b43_wldev *dev) 1626{ 1627 struct b43_wl *wl = dev->wl; 1628 1629 if (wl->beacon1_uploaded) 1630 return; 1631 b43_write_beacon_template(dev, 0x468, 0x1A); 1632 wl->beacon1_uploaded = true; 1633} 1634 1635static void handle_irq_beacon(struct b43_wldev *dev) 1636{ 1637 struct b43_wl *wl = dev->wl; 1638 u32 cmd, beacon0_valid, beacon1_valid; 1639 1640 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && 1641 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) && 1642 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 1643 return; 1644 1645 /* This is the bottom half of the asynchronous beacon update. */ 1646 1647 /* Ignore interrupt in the future. */ 1648 dev->irq_mask &= ~B43_IRQ_BEACON; 1649 1650 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1651 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); 1652 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); 1653 1654 /* Schedule interrupt manually, if busy. */ 1655 if (beacon0_valid && beacon1_valid) { 1656 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1657 dev->irq_mask |= B43_IRQ_BEACON; 1658 return; 1659 } 1660 1661 if (unlikely(wl->beacon_templates_virgin)) { 1662 /* We never uploaded a beacon before. 1663 * Upload both templates now, but only mark one valid. */ 1664 wl->beacon_templates_virgin = false; 1665 b43_upload_beacon0(dev); 1666 b43_upload_beacon1(dev); 1667 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1668 cmd |= B43_MACCMD_BEACON0_VALID; 1669 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1670 } else { 1671 if (!beacon0_valid) { 1672 b43_upload_beacon0(dev); 1673 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1674 cmd |= B43_MACCMD_BEACON0_VALID; 1675 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1676 } else if (!beacon1_valid) { 1677 b43_upload_beacon1(dev); 1678 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1679 cmd |= B43_MACCMD_BEACON1_VALID; 1680 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1681 } 1682 } 1683} 1684 1685static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev) 1686{ 1687 u32 old_irq_mask = dev->irq_mask; 1688 1689 /* update beacon right away or defer to irq */ 1690 handle_irq_beacon(dev); 1691 if (old_irq_mask != dev->irq_mask) { 1692 /* The handler updated the IRQ mask. */ 1693 B43_WARN_ON(!dev->irq_mask); 1694 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) { 1695 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1696 } else { 1697 /* Device interrupts are currently disabled. That means 1698 * we just ran the hardirq handler and scheduled the 1699 * IRQ thread. The thread will write the IRQ mask when 1700 * it finished, so there's nothing to do here. Writing 1701 * the mask _here_ would incorrectly re-enable IRQs. */ 1702 } 1703 } 1704} 1705 1706static void b43_beacon_update_trigger_work(struct work_struct *work) 1707{ 1708 struct b43_wl *wl = container_of(work, struct b43_wl, 1709 beacon_update_trigger); 1710 struct b43_wldev *dev; 1711 1712 mutex_lock(&wl->mutex); 1713 dev = wl->current_dev; 1714 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { 1715 if (b43_bus_host_is_sdio(dev->dev)) { 1716 /* wl->mutex is enough. */ 1717 b43_do_beacon_update_trigger_work(dev); 1718 mmiowb(); 1719 } else { 1720 spin_lock_irq(&wl->hardirq_lock); 1721 b43_do_beacon_update_trigger_work(dev); 1722 mmiowb(); 1723 spin_unlock_irq(&wl->hardirq_lock); 1724 } 1725 } 1726 mutex_unlock(&wl->mutex); 1727} 1728 1729/* Asynchronously update the packet templates in template RAM. 1730 * Locking: Requires wl->mutex to be locked. */ 1731static void b43_update_templates(struct b43_wl *wl) 1732{ 1733 struct sk_buff *beacon; 1734 1735 /* This is the top half of the ansynchronous beacon update. 1736 * The bottom half is the beacon IRQ. 1737 * Beacon update must be asynchronous to avoid sending an 1738 * invalid beacon. This can happen for example, if the firmware 1739 * transmits a beacon while we are updating it. */ 1740 1741 /* We could modify the existing beacon and set the aid bit in 1742 * the TIM field, but that would probably require resizing and 1743 * moving of data within the beacon template. 1744 * Simply request a new beacon and let mac80211 do the hard work. */ 1745 beacon = ieee80211_beacon_get(wl->hw, wl->vif); 1746 if (unlikely(!beacon)) 1747 return; 1748 1749 if (wl->current_beacon) 1750 dev_kfree_skb_any(wl->current_beacon); 1751 wl->current_beacon = beacon; 1752 wl->beacon0_uploaded = false; 1753 wl->beacon1_uploaded = false; 1754 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); 1755} 1756 1757static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1758{ 1759 b43_time_lock(dev); 1760 if (dev->dev->core_rev >= 3) { 1761 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); 1762 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); 1763 } else { 1764 b43_write16(dev, 0x606, (beacon_int >> 6)); 1765 b43_write16(dev, 0x610, beacon_int); 1766 } 1767 b43_time_unlock(dev); 1768 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1769} 1770 1771static void b43_handle_firmware_panic(struct b43_wldev *dev) 1772{ 1773 u16 reason; 1774 1775 /* Read the register that contains the reason code for the panic. */ 1776 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG); 1777 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason); 1778 1779 switch (reason) { 1780 default: 1781 b43dbg(dev->wl, "The panic reason is unknown.\n"); 1782 /* fallthrough */ 1783 case B43_FWPANIC_DIE: 1784 /* Do not restart the controller or firmware. 1785 * The device is nonfunctional from now on. 1786 * Restarting would result in this panic to trigger again, 1787 * so we avoid that recursion. */ 1788 break; 1789 case B43_FWPANIC_RESTART: 1790 b43_controller_restart(dev, "Microcode panic"); 1791 break; 1792 } 1793} 1794 1795static void handle_irq_ucode_debug(struct b43_wldev *dev) 1796{ 1797 unsigned int i, cnt; 1798 u16 reason, marker_id, marker_line; 1799 __le16 *buf; 1800 1801 /* The proprietary firmware doesn't have this IRQ. */ 1802 if (!dev->fw.opensource) 1803 return; 1804 1805 /* Read the register that contains the reason code for this IRQ. */ 1806 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG); 1807 1808 switch (reason) { 1809 case B43_DEBUGIRQ_PANIC: 1810 b43_handle_firmware_panic(dev); 1811 break; 1812 case B43_DEBUGIRQ_DUMP_SHM: 1813 if (!B43_DEBUG) 1814 break; /* Only with driver debugging enabled. */ 1815 buf = kmalloc(4096, GFP_ATOMIC); 1816 if (!buf) { 1817 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n"); 1818 goto out; 1819 } 1820 for (i = 0; i < 4096; i += 2) { 1821 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i); 1822 buf[i / 2] = cpu_to_le16(tmp); 1823 } 1824 b43info(dev->wl, "Shared memory dump:\n"); 1825 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 1826 16, 2, buf, 4096, 1); 1827 kfree(buf); 1828 break; 1829 case B43_DEBUGIRQ_DUMP_REGS: 1830 if (!B43_DEBUG) 1831 break; /* Only with driver debugging enabled. */ 1832 b43info(dev->wl, "Microcode register dump:\n"); 1833 for (i = 0, cnt = 0; i < 64; i++) { 1834 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i); 1835 if (cnt == 0) 1836 printk(KERN_INFO); 1837 printk("r%02u: 0x%04X ", i, tmp); 1838 cnt++; 1839 if (cnt == 6) { 1840 printk("\n"); 1841 cnt = 0; 1842 } 1843 } 1844 printk("\n"); 1845 break; 1846 case B43_DEBUGIRQ_MARKER: 1847 if (!B43_DEBUG) 1848 break; /* Only with driver debugging enabled. */ 1849 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH, 1850 B43_MARKER_ID_REG); 1851 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH, 1852 B43_MARKER_LINE_REG); 1853 b43info(dev->wl, "The firmware just executed the MARKER(%u) " 1854 "at line number %u\n", 1855 marker_id, marker_line); 1856 break; 1857 default: 1858 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n", 1859 reason); 1860 } 1861out: 1862 /* Acknowledge the debug-IRQ, so the firmware can continue. */ 1863 b43_shm_write16(dev, B43_SHM_SCRATCH, 1864 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK); 1865} 1866 1867static void b43_do_interrupt_thread(struct b43_wldev *dev) 1868{ 1869 u32 reason; 1870 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1871 u32 merged_dma_reason = 0; 1872 int i; 1873 1874 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 1875 return; 1876 1877 reason = dev->irq_reason; 1878 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1879 dma_reason[i] = dev->dma_reason[i]; 1880 merged_dma_reason |= dma_reason[i]; 1881 } 1882 1883 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1884 b43err(dev->wl, "MAC transmission error\n"); 1885 1886 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1887 b43err(dev->wl, "PHY transmission error\n"); 1888 rmb(); 1889 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1890 atomic_set(&dev->phy.txerr_cnt, 1891 B43_PHY_TX_BADNESS_LIMIT); 1892 b43err(dev->wl, "Too many PHY TX errors, " 1893 "restarting the controller\n"); 1894 b43_controller_restart(dev, "PHY TX errors"); 1895 } 1896 } 1897 1898 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1899 B43_DMAIRQ_NONFATALMASK))) { 1900 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1901 b43err(dev->wl, "Fatal DMA error: " 1902 "0x%08X, 0x%08X, 0x%08X, " 1903 "0x%08X, 0x%08X, 0x%08X\n", 1904 dma_reason[0], dma_reason[1], 1905 dma_reason[2], dma_reason[3], 1906 dma_reason[4], dma_reason[5]); 1907 b43err(dev->wl, "This device does not support DMA " 1908 "on your system. It will now be switched to PIO.\n"); 1909 /* Fall back to PIO transfers if we get fatal DMA errors! */ 1910 dev->use_pio = true; 1911 b43_controller_restart(dev, "DMA error"); 1912 return; 1913 } 1914 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1915 b43err(dev->wl, "DMA error: " 1916 "0x%08X, 0x%08X, 0x%08X, " 1917 "0x%08X, 0x%08X, 0x%08X\n", 1918 dma_reason[0], dma_reason[1], 1919 dma_reason[2], dma_reason[3], 1920 dma_reason[4], dma_reason[5]); 1921 } 1922 } 1923 1924 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1925 handle_irq_ucode_debug(dev); 1926 if (reason & B43_IRQ_TBTT_INDI) 1927 handle_irq_tbtt_indication(dev); 1928 if (reason & B43_IRQ_ATIM_END) 1929 handle_irq_atim_end(dev); 1930 if (reason & B43_IRQ_BEACON) 1931 handle_irq_beacon(dev); 1932 if (reason & B43_IRQ_PMQ) 1933 handle_irq_pmq(dev); 1934 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1935 ;/* TODO */ 1936 if (reason & B43_IRQ_NOISESAMPLE_OK) 1937 handle_irq_noise(dev); 1938 1939 /* Check the DMA reason registers for received data. */ 1940 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 1941 if (b43_using_pio_transfers(dev)) 1942 b43_pio_rx(dev->pio.rx_queue); 1943 else 1944 b43_dma_rx(dev->dma.rx_ring); 1945 } 1946 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1947 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1948 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); 1949 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1950 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1951 1952 if (reason & B43_IRQ_TX_OK) 1953 handle_irq_transmit_status(dev); 1954 1955 /* Re-enable interrupts on the device by restoring the current interrupt mask. */ 1956 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1957 1958#if B43_DEBUG 1959 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 1960 dev->irq_count++; 1961 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 1962 if (reason & (1 << i)) 1963 dev->irq_bit_count[i]++; 1964 } 1965 } 1966#endif 1967} 1968 1969/* Interrupt thread handler. Handles device interrupts in thread context. */ 1970static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id) 1971{ 1972 struct b43_wldev *dev = dev_id; 1973 1974 mutex_lock(&dev->wl->mutex); 1975 b43_do_interrupt_thread(dev); 1976 mmiowb(); 1977 mutex_unlock(&dev->wl->mutex); 1978 1979 return IRQ_HANDLED; 1980} 1981 1982static irqreturn_t b43_do_interrupt(struct b43_wldev *dev) 1983{ 1984 u32 reason; 1985 1986 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses. 1987 * On SDIO, this runs under wl->mutex. */ 1988 1989 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1990 if (reason == 0xffffffff) /* shared IRQ */ 1991 return IRQ_NONE; 1992 reason &= dev->irq_mask; 1993 if (!reason) 1994 return IRQ_NONE; 1995 1996 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1997 & 0x0001DC00; 1998 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1999 & 0x0000DC00; 2000 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 2001 & 0x0000DC00; 2002 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 2003 & 0x0001DC00; 2004 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 2005 & 0x0000DC00; 2006/* Unused ring 2007 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 2008 & 0x0000DC00; 2009*/ 2010 2011 /* ACK the interrupt. */ 2012 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 2013 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 2014 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 2015 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 2016 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 2017 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 2018/* Unused ring 2019 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 2020*/ 2021 2022 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */ 2023 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 2024 /* Save the reason bitmasks for the IRQ thread handler. */ 2025 dev->irq_reason = reason; 2026 2027 return IRQ_WAKE_THREAD; 2028} 2029 2030/* Interrupt handler top-half. This runs with interrupts disabled. */ 2031static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 2032{ 2033 struct b43_wldev *dev = dev_id; 2034 irqreturn_t ret; 2035 2036 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2037 return IRQ_NONE; 2038 2039 spin_lock(&dev->wl->hardirq_lock); 2040 ret = b43_do_interrupt(dev); 2041 mmiowb(); 2042 spin_unlock(&dev->wl->hardirq_lock); 2043 2044 return ret; 2045} 2046 2047/* SDIO interrupt handler. This runs in process context. */ 2048static void b43_sdio_interrupt_handler(struct b43_wldev *dev) 2049{ 2050 struct b43_wl *wl = dev->wl; 2051 irqreturn_t ret; 2052 2053 mutex_lock(&wl->mutex); 2054 2055 ret = b43_do_interrupt(dev); 2056 if (ret == IRQ_WAKE_THREAD) 2057 b43_do_interrupt_thread(dev); 2058 2059 mutex_unlock(&wl->mutex); 2060} 2061 2062void b43_do_release_fw(struct b43_firmware_file *fw) 2063{ 2064 release_firmware(fw->data); 2065 fw->data = NULL; 2066 fw->filename = NULL; 2067} 2068 2069static void b43_release_firmware(struct b43_wldev *dev) 2070{ 2071 b43_do_release_fw(&dev->fw.ucode); 2072 b43_do_release_fw(&dev->fw.pcm); 2073 b43_do_release_fw(&dev->fw.initvals); 2074 b43_do_release_fw(&dev->fw.initvals_band); 2075} 2076 2077static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 2078{ 2079 const char text[] = 2080 "You must go to " \ 2081 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \ 2082 "and download the correct firmware for this driver version. " \ 2083 "Please carefully read all instructions on this website.\n"; 2084 2085 if (error) 2086 b43err(wl, text); 2087 else 2088 b43warn(wl, text); 2089} 2090 2091int b43_do_request_fw(struct b43_request_fw_context *ctx, 2092 const char *name, 2093 struct b43_firmware_file *fw) 2094{ 2095 const struct firmware *blob; 2096 struct b43_fw_header *hdr; 2097 u32 size; 2098 int err; 2099 2100 if (!name) { 2101 /* Don't fetch anything. Free possibly cached firmware. */ 2102 /* FIXME: We should probably keep it anyway, to save some headache 2103 * on suspend/resume with multiband devices. */ 2104 b43_do_release_fw(fw); 2105 return 0; 2106 } 2107 if (fw->filename) { 2108 if ((fw->type == ctx->req_type) && 2109 (strcmp(fw->filename, name) == 0)) 2110 return 0; /* Already have this fw. */ 2111 /* Free the cached firmware first. */ 2112 /* FIXME: We should probably do this later after we successfully 2113 * got the new fw. This could reduce headache with multiband devices. 2114 * We could also redesign this to cache the firmware for all possible 2115 * bands all the time. */ 2116 b43_do_release_fw(fw); 2117 } 2118 2119 switch (ctx->req_type) { 2120 case B43_FWTYPE_PROPRIETARY: 2121 snprintf(ctx->fwname, sizeof(ctx->fwname), 2122 "b43%s/%s.fw", 2123 modparam_fwpostfix, name); 2124 break; 2125 case B43_FWTYPE_OPENSOURCE: 2126 snprintf(ctx->fwname, sizeof(ctx->fwname), 2127 "b43-open%s/%s.fw", 2128 modparam_fwpostfix, name); 2129 break; 2130 default: 2131 B43_WARN_ON(1); 2132 return -ENOSYS; 2133 } 2134 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev); 2135 if (err == -ENOENT) { 2136 snprintf(ctx->errors[ctx->req_type], 2137 sizeof(ctx->errors[ctx->req_type]), 2138 "Firmware file \"%s\" not found\n", ctx->fwname); 2139 return err; 2140 } else if (err) { 2141 snprintf(ctx->errors[ctx->req_type], 2142 sizeof(ctx->errors[ctx->req_type]), 2143 "Firmware file \"%s\" request failed (err=%d)\n", 2144 ctx->fwname, err); 2145 return err; 2146 } 2147 if (blob->size < sizeof(struct b43_fw_header)) 2148 goto err_format; 2149 hdr = (struct b43_fw_header *)(blob->data); 2150 switch (hdr->type) { 2151 case B43_FW_TYPE_UCODE: 2152 case B43_FW_TYPE_PCM: 2153 size = be32_to_cpu(hdr->size); 2154 if (size != blob->size - sizeof(struct b43_fw_header)) 2155 goto err_format; 2156 /* fallthrough */ 2157 case B43_FW_TYPE_IV: 2158 if (hdr->ver != 1) 2159 goto err_format; 2160 break; 2161 default: 2162 goto err_format; 2163 } 2164 2165 fw->data = blob; 2166 fw->filename = name; 2167 fw->type = ctx->req_type; 2168 2169 return 0; 2170 2171err_format: 2172 snprintf(ctx->errors[ctx->req_type], 2173 sizeof(ctx->errors[ctx->req_type]), 2174 "Firmware file \"%s\" format error.\n", ctx->fwname); 2175 release_firmware(blob); 2176 2177 return -EPROTO; 2178} 2179 2180static int b43_try_request_fw(struct b43_request_fw_context *ctx) 2181{ 2182 struct b43_wldev *dev = ctx->dev; 2183 struct b43_firmware *fw = &ctx->dev->fw; 2184 const u8 rev = ctx->dev->dev->core_rev; 2185 const char *filename; 2186 u32 tmshigh; 2187 int err; 2188 2189 /* Files for HT and LCN were found by trying one by one */ 2190 2191 /* Get microcode */ 2192 if ((rev >= 5) && (rev <= 10)) { 2193 filename = "ucode5"; 2194 } else if ((rev >= 11) && (rev <= 12)) { 2195 filename = "ucode11"; 2196 } else if (rev == 13) { 2197 filename = "ucode13"; 2198 } else if (rev == 14) { 2199 filename = "ucode14"; 2200 } else if (rev == 15) { 2201 filename = "ucode15"; 2202 } else { 2203 switch (dev->phy.type) { 2204 case B43_PHYTYPE_N: 2205 if (rev >= 16) 2206 filename = "ucode16_mimo"; 2207 else 2208 goto err_no_ucode; 2209 break; 2210 case B43_PHYTYPE_HT: 2211 if (rev == 29) 2212 filename = "ucode29_mimo"; 2213 else 2214 goto err_no_ucode; 2215 break; 2216 case B43_PHYTYPE_LCN: 2217 if (rev == 24) 2218 filename = "ucode24_mimo"; 2219 else 2220 goto err_no_ucode; 2221 break; 2222 default: 2223 goto err_no_ucode; 2224 } 2225 } 2226 err = b43_do_request_fw(ctx, filename, &fw->ucode); 2227 if (err) 2228 goto err_load; 2229 2230 /* Get PCM code */ 2231 if ((rev >= 5) && (rev <= 10)) 2232 filename = "pcm5"; 2233 else if (rev >= 11) 2234 filename = NULL; 2235 else 2236 goto err_no_pcm; 2237 fw->pcm_request_failed = false; 2238 err = b43_do_request_fw(ctx, filename, &fw->pcm); 2239 if (err == -ENOENT) { 2240 /* We did not find a PCM file? Not fatal, but 2241 * core rev <= 10 must do without hwcrypto then. */ 2242 fw->pcm_request_failed = true; 2243 } else if (err) 2244 goto err_load; 2245 2246 /* Get initvals */ 2247 switch (dev->phy.type) { 2248 case B43_PHYTYPE_A: 2249 if ((rev >= 5) && (rev <= 10)) { 2250 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 2251 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2252 filename = "a0g1initvals5"; 2253 else 2254 filename = "a0g0initvals5"; 2255 } else 2256 goto err_no_initvals; 2257 break; 2258 case B43_PHYTYPE_G: 2259 if ((rev >= 5) && (rev <= 10)) 2260 filename = "b0g0initvals5"; 2261 else if (rev >= 13) 2262 filename = "b0g0initvals13"; 2263 else 2264 goto err_no_initvals; 2265 break; 2266 case B43_PHYTYPE_N: 2267 if (rev >= 16) 2268 filename = "n0initvals16"; 2269 else if ((rev >= 11) && (rev <= 12)) 2270 filename = "n0initvals11"; 2271 else 2272 goto err_no_initvals; 2273 break; 2274 case B43_PHYTYPE_LP: 2275 if (rev == 13) 2276 filename = "lp0initvals13"; 2277 else if (rev == 14) 2278 filename = "lp0initvals14"; 2279 else if (rev >= 15) 2280 filename = "lp0initvals15"; 2281 else 2282 goto err_no_initvals; 2283 break; 2284 case B43_PHYTYPE_HT: 2285 if (rev == 29) 2286 filename = "ht0initvals29"; 2287 else 2288 goto err_no_initvals; 2289 break; 2290 case B43_PHYTYPE_LCN: 2291 if (rev == 24) 2292 filename = "lcn0initvals24"; 2293 else 2294 goto err_no_initvals; 2295 break; 2296 default: 2297 goto err_no_initvals; 2298 } 2299 err = b43_do_request_fw(ctx, filename, &fw->initvals); 2300 if (err) 2301 goto err_load; 2302 2303 /* Get bandswitch initvals */ 2304 switch (dev->phy.type) { 2305 case B43_PHYTYPE_A: 2306 if ((rev >= 5) && (rev <= 10)) { 2307 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 2308 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2309 filename = "a0g1bsinitvals5"; 2310 else 2311 filename = "a0g0bsinitvals5"; 2312 } else if (rev >= 11) 2313 filename = NULL; 2314 else 2315 goto err_no_initvals; 2316 break; 2317 case B43_PHYTYPE_G: 2318 if ((rev >= 5) && (rev <= 10)) 2319 filename = "b0g0bsinitvals5"; 2320 else if (rev >= 11) 2321 filename = NULL; 2322 else 2323 goto err_no_initvals; 2324 break; 2325 case B43_PHYTYPE_N: 2326 if (rev >= 16) 2327 filename = "n0bsinitvals16"; 2328 else if ((rev >= 11) && (rev <= 12)) 2329 filename = "n0bsinitvals11"; 2330 else 2331 goto err_no_initvals; 2332 break; 2333 case B43_PHYTYPE_LP: 2334 if (rev == 13) 2335 filename = "lp0bsinitvals13"; 2336 else if (rev == 14) 2337 filename = "lp0bsinitvals14"; 2338 else if (rev >= 15) 2339 filename = "lp0bsinitvals15"; 2340 else 2341 goto err_no_initvals; 2342 break; 2343 case B43_PHYTYPE_HT: 2344 if (rev == 29) 2345 filename = "ht0bsinitvals29"; 2346 else 2347 goto err_no_initvals; 2348 break; 2349 case B43_PHYTYPE_LCN: 2350 if (rev == 24) 2351 filename = "lcn0bsinitvals24"; 2352 else 2353 goto err_no_initvals; 2354 break; 2355 default: 2356 goto err_no_initvals; 2357 } 2358 err = b43_do_request_fw(ctx, filename, &fw->initvals_band); 2359 if (err) 2360 goto err_load; 2361 2362 return 0; 2363 2364err_no_ucode: 2365 err = ctx->fatal_failure = -EOPNOTSUPP; 2366 b43err(dev->wl, "The driver does not know which firmware (ucode) " 2367 "is required for your device (wl-core rev %u)\n", rev); 2368 goto error; 2369 2370err_no_pcm: 2371 err = ctx->fatal_failure = -EOPNOTSUPP; 2372 b43err(dev->wl, "The driver does not know which firmware (PCM) " 2373 "is required for your device (wl-core rev %u)\n", rev); 2374 goto error; 2375 2376err_no_initvals: 2377 err = ctx->fatal_failure = -EOPNOTSUPP; 2378 b43err(dev->wl, "The driver does not know which firmware (initvals) " 2379 "is required for your device (wl-core rev %u)\n", rev); 2380 goto error; 2381 2382err_load: 2383 /* We failed to load this firmware image. The error message 2384 * already is in ctx->errors. Return and let our caller decide 2385 * what to do. */ 2386 goto error; 2387 2388error: 2389 b43_release_firmware(dev); 2390 return err; 2391} 2392 2393static int b43_request_firmware(struct b43_wldev *dev) 2394{ 2395 struct b43_request_fw_context *ctx; 2396 unsigned int i; 2397 int err; 2398 const char *errmsg; 2399 2400 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2401 if (!ctx) 2402 return -ENOMEM; 2403 ctx->dev = dev; 2404 2405 ctx->req_type = B43_FWTYPE_PROPRIETARY; 2406 err = b43_try_request_fw(ctx); 2407 if (!err) 2408 goto out; /* Successfully loaded it. */ 2409 err = ctx->fatal_failure; 2410 if (err) 2411 goto out; 2412 2413 ctx->req_type = B43_FWTYPE_OPENSOURCE; 2414 err = b43_try_request_fw(ctx); 2415 if (!err) 2416 goto out; /* Successfully loaded it. */ 2417 err = ctx->fatal_failure; 2418 if (err) 2419 goto out; 2420 2421 /* Could not find a usable firmware. Print the errors. */ 2422 for (i = 0; i < B43_NR_FWTYPES; i++) { 2423 errmsg = ctx->errors[i]; 2424 if (strlen(errmsg)) 2425 b43err(dev->wl, errmsg); 2426 } 2427 b43_print_fw_helptext(dev->wl, 1); 2428 err = -ENOENT; 2429 2430out: 2431 kfree(ctx); 2432 return err; 2433} 2434 2435static int b43_upload_microcode(struct b43_wldev *dev) 2436{ 2437 struct wiphy *wiphy = dev->wl->hw->wiphy; 2438 const size_t hdr_len = sizeof(struct b43_fw_header); 2439 const __be32 *data; 2440 unsigned int i, len; 2441 u16 fwrev, fwpatch, fwdate, fwtime; 2442 u32 tmp, macctl; 2443 int err = 0; 2444 2445 /* Jump the microcode PSM to offset 0 */ 2446 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2447 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); 2448 macctl |= B43_MACCTL_PSM_JMP0; 2449 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2450 /* Zero out all microcode PSM registers and shared memory. */ 2451 for (i = 0; i < 64; i++) 2452 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); 2453 for (i = 0; i < 4096; i += 2) 2454 b43_shm_write16(dev, B43_SHM_SHARED, i, 0); 2455 2456 /* Upload Microcode. */ 2457 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); 2458 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); 2459 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 2460 for (i = 0; i < len; i++) { 2461 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2462 udelay(10); 2463 } 2464 2465 if (dev->fw.pcm.data) { 2466 /* Upload PCM data. */ 2467 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); 2468 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); 2469 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 2470 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 2471 /* No need for autoinc bit in SHM_HW */ 2472 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 2473 for (i = 0; i < len; i++) { 2474 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2475 udelay(10); 2476 } 2477 } 2478 2479 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 2480 2481 /* Start the microcode PSM */ 2482 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0, 2483 B43_MACCTL_PSM_RUN); 2484 2485 /* Wait for the microcode to load and respond */ 2486 i = 0; 2487 while (1) { 2488 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2489 if (tmp == B43_IRQ_MAC_SUSPENDED) 2490 break; 2491 i++; 2492 if (i >= 20) { 2493 b43err(dev->wl, "Microcode not responding\n"); 2494 b43_print_fw_helptext(dev->wl, 1); 2495 err = -ENODEV; 2496 goto error; 2497 } 2498 msleep(50); 2499 } 2500 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 2501 2502 /* Get and check the revisions. */ 2503 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 2504 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 2505 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 2506 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 2507 2508 if (fwrev <= 0x128) { 2509 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 2510 "binary drivers older than version 4.x is unsupported. " 2511 "You must upgrade your firmware files.\n"); 2512 b43_print_fw_helptext(dev->wl, 1); 2513 err = -EOPNOTSUPP; 2514 goto error; 2515 } 2516 dev->fw.rev = fwrev; 2517 dev->fw.patch = fwpatch; 2518 if (dev->fw.rev >= 598) 2519 dev->fw.hdr_format = B43_FW_HDR_598; 2520 else if (dev->fw.rev >= 410) 2521 dev->fw.hdr_format = B43_FW_HDR_410; 2522 else 2523 dev->fw.hdr_format = B43_FW_HDR_351; 2524 dev->fw.opensource = (fwdate == 0xFFFF); 2525 2526 /* Default to use-all-queues. */ 2527 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues; 2528 dev->qos_enabled = !!modparam_qos; 2529 /* Default to firmware/hardware crypto acceleration. */ 2530 dev->hwcrypto_enabled = true; 2531 2532 if (dev->fw.opensource) { 2533 u16 fwcapa; 2534 2535 /* Patchlevel info is encoded in the "time" field. */ 2536 dev->fw.patch = fwtime; 2537 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n", 2538 dev->fw.rev, dev->fw.patch); 2539 2540 fwcapa = b43_fwcapa_read(dev); 2541 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) { 2542 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n"); 2543 /* Disable hardware crypto and fall back to software crypto. */ 2544 dev->hwcrypto_enabled = false; 2545 } 2546 if (!(fwcapa & B43_FWCAPA_QOS)) { 2547 b43info(dev->wl, "QoS not supported by firmware\n"); 2548 /* Disable QoS. Tweak hw->queues to 1. It will be restored before 2549 * ieee80211_unregister to make sure the networking core can 2550 * properly free possible resources. */ 2551 dev->wl->hw->queues = 1; 2552 dev->qos_enabled = false; 2553 } 2554 } else { 2555 b43info(dev->wl, "Loading firmware version %u.%u " 2556 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 2557 fwrev, fwpatch, 2558 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 2559 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 2560 if (dev->fw.pcm_request_failed) { 2561 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. " 2562 "Hardware accelerated cryptography is disabled.\n"); 2563 b43_print_fw_helptext(dev->wl, 0); 2564 } 2565 } 2566 2567 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", 2568 dev->fw.rev, dev->fw.patch); 2569 wiphy->hw_version = dev->dev->core_id; 2570 2571 if (dev->fw.hdr_format == B43_FW_HDR_351) { 2572 /* We're over the deadline, but we keep support for old fw 2573 * until it turns out to be in major conflict with something new. */ 2574 b43warn(dev->wl, "You are using an old firmware image. " 2575 "Support for old firmware will be removed soon " 2576 "(official deadline was July 2008).\n"); 2577 b43_print_fw_helptext(dev->wl, 0); 2578 } 2579 2580 return 0; 2581 2582error: 2583 /* Stop the microcode PSM. */ 2584 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN, 2585 B43_MACCTL_PSM_JMP0); 2586 2587 return err; 2588} 2589 2590static int b43_write_initvals(struct b43_wldev *dev, 2591 const struct b43_iv *ivals, 2592 size_t count, 2593 size_t array_size) 2594{ 2595 const struct b43_iv *iv; 2596 u16 offset; 2597 size_t i; 2598 bool bit32; 2599 2600 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 2601 iv = ivals; 2602 for (i = 0; i < count; i++) { 2603 if (array_size < sizeof(iv->offset_size)) 2604 goto err_format; 2605 array_size -= sizeof(iv->offset_size); 2606 offset = be16_to_cpu(iv->offset_size); 2607 bit32 = !!(offset & B43_IV_32BIT); 2608 offset &= B43_IV_OFFSET_MASK; 2609 if (offset >= 0x1000) 2610 goto err_format; 2611 if (bit32) { 2612 u32 value; 2613 2614 if (array_size < sizeof(iv->data.d32)) 2615 goto err_format; 2616 array_size -= sizeof(iv->data.d32); 2617 2618 value = get_unaligned_be32(&iv->data.d32); 2619 b43_write32(dev, offset, value); 2620 2621 iv = (const struct b43_iv *)((const uint8_t *)iv + 2622 sizeof(__be16) + 2623 sizeof(__be32)); 2624 } else { 2625 u16 value; 2626 2627 if (array_size < sizeof(iv->data.d16)) 2628 goto err_format; 2629 array_size -= sizeof(iv->data.d16); 2630 2631 value = be16_to_cpu(iv->data.d16); 2632 b43_write16(dev, offset, value); 2633 2634 iv = (const struct b43_iv *)((const uint8_t *)iv + 2635 sizeof(__be16) + 2636 sizeof(__be16)); 2637 } 2638 } 2639 if (array_size) 2640 goto err_format; 2641 2642 return 0; 2643 2644err_format: 2645 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 2646 b43_print_fw_helptext(dev->wl, 1); 2647 2648 return -EPROTO; 2649} 2650 2651static int b43_upload_initvals(struct b43_wldev *dev) 2652{ 2653 const size_t hdr_len = sizeof(struct b43_fw_header); 2654 const struct b43_fw_header *hdr; 2655 struct b43_firmware *fw = &dev->fw; 2656 const struct b43_iv *ivals; 2657 size_t count; 2658 int err; 2659 2660 hdr = (const struct b43_fw_header *)(fw->initvals.data->data); 2661 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); 2662 count = be32_to_cpu(hdr->size); 2663 err = b43_write_initvals(dev, ivals, count, 2664 fw->initvals.data->size - hdr_len); 2665 if (err) 2666 goto out; 2667 if (fw->initvals_band.data) { 2668 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); 2669 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); 2670 count = be32_to_cpu(hdr->size); 2671 err = b43_write_initvals(dev, ivals, count, 2672 fw->initvals_band.data->size - hdr_len); 2673 if (err) 2674 goto out; 2675 } 2676out: 2677 2678 return err; 2679} 2680 2681/* Initialize the GPIOs 2682 * http://bcm-specs.sipsolutions.net/GPIO 2683 */ 2684static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev) 2685{ 2686 struct ssb_bus *bus = dev->dev->sdev->bus; 2687 2688#ifdef CONFIG_SSB_DRIVER_PCICORE 2689 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev); 2690#else 2691 return bus->chipco.dev; 2692#endif 2693} 2694 2695static int b43_gpio_init(struct b43_wldev *dev) 2696{ 2697 struct ssb_device *gpiodev; 2698 u32 mask, set; 2699 2700 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); 2701 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF); 2702 2703 mask = 0x0000001F; 2704 set = 0x0000000F; 2705 if (dev->dev->chip_id == 0x4301) { 2706 mask |= 0x0060; 2707 set |= 0x0060; 2708 } 2709 if (0 /* FIXME: conditional unknown */ ) { 2710 b43_write16(dev, B43_MMIO_GPIO_MASK, 2711 b43_read16(dev, B43_MMIO_GPIO_MASK) 2712 | 0x0100); 2713 mask |= 0x0180; 2714 set |= 0x0180; 2715 } 2716 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) { 2717 b43_write16(dev, B43_MMIO_GPIO_MASK, 2718 b43_read16(dev, B43_MMIO_GPIO_MASK) 2719 | 0x0200); 2720 mask |= 0x0200; 2721 set |= 0x0200; 2722 } 2723 if (dev->dev->core_rev >= 2) 2724 mask |= 0x0010; /* FIXME: This is redundant. */ 2725 2726 switch (dev->dev->bus_type) { 2727#ifdef CONFIG_B43_BCMA 2728 case B43_BUS_BCMA: 2729 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL, 2730 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc, 2731 BCMA_CC_GPIOCTL) & mask) | set); 2732 break; 2733#endif 2734#ifdef CONFIG_B43_SSB 2735 case B43_BUS_SSB: 2736 gpiodev = b43_ssb_gpio_dev(dev); 2737 if (gpiodev) 2738 ssb_write32(gpiodev, B43_GPIO_CONTROL, 2739 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2740 & mask) | set); 2741 break; 2742#endif 2743 } 2744 2745 return 0; 2746} 2747 2748/* Turn off all GPIO stuff. Call this on module unload, for example. */ 2749static void b43_gpio_cleanup(struct b43_wldev *dev) 2750{ 2751 struct ssb_device *gpiodev; 2752 2753 switch (dev->dev->bus_type) { 2754#ifdef CONFIG_B43_BCMA 2755 case B43_BUS_BCMA: 2756 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL, 2757 0); 2758 break; 2759#endif 2760#ifdef CONFIG_B43_SSB 2761 case B43_BUS_SSB: 2762 gpiodev = b43_ssb_gpio_dev(dev); 2763 if (gpiodev) 2764 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2765 break; 2766#endif 2767 } 2768} 2769 2770/* http://bcm-specs.sipsolutions.net/EnableMac */ 2771void b43_mac_enable(struct b43_wldev *dev) 2772{ 2773 if (b43_debug(dev, B43_DBG_FIRMWARE)) { 2774 u16 fwstate; 2775 2776 fwstate = b43_shm_read16(dev, B43_SHM_SHARED, 2777 B43_SHM_SH_UCODESTAT); 2778 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) && 2779 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) { 2780 b43err(dev->wl, "b43_mac_enable(): The firmware " 2781 "should be suspended, but current state is %u\n", 2782 fwstate); 2783 } 2784 } 2785 2786 dev->mac_suspended--; 2787 B43_WARN_ON(dev->mac_suspended < 0); 2788 if (dev->mac_suspended == 0) { 2789 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED); 2790 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2791 B43_IRQ_MAC_SUSPENDED); 2792 /* Commit writes */ 2793 b43_read32(dev, B43_MMIO_MACCTL); 2794 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2795 b43_power_saving_ctl_bits(dev, 0); 2796 } 2797} 2798 2799/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2800void b43_mac_suspend(struct b43_wldev *dev) 2801{ 2802 int i; 2803 u32 tmp; 2804 2805 might_sleep(); 2806 B43_WARN_ON(dev->mac_suspended < 0); 2807 2808 if (dev->mac_suspended == 0) { 2809 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2810 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0); 2811 /* force pci to flush the write */ 2812 b43_read32(dev, B43_MMIO_MACCTL); 2813 for (i = 35; i; i--) { 2814 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2815 if (tmp & B43_IRQ_MAC_SUSPENDED) 2816 goto out; 2817 udelay(10); 2818 } 2819 /* Hm, it seems this will take some time. Use msleep(). */ 2820 for (i = 40; i; i--) { 2821 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2822 if (tmp & B43_IRQ_MAC_SUSPENDED) 2823 goto out; 2824 msleep(1); 2825 } 2826 b43err(dev->wl, "MAC suspend failed\n"); 2827 } 2828out: 2829 dev->mac_suspended++; 2830} 2831 2832/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 2833void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on) 2834{ 2835 u32 tmp; 2836 2837 switch (dev->dev->bus_type) { 2838#ifdef CONFIG_B43_BCMA 2839 case B43_BUS_BCMA: 2840 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 2841 if (on) 2842 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN; 2843 else 2844 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN; 2845 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); 2846 break; 2847#endif 2848#ifdef CONFIG_B43_SSB 2849 case B43_BUS_SSB: 2850 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 2851 if (on) 2852 tmp |= B43_TMSLOW_MACPHYCLKEN; 2853 else 2854 tmp &= ~B43_TMSLOW_MACPHYCLKEN; 2855 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 2856 break; 2857#endif 2858 } 2859} 2860 2861static void b43_adjust_opmode(struct b43_wldev *dev) 2862{ 2863 struct b43_wl *wl = dev->wl; 2864 u32 ctl; 2865 u16 cfp_pretbtt; 2866 2867 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2868 /* Reset status to STA infrastructure mode. */ 2869 ctl &= ~B43_MACCTL_AP; 2870 ctl &= ~B43_MACCTL_KEEP_CTL; 2871 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2872 ctl &= ~B43_MACCTL_KEEP_BAD; 2873 ctl &= ~B43_MACCTL_PROMISC; 2874 ctl &= ~B43_MACCTL_BEACPROMISC; 2875 ctl |= B43_MACCTL_INFRA; 2876 2877 if (b43_is_mode(wl, NL80211_IFTYPE_AP) || 2878 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 2879 ctl |= B43_MACCTL_AP; 2880 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 2881 ctl &= ~B43_MACCTL_INFRA; 2882 2883 if (wl->filter_flags & FIF_CONTROL) 2884 ctl |= B43_MACCTL_KEEP_CTL; 2885 if (wl->filter_flags & FIF_FCSFAIL) 2886 ctl |= B43_MACCTL_KEEP_BAD; 2887 if (wl->filter_flags & FIF_PLCPFAIL) 2888 ctl |= B43_MACCTL_KEEP_BADPLCP; 2889 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2890 ctl |= B43_MACCTL_PROMISC; 2891 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2892 ctl |= B43_MACCTL_BEACPROMISC; 2893 2894 /* Workaround: On old hardware the HW-MAC-address-filter 2895 * doesn't work properly, so always run promisc in filter 2896 * it in software. */ 2897 if (dev->dev->core_rev <= 4) 2898 ctl |= B43_MACCTL_PROMISC; 2899 2900 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2901 2902 cfp_pretbtt = 2; 2903 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2904 if (dev->dev->chip_id == 0x4306 && 2905 dev->dev->chip_rev == 3) 2906 cfp_pretbtt = 100; 2907 else 2908 cfp_pretbtt = 50; 2909 } 2910 b43_write16(dev, 0x612, cfp_pretbtt); 2911 2912 /* FIXME: We don't currently implement the PMQ mechanism, 2913 * so always disable it. If we want to implement PMQ, 2914 * we need to enable it here (clear DISCPMQ) in AP mode. 2915 */ 2916 if (0 /* ctl & B43_MACCTL_AP */) 2917 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0); 2918 else 2919 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ); 2920} 2921 2922static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2923{ 2924 u16 offset; 2925 2926 if (is_ofdm) { 2927 offset = 0x480; 2928 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2929 } else { 2930 offset = 0x4C0; 2931 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2932 } 2933 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2934 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2935} 2936 2937static void b43_rate_memory_init(struct b43_wldev *dev) 2938{ 2939 switch (dev->phy.type) { 2940 case B43_PHYTYPE_A: 2941 case B43_PHYTYPE_G: 2942 case B43_PHYTYPE_N: 2943 case B43_PHYTYPE_LP: 2944 case B43_PHYTYPE_HT: 2945 case B43_PHYTYPE_LCN: 2946 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2947 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2948 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2949 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2950 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2951 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2952 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2953 if (dev->phy.type == B43_PHYTYPE_A) 2954 break; 2955 /* fallthrough */ 2956 case B43_PHYTYPE_B: 2957 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2958 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2959 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2960 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2961 break; 2962 default: 2963 B43_WARN_ON(1); 2964 } 2965} 2966 2967/* Set the default values for the PHY TX Control Words. */ 2968static void b43_set_phytxctl_defaults(struct b43_wldev *dev) 2969{ 2970 u16 ctl = 0; 2971 2972 ctl |= B43_TXH_PHY_ENC_CCK; 2973 ctl |= B43_TXH_PHY_ANT01AUTO; 2974 ctl |= B43_TXH_PHY_TXPWR; 2975 2976 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 2977 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); 2978 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); 2979} 2980 2981/* Set the TX-Antenna for management frames sent by firmware. */ 2982static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2983{ 2984 u16 ant; 2985 u16 tmp; 2986 2987 ant = b43_antenna_to_phyctl(antenna); 2988 2989 /* For ACK/CTS */ 2990 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2991 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2992 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2993 /* For Probe Resposes */ 2994 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2995 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2996 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2997} 2998 2999/* This is the opposite of b43_chip_init() */ 3000static void b43_chip_exit(struct b43_wldev *dev) 3001{ 3002 b43_phy_exit(dev); 3003 b43_gpio_cleanup(dev); 3004 /* firmware is released later */ 3005} 3006 3007/* Initialize the chip 3008 * http://bcm-specs.sipsolutions.net/ChipInit 3009 */ 3010static int b43_chip_init(struct b43_wldev *dev) 3011{ 3012 struct b43_phy *phy = &dev->phy; 3013 int err; 3014 u32 macctl; 3015 u16 value16; 3016 3017 /* Initialize the MAC control */ 3018 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; 3019 if (dev->phy.gmode) 3020 macctl |= B43_MACCTL_GMODE; 3021 macctl |= B43_MACCTL_INFRA; 3022 b43_write32(dev, B43_MMIO_MACCTL, macctl); 3023 3024 err = b43_request_firmware(dev); 3025 if (err) 3026 goto out; 3027 err = b43_upload_microcode(dev); 3028 if (err) 3029 goto out; /* firmware is released later */ 3030 3031 err = b43_gpio_init(dev); 3032 if (err) 3033 goto out; /* firmware is released later */ 3034 3035 err = b43_upload_initvals(dev); 3036 if (err) 3037 goto err_gpio_clean; 3038 3039 /* Turn the Analog on and initialize the PHY. */ 3040 phy->ops->switch_analog(dev, 1); 3041 err = b43_phy_init(dev); 3042 if (err) 3043 goto err_gpio_clean; 3044 3045 /* Disable Interference Mitigation. */ 3046 if (phy->ops->interf_mitigation) 3047 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); 3048 3049 /* Select the antennae */ 3050 if (phy->ops->set_rx_antenna) 3051 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 3052 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 3053 3054 if (phy->type == B43_PHYTYPE_B) { 3055 value16 = b43_read16(dev, 0x005E); 3056 value16 |= 0x0004; 3057 b43_write16(dev, 0x005E, value16); 3058 } 3059 b43_write32(dev, 0x0100, 0x01000000); 3060 if (dev->dev->core_rev < 5) 3061 b43_write32(dev, 0x010C, 0x01000000); 3062 3063 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0); 3064 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA); 3065 3066 /* Probe Response Timeout value */ 3067 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 3068 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 3069 3070 /* Initially set the wireless operation mode. */ 3071 b43_adjust_opmode(dev); 3072 3073 if (dev->dev->core_rev < 3) { 3074 b43_write16(dev, 0x060E, 0x0000); 3075 b43_write16(dev, 0x0610, 0x8000); 3076 b43_write16(dev, 0x0604, 0x0000); 3077 b43_write16(dev, 0x0606, 0x0200); 3078 } else { 3079 b43_write32(dev, 0x0188, 0x80000000); 3080 b43_write32(dev, 0x018C, 0x02000000); 3081 } 3082 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 3083 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 3084 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 3085 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 3086 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 3087 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 3088 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 3089 3090 b43_mac_phy_clock_set(dev, true); 3091 3092 switch (dev->dev->bus_type) { 3093#ifdef CONFIG_B43_BCMA 3094 case B43_BUS_BCMA: 3095 /* FIXME: 0xE74 is quite common, but should be read from CC */ 3096 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74); 3097 break; 3098#endif 3099#ifdef CONFIG_B43_SSB 3100 case B43_BUS_SSB: 3101 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 3102 dev->dev->sdev->bus->chipco.fast_pwrup_delay); 3103 break; 3104#endif 3105 } 3106 3107 err = 0; 3108 b43dbg(dev->wl, "Chip initialized\n"); 3109out: 3110 return err; 3111 3112err_gpio_clean: 3113 b43_gpio_cleanup(dev); 3114 return err; 3115} 3116 3117static void b43_periodic_every60sec(struct b43_wldev *dev) 3118{ 3119 const struct b43_phy_operations *ops = dev->phy.ops; 3120 3121 if (ops->pwork_60sec) 3122 ops->pwork_60sec(dev); 3123 3124 /* Force check the TX power emission now. */ 3125 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME); 3126} 3127 3128static void b43_periodic_every30sec(struct b43_wldev *dev) 3129{ 3130 /* Update device statistics. */ 3131 b43_calculate_link_quality(dev); 3132} 3133 3134static void b43_periodic_every15sec(struct b43_wldev *dev) 3135{ 3136 struct b43_phy *phy = &dev->phy; 3137 u16 wdr; 3138 3139 if (dev->fw.opensource) { 3140 /* Check if the firmware is still alive. 3141 * It will reset the watchdog counter to 0 in its idle loop. */ 3142 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG); 3143 if (unlikely(wdr)) { 3144 b43err(dev->wl, "Firmware watchdog: The firmware died!\n"); 3145 b43_controller_restart(dev, "Firmware watchdog"); 3146 return; 3147 } else { 3148 b43_shm_write16(dev, B43_SHM_SCRATCH, 3149 B43_WATCHDOG_REG, 1); 3150 } 3151 } 3152 3153 if (phy->ops->pwork_15sec) 3154 phy->ops->pwork_15sec(dev); 3155 3156 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3157 wmb(); 3158 3159#if B43_DEBUG 3160 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 3161 unsigned int i; 3162 3163 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n", 3164 dev->irq_count / 15, 3165 dev->tx_count / 15, 3166 dev->rx_count / 15); 3167 dev->irq_count = 0; 3168 dev->tx_count = 0; 3169 dev->rx_count = 0; 3170 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 3171 if (dev->irq_bit_count[i]) { 3172 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", 3173 dev->irq_bit_count[i] / 15, i, (1 << i)); 3174 dev->irq_bit_count[i] = 0; 3175 } 3176 } 3177 } 3178#endif 3179} 3180 3181static void do_periodic_work(struct b43_wldev *dev) 3182{ 3183 unsigned int state; 3184 3185 state = dev->periodic_state; 3186 if (state % 4 == 0) 3187 b43_periodic_every60sec(dev); 3188 if (state % 2 == 0) 3189 b43_periodic_every30sec(dev); 3190 b43_periodic_every15sec(dev); 3191} 3192 3193/* Periodic work locking policy: 3194 * The whole periodic work handler is protected by 3195 * wl->mutex. If another lock is needed somewhere in the 3196 * pwork callchain, it's acquired in-place, where it's needed. 3197 */ 3198static void b43_periodic_work_handler(struct work_struct *work) 3199{ 3200 struct b43_wldev *dev = container_of(work, struct b43_wldev, 3201 periodic_work.work); 3202 struct b43_wl *wl = dev->wl; 3203 unsigned long delay; 3204 3205 mutex_lock(&wl->mutex); 3206 3207 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 3208 goto out; 3209 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 3210 goto out_requeue; 3211 3212 do_periodic_work(dev); 3213 3214 dev->periodic_state++; 3215out_requeue: 3216 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 3217 delay = msecs_to_jiffies(50); 3218 else 3219 delay = round_jiffies_relative(HZ * 15); 3220 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); 3221out: 3222 mutex_unlock(&wl->mutex); 3223} 3224 3225static void b43_periodic_tasks_setup(struct b43_wldev *dev) 3226{ 3227 struct delayed_work *work = &dev->periodic_work; 3228 3229 dev->periodic_state = 0; 3230 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 3231 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); 3232} 3233 3234/* Check if communication with the device works correctly. */ 3235static int b43_validate_chipaccess(struct b43_wldev *dev) 3236{ 3237 u32 v, backup0, backup4; 3238 3239 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); 3240 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4); 3241 3242 /* Check for read/write and endianness problems. */ 3243 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 3244 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 3245 goto error; 3246 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 3247 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 3248 goto error; 3249 3250 /* Check if unaligned 32bit SHM_SHARED access works properly. 3251 * However, don't bail out on failure, because it's noncritical. */ 3252 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); 3253 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); 3254 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); 3255 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); 3256 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) 3257 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n"); 3258 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); 3259 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || 3260 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || 3261 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || 3262 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) 3263 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n"); 3264 3265 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); 3266 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); 3267 3268 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) { 3269 /* The 32bit register shadows the two 16bit registers 3270 * with update sideeffects. Validate this. */ 3271 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 3272 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 3273 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 3274 goto error; 3275 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 3276 goto error; 3277 } 3278 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 3279 3280 v = b43_read32(dev, B43_MMIO_MACCTL); 3281 v |= B43_MACCTL_GMODE; 3282 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 3283 goto error; 3284 3285 return 0; 3286error: 3287 b43err(dev->wl, "Failed to validate the chipaccess\n"); 3288 return -ENODEV; 3289} 3290 3291static void b43_security_init(struct b43_wldev *dev) 3292{ 3293 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 3294 /* KTP is a word address, but we address SHM bytewise. 3295 * So multiply by two. 3296 */ 3297 dev->ktp *= 2; 3298 /* Number of RCMTA address slots */ 3299 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS); 3300 /* Clear the key memory. */ 3301 b43_clear_keys(dev); 3302} 3303 3304#ifdef CONFIG_B43_HWRNG 3305static int b43_rng_read(struct hwrng *rng, u32 *data) 3306{ 3307 struct b43_wl *wl = (struct b43_wl *)rng->priv; 3308 struct b43_wldev *dev; 3309 int count = -ENODEV; 3310 3311 mutex_lock(&wl->mutex); 3312 dev = wl->current_dev; 3313 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) { 3314 *data = b43_read16(dev, B43_MMIO_RNG); 3315 count = sizeof(u16); 3316 } 3317 mutex_unlock(&wl->mutex); 3318 3319 return count; 3320} 3321#endif /* CONFIG_B43_HWRNG */ 3322 3323static void b43_rng_exit(struct b43_wl *wl) 3324{ 3325#ifdef CONFIG_B43_HWRNG 3326 if (wl->rng_initialized) 3327 hwrng_unregister(&wl->rng); 3328#endif /* CONFIG_B43_HWRNG */ 3329} 3330 3331static int b43_rng_init(struct b43_wl *wl) 3332{ 3333 int err = 0; 3334 3335#ifdef CONFIG_B43_HWRNG 3336 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 3337 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 3338 wl->rng.name = wl->rng_name; 3339 wl->rng.data_read = b43_rng_read; 3340 wl->rng.priv = (unsigned long)wl; 3341 wl->rng_initialized = true; 3342 err = hwrng_register(&wl->rng); 3343 if (err) { 3344 wl->rng_initialized = false; 3345 b43err(wl, "Failed to register the random " 3346 "number generator (%d)\n", err); 3347 } 3348#endif /* CONFIG_B43_HWRNG */ 3349 3350 return err; 3351} 3352 3353static void b43_tx_work(struct work_struct *work) 3354{ 3355 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work); 3356 struct b43_wldev *dev; 3357 struct sk_buff *skb; 3358 int queue_num; 3359 int err = 0; 3360 3361 mutex_lock(&wl->mutex); 3362 dev = wl->current_dev; 3363 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) { 3364 mutex_unlock(&wl->mutex); 3365 return; 3366 } 3367 3368 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { 3369 while (skb_queue_len(&wl->tx_queue[queue_num])) { 3370 skb = skb_dequeue(&wl->tx_queue[queue_num]); 3371 if (b43_using_pio_transfers(dev)) 3372 err = b43_pio_tx(dev, skb); 3373 else 3374 err = b43_dma_tx(dev, skb); 3375 if (err == -ENOSPC) { 3376 wl->tx_queue_stopped[queue_num] = 1; 3377 ieee80211_stop_queue(wl->hw, queue_num); 3378 skb_queue_head(&wl->tx_queue[queue_num], skb); 3379 break; 3380 } 3381 if (unlikely(err)) 3382 dev_kfree_skb(skb); /* Drop it */ 3383 err = 0; 3384 } 3385 3386 if (!err) 3387 wl->tx_queue_stopped[queue_num] = 0; 3388 } 3389 3390#if B43_DEBUG 3391 dev->tx_count++; 3392#endif 3393 mutex_unlock(&wl->mutex); 3394} 3395 3396static void b43_op_tx(struct ieee80211_hw *hw, 3397 struct sk_buff *skb) 3398{ 3399 struct b43_wl *wl = hw_to_b43_wl(hw); 3400 3401 if (unlikely(skb->len < 2 + 2 + 6)) { 3402 /* Too short, this can't be a valid frame. */ 3403 dev_kfree_skb_any(skb); 3404 return; 3405 } 3406 B43_WARN_ON(skb_shinfo(skb)->nr_frags); 3407 3408 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb); 3409 if (!wl->tx_queue_stopped[skb->queue_mapping]) { 3410 ieee80211_queue_work(wl->hw, &wl->tx_work); 3411 } else { 3412 ieee80211_stop_queue(wl->hw, skb->queue_mapping); 3413 } 3414} 3415 3416static void b43_qos_params_upload(struct b43_wldev *dev, 3417 const struct ieee80211_tx_queue_params *p, 3418 u16 shm_offset) 3419{ 3420 u16 params[B43_NR_QOSPARAMS]; 3421 int bslots, tmp; 3422 unsigned int i; 3423 3424 if (!dev->qos_enabled) 3425 return; 3426 3427 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min; 3428 3429 memset(¶ms, 0, sizeof(params)); 3430 3431 params[B43_QOSPARAM_TXOP] = p->txop * 32; 3432 params[B43_QOSPARAM_CWMIN] = p->cw_min; 3433 params[B43_QOSPARAM_CWMAX] = p->cw_max; 3434 params[B43_QOSPARAM_CWCUR] = p->cw_min; 3435 params[B43_QOSPARAM_AIFS] = p->aifs; 3436 params[B43_QOSPARAM_BSLOTS] = bslots; 3437 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs; 3438 3439 for (i = 0; i < ARRAY_SIZE(params); i++) { 3440 if (i == B43_QOSPARAM_STATUS) { 3441 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 3442 shm_offset + (i * 2)); 3443 /* Mark the parameters as updated. */ 3444 tmp |= 0x100; 3445 b43_shm_write16(dev, B43_SHM_SHARED, 3446 shm_offset + (i * 2), 3447 tmp); 3448 } else { 3449 b43_shm_write16(dev, B43_SHM_SHARED, 3450 shm_offset + (i * 2), 3451 params[i]); 3452 } 3453 } 3454} 3455 3456/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */ 3457static const u16 b43_qos_shm_offsets[] = { 3458 /* [mac80211-queue-nr] = SHM_OFFSET, */ 3459 [0] = B43_QOS_VOICE, 3460 [1] = B43_QOS_VIDEO, 3461 [2] = B43_QOS_BESTEFFORT, 3462 [3] = B43_QOS_BACKGROUND, 3463}; 3464 3465/* Update all QOS parameters in hardware. */ 3466static void b43_qos_upload_all(struct b43_wldev *dev) 3467{ 3468 struct b43_wl *wl = dev->wl; 3469 struct b43_qos_params *params; 3470 unsigned int i; 3471 3472 if (!dev->qos_enabled) 3473 return; 3474 3475 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3476 ARRAY_SIZE(wl->qos_params)); 3477 3478 b43_mac_suspend(dev); 3479 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3480 params = &(wl->qos_params[i]); 3481 b43_qos_params_upload(dev, &(params->p), 3482 b43_qos_shm_offsets[i]); 3483 } 3484 b43_mac_enable(dev); 3485} 3486 3487static void b43_qos_clear(struct b43_wl *wl) 3488{ 3489 struct b43_qos_params *params; 3490 unsigned int i; 3491 3492 /* Initialize QoS parameters to sane defaults. */ 3493 3494 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3495 ARRAY_SIZE(wl->qos_params)); 3496 3497 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3498 params = &(wl->qos_params[i]); 3499 3500 switch (b43_qos_shm_offsets[i]) { 3501 case B43_QOS_VOICE: 3502 params->p.txop = 0; 3503 params->p.aifs = 2; 3504 params->p.cw_min = 0x0001; 3505 params->p.cw_max = 0x0001; 3506 break; 3507 case B43_QOS_VIDEO: 3508 params->p.txop = 0; 3509 params->p.aifs = 2; 3510 params->p.cw_min = 0x0001; 3511 params->p.cw_max = 0x0001; 3512 break; 3513 case B43_QOS_BESTEFFORT: 3514 params->p.txop = 0; 3515 params->p.aifs = 3; 3516 params->p.cw_min = 0x0001; 3517 params->p.cw_max = 0x03FF; 3518 break; 3519 case B43_QOS_BACKGROUND: 3520 params->p.txop = 0; 3521 params->p.aifs = 7; 3522 params->p.cw_min = 0x0001; 3523 params->p.cw_max = 0x03FF; 3524 break; 3525 default: 3526 B43_WARN_ON(1); 3527 } 3528 } 3529} 3530 3531/* Initialize the core's QOS capabilities */ 3532static void b43_qos_init(struct b43_wldev *dev) 3533{ 3534 if (!dev->qos_enabled) { 3535 /* Disable QOS support. */ 3536 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF); 3537 b43_write16(dev, B43_MMIO_IFSCTL, 3538 b43_read16(dev, B43_MMIO_IFSCTL) 3539 & ~B43_MMIO_IFSCTL_USE_EDCF); 3540 b43dbg(dev->wl, "QoS disabled\n"); 3541 return; 3542 } 3543 3544 /* Upload the current QOS parameters. */ 3545 b43_qos_upload_all(dev); 3546 3547 /* Enable QOS support. */ 3548 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); 3549 b43_write16(dev, B43_MMIO_IFSCTL, 3550 b43_read16(dev, B43_MMIO_IFSCTL) 3551 | B43_MMIO_IFSCTL_USE_EDCF); 3552 b43dbg(dev->wl, "QoS enabled\n"); 3553} 3554 3555static int b43_op_conf_tx(struct ieee80211_hw *hw, 3556 struct ieee80211_vif *vif, u16 _queue, 3557 const struct ieee80211_tx_queue_params *params) 3558{ 3559 struct b43_wl *wl = hw_to_b43_wl(hw); 3560 struct b43_wldev *dev; 3561 unsigned int queue = (unsigned int)_queue; 3562 int err = -ENODEV; 3563 3564 if (queue >= ARRAY_SIZE(wl->qos_params)) { 3565 /* Queue not available or don't support setting 3566 * params on this queue. Return success to not 3567 * confuse mac80211. */ 3568 return 0; 3569 } 3570 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3571 ARRAY_SIZE(wl->qos_params)); 3572 3573 mutex_lock(&wl->mutex); 3574 dev = wl->current_dev; 3575 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) 3576 goto out_unlock; 3577 3578 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params)); 3579 b43_mac_suspend(dev); 3580 b43_qos_params_upload(dev, &(wl->qos_params[queue].p), 3581 b43_qos_shm_offsets[queue]); 3582 b43_mac_enable(dev); 3583 err = 0; 3584 3585out_unlock: 3586 mutex_unlock(&wl->mutex); 3587 3588 return err; 3589} 3590 3591static int b43_op_get_stats(struct ieee80211_hw *hw, 3592 struct ieee80211_low_level_stats *stats) 3593{ 3594 struct b43_wl *wl = hw_to_b43_wl(hw); 3595 3596 mutex_lock(&wl->mutex); 3597 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 3598 mutex_unlock(&wl->mutex); 3599 3600 return 0; 3601} 3602 3603static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 3604{ 3605 struct b43_wl *wl = hw_to_b43_wl(hw); 3606 struct b43_wldev *dev; 3607 u64 tsf; 3608 3609 mutex_lock(&wl->mutex); 3610 dev = wl->current_dev; 3611 3612 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3613 b43_tsf_read(dev, &tsf); 3614 else 3615 tsf = 0; 3616 3617 mutex_unlock(&wl->mutex); 3618 3619 return tsf; 3620} 3621 3622static void b43_op_set_tsf(struct ieee80211_hw *hw, 3623 struct ieee80211_vif *vif, u64 tsf) 3624{ 3625 struct b43_wl *wl = hw_to_b43_wl(hw); 3626 struct b43_wldev *dev; 3627 3628 mutex_lock(&wl->mutex); 3629 dev = wl->current_dev; 3630 3631 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3632 b43_tsf_write(dev, tsf); 3633 3634 mutex_unlock(&wl->mutex); 3635} 3636 3637static void b43_put_phy_into_reset(struct b43_wldev *dev) 3638{ 3639 u32 tmp; 3640 3641 switch (dev->dev->bus_type) { 3642#ifdef CONFIG_B43_BCMA 3643 case B43_BUS_BCMA: 3644 b43err(dev->wl, 3645 "Putting PHY into reset not supported on BCMA\n"); 3646 break; 3647#endif 3648#ifdef CONFIG_B43_SSB 3649 case B43_BUS_SSB: 3650 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 3651 tmp &= ~B43_TMSLOW_GMODE; 3652 tmp |= B43_TMSLOW_PHYRESET; 3653 tmp |= SSB_TMSLOW_FGC; 3654 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 3655 msleep(1); 3656 3657 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 3658 tmp &= ~SSB_TMSLOW_FGC; 3659 tmp |= B43_TMSLOW_PHYRESET; 3660 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 3661 msleep(1); 3662 3663 break; 3664#endif 3665 } 3666} 3667 3668static const char *band_to_string(enum ieee80211_band band) 3669{ 3670 switch (band) { 3671 case IEEE80211_BAND_5GHZ: 3672 return "5"; 3673 case IEEE80211_BAND_2GHZ: 3674 return "2.4"; 3675 default: 3676 break; 3677 } 3678 B43_WARN_ON(1); 3679 return ""; 3680} 3681 3682/* Expects wl->mutex locked */ 3683static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan) 3684{ 3685 struct b43_wldev *up_dev = NULL; 3686 struct b43_wldev *down_dev; 3687 struct b43_wldev *d; 3688 int err; 3689 bool uninitialized_var(gmode); 3690 int prev_status; 3691 3692 /* Find a device and PHY which supports the band. */ 3693 list_for_each_entry(d, &wl->devlist, list) { 3694 switch (chan->band) { 3695 case IEEE80211_BAND_5GHZ: 3696 if (d->phy.supports_5ghz) { 3697 up_dev = d; 3698 gmode = false; 3699 } 3700 break; 3701 case IEEE80211_BAND_2GHZ: 3702 if (d->phy.supports_2ghz) { 3703 up_dev = d; 3704 gmode = true; 3705 } 3706 break; 3707 default: 3708 B43_WARN_ON(1); 3709 return -EINVAL; 3710 } 3711 if (up_dev) 3712 break; 3713 } 3714 if (!up_dev) { 3715 b43err(wl, "Could not find a device for %s-GHz band operation\n", 3716 band_to_string(chan->band)); 3717 return -ENODEV; 3718 } 3719 if ((up_dev == wl->current_dev) && 3720 (!!wl->current_dev->phy.gmode == !!gmode)) { 3721 /* This device is already running. */ 3722 return 0; 3723 } 3724 b43dbg(wl, "Switching to %s-GHz band\n", 3725 band_to_string(chan->band)); 3726 down_dev = wl->current_dev; 3727 3728 prev_status = b43_status(down_dev); 3729 /* Shutdown the currently running core. */ 3730 if (prev_status >= B43_STAT_STARTED) 3731 down_dev = b43_wireless_core_stop(down_dev); 3732 if (prev_status >= B43_STAT_INITIALIZED) 3733 b43_wireless_core_exit(down_dev); 3734 3735 if (down_dev != up_dev) { 3736 /* We switch to a different core, so we put PHY into 3737 * RESET on the old core. */ 3738 b43_put_phy_into_reset(down_dev); 3739 } 3740 3741 /* Now start the new core. */ 3742 up_dev->phy.gmode = gmode; 3743 if (prev_status >= B43_STAT_INITIALIZED) { 3744 err = b43_wireless_core_init(up_dev); 3745 if (err) { 3746 b43err(wl, "Fatal: Could not initialize device for " 3747 "selected %s-GHz band\n", 3748 band_to_string(chan->band)); 3749 goto init_failure; 3750 } 3751 } 3752 if (prev_status >= B43_STAT_STARTED) { 3753 err = b43_wireless_core_start(up_dev); 3754 if (err) { 3755 b43err(wl, "Fatal: Coult not start device for " 3756 "selected %s-GHz band\n", 3757 band_to_string(chan->band)); 3758 b43_wireless_core_exit(up_dev); 3759 goto init_failure; 3760 } 3761 } 3762 B43_WARN_ON(b43_status(up_dev) != prev_status); 3763 3764 wl->current_dev = up_dev; 3765 3766 return 0; 3767init_failure: 3768 /* Whoops, failed to init the new core. No core is operating now. */ 3769 wl->current_dev = NULL; 3770 return err; 3771} 3772 3773/* Write the short and long frame retry limit values. */ 3774static void b43_set_retry_limits(struct b43_wldev *dev, 3775 unsigned int short_retry, 3776 unsigned int long_retry) 3777{ 3778 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3779 * the chip-internal counter. */ 3780 short_retry = min(short_retry, (unsigned int)0xF); 3781 long_retry = min(long_retry, (unsigned int)0xF); 3782 3783 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3784 short_retry); 3785 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3786 long_retry); 3787} 3788 3789static int b43_op_config(struct ieee80211_hw *hw, u32 changed) 3790{ 3791 struct b43_wl *wl = hw_to_b43_wl(hw); 3792 struct b43_wldev *dev; 3793 struct b43_phy *phy; 3794 struct ieee80211_conf *conf = &hw->conf; 3795 int antenna; 3796 int err = 0; 3797 bool reload_bss = false; 3798 3799 mutex_lock(&wl->mutex); 3800 3801 dev = wl->current_dev; 3802 3803 /* Switch the band (if necessary). This might change the active core. */ 3804 err = b43_switch_band(wl, conf->channel); 3805 if (err) 3806 goto out_unlock_mutex; 3807 3808 /* Need to reload all settings if the core changed */ 3809 if (dev != wl->current_dev) { 3810 dev = wl->current_dev; 3811 changed = ~0; 3812 reload_bss = true; 3813 } 3814 3815 phy = &dev->phy; 3816 3817 if (conf_is_ht(conf)) 3818 phy->is_40mhz = 3819 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf)); 3820 else 3821 phy->is_40mhz = false; 3822 3823 b43_mac_suspend(dev); 3824 3825 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 3826 b43_set_retry_limits(dev, conf->short_frame_max_tx_count, 3827 conf->long_frame_max_tx_count); 3828 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; 3829 if (!changed) 3830 goto out_mac_enable; 3831 3832 /* Switch to the requested channel. 3833 * The firmware takes care of races with the TX handler. */ 3834 if (conf->channel->hw_value != phy->channel) 3835 b43_switch_channel(dev, conf->channel->hw_value); 3836 3837 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 3838 3839 /* Adjust the desired TX power level. */ 3840 if (conf->power_level != 0) { 3841 if (conf->power_level != phy->desired_txpower) { 3842 phy->desired_txpower = conf->power_level; 3843 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME | 3844 B43_TXPWR_IGNORE_TSSI); 3845 } 3846 } 3847 3848 /* Antennas for RX and management frame TX. */ 3849 antenna = B43_ANTENNA_DEFAULT; 3850 b43_mgmtframe_txantenna(dev, antenna); 3851 antenna = B43_ANTENNA_DEFAULT; 3852 if (phy->ops->set_rx_antenna) 3853 phy->ops->set_rx_antenna(dev, antenna); 3854 3855 if (wl->radio_enabled != phy->radio_on) { 3856 if (wl->radio_enabled) { 3857 b43_software_rfkill(dev, false); 3858 b43info(dev->wl, "Radio turned on by software\n"); 3859 if (!dev->radio_hw_enable) { 3860 b43info(dev->wl, "The hardware RF-kill button " 3861 "still turns the radio physically off. " 3862 "Press the button to turn it on.\n"); 3863 } 3864 } else { 3865 b43_software_rfkill(dev, true); 3866 b43info(dev->wl, "Radio turned off by software\n"); 3867 } 3868 } 3869 3870out_mac_enable: 3871 b43_mac_enable(dev); 3872out_unlock_mutex: 3873 mutex_unlock(&wl->mutex); 3874 3875 if (wl->vif && reload_bss) 3876 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0); 3877 3878 return err; 3879} 3880 3881static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates) 3882{ 3883 struct ieee80211_supported_band *sband = 3884 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)]; 3885 struct ieee80211_rate *rate; 3886 int i; 3887 u16 basic, direct, offset, basic_offset, rateptr; 3888 3889 for (i = 0; i < sband->n_bitrates; i++) { 3890 rate = &sband->bitrates[i]; 3891 3892 if (b43_is_cck_rate(rate->hw_value)) { 3893 direct = B43_SHM_SH_CCKDIRECT; 3894 basic = B43_SHM_SH_CCKBASIC; 3895 offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3896 offset &= 0xF; 3897 } else { 3898 direct = B43_SHM_SH_OFDMDIRECT; 3899 basic = B43_SHM_SH_OFDMBASIC; 3900 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3901 offset &= 0xF; 3902 } 3903 3904 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); 3905 3906 if (b43_is_cck_rate(rate->hw_value)) { 3907 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3908 basic_offset &= 0xF; 3909 } else { 3910 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3911 basic_offset &= 0xF; 3912 } 3913 3914 /* 3915 * Get the pointer that we need to point to 3916 * from the direct map 3917 */ 3918 rateptr = b43_shm_read16(dev, B43_SHM_SHARED, 3919 direct + 2 * basic_offset); 3920 /* and write it to the basic map */ 3921 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset, 3922 rateptr); 3923 } 3924} 3925 3926static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 3927 struct ieee80211_vif *vif, 3928 struct ieee80211_bss_conf *conf, 3929 u32 changed) 3930{ 3931 struct b43_wl *wl = hw_to_b43_wl(hw); 3932 struct b43_wldev *dev; 3933 3934 mutex_lock(&wl->mutex); 3935 3936 dev = wl->current_dev; 3937 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3938 goto out_unlock_mutex; 3939 3940 B43_WARN_ON(wl->vif != vif); 3941 3942 if (changed & BSS_CHANGED_BSSID) { 3943 if (conf->bssid) 3944 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3945 else 3946 memset(wl->bssid, 0, ETH_ALEN); 3947 } 3948 3949 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3950 if (changed & BSS_CHANGED_BEACON && 3951 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3952 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3953 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3954 b43_update_templates(wl); 3955 3956 if (changed & BSS_CHANGED_BSSID) 3957 b43_write_mac_bssid_templates(dev); 3958 } 3959 3960 b43_mac_suspend(dev); 3961 3962 /* Update templates for AP/mesh mode. */ 3963 if (changed & BSS_CHANGED_BEACON_INT && 3964 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3965 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3966 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) && 3967 conf->beacon_int) 3968 b43_set_beacon_int(dev, conf->beacon_int); 3969 3970 if (changed & BSS_CHANGED_BASIC_RATES) 3971 b43_update_basic_rates(dev, conf->basic_rates); 3972 3973 if (changed & BSS_CHANGED_ERP_SLOT) { 3974 if (conf->use_short_slot) 3975 b43_short_slot_timing_enable(dev); 3976 else 3977 b43_short_slot_timing_disable(dev); 3978 } 3979 3980 b43_mac_enable(dev); 3981out_unlock_mutex: 3982 mutex_unlock(&wl->mutex); 3983} 3984 3985static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3986 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3987 struct ieee80211_key_conf *key) 3988{ 3989 struct b43_wl *wl = hw_to_b43_wl(hw); 3990 struct b43_wldev *dev; 3991 u8 algorithm; 3992 u8 index; 3993 int err; 3994 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3995 3996 if (modparam_nohwcrypt) 3997 return -ENOSPC; /* User disabled HW-crypto */ 3998 3999 mutex_lock(&wl->mutex); 4000 4001 dev = wl->current_dev; 4002 err = -ENODEV; 4003 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 4004 goto out_unlock; 4005 4006 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) { 4007 /* We don't have firmware for the crypto engine. 4008 * Must use software-crypto. */ 4009 err = -EOPNOTSUPP; 4010 goto out_unlock; 4011 } 4012 4013 err = -EINVAL; 4014 switch (key->cipher) { 4015 case WLAN_CIPHER_SUITE_WEP40: 4016 algorithm = B43_SEC_ALGO_WEP40; 4017 break; 4018 case WLAN_CIPHER_SUITE_WEP104: 4019 algorithm = B43_SEC_ALGO_WEP104; 4020 break; 4021 case WLAN_CIPHER_SUITE_TKIP: 4022 algorithm = B43_SEC_ALGO_TKIP; 4023 break; 4024 case WLAN_CIPHER_SUITE_CCMP: 4025 algorithm = B43_SEC_ALGO_AES; 4026 break; 4027 default: 4028 B43_WARN_ON(1); 4029 goto out_unlock; 4030 } 4031 index = (u8) (key->keyidx); 4032 if (index > 3) 4033 goto out_unlock; 4034 4035 switch (cmd) { 4036 case SET_KEY: 4037 if (algorithm == B43_SEC_ALGO_TKIP && 4038 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) || 4039 !modparam_hwtkip)) { 4040 /* We support only pairwise key */ 4041 err = -EOPNOTSUPP; 4042 goto out_unlock; 4043 } 4044 4045 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 4046 if (WARN_ON(!sta)) { 4047 err = -EOPNOTSUPP; 4048 goto out_unlock; 4049 } 4050 /* Pairwise key with an assigned MAC address. */ 4051 err = b43_key_write(dev, -1, algorithm, 4052 key->key, key->keylen, 4053 sta->addr, key); 4054 } else { 4055 /* Group key */ 4056 err = b43_key_write(dev, index, algorithm, 4057 key->key, key->keylen, NULL, key); 4058 } 4059 if (err) 4060 goto out_unlock; 4061 4062 if (algorithm == B43_SEC_ALGO_WEP40 || 4063 algorithm == B43_SEC_ALGO_WEP104) { 4064 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 4065 } else { 4066 b43_hf_write(dev, 4067 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 4068 } 4069 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 4070 if (algorithm == B43_SEC_ALGO_TKIP) 4071 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 4072 break; 4073 case DISABLE_KEY: { 4074 err = b43_key_clear(dev, key->hw_key_idx); 4075 if (err) 4076 goto out_unlock; 4077 break; 4078 } 4079 default: 4080 B43_WARN_ON(1); 4081 } 4082 4083out_unlock: 4084 if (!err) { 4085 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 4086 "mac: %pM\n", 4087 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 4088 sta ? sta->addr : bcast_addr); 4089 b43_dump_keymemory(dev); 4090 } 4091 mutex_unlock(&wl->mutex); 4092 4093 return err; 4094} 4095 4096static void b43_op_configure_filter(struct ieee80211_hw *hw, 4097 unsigned int changed, unsigned int *fflags, 4098 u64 multicast) 4099{ 4100 struct b43_wl *wl = hw_to_b43_wl(hw); 4101 struct b43_wldev *dev; 4102 4103 mutex_lock(&wl->mutex); 4104 dev = wl->current_dev; 4105 if (!dev) { 4106 *fflags = 0; 4107 goto out_unlock; 4108 } 4109 4110 *fflags &= FIF_PROMISC_IN_BSS | 4111 FIF_ALLMULTI | 4112 FIF_FCSFAIL | 4113 FIF_PLCPFAIL | 4114 FIF_CONTROL | 4115 FIF_OTHER_BSS | 4116 FIF_BCN_PRBRESP_PROMISC; 4117 4118 changed &= FIF_PROMISC_IN_BSS | 4119 FIF_ALLMULTI | 4120 FIF_FCSFAIL | 4121 FIF_PLCPFAIL | 4122 FIF_CONTROL | 4123 FIF_OTHER_BSS | 4124 FIF_BCN_PRBRESP_PROMISC; 4125 4126 wl->filter_flags = *fflags; 4127 4128 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 4129 b43_adjust_opmode(dev); 4130 4131out_unlock: 4132 mutex_unlock(&wl->mutex); 4133} 4134 4135/* Locking: wl->mutex 4136 * Returns the current dev. This might be different from the passed in dev, 4137 * because the core might be gone away while we unlocked the mutex. */ 4138static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev) 4139{ 4140 struct b43_wl *wl; 4141 struct b43_wldev *orig_dev; 4142 u32 mask; 4143 int queue_num; 4144 4145 if (!dev) 4146 return NULL; 4147 wl = dev->wl; 4148redo: 4149 if (!dev || b43_status(dev) < B43_STAT_STARTED) 4150 return dev; 4151 4152 /* Cancel work. Unlock to avoid deadlocks. */ 4153 mutex_unlock(&wl->mutex); 4154 cancel_delayed_work_sync(&dev->periodic_work); 4155 cancel_work_sync(&wl->tx_work); 4156 mutex_lock(&wl->mutex); 4157 dev = wl->current_dev; 4158 if (!dev || b43_status(dev) < B43_STAT_STARTED) { 4159 /* Whoops, aliens ate up the device while we were unlocked. */ 4160 return dev; 4161 } 4162 4163 /* Disable interrupts on the device. */ 4164 b43_set_status(dev, B43_STAT_INITIALIZED); 4165 if (b43_bus_host_is_sdio(dev->dev)) { 4166 /* wl->mutex is locked. That is enough. */ 4167 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4168 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4169 } else { 4170 spin_lock_irq(&wl->hardirq_lock); 4171 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4172 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4173 spin_unlock_irq(&wl->hardirq_lock); 4174 } 4175 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ 4176 orig_dev = dev; 4177 mutex_unlock(&wl->mutex); 4178 if (b43_bus_host_is_sdio(dev->dev)) { 4179 b43_sdio_free_irq(dev); 4180 } else { 4181 synchronize_irq(dev->dev->irq); 4182 free_irq(dev->dev->irq, dev); 4183 } 4184 mutex_lock(&wl->mutex); 4185 dev = wl->current_dev; 4186 if (!dev) 4187 return dev; 4188 if (dev != orig_dev) { 4189 if (b43_status(dev) >= B43_STAT_STARTED) 4190 goto redo; 4191 return dev; 4192 } 4193 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 4194 B43_WARN_ON(mask != 0xFFFFFFFF && mask); 4195 4196 /* Drain all TX queues. */ 4197 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { 4198 while (skb_queue_len(&wl->tx_queue[queue_num])) 4199 dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num])); 4200 } 4201 4202 b43_mac_suspend(dev); 4203 b43_leds_exit(dev); 4204 b43dbg(wl, "Wireless interface stopped\n"); 4205 4206 return dev; 4207} 4208 4209/* Locking: wl->mutex */ 4210static int b43_wireless_core_start(struct b43_wldev *dev) 4211{ 4212 int err; 4213 4214 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 4215 4216 drain_txstatus_queue(dev); 4217 if (b43_bus_host_is_sdio(dev->dev)) { 4218 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); 4219 if (err) { 4220 b43err(dev->wl, "Cannot request SDIO IRQ\n"); 4221 goto out; 4222 } 4223 } else { 4224 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler, 4225 b43_interrupt_thread_handler, 4226 IRQF_SHARED, KBUILD_MODNAME, dev); 4227 if (err) { 4228 b43err(dev->wl, "Cannot request IRQ-%d\n", 4229 dev->dev->irq); 4230 goto out; 4231 } 4232 } 4233 4234 /* We are ready to run. */ 4235 ieee80211_wake_queues(dev->wl->hw); 4236 b43_set_status(dev, B43_STAT_STARTED); 4237 4238 /* Start data flow (TX/RX). */ 4239 b43_mac_enable(dev); 4240 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 4241 4242 /* Start maintenance work */ 4243 b43_periodic_tasks_setup(dev); 4244 4245 b43_leds_init(dev); 4246 4247 b43dbg(dev->wl, "Wireless interface started\n"); 4248out: 4249 return err; 4250} 4251 4252/* Get PHY and RADIO versioning numbers */ 4253static int b43_phy_versioning(struct b43_wldev *dev) 4254{ 4255 struct b43_phy *phy = &dev->phy; 4256 u32 tmp; 4257 u8 analog_type; 4258 u8 phy_type; 4259 u8 phy_rev; 4260 u16 radio_manuf; 4261 u16 radio_ver; 4262 u16 radio_rev; 4263 int unsupported = 0; 4264 4265 /* Get PHY versioning */ 4266 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 4267 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 4268 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 4269 phy_rev = (tmp & B43_PHYVER_VERSION); 4270 switch (phy_type) { 4271 case B43_PHYTYPE_A: 4272 if (phy_rev >= 4) 4273 unsupported = 1; 4274 break; 4275 case B43_PHYTYPE_B: 4276 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 4277 && phy_rev != 7) 4278 unsupported = 1; 4279 break; 4280 case B43_PHYTYPE_G: 4281 if (phy_rev > 9) 4282 unsupported = 1; 4283 break; 4284#ifdef CONFIG_B43_PHY_N 4285 case B43_PHYTYPE_N: 4286 if (phy_rev > 9) 4287 unsupported = 1; 4288 break; 4289#endif 4290#ifdef CONFIG_B43_PHY_LP 4291 case B43_PHYTYPE_LP: 4292 if (phy_rev > 2) 4293 unsupported = 1; 4294 break; 4295#endif 4296#ifdef CONFIG_B43_PHY_HT 4297 case B43_PHYTYPE_HT: 4298 if (phy_rev > 1) 4299 unsupported = 1; 4300 break; 4301#endif 4302#ifdef CONFIG_B43_PHY_LCN 4303 case B43_PHYTYPE_LCN: 4304 if (phy_rev > 1) 4305 unsupported = 1; 4306 break; 4307#endif 4308 default: 4309 unsupported = 1; 4310 } 4311 if (unsupported) { 4312 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 4313 "(Analog %u, Type %u, Revision %u)\n", 4314 analog_type, phy_type, phy_rev); 4315 return -EOPNOTSUPP; 4316 } 4317 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 4318 analog_type, phy_type, phy_rev); 4319 4320 /* Get RADIO versioning */ 4321 if (dev->dev->core_rev >= 24) { 4322 u16 radio24[3]; 4323 4324 for (tmp = 0; tmp < 3; tmp++) { 4325 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp); 4326 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4327 } 4328 4329 /* Broadcom uses "id" for our "ver" and has separated "ver" */ 4330 /* radio_ver = (radio24[0] & 0xF0) >> 4; */ 4331 4332 radio_manuf = 0x17F; 4333 radio_ver = (radio24[2] << 8) | radio24[1]; 4334 radio_rev = (radio24[0] & 0xF); 4335 } else { 4336 if (dev->dev->chip_id == 0x4317) { 4337 if (dev->dev->chip_rev == 0) 4338 tmp = 0x3205017F; 4339 else if (dev->dev->chip_rev == 1) 4340 tmp = 0x4205017F; 4341 else 4342 tmp = 0x5205017F; 4343 } else { 4344 b43_write16(dev, B43_MMIO_RADIO_CONTROL, 4345 B43_RADIOCTL_ID); 4346 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 4347 b43_write16(dev, B43_MMIO_RADIO_CONTROL, 4348 B43_RADIOCTL_ID); 4349 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) 4350 << 16; 4351 } 4352 radio_manuf = (tmp & 0x00000FFF); 4353 radio_ver = (tmp & 0x0FFFF000) >> 12; 4354 radio_rev = (tmp & 0xF0000000) >> 28; 4355 } 4356 4357 if (radio_manuf != 0x17F /* Broadcom */) 4358 unsupported = 1; 4359 switch (phy_type) { 4360 case B43_PHYTYPE_A: 4361 if (radio_ver != 0x2060) 4362 unsupported = 1; 4363 if (radio_rev != 1) 4364 unsupported = 1; 4365 if (radio_manuf != 0x17F) 4366 unsupported = 1; 4367 break; 4368 case B43_PHYTYPE_B: 4369 if ((radio_ver & 0xFFF0) != 0x2050) 4370 unsupported = 1; 4371 break; 4372 case B43_PHYTYPE_G: 4373 if (radio_ver != 0x2050) 4374 unsupported = 1; 4375 break; 4376 case B43_PHYTYPE_N: 4377 if (radio_ver != 0x2055 && radio_ver != 0x2056) 4378 unsupported = 1; 4379 break; 4380 case B43_PHYTYPE_LP: 4381 if (radio_ver != 0x2062 && radio_ver != 0x2063) 4382 unsupported = 1; 4383 break; 4384 case B43_PHYTYPE_HT: 4385 if (radio_ver != 0x2059) 4386 unsupported = 1; 4387 break; 4388 case B43_PHYTYPE_LCN: 4389 if (radio_ver != 0x2064) 4390 unsupported = 1; 4391 break; 4392 default: 4393 B43_WARN_ON(1); 4394 } 4395 if (unsupported) { 4396 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 4397 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 4398 radio_manuf, radio_ver, radio_rev); 4399 return -EOPNOTSUPP; 4400 } 4401 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 4402 radio_manuf, radio_ver, radio_rev); 4403 4404 phy->radio_manuf = radio_manuf; 4405 phy->radio_ver = radio_ver; 4406 phy->radio_rev = radio_rev; 4407 4408 phy->analog = analog_type; 4409 phy->type = phy_type; 4410 phy->rev = phy_rev; 4411 4412 return 0; 4413} 4414 4415static void setup_struct_phy_for_init(struct b43_wldev *dev, 4416 struct b43_phy *phy) 4417{ 4418 phy->hardware_power_control = !!modparam_hwpctl; 4419 phy->next_txpwr_check_time = jiffies; 4420 /* PHY TX errors counter. */ 4421 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 4422 4423#if B43_DEBUG 4424 phy->phy_locked = false; 4425 phy->radio_locked = false; 4426#endif 4427} 4428 4429static void setup_struct_wldev_for_init(struct b43_wldev *dev) 4430{ 4431 dev->dfq_valid = false; 4432 4433 /* Assume the radio is enabled. If it's not enabled, the state will 4434 * immediately get fixed on the first periodic work run. */ 4435 dev->radio_hw_enable = true; 4436 4437 /* Stats */ 4438 memset(&dev->stats, 0, sizeof(dev->stats)); 4439 4440 setup_struct_phy_for_init(dev, &dev->phy); 4441 4442 /* IRQ related flags */ 4443 dev->irq_reason = 0; 4444 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 4445 dev->irq_mask = B43_IRQ_MASKTEMPLATE; 4446 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 4447 dev->irq_mask &= ~B43_IRQ_PHY_TXERR; 4448 4449 dev->mac_suspended = 1; 4450 4451 /* Noise calculation context */ 4452 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 4453} 4454 4455static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 4456{ 4457 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4458 u64 hf; 4459 4460 if (!modparam_btcoex) 4461 return; 4462 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 4463 return; 4464 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 4465 return; 4466 4467 hf = b43_hf_read(dev); 4468 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 4469 hf |= B43_HF_BTCOEXALT; 4470 else 4471 hf |= B43_HF_BTCOEX; 4472 b43_hf_write(dev, hf); 4473} 4474 4475static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 4476{ 4477 if (!modparam_btcoex) 4478 return; 4479 //TODO 4480} 4481 4482static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 4483{ 4484 struct ssb_bus *bus; 4485 u32 tmp; 4486 4487 if (dev->dev->bus_type != B43_BUS_SSB) 4488 return; 4489 4490 bus = dev->dev->sdev->bus; 4491 4492 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || 4493 (bus->chip_id == 0x4312)) { 4494 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO); 4495 tmp &= ~SSB_IMCFGLO_REQTO; 4496 tmp &= ~SSB_IMCFGLO_SERTO; 4497 tmp |= 0x3; 4498 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp); 4499 ssb_commit_settings(bus); 4500 } 4501} 4502 4503static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) 4504{ 4505 u16 pu_delay; 4506 4507 /* The time value is in microseconds. */ 4508 if (dev->phy.type == B43_PHYTYPE_A) 4509 pu_delay = 3700; 4510 else 4511 pu_delay = 1050; 4512 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) 4513 pu_delay = 500; 4514 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) 4515 pu_delay = max(pu_delay, (u16)2400); 4516 4517 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); 4518} 4519 4520/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ 4521static void b43_set_pretbtt(struct b43_wldev *dev) 4522{ 4523 u16 pretbtt; 4524 4525 /* The time value is in microseconds. */ 4526 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) { 4527 pretbtt = 2; 4528 } else { 4529 if (dev->phy.type == B43_PHYTYPE_A) 4530 pretbtt = 120; 4531 else 4532 pretbtt = 250; 4533 } 4534 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); 4535 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); 4536} 4537 4538/* Shutdown a wireless core */ 4539/* Locking: wl->mutex */ 4540static void b43_wireless_core_exit(struct b43_wldev *dev) 4541{ 4542 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED); 4543 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED) 4544 return; 4545 4546 /* Unregister HW RNG driver */ 4547 b43_rng_exit(dev->wl); 4548 4549 b43_set_status(dev, B43_STAT_UNINIT); 4550 4551 /* Stop the microcode PSM. */ 4552 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN, 4553 B43_MACCTL_PSM_JMP0); 4554 4555 b43_dma_free(dev); 4556 b43_pio_free(dev); 4557 b43_chip_exit(dev); 4558 dev->phy.ops->switch_analog(dev, 0); 4559 if (dev->wl->current_beacon) { 4560 dev_kfree_skb_any(dev->wl->current_beacon); 4561 dev->wl->current_beacon = NULL; 4562 } 4563 4564 b43_device_disable(dev, 0); 4565 b43_bus_may_powerdown(dev); 4566} 4567 4568/* Initialize a wireless core */ 4569static int b43_wireless_core_init(struct b43_wldev *dev) 4570{ 4571 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4572 struct b43_phy *phy = &dev->phy; 4573 int err; 4574 u64 hf; 4575 4576 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4577 4578 err = b43_bus_powerup(dev, 0); 4579 if (err) 4580 goto out; 4581 if (!b43_device_is_enabled(dev)) 4582 b43_wireless_core_reset(dev, phy->gmode); 4583 4584 /* Reset all data structures. */ 4585 setup_struct_wldev_for_init(dev); 4586 phy->ops->prepare_structs(dev); 4587 4588 /* Enable IRQ routing to this device. */ 4589 switch (dev->dev->bus_type) { 4590#ifdef CONFIG_B43_BCMA 4591 case B43_BUS_BCMA: 4592 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci, 4593 dev->dev->bdev, true); 4594 break; 4595#endif 4596#ifdef CONFIG_B43_SSB 4597 case B43_BUS_SSB: 4598 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore, 4599 dev->dev->sdev); 4600 break; 4601#endif 4602 } 4603 4604 b43_imcfglo_timeouts_workaround(dev); 4605 b43_bluetooth_coext_disable(dev); 4606 if (phy->ops->prepare_hardware) { 4607 err = phy->ops->prepare_hardware(dev); 4608 if (err) 4609 goto err_busdown; 4610 } 4611 err = b43_chip_init(dev); 4612 if (err) 4613 goto err_busdown; 4614 b43_shm_write16(dev, B43_SHM_SHARED, 4615 B43_SHM_SH_WLCOREREV, dev->dev->core_rev); 4616 hf = b43_hf_read(dev); 4617 if (phy->type == B43_PHYTYPE_G) { 4618 hf |= B43_HF_SYMW; 4619 if (phy->rev == 1) 4620 hf |= B43_HF_GDCW; 4621 if (sprom->boardflags_lo & B43_BFL_PACTRL) 4622 hf |= B43_HF_OFDMPABOOST; 4623 } 4624 if (phy->radio_ver == 0x2050) { 4625 if (phy->radio_rev == 6) 4626 hf |= B43_HF_4318TSSI; 4627 if (phy->radio_rev < 6) 4628 hf |= B43_HF_VCORECALC; 4629 } 4630 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) 4631 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ 4632#ifdef CONFIG_SSB_DRIVER_PCICORE 4633 if (dev->dev->bus_type == B43_BUS_SSB && 4634 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI && 4635 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10) 4636 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ 4637#endif 4638 hf &= ~B43_HF_SKCFPUP; 4639 b43_hf_write(dev, hf); 4640 4641 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 4642 B43_DEFAULT_LONG_RETRY_LIMIT); 4643 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 4644 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 4645 4646 /* Disable sending probe responses from firmware. 4647 * Setting the MaxTime to one usec will always trigger 4648 * a timeout, so we never send any probe resp. 4649 * A timeout of zero is infinite. */ 4650 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 4651 4652 b43_rate_memory_init(dev); 4653 b43_set_phytxctl_defaults(dev); 4654 4655 /* Minimum Contention Window */ 4656 if (phy->type == B43_PHYTYPE_B) 4657 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 4658 else 4659 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 4660 /* Maximum Contention Window */ 4661 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 4662 4663 if (b43_bus_host_is_pcmcia(dev->dev) || 4664 b43_bus_host_is_sdio(dev->dev)) { 4665 dev->__using_pio_transfers = true; 4666 err = b43_pio_init(dev); 4667 } else if (dev->use_pio) { 4668 b43warn(dev->wl, "Forced PIO by use_pio module parameter. " 4669 "This should not be needed and will result in lower " 4670 "performance.\n"); 4671 dev->__using_pio_transfers = true; 4672 err = b43_pio_init(dev); 4673 } else { 4674 dev->__using_pio_transfers = false; 4675 err = b43_dma_init(dev); 4676 } 4677 if (err) 4678 goto err_chip_exit; 4679 b43_qos_init(dev); 4680 b43_set_synth_pu_delay(dev, 1); 4681 b43_bluetooth_coext_enable(dev); 4682 4683 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); 4684 b43_upload_card_macaddress(dev); 4685 b43_security_init(dev); 4686 4687 ieee80211_wake_queues(dev->wl->hw); 4688 4689 b43_set_status(dev, B43_STAT_INITIALIZED); 4690 4691 /* Register HW RNG driver */ 4692 b43_rng_init(dev->wl); 4693 4694out: 4695 return err; 4696 4697err_chip_exit: 4698 b43_chip_exit(dev); 4699err_busdown: 4700 b43_bus_may_powerdown(dev); 4701 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4702 return err; 4703} 4704 4705static int b43_op_add_interface(struct ieee80211_hw *hw, 4706 struct ieee80211_vif *vif) 4707{ 4708 struct b43_wl *wl = hw_to_b43_wl(hw); 4709 struct b43_wldev *dev; 4710 int err = -EOPNOTSUPP; 4711 4712 /* TODO: allow WDS/AP devices to coexist */ 4713 4714 if (vif->type != NL80211_IFTYPE_AP && 4715 vif->type != NL80211_IFTYPE_MESH_POINT && 4716 vif->type != NL80211_IFTYPE_STATION && 4717 vif->type != NL80211_IFTYPE_WDS && 4718 vif->type != NL80211_IFTYPE_ADHOC) 4719 return -EOPNOTSUPP; 4720 4721 mutex_lock(&wl->mutex); 4722 if (wl->operating) 4723 goto out_mutex_unlock; 4724 4725 b43dbg(wl, "Adding Interface type %d\n", vif->type); 4726 4727 dev = wl->current_dev; 4728 wl->operating = true; 4729 wl->vif = vif; 4730 wl->if_type = vif->type; 4731 memcpy(wl->mac_addr, vif->addr, ETH_ALEN); 4732 4733 b43_adjust_opmode(dev); 4734 b43_set_pretbtt(dev); 4735 b43_set_synth_pu_delay(dev, 0); 4736 b43_upload_card_macaddress(dev); 4737 4738 err = 0; 4739 out_mutex_unlock: 4740 mutex_unlock(&wl->mutex); 4741 4742 if (err == 0) 4743 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0); 4744 4745 return err; 4746} 4747 4748static void b43_op_remove_interface(struct ieee80211_hw *hw, 4749 struct ieee80211_vif *vif) 4750{ 4751 struct b43_wl *wl = hw_to_b43_wl(hw); 4752 struct b43_wldev *dev = wl->current_dev; 4753 4754 b43dbg(wl, "Removing Interface type %d\n", vif->type); 4755 4756 mutex_lock(&wl->mutex); 4757 4758 B43_WARN_ON(!wl->operating); 4759 B43_WARN_ON(wl->vif != vif); 4760 wl->vif = NULL; 4761 4762 wl->operating = false; 4763 4764 b43_adjust_opmode(dev); 4765 memset(wl->mac_addr, 0, ETH_ALEN); 4766 b43_upload_card_macaddress(dev); 4767 4768 mutex_unlock(&wl->mutex); 4769} 4770 4771static int b43_op_start(struct ieee80211_hw *hw) 4772{ 4773 struct b43_wl *wl = hw_to_b43_wl(hw); 4774 struct b43_wldev *dev = wl->current_dev; 4775 int did_init = 0; 4776 int err = 0; 4777 4778 /* Kill all old instance specific information to make sure 4779 * the card won't use it in the short timeframe between start 4780 * and mac80211 reconfiguring it. */ 4781 memset(wl->bssid, 0, ETH_ALEN); 4782 memset(wl->mac_addr, 0, ETH_ALEN); 4783 wl->filter_flags = 0; 4784 wl->radiotap_enabled = false; 4785 b43_qos_clear(wl); 4786 wl->beacon0_uploaded = false; 4787 wl->beacon1_uploaded = false; 4788 wl->beacon_templates_virgin = true; 4789 wl->radio_enabled = true; 4790 4791 mutex_lock(&wl->mutex); 4792 4793 if (b43_status(dev) < B43_STAT_INITIALIZED) { 4794 err = b43_wireless_core_init(dev); 4795 if (err) 4796 goto out_mutex_unlock; 4797 did_init = 1; 4798 } 4799 4800 if (b43_status(dev) < B43_STAT_STARTED) { 4801 err = b43_wireless_core_start(dev); 4802 if (err) { 4803 if (did_init) 4804 b43_wireless_core_exit(dev); 4805 goto out_mutex_unlock; 4806 } 4807 } 4808 4809 /* XXX: only do if device doesn't support rfkill irq */ 4810 wiphy_rfkill_start_polling(hw->wiphy); 4811 4812 out_mutex_unlock: 4813 mutex_unlock(&wl->mutex); 4814 4815 /* reload configuration */ 4816 b43_op_config(hw, ~0); 4817 4818 return err; 4819} 4820 4821static void b43_op_stop(struct ieee80211_hw *hw) 4822{ 4823 struct b43_wl *wl = hw_to_b43_wl(hw); 4824 struct b43_wldev *dev = wl->current_dev; 4825 4826 cancel_work_sync(&(wl->beacon_update_trigger)); 4827 4828 if (!dev) 4829 goto out; 4830 4831 mutex_lock(&wl->mutex); 4832 if (b43_status(dev) >= B43_STAT_STARTED) { 4833 dev = b43_wireless_core_stop(dev); 4834 if (!dev) 4835 goto out_unlock; 4836 } 4837 b43_wireless_core_exit(dev); 4838 wl->radio_enabled = false; 4839 4840out_unlock: 4841 mutex_unlock(&wl->mutex); 4842out: 4843 cancel_work_sync(&(wl->txpower_adjust_work)); 4844} 4845 4846static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, 4847 struct ieee80211_sta *sta, bool set) 4848{ 4849 struct b43_wl *wl = hw_to_b43_wl(hw); 4850 4851 /* FIXME: add locking */ 4852 b43_update_templates(wl); 4853 4854 return 0; 4855} 4856 4857static void b43_op_sta_notify(struct ieee80211_hw *hw, 4858 struct ieee80211_vif *vif, 4859 enum sta_notify_cmd notify_cmd, 4860 struct ieee80211_sta *sta) 4861{ 4862 struct b43_wl *wl = hw_to_b43_wl(hw); 4863 4864 B43_WARN_ON(!vif || wl->vif != vif); 4865} 4866 4867static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw) 4868{ 4869 struct b43_wl *wl = hw_to_b43_wl(hw); 4870 struct b43_wldev *dev; 4871 4872 mutex_lock(&wl->mutex); 4873 dev = wl->current_dev; 4874 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4875 /* Disable CFP update during scan on other channels. */ 4876 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP); 4877 } 4878 mutex_unlock(&wl->mutex); 4879} 4880 4881static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw) 4882{ 4883 struct b43_wl *wl = hw_to_b43_wl(hw); 4884 struct b43_wldev *dev; 4885 4886 mutex_lock(&wl->mutex); 4887 dev = wl->current_dev; 4888 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4889 /* Re-enable CFP update. */ 4890 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP); 4891 } 4892 mutex_unlock(&wl->mutex); 4893} 4894 4895static int b43_op_get_survey(struct ieee80211_hw *hw, int idx, 4896 struct survey_info *survey) 4897{ 4898 struct b43_wl *wl = hw_to_b43_wl(hw); 4899 struct b43_wldev *dev = wl->current_dev; 4900 struct ieee80211_conf *conf = &hw->conf; 4901 4902 if (idx != 0) 4903 return -ENOENT; 4904 4905 survey->channel = conf->channel; 4906 survey->filled = SURVEY_INFO_NOISE_DBM; 4907 survey->noise = dev->stats.link_noise; 4908 4909 return 0; 4910} 4911 4912static const struct ieee80211_ops b43_hw_ops = { 4913 .tx = b43_op_tx, 4914 .conf_tx = b43_op_conf_tx, 4915 .add_interface = b43_op_add_interface, 4916 .remove_interface = b43_op_remove_interface, 4917 .config = b43_op_config, 4918 .bss_info_changed = b43_op_bss_info_changed, 4919 .configure_filter = b43_op_configure_filter, 4920 .set_key = b43_op_set_key, 4921 .update_tkip_key = b43_op_update_tkip_key, 4922 .get_stats = b43_op_get_stats, 4923 .get_tsf = b43_op_get_tsf, 4924 .set_tsf = b43_op_set_tsf, 4925 .start = b43_op_start, 4926 .stop = b43_op_stop, 4927 .set_tim = b43_op_beacon_set_tim, 4928 .sta_notify = b43_op_sta_notify, 4929 .sw_scan_start = b43_op_sw_scan_start_notifier, 4930 .sw_scan_complete = b43_op_sw_scan_complete_notifier, 4931 .get_survey = b43_op_get_survey, 4932 .rfkill_poll = b43_rfkill_poll, 4933}; 4934 4935/* Hard-reset the chip. Do not call this directly. 4936 * Use b43_controller_restart() 4937 */ 4938static void b43_chip_reset(struct work_struct *work) 4939{ 4940 struct b43_wldev *dev = 4941 container_of(work, struct b43_wldev, restart_work); 4942 struct b43_wl *wl = dev->wl; 4943 int err = 0; 4944 int prev_status; 4945 4946 mutex_lock(&wl->mutex); 4947 4948 prev_status = b43_status(dev); 4949 /* Bring the device down... */ 4950 if (prev_status >= B43_STAT_STARTED) { 4951 dev = b43_wireless_core_stop(dev); 4952 if (!dev) { 4953 err = -ENODEV; 4954 goto out; 4955 } 4956 } 4957 if (prev_status >= B43_STAT_INITIALIZED) 4958 b43_wireless_core_exit(dev); 4959 4960 /* ...and up again. */ 4961 if (prev_status >= B43_STAT_INITIALIZED) { 4962 err = b43_wireless_core_init(dev); 4963 if (err) 4964 goto out; 4965 } 4966 if (prev_status >= B43_STAT_STARTED) { 4967 err = b43_wireless_core_start(dev); 4968 if (err) { 4969 b43_wireless_core_exit(dev); 4970 goto out; 4971 } 4972 } 4973out: 4974 if (err) 4975 wl->current_dev = NULL; /* Failed to init the dev. */ 4976 mutex_unlock(&wl->mutex); 4977 4978 if (err) { 4979 b43err(wl, "Controller restart FAILED\n"); 4980 return; 4981 } 4982 4983 /* reload configuration */ 4984 b43_op_config(wl->hw, ~0); 4985 if (wl->vif) 4986 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0); 4987 4988 b43info(wl, "Controller restarted\n"); 4989} 4990 4991static int b43_setup_bands(struct b43_wldev *dev, 4992 bool have_2ghz_phy, bool have_5ghz_phy) 4993{ 4994 struct ieee80211_hw *hw = dev->wl->hw; 4995 4996 if (have_2ghz_phy) 4997 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz; 4998 if (dev->phy.type == B43_PHYTYPE_N) { 4999 if (have_5ghz_phy) 5000 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy; 5001 } else { 5002 if (have_5ghz_phy) 5003 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy; 5004 } 5005 5006 dev->phy.supports_2ghz = have_2ghz_phy; 5007 dev->phy.supports_5ghz = have_5ghz_phy; 5008 5009 return 0; 5010} 5011 5012static void b43_wireless_core_detach(struct b43_wldev *dev) 5013{ 5014 /* We release firmware that late to not be required to re-request 5015 * is all the time when we reinit the core. */ 5016 b43_release_firmware(dev); 5017 b43_phy_free(dev); 5018} 5019 5020static int b43_wireless_core_attach(struct b43_wldev *dev) 5021{ 5022 struct b43_wl *wl = dev->wl; 5023 struct pci_dev *pdev = NULL; 5024 int err; 5025 u32 tmp; 5026 bool have_2ghz_phy = false, have_5ghz_phy = false; 5027 5028 /* Do NOT do any device initialization here. 5029 * Do it in wireless_core_init() instead. 5030 * This function is for gathering basic information about the HW, only. 5031 * Also some structs may be set up here. But most likely you want to have 5032 * that in core_init(), too. 5033 */ 5034 5035#ifdef CONFIG_B43_SSB 5036 if (dev->dev->bus_type == B43_BUS_SSB && 5037 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) 5038 pdev = dev->dev->sdev->bus->host_pci; 5039#endif 5040 5041 err = b43_bus_powerup(dev, 0); 5042 if (err) { 5043 b43err(wl, "Bus powerup failed\n"); 5044 goto out; 5045 } 5046 5047 /* Get the PHY type. */ 5048 switch (dev->dev->bus_type) { 5049#ifdef CONFIG_B43_BCMA 5050 case B43_BUS_BCMA: 5051 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST); 5052 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY); 5053 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY); 5054 break; 5055#endif 5056#ifdef CONFIG_B43_SSB 5057 case B43_BUS_SSB: 5058 if (dev->dev->core_rev >= 5) { 5059 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 5060 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY); 5061 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY); 5062 } else 5063 B43_WARN_ON(1); 5064 break; 5065#endif 5066 } 5067 5068 dev->phy.gmode = have_2ghz_phy; 5069 dev->phy.radio_on = true; 5070 b43_wireless_core_reset(dev, dev->phy.gmode); 5071 5072 err = b43_phy_versioning(dev); 5073 if (err) 5074 goto err_powerdown; 5075 /* Check if this device supports multiband. */ 5076 if (!pdev || 5077 (pdev->device != 0x4312 && 5078 pdev->device != 0x4319 && pdev->device != 0x4324)) { 5079 /* No multiband support. */ 5080 have_2ghz_phy = false; 5081 have_5ghz_phy = false; 5082 switch (dev->phy.type) { 5083 case B43_PHYTYPE_A: 5084 have_5ghz_phy = true; 5085 break; 5086 case B43_PHYTYPE_LP: //FIXME not always! 5087#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference 5088 have_5ghz_phy = 1; 5089#endif 5090 case B43_PHYTYPE_G: 5091 case B43_PHYTYPE_N: 5092 case B43_PHYTYPE_HT: 5093 case B43_PHYTYPE_LCN: 5094 have_2ghz_phy = true; 5095 break; 5096 default: 5097 B43_WARN_ON(1); 5098 } 5099 } 5100 if (dev->phy.type == B43_PHYTYPE_A) { 5101 /* FIXME */ 5102 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 5103 err = -EOPNOTSUPP; 5104 goto err_powerdown; 5105 } 5106 if (1 /* disable A-PHY */) { 5107 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */ 5108 if (dev->phy.type != B43_PHYTYPE_N && 5109 dev->phy.type != B43_PHYTYPE_LP) { 5110 have_2ghz_phy = true; 5111 have_5ghz_phy = false; 5112 } 5113 } 5114 5115 err = b43_phy_allocate(dev); 5116 if (err) 5117 goto err_powerdown; 5118 5119 dev->phy.gmode = have_2ghz_phy; 5120 b43_wireless_core_reset(dev, dev->phy.gmode); 5121 5122 err = b43_validate_chipaccess(dev); 5123 if (err) 5124 goto err_phy_free; 5125 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); 5126 if (err) 5127 goto err_phy_free; 5128 5129 /* Now set some default "current_dev" */ 5130 if (!wl->current_dev) 5131 wl->current_dev = dev; 5132 INIT_WORK(&dev->restart_work, b43_chip_reset); 5133 5134 dev->phy.ops->switch_analog(dev, 0); 5135 b43_device_disable(dev, 0); 5136 b43_bus_may_powerdown(dev); 5137 5138out: 5139 return err; 5140 5141err_phy_free: 5142 b43_phy_free(dev); 5143err_powerdown: 5144 b43_bus_may_powerdown(dev); 5145 return err; 5146} 5147 5148static void b43_one_core_detach(struct b43_bus_dev *dev) 5149{ 5150 struct b43_wldev *wldev; 5151 struct b43_wl *wl; 5152 5153 /* Do not cancel ieee80211-workqueue based work here. 5154 * See comment in b43_remove(). */ 5155 5156 wldev = b43_bus_get_wldev(dev); 5157 wl = wldev->wl; 5158 b43_debugfs_remove_device(wldev); 5159 b43_wireless_core_detach(wldev); 5160 list_del(&wldev->list); 5161 wl->nr_devs--; 5162 b43_bus_set_wldev(dev, NULL); 5163 kfree(wldev); 5164} 5165 5166static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl) 5167{ 5168 struct b43_wldev *wldev; 5169 int err = -ENOMEM; 5170 5171 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 5172 if (!wldev) 5173 goto out; 5174 5175 wldev->use_pio = b43_modparam_pio; 5176 wldev->dev = dev; 5177 wldev->wl = wl; 5178 b43_set_status(wldev, B43_STAT_UNINIT); 5179 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 5180 INIT_LIST_HEAD(&wldev->list); 5181 5182 err = b43_wireless_core_attach(wldev); 5183 if (err) 5184 goto err_kfree_wldev; 5185 5186 list_add(&wldev->list, &wl->devlist); 5187 wl->nr_devs++; 5188 b43_bus_set_wldev(dev, wldev); 5189 b43_debugfs_add_device(wldev); 5190 5191 out: 5192 return err; 5193 5194 err_kfree_wldev: 5195 kfree(wldev); 5196 return err; 5197} 5198 5199#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ 5200 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ 5201 (pdev->device == _device) && \ 5202 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ 5203 (pdev->subsystem_device == _subdevice) ) 5204 5205static void b43_sprom_fixup(struct ssb_bus *bus) 5206{ 5207 struct pci_dev *pdev; 5208 5209 /* boardflags workarounds */ 5210 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 5211 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 5212 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 5213 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 5214 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 5215 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 5216 if (bus->bustype == SSB_BUSTYPE_PCI) { 5217 pdev = bus->host_pci; 5218 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || 5219 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || 5220 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || 5221 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || 5222 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || 5223 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || 5224 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) 5225 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; 5226 } 5227} 5228 5229static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl) 5230{ 5231 struct ieee80211_hw *hw = wl->hw; 5232 5233 ssb_set_devtypedata(dev->sdev, NULL); 5234 ieee80211_free_hw(hw); 5235} 5236 5237static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev) 5238{ 5239 struct ssb_sprom *sprom = dev->bus_sprom; 5240 struct ieee80211_hw *hw; 5241 struct b43_wl *wl; 5242 char chip_name[6]; 5243 int queue_num; 5244 5245 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 5246 if (!hw) { 5247 b43err(NULL, "Could not allocate ieee80211 device\n"); 5248 return ERR_PTR(-ENOMEM); 5249 } 5250 wl = hw_to_b43_wl(hw); 5251 5252 /* fill hw info */ 5253 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 5254 IEEE80211_HW_SIGNAL_DBM; 5255 5256 hw->wiphy->interface_modes = 5257 BIT(NL80211_IFTYPE_AP) | 5258 BIT(NL80211_IFTYPE_MESH_POINT) | 5259 BIT(NL80211_IFTYPE_STATION) | 5260 BIT(NL80211_IFTYPE_WDS) | 5261 BIT(NL80211_IFTYPE_ADHOC); 5262 5263 hw->queues = modparam_qos ? B43_QOS_QUEUE_NUM : 1; 5264 wl->mac80211_initially_registered_queues = hw->queues; 5265 hw->max_rates = 2; 5266 SET_IEEE80211_DEV(hw, dev->dev); 5267 if (is_valid_ether_addr(sprom->et1mac)) 5268 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 5269 else 5270 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 5271 5272 /* Initialize struct b43_wl */ 5273 wl->hw = hw; 5274 mutex_init(&wl->mutex); 5275 spin_lock_init(&wl->hardirq_lock); 5276 INIT_LIST_HEAD(&wl->devlist); 5277 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); 5278 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work); 5279 INIT_WORK(&wl->tx_work, b43_tx_work); 5280 5281 /* Initialize queues and flags. */ 5282 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { 5283 skb_queue_head_init(&wl->tx_queue[queue_num]); 5284 wl->tx_queue_stopped[queue_num] = 0; 5285 } 5286 5287 snprintf(chip_name, ARRAY_SIZE(chip_name), 5288 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id); 5289 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name, 5290 dev->core_rev); 5291 return wl; 5292} 5293 5294#ifdef CONFIG_B43_BCMA 5295static int b43_bcma_probe(struct bcma_device *core) 5296{ 5297 struct b43_bus_dev *dev; 5298 struct b43_wl *wl; 5299 int err; 5300 5301 dev = b43_bus_dev_bcma_init(core); 5302 if (!dev) 5303 return -ENODEV; 5304 5305 wl = b43_wireless_init(dev); 5306 if (IS_ERR(wl)) { 5307 err = PTR_ERR(wl); 5308 goto bcma_out; 5309 } 5310 5311 err = b43_one_core_attach(dev, wl); 5312 if (err) 5313 goto bcma_err_wireless_exit; 5314 5315 err = ieee80211_register_hw(wl->hw); 5316 if (err) 5317 goto bcma_err_one_core_detach; 5318 b43_leds_register(wl->current_dev); 5319 5320bcma_out: 5321 return err; 5322 5323bcma_err_one_core_detach: 5324 b43_one_core_detach(dev); 5325bcma_err_wireless_exit: 5326 ieee80211_free_hw(wl->hw); 5327 return err; 5328} 5329 5330static void b43_bcma_remove(struct bcma_device *core) 5331{ 5332 struct b43_wldev *wldev = bcma_get_drvdata(core); 5333 struct b43_wl *wl = wldev->wl; 5334 5335 /* We must cancel any work here before unregistering from ieee80211, 5336 * as the ieee80211 unreg will destroy the workqueue. */ 5337 cancel_work_sync(&wldev->restart_work); 5338 5339 /* Restore the queues count before unregistering, because firmware detect 5340 * might have modified it. Restoring is important, so the networking 5341 * stack can properly free resources. */ 5342 wl->hw->queues = wl->mac80211_initially_registered_queues; 5343 b43_leds_stop(wldev); 5344 ieee80211_unregister_hw(wl->hw); 5345 5346 b43_one_core_detach(wldev->dev); 5347 5348 b43_leds_unregister(wl); 5349 5350 ieee80211_free_hw(wl->hw); 5351} 5352 5353static struct bcma_driver b43_bcma_driver = { 5354 .name = KBUILD_MODNAME, 5355 .id_table = b43_bcma_tbl, 5356 .probe = b43_bcma_probe, 5357 .remove = b43_bcma_remove, 5358}; 5359#endif 5360 5361#ifdef CONFIG_B43_SSB 5362static 5363int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id) 5364{ 5365 struct b43_bus_dev *dev; 5366 struct b43_wl *wl; 5367 int err; 5368 int first = 0; 5369 5370 dev = b43_bus_dev_ssb_init(sdev); 5371 if (!dev) 5372 return -ENOMEM; 5373 5374 wl = ssb_get_devtypedata(sdev); 5375 if (!wl) { 5376 /* Probing the first core. Must setup common struct b43_wl */ 5377 first = 1; 5378 b43_sprom_fixup(sdev->bus); 5379 wl = b43_wireless_init(dev); 5380 if (IS_ERR(wl)) { 5381 err = PTR_ERR(wl); 5382 goto out; 5383 } 5384 ssb_set_devtypedata(sdev, wl); 5385 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl); 5386 } 5387 err = b43_one_core_attach(dev, wl); 5388 if (err) 5389 goto err_wireless_exit; 5390 5391 if (first) { 5392 err = ieee80211_register_hw(wl->hw); 5393 if (err) 5394 goto err_one_core_detach; 5395 b43_leds_register(wl->current_dev); 5396 } 5397 5398 out: 5399 return err; 5400 5401 err_one_core_detach: 5402 b43_one_core_detach(dev); 5403 err_wireless_exit: 5404 if (first) 5405 b43_wireless_exit(dev, wl); 5406 return err; 5407} 5408 5409static void b43_ssb_remove(struct ssb_device *sdev) 5410{ 5411 struct b43_wl *wl = ssb_get_devtypedata(sdev); 5412 struct b43_wldev *wldev = ssb_get_drvdata(sdev); 5413 struct b43_bus_dev *dev = wldev->dev; 5414 5415 /* We must cancel any work here before unregistering from ieee80211, 5416 * as the ieee80211 unreg will destroy the workqueue. */ 5417 cancel_work_sync(&wldev->restart_work); 5418 5419 B43_WARN_ON(!wl); 5420 if (wl->current_dev == wldev) { 5421 /* Restore the queues count before unregistering, because firmware detect 5422 * might have modified it. Restoring is important, so the networking 5423 * stack can properly free resources. */ 5424 wl->hw->queues = wl->mac80211_initially_registered_queues; 5425 b43_leds_stop(wldev); 5426 ieee80211_unregister_hw(wl->hw); 5427 } 5428 5429 b43_one_core_detach(dev); 5430 5431 if (list_empty(&wl->devlist)) { 5432 b43_leds_unregister(wl); 5433 /* Last core on the chip unregistered. 5434 * We can destroy common struct b43_wl. 5435 */ 5436 b43_wireless_exit(dev, wl); 5437 } 5438} 5439 5440static struct ssb_driver b43_ssb_driver = { 5441 .name = KBUILD_MODNAME, 5442 .id_table = b43_ssb_tbl, 5443 .probe = b43_ssb_probe, 5444 .remove = b43_ssb_remove, 5445}; 5446#endif /* CONFIG_B43_SSB */ 5447 5448/* Perform a hardware reset. This can be called from any context. */ 5449void b43_controller_restart(struct b43_wldev *dev, const char *reason) 5450{ 5451 /* Must avoid requeueing, if we are in shutdown. */ 5452 if (b43_status(dev) < B43_STAT_INITIALIZED) 5453 return; 5454 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 5455 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 5456} 5457 5458static void b43_print_driverinfo(void) 5459{ 5460 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", 5461 *feat_leds = "", *feat_sdio = ""; 5462 5463#ifdef CONFIG_B43_PCI_AUTOSELECT 5464 feat_pci = "P"; 5465#endif 5466#ifdef CONFIG_B43_PCMCIA 5467 feat_pcmcia = "M"; 5468#endif 5469#ifdef CONFIG_B43_PHY_N 5470 feat_nphy = "N"; 5471#endif 5472#ifdef CONFIG_B43_LEDS 5473 feat_leds = "L"; 5474#endif 5475#ifdef CONFIG_B43_SDIO 5476 feat_sdio = "S"; 5477#endif 5478 printk(KERN_INFO "Broadcom 43xx driver loaded " 5479 "[ Features: %s%s%s%s%s ]\n", 5480 feat_pci, feat_pcmcia, feat_nphy, 5481 feat_leds, feat_sdio); 5482} 5483 5484static int __init b43_init(void) 5485{ 5486 int err; 5487 5488 b43_debugfs_init(); 5489 err = b43_pcmcia_init(); 5490 if (err) 5491 goto err_dfs_exit; 5492 err = b43_sdio_init(); 5493 if (err) 5494 goto err_pcmcia_exit; 5495#ifdef CONFIG_B43_BCMA 5496 err = bcma_driver_register(&b43_bcma_driver); 5497 if (err) 5498 goto err_sdio_exit; 5499#endif 5500#ifdef CONFIG_B43_SSB 5501 err = ssb_driver_register(&b43_ssb_driver); 5502 if (err) 5503 goto err_bcma_driver_exit; 5504#endif 5505 b43_print_driverinfo(); 5506 5507 return err; 5508 5509#ifdef CONFIG_B43_SSB 5510err_bcma_driver_exit: 5511#endif 5512#ifdef CONFIG_B43_BCMA 5513 bcma_driver_unregister(&b43_bcma_driver); 5514err_sdio_exit: 5515#endif 5516 b43_sdio_exit(); 5517err_pcmcia_exit: 5518 b43_pcmcia_exit(); 5519err_dfs_exit: 5520 b43_debugfs_exit(); 5521 return err; 5522} 5523 5524static void __exit b43_exit(void) 5525{ 5526#ifdef CONFIG_B43_SSB 5527 ssb_driver_unregister(&b43_ssb_driver); 5528#endif 5529#ifdef CONFIG_B43_BCMA 5530 bcma_driver_unregister(&b43_bcma_driver); 5531#endif 5532 b43_sdio_exit(); 5533 b43_pcmcia_exit(); 5534 b43_debugfs_exit(); 5535} 5536 5537module_init(b43_init) 5538module_exit(b43_exit) 5539