main.c revision 9a5a133df35bc76191c1e3532369b2c39cf88a5b
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 SDIO support 12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> 13 14 Some parts of the code in this file are derived from the ipw2200 15 driver Copyright(c) 2003 - 2004 Intel Corporation. 16 17 This program is free software; you can redistribute it and/or modify 18 it under the terms of the GNU General Public License as published by 19 the Free Software Foundation; either version 2 of the License, or 20 (at your option) any later version. 21 22 This program is distributed in the hope that it will be useful, 23 but WITHOUT ANY WARRANTY; without even the implied warranty of 24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 GNU General Public License for more details. 26 27 You should have received a copy of the GNU General Public License 28 along with this program; see the file COPYING. If not, write to 29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 30 Boston, MA 02110-1301, USA. 31 32*/ 33 34#include <linux/delay.h> 35#include <linux/init.h> 36#include <linux/moduleparam.h> 37#include <linux/if_arp.h> 38#include <linux/etherdevice.h> 39#include <linux/firmware.h> 40#include <linux/workqueue.h> 41#include <linux/skbuff.h> 42#include <linux/io.h> 43#include <linux/dma-mapping.h> 44#include <linux/slab.h> 45#include <asm/unaligned.h> 46 47#include "b43.h" 48#include "main.h" 49#include "debugfs.h" 50#include "phy_common.h" 51#include "phy_g.h" 52#include "phy_n.h" 53#include "dma.h" 54#include "pio.h" 55#include "sysfs.h" 56#include "xmit.h" 57#include "lo.h" 58#include "pcmcia.h" 59#include "sdio.h" 60#include <linux/mmc/sdio_func.h> 61 62MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 63MODULE_AUTHOR("Martin Langer"); 64MODULE_AUTHOR("Stefano Brivio"); 65MODULE_AUTHOR("Michael Buesch"); 66MODULE_AUTHOR("Gábor Stefanik"); 67MODULE_LICENSE("GPL"); 68 69MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID); 70MODULE_FIRMWARE("b43/ucode11.fw"); 71MODULE_FIRMWARE("b43/ucode13.fw"); 72MODULE_FIRMWARE("b43/ucode14.fw"); 73MODULE_FIRMWARE("b43/ucode15.fw"); 74MODULE_FIRMWARE("b43/ucode16_mimo.fw"); 75MODULE_FIRMWARE("b43/ucode5.fw"); 76MODULE_FIRMWARE("b43/ucode9.fw"); 77 78static int modparam_bad_frames_preempt; 79module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 80MODULE_PARM_DESC(bad_frames_preempt, 81 "enable(1) / disable(0) Bad Frames Preemption"); 82 83static char modparam_fwpostfix[16]; 84module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 85MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 86 87static int modparam_hwpctl; 88module_param_named(hwpctl, modparam_hwpctl, int, 0444); 89MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 90 91static int modparam_nohwcrypt; 92module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 93MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 94 95static int modparam_hwtkip; 96module_param_named(hwtkip, modparam_hwtkip, int, 0444); 97MODULE_PARM_DESC(hwtkip, "Enable hardware tkip."); 98 99static int modparam_qos = 1; 100module_param_named(qos, modparam_qos, int, 0444); 101MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); 102 103static int modparam_btcoex = 1; 104module_param_named(btcoex, modparam_btcoex, int, 0444); 105MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)"); 106 107int b43_modparam_verbose = B43_VERBOSITY_DEFAULT; 108module_param_named(verbose, b43_modparam_verbose, int, 0644); 109MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug"); 110 111static int b43_modparam_pio = B43_PIO_DEFAULT; 112module_param_named(pio, b43_modparam_pio, int, 0644); 113MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO"); 114 115#ifdef CONFIG_B43_BCMA 116static const struct bcma_device_id b43_bcma_tbl[] = { 117 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS), 118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS), 119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS), 120 BCMA_CORETABLE_END 121}; 122MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl); 123#endif 124 125#ifdef CONFIG_B43_SSB 126static const struct ssb_device_id b43_ssb_tbl[] = { 127 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 128 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12), 134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15), 136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), 137 SSB_DEVTABLE_END 138}; 139MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 140#endif 141 142/* Channel and ratetables are shared for all devices. 143 * They can't be const, because ieee80211 puts some precalculated 144 * data in there. This data is the same for all devices, so we don't 145 * get concurrency issues */ 146#define RATETAB_ENT(_rateid, _flags) \ 147 { \ 148 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ 149 .hw_value = (_rateid), \ 150 .flags = (_flags), \ 151 } 152 153/* 154 * NOTE: When changing this, sync with xmit.c's 155 * b43_plcp_get_bitrate_idx_* functions! 156 */ 157static struct ieee80211_rate __b43_ratetable[] = { 158 RATETAB_ENT(B43_CCK_RATE_1MB, 0), 159 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), 160 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), 161 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), 162 RATETAB_ENT(B43_OFDM_RATE_6MB, 0), 163 RATETAB_ENT(B43_OFDM_RATE_9MB, 0), 164 RATETAB_ENT(B43_OFDM_RATE_12MB, 0), 165 RATETAB_ENT(B43_OFDM_RATE_18MB, 0), 166 RATETAB_ENT(B43_OFDM_RATE_24MB, 0), 167 RATETAB_ENT(B43_OFDM_RATE_36MB, 0), 168 RATETAB_ENT(B43_OFDM_RATE_48MB, 0), 169 RATETAB_ENT(B43_OFDM_RATE_54MB, 0), 170}; 171 172#define b43_a_ratetable (__b43_ratetable + 4) 173#define b43_a_ratetable_size 8 174#define b43_b_ratetable (__b43_ratetable + 0) 175#define b43_b_ratetable_size 4 176#define b43_g_ratetable (__b43_ratetable + 0) 177#define b43_g_ratetable_size 12 178 179#define CHAN4G(_channel, _freq, _flags) { \ 180 .band = IEEE80211_BAND_2GHZ, \ 181 .center_freq = (_freq), \ 182 .hw_value = (_channel), \ 183 .flags = (_flags), \ 184 .max_antenna_gain = 0, \ 185 .max_power = 30, \ 186} 187static struct ieee80211_channel b43_2ghz_chantable[] = { 188 CHAN4G(1, 2412, 0), 189 CHAN4G(2, 2417, 0), 190 CHAN4G(3, 2422, 0), 191 CHAN4G(4, 2427, 0), 192 CHAN4G(5, 2432, 0), 193 CHAN4G(6, 2437, 0), 194 CHAN4G(7, 2442, 0), 195 CHAN4G(8, 2447, 0), 196 CHAN4G(9, 2452, 0), 197 CHAN4G(10, 2457, 0), 198 CHAN4G(11, 2462, 0), 199 CHAN4G(12, 2467, 0), 200 CHAN4G(13, 2472, 0), 201 CHAN4G(14, 2484, 0), 202}; 203#undef CHAN4G 204 205#define CHAN5G(_channel, _flags) { \ 206 .band = IEEE80211_BAND_5GHZ, \ 207 .center_freq = 5000 + (5 * (_channel)), \ 208 .hw_value = (_channel), \ 209 .flags = (_flags), \ 210 .max_antenna_gain = 0, \ 211 .max_power = 30, \ 212} 213static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { 214 CHAN5G(32, 0), CHAN5G(34, 0), 215 CHAN5G(36, 0), CHAN5G(38, 0), 216 CHAN5G(40, 0), CHAN5G(42, 0), 217 CHAN5G(44, 0), CHAN5G(46, 0), 218 CHAN5G(48, 0), CHAN5G(50, 0), 219 CHAN5G(52, 0), CHAN5G(54, 0), 220 CHAN5G(56, 0), CHAN5G(58, 0), 221 CHAN5G(60, 0), CHAN5G(62, 0), 222 CHAN5G(64, 0), CHAN5G(66, 0), 223 CHAN5G(68, 0), CHAN5G(70, 0), 224 CHAN5G(72, 0), CHAN5G(74, 0), 225 CHAN5G(76, 0), CHAN5G(78, 0), 226 CHAN5G(80, 0), CHAN5G(82, 0), 227 CHAN5G(84, 0), CHAN5G(86, 0), 228 CHAN5G(88, 0), CHAN5G(90, 0), 229 CHAN5G(92, 0), CHAN5G(94, 0), 230 CHAN5G(96, 0), CHAN5G(98, 0), 231 CHAN5G(100, 0), CHAN5G(102, 0), 232 CHAN5G(104, 0), CHAN5G(106, 0), 233 CHAN5G(108, 0), CHAN5G(110, 0), 234 CHAN5G(112, 0), CHAN5G(114, 0), 235 CHAN5G(116, 0), CHAN5G(118, 0), 236 CHAN5G(120, 0), CHAN5G(122, 0), 237 CHAN5G(124, 0), CHAN5G(126, 0), 238 CHAN5G(128, 0), CHAN5G(130, 0), 239 CHAN5G(132, 0), CHAN5G(134, 0), 240 CHAN5G(136, 0), CHAN5G(138, 0), 241 CHAN5G(140, 0), CHAN5G(142, 0), 242 CHAN5G(144, 0), CHAN5G(145, 0), 243 CHAN5G(146, 0), CHAN5G(147, 0), 244 CHAN5G(148, 0), CHAN5G(149, 0), 245 CHAN5G(150, 0), CHAN5G(151, 0), 246 CHAN5G(152, 0), CHAN5G(153, 0), 247 CHAN5G(154, 0), CHAN5G(155, 0), 248 CHAN5G(156, 0), CHAN5G(157, 0), 249 CHAN5G(158, 0), CHAN5G(159, 0), 250 CHAN5G(160, 0), CHAN5G(161, 0), 251 CHAN5G(162, 0), CHAN5G(163, 0), 252 CHAN5G(164, 0), CHAN5G(165, 0), 253 CHAN5G(166, 0), CHAN5G(168, 0), 254 CHAN5G(170, 0), CHAN5G(172, 0), 255 CHAN5G(174, 0), CHAN5G(176, 0), 256 CHAN5G(178, 0), CHAN5G(180, 0), 257 CHAN5G(182, 0), CHAN5G(184, 0), 258 CHAN5G(186, 0), CHAN5G(188, 0), 259 CHAN5G(190, 0), CHAN5G(192, 0), 260 CHAN5G(194, 0), CHAN5G(196, 0), 261 CHAN5G(198, 0), CHAN5G(200, 0), 262 CHAN5G(202, 0), CHAN5G(204, 0), 263 CHAN5G(206, 0), CHAN5G(208, 0), 264 CHAN5G(210, 0), CHAN5G(212, 0), 265 CHAN5G(214, 0), CHAN5G(216, 0), 266 CHAN5G(218, 0), CHAN5G(220, 0), 267 CHAN5G(222, 0), CHAN5G(224, 0), 268 CHAN5G(226, 0), CHAN5G(228, 0), 269}; 270 271static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { 272 CHAN5G(34, 0), CHAN5G(36, 0), 273 CHAN5G(38, 0), CHAN5G(40, 0), 274 CHAN5G(42, 0), CHAN5G(44, 0), 275 CHAN5G(46, 0), CHAN5G(48, 0), 276 CHAN5G(52, 0), CHAN5G(56, 0), 277 CHAN5G(60, 0), CHAN5G(64, 0), 278 CHAN5G(100, 0), CHAN5G(104, 0), 279 CHAN5G(108, 0), CHAN5G(112, 0), 280 CHAN5G(116, 0), CHAN5G(120, 0), 281 CHAN5G(124, 0), CHAN5G(128, 0), 282 CHAN5G(132, 0), CHAN5G(136, 0), 283 CHAN5G(140, 0), CHAN5G(149, 0), 284 CHAN5G(153, 0), CHAN5G(157, 0), 285 CHAN5G(161, 0), CHAN5G(165, 0), 286 CHAN5G(184, 0), CHAN5G(188, 0), 287 CHAN5G(192, 0), CHAN5G(196, 0), 288 CHAN5G(200, 0), CHAN5G(204, 0), 289 CHAN5G(208, 0), CHAN5G(212, 0), 290 CHAN5G(216, 0), 291}; 292#undef CHAN5G 293 294static struct ieee80211_supported_band b43_band_5GHz_nphy = { 295 .band = IEEE80211_BAND_5GHZ, 296 .channels = b43_5ghz_nphy_chantable, 297 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), 298 .bitrates = b43_a_ratetable, 299 .n_bitrates = b43_a_ratetable_size, 300}; 301 302static struct ieee80211_supported_band b43_band_5GHz_aphy = { 303 .band = IEEE80211_BAND_5GHZ, 304 .channels = b43_5ghz_aphy_chantable, 305 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), 306 .bitrates = b43_a_ratetable, 307 .n_bitrates = b43_a_ratetable_size, 308}; 309 310static struct ieee80211_supported_band b43_band_2GHz = { 311 .band = IEEE80211_BAND_2GHZ, 312 .channels = b43_2ghz_chantable, 313 .n_channels = ARRAY_SIZE(b43_2ghz_chantable), 314 .bitrates = b43_g_ratetable, 315 .n_bitrates = b43_g_ratetable_size, 316}; 317 318static void b43_wireless_core_exit(struct b43_wldev *dev); 319static int b43_wireless_core_init(struct b43_wldev *dev); 320static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev); 321static int b43_wireless_core_start(struct b43_wldev *dev); 322 323static int b43_ratelimit(struct b43_wl *wl) 324{ 325 if (!wl || !wl->current_dev) 326 return 1; 327 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 328 return 1; 329 /* We are up and running. 330 * Ratelimit the messages to avoid DoS over the net. */ 331 return net_ratelimit(); 332} 333 334void b43info(struct b43_wl *wl, const char *fmt, ...) 335{ 336 struct va_format vaf; 337 va_list args; 338 339 if (b43_modparam_verbose < B43_VERBOSITY_INFO) 340 return; 341 if (!b43_ratelimit(wl)) 342 return; 343 344 va_start(args, fmt); 345 346 vaf.fmt = fmt; 347 vaf.va = &args; 348 349 printk(KERN_INFO "b43-%s: %pV", 350 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 351 352 va_end(args); 353} 354 355void b43err(struct b43_wl *wl, const char *fmt, ...) 356{ 357 struct va_format vaf; 358 va_list args; 359 360 if (b43_modparam_verbose < B43_VERBOSITY_ERROR) 361 return; 362 if (!b43_ratelimit(wl)) 363 return; 364 365 va_start(args, fmt); 366 367 vaf.fmt = fmt; 368 vaf.va = &args; 369 370 printk(KERN_ERR "b43-%s ERROR: %pV", 371 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 372 373 va_end(args); 374} 375 376void b43warn(struct b43_wl *wl, const char *fmt, ...) 377{ 378 struct va_format vaf; 379 va_list args; 380 381 if (b43_modparam_verbose < B43_VERBOSITY_WARN) 382 return; 383 if (!b43_ratelimit(wl)) 384 return; 385 386 va_start(args, fmt); 387 388 vaf.fmt = fmt; 389 vaf.va = &args; 390 391 printk(KERN_WARNING "b43-%s warning: %pV", 392 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 393 394 va_end(args); 395} 396 397void b43dbg(struct b43_wl *wl, const char *fmt, ...) 398{ 399 struct va_format vaf; 400 va_list args; 401 402 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 403 return; 404 405 va_start(args, fmt); 406 407 vaf.fmt = fmt; 408 vaf.va = &args; 409 410 printk(KERN_DEBUG "b43-%s debug: %pV", 411 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 412 413 va_end(args); 414} 415 416static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 417{ 418 u32 macctl; 419 420 B43_WARN_ON(offset % 4 != 0); 421 422 macctl = b43_read32(dev, B43_MMIO_MACCTL); 423 if (macctl & B43_MACCTL_BE) 424 val = swab32(val); 425 426 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 427 mmiowb(); 428 b43_write32(dev, B43_MMIO_RAM_DATA, val); 429} 430 431static inline void b43_shm_control_word(struct b43_wldev *dev, 432 u16 routing, u16 offset) 433{ 434 u32 control; 435 436 /* "offset" is the WORD offset. */ 437 control = routing; 438 control <<= 16; 439 control |= offset; 440 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 441} 442 443u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 444{ 445 u32 ret; 446 447 if (routing == B43_SHM_SHARED) { 448 B43_WARN_ON(offset & 0x0001); 449 if (offset & 0x0003) { 450 /* Unaligned access */ 451 b43_shm_control_word(dev, routing, offset >> 2); 452 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 453 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 454 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16; 455 456 goto out; 457 } 458 offset >>= 2; 459 } 460 b43_shm_control_word(dev, routing, offset); 461 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 462out: 463 return ret; 464} 465 466u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset) 467{ 468 u16 ret; 469 470 if (routing == B43_SHM_SHARED) { 471 B43_WARN_ON(offset & 0x0001); 472 if (offset & 0x0003) { 473 /* Unaligned access */ 474 b43_shm_control_word(dev, routing, offset >> 2); 475 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 476 477 goto out; 478 } 479 offset >>= 2; 480 } 481 b43_shm_control_word(dev, routing, offset); 482 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 483out: 484 return ret; 485} 486 487void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 488{ 489 if (routing == B43_SHM_SHARED) { 490 B43_WARN_ON(offset & 0x0001); 491 if (offset & 0x0003) { 492 /* Unaligned access */ 493 b43_shm_control_word(dev, routing, offset >> 2); 494 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 495 value & 0xFFFF); 496 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 497 b43_write16(dev, B43_MMIO_SHM_DATA, 498 (value >> 16) & 0xFFFF); 499 return; 500 } 501 offset >>= 2; 502 } 503 b43_shm_control_word(dev, routing, offset); 504 b43_write32(dev, B43_MMIO_SHM_DATA, value); 505} 506 507void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 508{ 509 if (routing == B43_SHM_SHARED) { 510 B43_WARN_ON(offset & 0x0001); 511 if (offset & 0x0003) { 512 /* Unaligned access */ 513 b43_shm_control_word(dev, routing, offset >> 2); 514 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 515 return; 516 } 517 offset >>= 2; 518 } 519 b43_shm_control_word(dev, routing, offset); 520 b43_write16(dev, B43_MMIO_SHM_DATA, value); 521} 522 523/* Read HostFlags */ 524u64 b43_hf_read(struct b43_wldev *dev) 525{ 526 u64 ret; 527 528 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 529 ret <<= 16; 530 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI); 531 ret <<= 16; 532 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 533 534 return ret; 535} 536 537/* Write HostFlags */ 538void b43_hf_write(struct b43_wldev *dev, u64 value) 539{ 540 u16 lo, mi, hi; 541 542 lo = (value & 0x00000000FFFFULL); 543 mi = (value & 0x0000FFFF0000ULL) >> 16; 544 hi = (value & 0xFFFF00000000ULL) >> 32; 545 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo); 546 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi); 547 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi); 548} 549 550/* Read the firmware capabilities bitmask (Opensource firmware only) */ 551static u16 b43_fwcapa_read(struct b43_wldev *dev) 552{ 553 B43_WARN_ON(!dev->fw.opensource); 554 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA); 555} 556 557void b43_tsf_read(struct b43_wldev *dev, u64 *tsf) 558{ 559 u32 low, high; 560 561 B43_WARN_ON(dev->dev->core_rev < 3); 562 563 /* The hardware guarantees us an atomic read, if we 564 * read the low register first. */ 565 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 566 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 567 568 *tsf = high; 569 *tsf <<= 32; 570 *tsf |= low; 571} 572 573static void b43_time_lock(struct b43_wldev *dev) 574{ 575 u32 macctl; 576 577 macctl = b43_read32(dev, B43_MMIO_MACCTL); 578 macctl |= B43_MACCTL_TBTTHOLD; 579 b43_write32(dev, B43_MMIO_MACCTL, macctl); 580 /* Commit the write */ 581 b43_read32(dev, B43_MMIO_MACCTL); 582} 583 584static void b43_time_unlock(struct b43_wldev *dev) 585{ 586 u32 macctl; 587 588 macctl = b43_read32(dev, B43_MMIO_MACCTL); 589 macctl &= ~B43_MACCTL_TBTTHOLD; 590 b43_write32(dev, B43_MMIO_MACCTL, macctl); 591 /* Commit the write */ 592 b43_read32(dev, B43_MMIO_MACCTL); 593} 594 595static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 596{ 597 u32 low, high; 598 599 B43_WARN_ON(dev->dev->core_rev < 3); 600 601 low = tsf; 602 high = (tsf >> 32); 603 /* The hardware guarantees us an atomic write, if we 604 * write the low register first. */ 605 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low); 606 mmiowb(); 607 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high); 608 mmiowb(); 609} 610 611void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 612{ 613 b43_time_lock(dev); 614 b43_tsf_write_locked(dev, tsf); 615 b43_time_unlock(dev); 616} 617 618static 619void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac) 620{ 621 static const u8 zero_addr[ETH_ALEN] = { 0 }; 622 u16 data; 623 624 if (!mac) 625 mac = zero_addr; 626 627 offset |= 0x0020; 628 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 629 630 data = mac[0]; 631 data |= mac[1] << 8; 632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 633 data = mac[2]; 634 data |= mac[3] << 8; 635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 636 data = mac[4]; 637 data |= mac[5] << 8; 638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 639} 640 641static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 642{ 643 const u8 *mac; 644 const u8 *bssid; 645 u8 mac_bssid[ETH_ALEN * 2]; 646 int i; 647 u32 tmp; 648 649 bssid = dev->wl->bssid; 650 mac = dev->wl->mac_addr; 651 652 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 653 654 memcpy(mac_bssid, mac, ETH_ALEN); 655 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 656 657 /* Write our MAC address and BSSID to template ram */ 658 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 659 tmp = (u32) (mac_bssid[i + 0]); 660 tmp |= (u32) (mac_bssid[i + 1]) << 8; 661 tmp |= (u32) (mac_bssid[i + 2]) << 16; 662 tmp |= (u32) (mac_bssid[i + 3]) << 24; 663 b43_ram_write(dev, 0x20 + i, tmp); 664 } 665} 666 667static void b43_upload_card_macaddress(struct b43_wldev *dev) 668{ 669 b43_write_mac_bssid_templates(dev); 670 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 671} 672 673static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 674{ 675 /* slot_time is in usec. */ 676 /* This test used to exit for all but a G PHY. */ 677 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 678 return; 679 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time); 680 /* Shared memory location 0x0010 is the slot time and should be 681 * set to slot_time; however, this register is initially 0 and changing 682 * the value adversely affects the transmit rate for BCM4311 683 * devices. Until this behavior is unterstood, delete this step 684 * 685 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 686 */ 687} 688 689static void b43_short_slot_timing_enable(struct b43_wldev *dev) 690{ 691 b43_set_slot_time(dev, 9); 692} 693 694static void b43_short_slot_timing_disable(struct b43_wldev *dev) 695{ 696 b43_set_slot_time(dev, 20); 697} 698 699/* DummyTransmission function, as documented on 700 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission 701 */ 702void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) 703{ 704 struct b43_phy *phy = &dev->phy; 705 unsigned int i, max_loop; 706 u16 value; 707 u32 buffer[5] = { 708 0x00000000, 709 0x00D40000, 710 0x00000000, 711 0x01000000, 712 0x00000000, 713 }; 714 715 if (ofdm) { 716 max_loop = 0x1E; 717 buffer[0] = 0x000201CC; 718 } else { 719 max_loop = 0xFA; 720 buffer[0] = 0x000B846E; 721 } 722 723 for (i = 0; i < 5; i++) 724 b43_ram_write(dev, i * 4, buffer[i]); 725 726 b43_write16(dev, 0x0568, 0x0000); 727 if (dev->dev->core_rev < 11) 728 b43_write16(dev, 0x07C0, 0x0000); 729 else 730 b43_write16(dev, 0x07C0, 0x0100); 731 value = (ofdm ? 0x41 : 0x40); 732 b43_write16(dev, 0x050C, value); 733 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP)) 734 b43_write16(dev, 0x0514, 0x1A02); 735 b43_write16(dev, 0x0508, 0x0000); 736 b43_write16(dev, 0x050A, 0x0000); 737 b43_write16(dev, 0x054C, 0x0000); 738 b43_write16(dev, 0x056A, 0x0014); 739 b43_write16(dev, 0x0568, 0x0826); 740 b43_write16(dev, 0x0500, 0x0000); 741 if (!pa_on && (phy->type == B43_PHYTYPE_N)) { 742 //SPEC TODO 743 } 744 745 switch (phy->type) { 746 case B43_PHYTYPE_N: 747 b43_write16(dev, 0x0502, 0x00D0); 748 break; 749 case B43_PHYTYPE_LP: 750 b43_write16(dev, 0x0502, 0x0050); 751 break; 752 default: 753 b43_write16(dev, 0x0502, 0x0030); 754 } 755 756 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 757 b43_radio_write16(dev, 0x0051, 0x0017); 758 for (i = 0x00; i < max_loop; i++) { 759 value = b43_read16(dev, 0x050E); 760 if (value & 0x0080) 761 break; 762 udelay(10); 763 } 764 for (i = 0x00; i < 0x0A; i++) { 765 value = b43_read16(dev, 0x050E); 766 if (value & 0x0400) 767 break; 768 udelay(10); 769 } 770 for (i = 0x00; i < 0x19; i++) { 771 value = b43_read16(dev, 0x0690); 772 if (!(value & 0x0100)) 773 break; 774 udelay(10); 775 } 776 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 777 b43_radio_write16(dev, 0x0051, 0x0037); 778} 779 780static void key_write(struct b43_wldev *dev, 781 u8 index, u8 algorithm, const u8 *key) 782{ 783 unsigned int i; 784 u32 offset; 785 u16 value; 786 u16 kidx; 787 788 /* Key index/algo block */ 789 kidx = b43_kidx_to_fw(dev, index); 790 value = ((kidx << 4) | algorithm); 791 b43_shm_write16(dev, B43_SHM_SHARED, 792 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 793 794 /* Write the key to the Key Table Pointer offset */ 795 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 796 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 797 value = key[i]; 798 value |= (u16) (key[i + 1]) << 8; 799 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 800 } 801} 802 803static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr) 804{ 805 u32 addrtmp[2] = { 0, 0, }; 806 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 807 808 if (b43_new_kidx_api(dev)) 809 pairwise_keys_start = B43_NR_GROUP_KEYS; 810 811 B43_WARN_ON(index < pairwise_keys_start); 812 /* We have four default TX keys and possibly four default RX keys. 813 * Physical mac 0 is mapped to physical key 4 or 8, depending 814 * on the firmware version. 815 * So we must adjust the index here. 816 */ 817 index -= pairwise_keys_start; 818 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 819 820 if (addr) { 821 addrtmp[0] = addr[0]; 822 addrtmp[0] |= ((u32) (addr[1]) << 8); 823 addrtmp[0] |= ((u32) (addr[2]) << 16); 824 addrtmp[0] |= ((u32) (addr[3]) << 24); 825 addrtmp[1] = addr[4]; 826 addrtmp[1] |= ((u32) (addr[5]) << 8); 827 } 828 829 /* Receive match transmitter address (RCMTA) mechanism */ 830 b43_shm_write32(dev, B43_SHM_RCMTA, 831 (index * 2) + 0, addrtmp[0]); 832 b43_shm_write16(dev, B43_SHM_RCMTA, 833 (index * 2) + 1, addrtmp[1]); 834} 835 836/* The ucode will use phase1 key with TEK key to decrypt rx packets. 837 * When a packet is received, the iv32 is checked. 838 * - if it doesn't the packet is returned without modification (and software 839 * decryption can be done). That's what happen when iv16 wrap. 840 * - if it does, the rc4 key is computed, and decryption is tried. 841 * Either it will success and B43_RX_MAC_DEC is returned, 842 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned 843 * and the packet is not usable (it got modified by the ucode). 844 * So in order to never have B43_RX_MAC_DECERR, we should provide 845 * a iv32 and phase1key that match. Because we drop packets in case of 846 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all 847 * packets will be lost without higher layer knowing (ie no resync possible 848 * until next wrap). 849 * 850 * NOTE : this should support 50 key like RCMTA because 851 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50 852 */ 853static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32, 854 u16 *phase1key) 855{ 856 unsigned int i; 857 u32 offset; 858 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 859 860 if (!modparam_hwtkip) 861 return; 862 863 if (b43_new_kidx_api(dev)) 864 pairwise_keys_start = B43_NR_GROUP_KEYS; 865 866 B43_WARN_ON(index < pairwise_keys_start); 867 /* We have four default TX keys and possibly four default RX keys. 868 * Physical mac 0 is mapped to physical key 4 or 8, depending 869 * on the firmware version. 870 * So we must adjust the index here. 871 */ 872 index -= pairwise_keys_start; 873 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 874 875 if (b43_debug(dev, B43_DBG_KEYS)) { 876 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", 877 index, iv32); 878 } 879 /* Write the key to the RX tkip shared mem */ 880 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4); 881 for (i = 0; i < 10; i += 2) { 882 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, 883 phase1key ? phase1key[i / 2] : 0); 884 } 885 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32); 886 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16); 887} 888 889static void b43_op_update_tkip_key(struct ieee80211_hw *hw, 890 struct ieee80211_vif *vif, 891 struct ieee80211_key_conf *keyconf, 892 struct ieee80211_sta *sta, 893 u32 iv32, u16 *phase1key) 894{ 895 struct b43_wl *wl = hw_to_b43_wl(hw); 896 struct b43_wldev *dev; 897 int index = keyconf->hw_key_idx; 898 899 if (B43_WARN_ON(!modparam_hwtkip)) 900 return; 901 902 /* This is only called from the RX path through mac80211, where 903 * our mutex is already locked. */ 904 B43_WARN_ON(!mutex_is_locked(&wl->mutex)); 905 dev = wl->current_dev; 906 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED); 907 908 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */ 909 910 rx_tkip_phase1_write(dev, index, iv32, phase1key); 911 /* only pairwise TKIP keys are supported right now */ 912 if (WARN_ON(!sta)) 913 return; 914 keymac_write(dev, index, sta->addr); 915} 916 917static void do_key_write(struct b43_wldev *dev, 918 u8 index, u8 algorithm, 919 const u8 *key, size_t key_len, const u8 *mac_addr) 920{ 921 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 922 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 923 924 if (b43_new_kidx_api(dev)) 925 pairwise_keys_start = B43_NR_GROUP_KEYS; 926 927 B43_WARN_ON(index >= ARRAY_SIZE(dev->key)); 928 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 929 930 if (index >= pairwise_keys_start) 931 keymac_write(dev, index, NULL); /* First zero out mac. */ 932 if (algorithm == B43_SEC_ALGO_TKIP) { 933 /* 934 * We should provide an initial iv32, phase1key pair. 935 * We could start with iv32=0 and compute the corresponding 936 * phase1key, but this means calling ieee80211_get_tkip_key 937 * with a fake skb (or export other tkip function). 938 * Because we are lazy we hope iv32 won't start with 939 * 0xffffffff and let's b43_op_update_tkip_key provide a 940 * correct pair. 941 */ 942 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); 943 } else if (index >= pairwise_keys_start) /* clear it */ 944 rx_tkip_phase1_write(dev, index, 0, NULL); 945 if (key) 946 memcpy(buf, key, key_len); 947 key_write(dev, index, algorithm, buf); 948 if (index >= pairwise_keys_start) 949 keymac_write(dev, index, mac_addr); 950 951 dev->key[index].algorithm = algorithm; 952} 953 954static int b43_key_write(struct b43_wldev *dev, 955 int index, u8 algorithm, 956 const u8 *key, size_t key_len, 957 const u8 *mac_addr, 958 struct ieee80211_key_conf *keyconf) 959{ 960 int i; 961 int pairwise_keys_start; 962 963 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block: 964 * - Temporal Encryption Key (128 bits) 965 * - Temporal Authenticator Tx MIC Key (64 bits) 966 * - Temporal Authenticator Rx MIC Key (64 bits) 967 * 968 * Hardware only store TEK 969 */ 970 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32) 971 key_len = 16; 972 if (key_len > B43_SEC_KEYSIZE) 973 return -EINVAL; 974 for (i = 0; i < ARRAY_SIZE(dev->key); i++) { 975 /* Check that we don't already have this key. */ 976 B43_WARN_ON(dev->key[i].keyconf == keyconf); 977 } 978 if (index < 0) { 979 /* Pairwise key. Get an empty slot for the key. */ 980 if (b43_new_kidx_api(dev)) 981 pairwise_keys_start = B43_NR_GROUP_KEYS; 982 else 983 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 984 for (i = pairwise_keys_start; 985 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS; 986 i++) { 987 B43_WARN_ON(i >= ARRAY_SIZE(dev->key)); 988 if (!dev->key[i].keyconf) { 989 /* found empty */ 990 index = i; 991 break; 992 } 993 } 994 if (index < 0) { 995 b43warn(dev->wl, "Out of hardware key memory\n"); 996 return -ENOSPC; 997 } 998 } else 999 B43_WARN_ON(index > 3); 1000 1001 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 1002 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1003 /* Default RX key */ 1004 B43_WARN_ON(mac_addr); 1005 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 1006 } 1007 keyconf->hw_key_idx = index; 1008 dev->key[index].keyconf = keyconf; 1009 1010 return 0; 1011} 1012 1013static int b43_key_clear(struct b43_wldev *dev, int index) 1014{ 1015 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) 1016 return -EINVAL; 1017 do_key_write(dev, index, B43_SEC_ALGO_NONE, 1018 NULL, B43_SEC_KEYSIZE, NULL); 1019 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1020 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 1021 NULL, B43_SEC_KEYSIZE, NULL); 1022 } 1023 dev->key[index].keyconf = NULL; 1024 1025 return 0; 1026} 1027 1028static void b43_clear_keys(struct b43_wldev *dev) 1029{ 1030 int i, count; 1031 1032 if (b43_new_kidx_api(dev)) 1033 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1034 else 1035 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1036 for (i = 0; i < count; i++) 1037 b43_key_clear(dev, i); 1038} 1039 1040static void b43_dump_keymemory(struct b43_wldev *dev) 1041{ 1042 unsigned int i, index, count, offset, pairwise_keys_start; 1043 u8 mac[ETH_ALEN]; 1044 u16 algo; 1045 u32 rcmta0; 1046 u16 rcmta1; 1047 u64 hf; 1048 struct b43_key *key; 1049 1050 if (!b43_debug(dev, B43_DBG_KEYS)) 1051 return; 1052 1053 hf = b43_hf_read(dev); 1054 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n", 1055 !!(hf & B43_HF_USEDEFKEYS)); 1056 if (b43_new_kidx_api(dev)) { 1057 pairwise_keys_start = B43_NR_GROUP_KEYS; 1058 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1059 } else { 1060 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 1061 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1062 } 1063 for (index = 0; index < count; index++) { 1064 key = &(dev->key[index]); 1065 printk(KERN_DEBUG "Key slot %02u: %s", 1066 index, (key->keyconf == NULL) ? " " : "*"); 1067 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 1068 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 1069 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1070 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1071 } 1072 1073 algo = b43_shm_read16(dev, B43_SHM_SHARED, 1074 B43_SHM_SH_KEYIDXBLOCK + (index * 2)); 1075 printk(" Algo: %04X/%02X", algo, key->algorithm); 1076 1077 if (index >= pairwise_keys_start) { 1078 if (key->algorithm == B43_SEC_ALGO_TKIP) { 1079 printk(" TKIP: "); 1080 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4); 1081 for (i = 0; i < 14; i += 2) { 1082 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1083 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1084 } 1085 } 1086 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA, 1087 ((index - pairwise_keys_start) * 2) + 0); 1088 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA, 1089 ((index - pairwise_keys_start) * 2) + 1); 1090 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); 1091 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1); 1092 printk(" MAC: %pM", mac); 1093 } else 1094 printk(" DEFAULT KEY"); 1095 printk("\n"); 1096 } 1097} 1098 1099void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 1100{ 1101 u32 macctl; 1102 u16 ucstat; 1103 bool hwps; 1104 bool awake; 1105 int i; 1106 1107 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 1108 (ps_flags & B43_PS_DISABLED)); 1109 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 1110 1111 if (ps_flags & B43_PS_ENABLED) { 1112 hwps = 1; 1113 } else if (ps_flags & B43_PS_DISABLED) { 1114 hwps = 0; 1115 } else { 1116 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 1117 // and thus is not an AP and we are associated, set bit 25 1118 } 1119 if (ps_flags & B43_PS_AWAKE) { 1120 awake = 1; 1121 } else if (ps_flags & B43_PS_ASLEEP) { 1122 awake = 0; 1123 } else { 1124 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 1125 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 1126 // successful, set bit26 1127 } 1128 1129/* FIXME: For now we force awake-on and hwps-off */ 1130 hwps = 0; 1131 awake = 1; 1132 1133 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1134 if (hwps) 1135 macctl |= B43_MACCTL_HWPS; 1136 else 1137 macctl &= ~B43_MACCTL_HWPS; 1138 if (awake) 1139 macctl |= B43_MACCTL_AWAKE; 1140 else 1141 macctl &= ~B43_MACCTL_AWAKE; 1142 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1143 /* Commit write */ 1144 b43_read32(dev, B43_MMIO_MACCTL); 1145 if (awake && dev->dev->core_rev >= 5) { 1146 /* Wait for the microcode to wake up. */ 1147 for (i = 0; i < 100; i++) { 1148 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 1149 B43_SHM_SH_UCODESTAT); 1150 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 1151 break; 1152 udelay(10); 1153 } 1154 } 1155} 1156 1157#ifdef CONFIG_B43_BCMA 1158static void b43_bcma_phy_reset(struct b43_wldev *dev) 1159{ 1160 u32 flags; 1161 1162 /* Put PHY into reset */ 1163 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1164 flags |= B43_BCMA_IOCTL_PHY_RESET; 1165 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */ 1166 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1167 udelay(2); 1168 1169 /* Take PHY out of reset */ 1170 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1171 flags &= ~B43_BCMA_IOCTL_PHY_RESET; 1172 flags |= BCMA_IOCTL_FGC; 1173 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1174 udelay(1); 1175 1176 /* Do not force clock anymore */ 1177 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1178 flags &= ~BCMA_IOCTL_FGC; 1179 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1180 udelay(1); 1181} 1182 1183static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1184{ 1185 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN); 1186 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST); 1187 b43_bcma_phy_reset(dev); 1188 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true); 1189} 1190#endif 1191 1192static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1193{ 1194 struct ssb_device *sdev = dev->dev->sdev; 1195 u32 tmslow; 1196 u32 flags = 0; 1197 1198 if (gmode) 1199 flags |= B43_TMSLOW_GMODE; 1200 flags |= B43_TMSLOW_PHYCLKEN; 1201 flags |= B43_TMSLOW_PHYRESET; 1202 if (dev->phy.type == B43_PHYTYPE_N) 1203 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */ 1204 b43_device_enable(dev, flags); 1205 msleep(2); /* Wait for the PLL to turn on. */ 1206 1207 /* Now take the PHY out of Reset again */ 1208 tmslow = ssb_read32(sdev, SSB_TMSLOW); 1209 tmslow |= SSB_TMSLOW_FGC; 1210 tmslow &= ~B43_TMSLOW_PHYRESET; 1211 ssb_write32(sdev, SSB_TMSLOW, tmslow); 1212 ssb_read32(sdev, SSB_TMSLOW); /* flush */ 1213 msleep(1); 1214 tmslow &= ~SSB_TMSLOW_FGC; 1215 ssb_write32(sdev, SSB_TMSLOW, tmslow); 1216 ssb_read32(sdev, SSB_TMSLOW); /* flush */ 1217 msleep(1); 1218} 1219 1220void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1221{ 1222 u32 macctl; 1223 1224 switch (dev->dev->bus_type) { 1225#ifdef CONFIG_B43_BCMA 1226 case B43_BUS_BCMA: 1227 b43_bcma_wireless_core_reset(dev, gmode); 1228 break; 1229#endif 1230#ifdef CONFIG_B43_SSB 1231 case B43_BUS_SSB: 1232 b43_ssb_wireless_core_reset(dev, gmode); 1233 break; 1234#endif 1235 } 1236 1237 /* Turn Analog ON, but only if we already know the PHY-type. 1238 * This protects against very early setup where we don't know the 1239 * PHY-type, yet. wireless_core_reset will be called once again later, 1240 * when we know the PHY-type. */ 1241 if (dev->phy.ops) 1242 dev->phy.ops->switch_analog(dev, 1); 1243 1244 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1245 macctl &= ~B43_MACCTL_GMODE; 1246 if (gmode) 1247 macctl |= B43_MACCTL_GMODE; 1248 macctl |= B43_MACCTL_IHR_ENABLED; 1249 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1250} 1251 1252static void handle_irq_transmit_status(struct b43_wldev *dev) 1253{ 1254 u32 v0, v1; 1255 u16 tmp; 1256 struct b43_txstatus stat; 1257 1258 while (1) { 1259 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1260 if (!(v0 & 0x00000001)) 1261 break; 1262 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1263 1264 stat.cookie = (v0 >> 16); 1265 stat.seq = (v1 & 0x0000FFFF); 1266 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 1267 tmp = (v0 & 0x0000FFFF); 1268 stat.frame_count = ((tmp & 0xF000) >> 12); 1269 stat.rts_count = ((tmp & 0x0F00) >> 8); 1270 stat.supp_reason = ((tmp & 0x001C) >> 2); 1271 stat.pm_indicated = !!(tmp & 0x0080); 1272 stat.intermediate = !!(tmp & 0x0040); 1273 stat.for_ampdu = !!(tmp & 0x0020); 1274 stat.acked = !!(tmp & 0x0002); 1275 1276 b43_handle_txstatus(dev, &stat); 1277 } 1278} 1279 1280static void drain_txstatus_queue(struct b43_wldev *dev) 1281{ 1282 u32 dummy; 1283 1284 if (dev->dev->core_rev < 5) 1285 return; 1286 /* Read all entries from the microcode TXstatus FIFO 1287 * and throw them away. 1288 */ 1289 while (1) { 1290 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1291 if (!(dummy & 0x00000001)) 1292 break; 1293 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1294 } 1295} 1296 1297static u32 b43_jssi_read(struct b43_wldev *dev) 1298{ 1299 u32 val = 0; 1300 1301 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 1302 val <<= 16; 1303 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1304 1305 return val; 1306} 1307 1308static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1309{ 1310 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1311 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1312} 1313 1314static void b43_generate_noise_sample(struct b43_wldev *dev) 1315{ 1316 b43_jssi_write(dev, 0x7F7F7F7F); 1317 b43_write32(dev, B43_MMIO_MACCMD, 1318 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1319} 1320 1321static void b43_calculate_link_quality(struct b43_wldev *dev) 1322{ 1323 /* Top half of Link Quality calculation. */ 1324 1325 if (dev->phy.type != B43_PHYTYPE_G) 1326 return; 1327 if (dev->noisecalc.calculation_running) 1328 return; 1329 dev->noisecalc.calculation_running = 1; 1330 dev->noisecalc.nr_samples = 0; 1331 1332 b43_generate_noise_sample(dev); 1333} 1334 1335static void handle_irq_noise(struct b43_wldev *dev) 1336{ 1337 struct b43_phy_g *phy = dev->phy.g; 1338 u16 tmp; 1339 u8 noise[4]; 1340 u8 i, j; 1341 s32 average; 1342 1343 /* Bottom half of Link Quality calculation. */ 1344 1345 if (dev->phy.type != B43_PHYTYPE_G) 1346 return; 1347 1348 /* Possible race condition: It might be possible that the user 1349 * changed to a different channel in the meantime since we 1350 * started the calculation. We ignore that fact, since it's 1351 * not really that much of a problem. The background noise is 1352 * an estimation only anyway. Slightly wrong results will get damped 1353 * by the averaging of the 8 sample rounds. Additionally the 1354 * value is shortlived. So it will be replaced by the next noise 1355 * calculation round soon. */ 1356 1357 B43_WARN_ON(!dev->noisecalc.calculation_running); 1358 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1359 if (noise[0] == 0x7F || noise[1] == 0x7F || 1360 noise[2] == 0x7F || noise[3] == 0x7F) 1361 goto generate_new; 1362 1363 /* Get the noise samples. */ 1364 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1365 i = dev->noisecalc.nr_samples; 1366 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1367 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1368 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1369 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1370 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1371 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1372 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1373 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1374 dev->noisecalc.nr_samples++; 1375 if (dev->noisecalc.nr_samples == 8) { 1376 /* Calculate the Link Quality by the noise samples. */ 1377 average = 0; 1378 for (i = 0; i < 8; i++) { 1379 for (j = 0; j < 4; j++) 1380 average += dev->noisecalc.samples[i][j]; 1381 } 1382 average /= (8 * 4); 1383 average *= 125; 1384 average += 64; 1385 average /= 128; 1386 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1387 tmp = (tmp / 128) & 0x1F; 1388 if (tmp >= 8) 1389 average += 2; 1390 else 1391 average -= 25; 1392 if (tmp == 8) 1393 average -= 72; 1394 else 1395 average -= 48; 1396 1397 dev->stats.link_noise = average; 1398 dev->noisecalc.calculation_running = 0; 1399 return; 1400 } 1401generate_new: 1402 b43_generate_noise_sample(dev); 1403} 1404 1405static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1406{ 1407 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) { 1408 ///TODO: PS TBTT 1409 } else { 1410 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1411 b43_power_saving_ctl_bits(dev, 0); 1412 } 1413 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 1414 dev->dfq_valid = 1; 1415} 1416 1417static void handle_irq_atim_end(struct b43_wldev *dev) 1418{ 1419 if (dev->dfq_valid) { 1420 b43_write32(dev, B43_MMIO_MACCMD, 1421 b43_read32(dev, B43_MMIO_MACCMD) 1422 | B43_MACCMD_DFQ_VALID); 1423 dev->dfq_valid = 0; 1424 } 1425} 1426 1427static void handle_irq_pmq(struct b43_wldev *dev) 1428{ 1429 u32 tmp; 1430 1431 //TODO: AP mode. 1432 1433 while (1) { 1434 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1435 if (!(tmp & 0x00000008)) 1436 break; 1437 } 1438 /* 16bit write is odd, but correct. */ 1439 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1440} 1441 1442static void b43_write_template_common(struct b43_wldev *dev, 1443 const u8 *data, u16 size, 1444 u16 ram_offset, 1445 u16 shm_size_offset, u8 rate) 1446{ 1447 u32 i, tmp; 1448 struct b43_plcp_hdr4 plcp; 1449 1450 plcp.data = 0; 1451 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1452 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1453 ram_offset += sizeof(u32); 1454 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1455 * So leave the first two bytes of the next write blank. 1456 */ 1457 tmp = (u32) (data[0]) << 16; 1458 tmp |= (u32) (data[1]) << 24; 1459 b43_ram_write(dev, ram_offset, tmp); 1460 ram_offset += sizeof(u32); 1461 for (i = 2; i < size; i += sizeof(u32)) { 1462 tmp = (u32) (data[i + 0]); 1463 if (i + 1 < size) 1464 tmp |= (u32) (data[i + 1]) << 8; 1465 if (i + 2 < size) 1466 tmp |= (u32) (data[i + 2]) << 16; 1467 if (i + 3 < size) 1468 tmp |= (u32) (data[i + 3]) << 24; 1469 b43_ram_write(dev, ram_offset + i - 2, tmp); 1470 } 1471 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1472 size + sizeof(struct b43_plcp_hdr6)); 1473} 1474 1475/* Check if the use of the antenna that ieee80211 told us to 1476 * use is possible. This will fall back to DEFAULT. 1477 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 1478u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 1479 u8 antenna_nr) 1480{ 1481 u8 antenna_mask; 1482 1483 if (antenna_nr == 0) { 1484 /* Zero means "use default antenna". That's always OK. */ 1485 return 0; 1486 } 1487 1488 /* Get the mask of available antennas. */ 1489 if (dev->phy.gmode) 1490 antenna_mask = dev->dev->bus_sprom->ant_available_bg; 1491 else 1492 antenna_mask = dev->dev->bus_sprom->ant_available_a; 1493 1494 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 1495 /* This antenna is not available. Fall back to default. */ 1496 return 0; 1497 } 1498 1499 return antenna_nr; 1500} 1501 1502/* Convert a b43 antenna number value to the PHY TX control value. */ 1503static u16 b43_antenna_to_phyctl(int antenna) 1504{ 1505 switch (antenna) { 1506 case B43_ANTENNA0: 1507 return B43_TXH_PHY_ANT0; 1508 case B43_ANTENNA1: 1509 return B43_TXH_PHY_ANT1; 1510 case B43_ANTENNA2: 1511 return B43_TXH_PHY_ANT2; 1512 case B43_ANTENNA3: 1513 return B43_TXH_PHY_ANT3; 1514 case B43_ANTENNA_AUTO0: 1515 case B43_ANTENNA_AUTO1: 1516 return B43_TXH_PHY_ANT01AUTO; 1517 } 1518 B43_WARN_ON(1); 1519 return 0; 1520} 1521 1522static void b43_write_beacon_template(struct b43_wldev *dev, 1523 u16 ram_offset, 1524 u16 shm_size_offset) 1525{ 1526 unsigned int i, len, variable_len; 1527 const struct ieee80211_mgmt *bcn; 1528 const u8 *ie; 1529 bool tim_found = 0; 1530 unsigned int rate; 1531 u16 ctl; 1532 int antenna; 1533 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon); 1534 1535 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1536 len = min((size_t) dev->wl->current_beacon->len, 1537 0x200 - sizeof(struct b43_plcp_hdr6)); 1538 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; 1539 1540 b43_write_template_common(dev, (const u8 *)bcn, 1541 len, ram_offset, shm_size_offset, rate); 1542 1543 /* Write the PHY TX control parameters. */ 1544 antenna = B43_ANTENNA_DEFAULT; 1545 antenna = b43_antenna_to_phyctl(antenna); 1546 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 1547 /* We can't send beacons with short preamble. Would get PHY errors. */ 1548 ctl &= ~B43_TXH_PHY_SHORTPRMBL; 1549 ctl &= ~B43_TXH_PHY_ANT; 1550 ctl &= ~B43_TXH_PHY_ENC; 1551 ctl |= antenna; 1552 if (b43_is_cck_rate(rate)) 1553 ctl |= B43_TXH_PHY_ENC_CCK; 1554 else 1555 ctl |= B43_TXH_PHY_ENC_OFDM; 1556 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 1557 1558 /* Find the position of the TIM and the DTIM_period value 1559 * and write them to SHM. */ 1560 ie = bcn->u.beacon.variable; 1561 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1562 for (i = 0; i < variable_len - 2; ) { 1563 uint8_t ie_id, ie_len; 1564 1565 ie_id = ie[i]; 1566 ie_len = ie[i + 1]; 1567 if (ie_id == 5) { 1568 u16 tim_position; 1569 u16 dtim_period; 1570 /* This is the TIM Information Element */ 1571 1572 /* Check whether the ie_len is in the beacon data range. */ 1573 if (variable_len < ie_len + 2 + i) 1574 break; 1575 /* A valid TIM is at least 4 bytes long. */ 1576 if (ie_len < 4) 1577 break; 1578 tim_found = 1; 1579 1580 tim_position = sizeof(struct b43_plcp_hdr6); 1581 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1582 tim_position += i; 1583 1584 dtim_period = ie[i + 3]; 1585 1586 b43_shm_write16(dev, B43_SHM_SHARED, 1587 B43_SHM_SH_TIMBPOS, tim_position); 1588 b43_shm_write16(dev, B43_SHM_SHARED, 1589 B43_SHM_SH_DTIMPER, dtim_period); 1590 break; 1591 } 1592 i += ie_len + 2; 1593 } 1594 if (!tim_found) { 1595 /* 1596 * If ucode wants to modify TIM do it behind the beacon, this 1597 * will happen, for example, when doing mesh networking. 1598 */ 1599 b43_shm_write16(dev, B43_SHM_SHARED, 1600 B43_SHM_SH_TIMBPOS, 1601 len + sizeof(struct b43_plcp_hdr6)); 1602 b43_shm_write16(dev, B43_SHM_SHARED, 1603 B43_SHM_SH_DTIMPER, 0); 1604 } 1605 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); 1606} 1607 1608static void b43_upload_beacon0(struct b43_wldev *dev) 1609{ 1610 struct b43_wl *wl = dev->wl; 1611 1612 if (wl->beacon0_uploaded) 1613 return; 1614 b43_write_beacon_template(dev, 0x68, 0x18); 1615 wl->beacon0_uploaded = 1; 1616} 1617 1618static void b43_upload_beacon1(struct b43_wldev *dev) 1619{ 1620 struct b43_wl *wl = dev->wl; 1621 1622 if (wl->beacon1_uploaded) 1623 return; 1624 b43_write_beacon_template(dev, 0x468, 0x1A); 1625 wl->beacon1_uploaded = 1; 1626} 1627 1628static void handle_irq_beacon(struct b43_wldev *dev) 1629{ 1630 struct b43_wl *wl = dev->wl; 1631 u32 cmd, beacon0_valid, beacon1_valid; 1632 1633 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && 1634 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 1635 return; 1636 1637 /* This is the bottom half of the asynchronous beacon update. */ 1638 1639 /* Ignore interrupt in the future. */ 1640 dev->irq_mask &= ~B43_IRQ_BEACON; 1641 1642 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1643 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); 1644 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); 1645 1646 /* Schedule interrupt manually, if busy. */ 1647 if (beacon0_valid && beacon1_valid) { 1648 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1649 dev->irq_mask |= B43_IRQ_BEACON; 1650 return; 1651 } 1652 1653 if (unlikely(wl->beacon_templates_virgin)) { 1654 /* We never uploaded a beacon before. 1655 * Upload both templates now, but only mark one valid. */ 1656 wl->beacon_templates_virgin = 0; 1657 b43_upload_beacon0(dev); 1658 b43_upload_beacon1(dev); 1659 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1660 cmd |= B43_MACCMD_BEACON0_VALID; 1661 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1662 } else { 1663 if (!beacon0_valid) { 1664 b43_upload_beacon0(dev); 1665 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1666 cmd |= B43_MACCMD_BEACON0_VALID; 1667 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1668 } else if (!beacon1_valid) { 1669 b43_upload_beacon1(dev); 1670 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1671 cmd |= B43_MACCMD_BEACON1_VALID; 1672 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1673 } 1674 } 1675} 1676 1677static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev) 1678{ 1679 u32 old_irq_mask = dev->irq_mask; 1680 1681 /* update beacon right away or defer to irq */ 1682 handle_irq_beacon(dev); 1683 if (old_irq_mask != dev->irq_mask) { 1684 /* The handler updated the IRQ mask. */ 1685 B43_WARN_ON(!dev->irq_mask); 1686 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) { 1687 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1688 } else { 1689 /* Device interrupts are currently disabled. That means 1690 * we just ran the hardirq handler and scheduled the 1691 * IRQ thread. The thread will write the IRQ mask when 1692 * it finished, so there's nothing to do here. Writing 1693 * the mask _here_ would incorrectly re-enable IRQs. */ 1694 } 1695 } 1696} 1697 1698static void b43_beacon_update_trigger_work(struct work_struct *work) 1699{ 1700 struct b43_wl *wl = container_of(work, struct b43_wl, 1701 beacon_update_trigger); 1702 struct b43_wldev *dev; 1703 1704 mutex_lock(&wl->mutex); 1705 dev = wl->current_dev; 1706 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { 1707 if (b43_bus_host_is_sdio(dev->dev)) { 1708 /* wl->mutex is enough. */ 1709 b43_do_beacon_update_trigger_work(dev); 1710 mmiowb(); 1711 } else { 1712 spin_lock_irq(&wl->hardirq_lock); 1713 b43_do_beacon_update_trigger_work(dev); 1714 mmiowb(); 1715 spin_unlock_irq(&wl->hardirq_lock); 1716 } 1717 } 1718 mutex_unlock(&wl->mutex); 1719} 1720 1721/* Asynchronously update the packet templates in template RAM. 1722 * Locking: Requires wl->mutex to be locked. */ 1723static void b43_update_templates(struct b43_wl *wl) 1724{ 1725 struct sk_buff *beacon; 1726 1727 /* This is the top half of the ansynchronous beacon update. 1728 * The bottom half is the beacon IRQ. 1729 * Beacon update must be asynchronous to avoid sending an 1730 * invalid beacon. This can happen for example, if the firmware 1731 * transmits a beacon while we are updating it. */ 1732 1733 /* We could modify the existing beacon and set the aid bit in 1734 * the TIM field, but that would probably require resizing and 1735 * moving of data within the beacon template. 1736 * Simply request a new beacon and let mac80211 do the hard work. */ 1737 beacon = ieee80211_beacon_get(wl->hw, wl->vif); 1738 if (unlikely(!beacon)) 1739 return; 1740 1741 if (wl->current_beacon) 1742 dev_kfree_skb_any(wl->current_beacon); 1743 wl->current_beacon = beacon; 1744 wl->beacon0_uploaded = 0; 1745 wl->beacon1_uploaded = 0; 1746 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); 1747} 1748 1749static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1750{ 1751 b43_time_lock(dev); 1752 if (dev->dev->core_rev >= 3) { 1753 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); 1754 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); 1755 } else { 1756 b43_write16(dev, 0x606, (beacon_int >> 6)); 1757 b43_write16(dev, 0x610, beacon_int); 1758 } 1759 b43_time_unlock(dev); 1760 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1761} 1762 1763static void b43_handle_firmware_panic(struct b43_wldev *dev) 1764{ 1765 u16 reason; 1766 1767 /* Read the register that contains the reason code for the panic. */ 1768 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG); 1769 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason); 1770 1771 switch (reason) { 1772 default: 1773 b43dbg(dev->wl, "The panic reason is unknown.\n"); 1774 /* fallthrough */ 1775 case B43_FWPANIC_DIE: 1776 /* Do not restart the controller or firmware. 1777 * The device is nonfunctional from now on. 1778 * Restarting would result in this panic to trigger again, 1779 * so we avoid that recursion. */ 1780 break; 1781 case B43_FWPANIC_RESTART: 1782 b43_controller_restart(dev, "Microcode panic"); 1783 break; 1784 } 1785} 1786 1787static void handle_irq_ucode_debug(struct b43_wldev *dev) 1788{ 1789 unsigned int i, cnt; 1790 u16 reason, marker_id, marker_line; 1791 __le16 *buf; 1792 1793 /* The proprietary firmware doesn't have this IRQ. */ 1794 if (!dev->fw.opensource) 1795 return; 1796 1797 /* Read the register that contains the reason code for this IRQ. */ 1798 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG); 1799 1800 switch (reason) { 1801 case B43_DEBUGIRQ_PANIC: 1802 b43_handle_firmware_panic(dev); 1803 break; 1804 case B43_DEBUGIRQ_DUMP_SHM: 1805 if (!B43_DEBUG) 1806 break; /* Only with driver debugging enabled. */ 1807 buf = kmalloc(4096, GFP_ATOMIC); 1808 if (!buf) { 1809 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n"); 1810 goto out; 1811 } 1812 for (i = 0; i < 4096; i += 2) { 1813 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i); 1814 buf[i / 2] = cpu_to_le16(tmp); 1815 } 1816 b43info(dev->wl, "Shared memory dump:\n"); 1817 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 1818 16, 2, buf, 4096, 1); 1819 kfree(buf); 1820 break; 1821 case B43_DEBUGIRQ_DUMP_REGS: 1822 if (!B43_DEBUG) 1823 break; /* Only with driver debugging enabled. */ 1824 b43info(dev->wl, "Microcode register dump:\n"); 1825 for (i = 0, cnt = 0; i < 64; i++) { 1826 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i); 1827 if (cnt == 0) 1828 printk(KERN_INFO); 1829 printk("r%02u: 0x%04X ", i, tmp); 1830 cnt++; 1831 if (cnt == 6) { 1832 printk("\n"); 1833 cnt = 0; 1834 } 1835 } 1836 printk("\n"); 1837 break; 1838 case B43_DEBUGIRQ_MARKER: 1839 if (!B43_DEBUG) 1840 break; /* Only with driver debugging enabled. */ 1841 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH, 1842 B43_MARKER_ID_REG); 1843 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH, 1844 B43_MARKER_LINE_REG); 1845 b43info(dev->wl, "The firmware just executed the MARKER(%u) " 1846 "at line number %u\n", 1847 marker_id, marker_line); 1848 break; 1849 default: 1850 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n", 1851 reason); 1852 } 1853out: 1854 /* Acknowledge the debug-IRQ, so the firmware can continue. */ 1855 b43_shm_write16(dev, B43_SHM_SCRATCH, 1856 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK); 1857} 1858 1859static void b43_do_interrupt_thread(struct b43_wldev *dev) 1860{ 1861 u32 reason; 1862 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1863 u32 merged_dma_reason = 0; 1864 int i; 1865 1866 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 1867 return; 1868 1869 reason = dev->irq_reason; 1870 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1871 dma_reason[i] = dev->dma_reason[i]; 1872 merged_dma_reason |= dma_reason[i]; 1873 } 1874 1875 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1876 b43err(dev->wl, "MAC transmission error\n"); 1877 1878 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1879 b43err(dev->wl, "PHY transmission error\n"); 1880 rmb(); 1881 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1882 atomic_set(&dev->phy.txerr_cnt, 1883 B43_PHY_TX_BADNESS_LIMIT); 1884 b43err(dev->wl, "Too many PHY TX errors, " 1885 "restarting the controller\n"); 1886 b43_controller_restart(dev, "PHY TX errors"); 1887 } 1888 } 1889 1890 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1891 B43_DMAIRQ_NONFATALMASK))) { 1892 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1893 b43err(dev->wl, "Fatal DMA error: " 1894 "0x%08X, 0x%08X, 0x%08X, " 1895 "0x%08X, 0x%08X, 0x%08X\n", 1896 dma_reason[0], dma_reason[1], 1897 dma_reason[2], dma_reason[3], 1898 dma_reason[4], dma_reason[5]); 1899 b43err(dev->wl, "This device does not support DMA " 1900 "on your system. It will now be switched to PIO.\n"); 1901 /* Fall back to PIO transfers if we get fatal DMA errors! */ 1902 dev->use_pio = 1; 1903 b43_controller_restart(dev, "DMA error"); 1904 return; 1905 } 1906 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1907 b43err(dev->wl, "DMA error: " 1908 "0x%08X, 0x%08X, 0x%08X, " 1909 "0x%08X, 0x%08X, 0x%08X\n", 1910 dma_reason[0], dma_reason[1], 1911 dma_reason[2], dma_reason[3], 1912 dma_reason[4], dma_reason[5]); 1913 } 1914 } 1915 1916 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1917 handle_irq_ucode_debug(dev); 1918 if (reason & B43_IRQ_TBTT_INDI) 1919 handle_irq_tbtt_indication(dev); 1920 if (reason & B43_IRQ_ATIM_END) 1921 handle_irq_atim_end(dev); 1922 if (reason & B43_IRQ_BEACON) 1923 handle_irq_beacon(dev); 1924 if (reason & B43_IRQ_PMQ) 1925 handle_irq_pmq(dev); 1926 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1927 ;/* TODO */ 1928 if (reason & B43_IRQ_NOISESAMPLE_OK) 1929 handle_irq_noise(dev); 1930 1931 /* Check the DMA reason registers for received data. */ 1932 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 1933 if (b43_using_pio_transfers(dev)) 1934 b43_pio_rx(dev->pio.rx_queue); 1935 else 1936 b43_dma_rx(dev->dma.rx_ring); 1937 } 1938 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1939 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1940 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); 1941 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1942 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1943 1944 if (reason & B43_IRQ_TX_OK) 1945 handle_irq_transmit_status(dev); 1946 1947 /* Re-enable interrupts on the device by restoring the current interrupt mask. */ 1948 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1949 1950#if B43_DEBUG 1951 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 1952 dev->irq_count++; 1953 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 1954 if (reason & (1 << i)) 1955 dev->irq_bit_count[i]++; 1956 } 1957 } 1958#endif 1959} 1960 1961/* Interrupt thread handler. Handles device interrupts in thread context. */ 1962static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id) 1963{ 1964 struct b43_wldev *dev = dev_id; 1965 1966 mutex_lock(&dev->wl->mutex); 1967 b43_do_interrupt_thread(dev); 1968 mmiowb(); 1969 mutex_unlock(&dev->wl->mutex); 1970 1971 return IRQ_HANDLED; 1972} 1973 1974static irqreturn_t b43_do_interrupt(struct b43_wldev *dev) 1975{ 1976 u32 reason; 1977 1978 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses. 1979 * On SDIO, this runs under wl->mutex. */ 1980 1981 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1982 if (reason == 0xffffffff) /* shared IRQ */ 1983 return IRQ_NONE; 1984 reason &= dev->irq_mask; 1985 if (!reason) 1986 return IRQ_NONE; 1987 1988 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1989 & 0x0001DC00; 1990 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1991 & 0x0000DC00; 1992 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1993 & 0x0000DC00; 1994 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1995 & 0x0001DC00; 1996 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1997 & 0x0000DC00; 1998/* Unused ring 1999 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 2000 & 0x0000DC00; 2001*/ 2002 2003 /* ACK the interrupt. */ 2004 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 2005 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 2006 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 2007 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 2008 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 2009 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 2010/* Unused ring 2011 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 2012*/ 2013 2014 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */ 2015 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 2016 /* Save the reason bitmasks for the IRQ thread handler. */ 2017 dev->irq_reason = reason; 2018 2019 return IRQ_WAKE_THREAD; 2020} 2021 2022/* Interrupt handler top-half. This runs with interrupts disabled. */ 2023static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 2024{ 2025 struct b43_wldev *dev = dev_id; 2026 irqreturn_t ret; 2027 2028 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2029 return IRQ_NONE; 2030 2031 spin_lock(&dev->wl->hardirq_lock); 2032 ret = b43_do_interrupt(dev); 2033 mmiowb(); 2034 spin_unlock(&dev->wl->hardirq_lock); 2035 2036 return ret; 2037} 2038 2039/* SDIO interrupt handler. This runs in process context. */ 2040static void b43_sdio_interrupt_handler(struct b43_wldev *dev) 2041{ 2042 struct b43_wl *wl = dev->wl; 2043 irqreturn_t ret; 2044 2045 mutex_lock(&wl->mutex); 2046 2047 ret = b43_do_interrupt(dev); 2048 if (ret == IRQ_WAKE_THREAD) 2049 b43_do_interrupt_thread(dev); 2050 2051 mutex_unlock(&wl->mutex); 2052} 2053 2054void b43_do_release_fw(struct b43_firmware_file *fw) 2055{ 2056 release_firmware(fw->data); 2057 fw->data = NULL; 2058 fw->filename = NULL; 2059} 2060 2061static void b43_release_firmware(struct b43_wldev *dev) 2062{ 2063 b43_do_release_fw(&dev->fw.ucode); 2064 b43_do_release_fw(&dev->fw.pcm); 2065 b43_do_release_fw(&dev->fw.initvals); 2066 b43_do_release_fw(&dev->fw.initvals_band); 2067} 2068 2069static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 2070{ 2071 const char text[] = 2072 "You must go to " \ 2073 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \ 2074 "and download the correct firmware for this driver version. " \ 2075 "Please carefully read all instructions on this website.\n"; 2076 2077 if (error) 2078 b43err(wl, text); 2079 else 2080 b43warn(wl, text); 2081} 2082 2083int b43_do_request_fw(struct b43_request_fw_context *ctx, 2084 const char *name, 2085 struct b43_firmware_file *fw) 2086{ 2087 const struct firmware *blob; 2088 struct b43_fw_header *hdr; 2089 u32 size; 2090 int err; 2091 2092 if (!name) { 2093 /* Don't fetch anything. Free possibly cached firmware. */ 2094 /* FIXME: We should probably keep it anyway, to save some headache 2095 * on suspend/resume with multiband devices. */ 2096 b43_do_release_fw(fw); 2097 return 0; 2098 } 2099 if (fw->filename) { 2100 if ((fw->type == ctx->req_type) && 2101 (strcmp(fw->filename, name) == 0)) 2102 return 0; /* Already have this fw. */ 2103 /* Free the cached firmware first. */ 2104 /* FIXME: We should probably do this later after we successfully 2105 * got the new fw. This could reduce headache with multiband devices. 2106 * We could also redesign this to cache the firmware for all possible 2107 * bands all the time. */ 2108 b43_do_release_fw(fw); 2109 } 2110 2111 switch (ctx->req_type) { 2112 case B43_FWTYPE_PROPRIETARY: 2113 snprintf(ctx->fwname, sizeof(ctx->fwname), 2114 "b43%s/%s.fw", 2115 modparam_fwpostfix, name); 2116 break; 2117 case B43_FWTYPE_OPENSOURCE: 2118 snprintf(ctx->fwname, sizeof(ctx->fwname), 2119 "b43-open%s/%s.fw", 2120 modparam_fwpostfix, name); 2121 break; 2122 default: 2123 B43_WARN_ON(1); 2124 return -ENOSYS; 2125 } 2126 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev); 2127 if (err == -ENOENT) { 2128 snprintf(ctx->errors[ctx->req_type], 2129 sizeof(ctx->errors[ctx->req_type]), 2130 "Firmware file \"%s\" not found\n", ctx->fwname); 2131 return err; 2132 } else if (err) { 2133 snprintf(ctx->errors[ctx->req_type], 2134 sizeof(ctx->errors[ctx->req_type]), 2135 "Firmware file \"%s\" request failed (err=%d)\n", 2136 ctx->fwname, err); 2137 return err; 2138 } 2139 if (blob->size < sizeof(struct b43_fw_header)) 2140 goto err_format; 2141 hdr = (struct b43_fw_header *)(blob->data); 2142 switch (hdr->type) { 2143 case B43_FW_TYPE_UCODE: 2144 case B43_FW_TYPE_PCM: 2145 size = be32_to_cpu(hdr->size); 2146 if (size != blob->size - sizeof(struct b43_fw_header)) 2147 goto err_format; 2148 /* fallthrough */ 2149 case B43_FW_TYPE_IV: 2150 if (hdr->ver != 1) 2151 goto err_format; 2152 break; 2153 default: 2154 goto err_format; 2155 } 2156 2157 fw->data = blob; 2158 fw->filename = name; 2159 fw->type = ctx->req_type; 2160 2161 return 0; 2162 2163err_format: 2164 snprintf(ctx->errors[ctx->req_type], 2165 sizeof(ctx->errors[ctx->req_type]), 2166 "Firmware file \"%s\" format error.\n", ctx->fwname); 2167 release_firmware(blob); 2168 2169 return -EPROTO; 2170} 2171 2172static int b43_try_request_fw(struct b43_request_fw_context *ctx) 2173{ 2174 struct b43_wldev *dev = ctx->dev; 2175 struct b43_firmware *fw = &ctx->dev->fw; 2176 const u8 rev = ctx->dev->dev->core_rev; 2177 const char *filename; 2178 u32 tmshigh; 2179 int err; 2180 2181 /* Files for HT and LCN were found by trying one by one */ 2182 2183 /* Get microcode */ 2184 if ((rev >= 5) && (rev <= 10)) { 2185 filename = "ucode5"; 2186 } else if ((rev >= 11) && (rev <= 12)) { 2187 filename = "ucode11"; 2188 } else if (rev == 13) { 2189 filename = "ucode13"; 2190 } else if (rev == 14) { 2191 filename = "ucode14"; 2192 } else if (rev == 15) { 2193 filename = "ucode15"; 2194 } else { 2195 switch (dev->phy.type) { 2196 case B43_PHYTYPE_N: 2197 if (rev >= 16) 2198 filename = "ucode16_mimo"; 2199 else 2200 goto err_no_ucode; 2201 break; 2202 case B43_PHYTYPE_HT: 2203 if (rev == 29) 2204 filename = "ucode29_mimo"; 2205 else 2206 goto err_no_ucode; 2207 break; 2208 case B43_PHYTYPE_LCN: 2209 if (rev == 24) 2210 filename = "ucode24_mimo"; 2211 else 2212 goto err_no_ucode; 2213 break; 2214 default: 2215 goto err_no_ucode; 2216 } 2217 } 2218 err = b43_do_request_fw(ctx, filename, &fw->ucode); 2219 if (err) 2220 goto err_load; 2221 2222 /* Get PCM code */ 2223 if ((rev >= 5) && (rev <= 10)) 2224 filename = "pcm5"; 2225 else if (rev >= 11) 2226 filename = NULL; 2227 else 2228 goto err_no_pcm; 2229 fw->pcm_request_failed = 0; 2230 err = b43_do_request_fw(ctx, filename, &fw->pcm); 2231 if (err == -ENOENT) { 2232 /* We did not find a PCM file? Not fatal, but 2233 * core rev <= 10 must do without hwcrypto then. */ 2234 fw->pcm_request_failed = 1; 2235 } else if (err) 2236 goto err_load; 2237 2238 /* Get initvals */ 2239 switch (dev->phy.type) { 2240 case B43_PHYTYPE_A: 2241 if ((rev >= 5) && (rev <= 10)) { 2242 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 2243 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2244 filename = "a0g1initvals5"; 2245 else 2246 filename = "a0g0initvals5"; 2247 } else 2248 goto err_no_initvals; 2249 break; 2250 case B43_PHYTYPE_G: 2251 if ((rev >= 5) && (rev <= 10)) 2252 filename = "b0g0initvals5"; 2253 else if (rev >= 13) 2254 filename = "b0g0initvals13"; 2255 else 2256 goto err_no_initvals; 2257 break; 2258 case B43_PHYTYPE_N: 2259 if (rev >= 16) 2260 filename = "n0initvals16"; 2261 else if ((rev >= 11) && (rev <= 12)) 2262 filename = "n0initvals11"; 2263 else 2264 goto err_no_initvals; 2265 break; 2266 case B43_PHYTYPE_LP: 2267 if (rev == 13) 2268 filename = "lp0initvals13"; 2269 else if (rev == 14) 2270 filename = "lp0initvals14"; 2271 else if (rev >= 15) 2272 filename = "lp0initvals15"; 2273 else 2274 goto err_no_initvals; 2275 break; 2276 case B43_PHYTYPE_HT: 2277 if (rev == 29) 2278 filename = "ht0initvals29"; 2279 else 2280 goto err_no_initvals; 2281 break; 2282 case B43_PHYTYPE_LCN: 2283 if (rev == 24) 2284 filename = "lcn0initvals24"; 2285 else 2286 goto err_no_initvals; 2287 break; 2288 default: 2289 goto err_no_initvals; 2290 } 2291 err = b43_do_request_fw(ctx, filename, &fw->initvals); 2292 if (err) 2293 goto err_load; 2294 2295 /* Get bandswitch initvals */ 2296 switch (dev->phy.type) { 2297 case B43_PHYTYPE_A: 2298 if ((rev >= 5) && (rev <= 10)) { 2299 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 2300 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2301 filename = "a0g1bsinitvals5"; 2302 else 2303 filename = "a0g0bsinitvals5"; 2304 } else if (rev >= 11) 2305 filename = NULL; 2306 else 2307 goto err_no_initvals; 2308 break; 2309 case B43_PHYTYPE_G: 2310 if ((rev >= 5) && (rev <= 10)) 2311 filename = "b0g0bsinitvals5"; 2312 else if (rev >= 11) 2313 filename = NULL; 2314 else 2315 goto err_no_initvals; 2316 break; 2317 case B43_PHYTYPE_N: 2318 if (rev >= 16) 2319 filename = "n0bsinitvals16"; 2320 else if ((rev >= 11) && (rev <= 12)) 2321 filename = "n0bsinitvals11"; 2322 else 2323 goto err_no_initvals; 2324 break; 2325 case B43_PHYTYPE_LP: 2326 if (rev == 13) 2327 filename = "lp0bsinitvals13"; 2328 else if (rev == 14) 2329 filename = "lp0bsinitvals14"; 2330 else if (rev >= 15) 2331 filename = "lp0bsinitvals15"; 2332 else 2333 goto err_no_initvals; 2334 break; 2335 case B43_PHYTYPE_HT: 2336 if (rev == 29) 2337 filename = "ht0bsinitvals29"; 2338 else 2339 goto err_no_initvals; 2340 break; 2341 case B43_PHYTYPE_LCN: 2342 if (rev == 24) 2343 filename = "lcn0bsinitvals24"; 2344 else 2345 goto err_no_initvals; 2346 break; 2347 default: 2348 goto err_no_initvals; 2349 } 2350 err = b43_do_request_fw(ctx, filename, &fw->initvals_band); 2351 if (err) 2352 goto err_load; 2353 2354 return 0; 2355 2356err_no_ucode: 2357 err = ctx->fatal_failure = -EOPNOTSUPP; 2358 b43err(dev->wl, "The driver does not know which firmware (ucode) " 2359 "is required for your device (wl-core rev %u)\n", rev); 2360 goto error; 2361 2362err_no_pcm: 2363 err = ctx->fatal_failure = -EOPNOTSUPP; 2364 b43err(dev->wl, "The driver does not know which firmware (PCM) " 2365 "is required for your device (wl-core rev %u)\n", rev); 2366 goto error; 2367 2368err_no_initvals: 2369 err = ctx->fatal_failure = -EOPNOTSUPP; 2370 b43err(dev->wl, "The driver does not know which firmware (initvals) " 2371 "is required for your device (wl-core rev %u)\n", rev); 2372 goto error; 2373 2374err_load: 2375 /* We failed to load this firmware image. The error message 2376 * already is in ctx->errors. Return and let our caller decide 2377 * what to do. */ 2378 goto error; 2379 2380error: 2381 b43_release_firmware(dev); 2382 return err; 2383} 2384 2385static int b43_request_firmware(struct b43_wldev *dev) 2386{ 2387 struct b43_request_fw_context *ctx; 2388 unsigned int i; 2389 int err; 2390 const char *errmsg; 2391 2392 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2393 if (!ctx) 2394 return -ENOMEM; 2395 ctx->dev = dev; 2396 2397 ctx->req_type = B43_FWTYPE_PROPRIETARY; 2398 err = b43_try_request_fw(ctx); 2399 if (!err) 2400 goto out; /* Successfully loaded it. */ 2401 err = ctx->fatal_failure; 2402 if (err) 2403 goto out; 2404 2405 ctx->req_type = B43_FWTYPE_OPENSOURCE; 2406 err = b43_try_request_fw(ctx); 2407 if (!err) 2408 goto out; /* Successfully loaded it. */ 2409 err = ctx->fatal_failure; 2410 if (err) 2411 goto out; 2412 2413 /* Could not find a usable firmware. Print the errors. */ 2414 for (i = 0; i < B43_NR_FWTYPES; i++) { 2415 errmsg = ctx->errors[i]; 2416 if (strlen(errmsg)) 2417 b43err(dev->wl, errmsg); 2418 } 2419 b43_print_fw_helptext(dev->wl, 1); 2420 err = -ENOENT; 2421 2422out: 2423 kfree(ctx); 2424 return err; 2425} 2426 2427static int b43_upload_microcode(struct b43_wldev *dev) 2428{ 2429 struct wiphy *wiphy = dev->wl->hw->wiphy; 2430 const size_t hdr_len = sizeof(struct b43_fw_header); 2431 const __be32 *data; 2432 unsigned int i, len; 2433 u16 fwrev, fwpatch, fwdate, fwtime; 2434 u32 tmp, macctl; 2435 int err = 0; 2436 2437 /* Jump the microcode PSM to offset 0 */ 2438 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2439 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); 2440 macctl |= B43_MACCTL_PSM_JMP0; 2441 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2442 /* Zero out all microcode PSM registers and shared memory. */ 2443 for (i = 0; i < 64; i++) 2444 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); 2445 for (i = 0; i < 4096; i += 2) 2446 b43_shm_write16(dev, B43_SHM_SHARED, i, 0); 2447 2448 /* Upload Microcode. */ 2449 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); 2450 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); 2451 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 2452 for (i = 0; i < len; i++) { 2453 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2454 udelay(10); 2455 } 2456 2457 if (dev->fw.pcm.data) { 2458 /* Upload PCM data. */ 2459 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); 2460 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); 2461 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 2462 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 2463 /* No need for autoinc bit in SHM_HW */ 2464 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 2465 for (i = 0; i < len; i++) { 2466 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2467 udelay(10); 2468 } 2469 } 2470 2471 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 2472 2473 /* Start the microcode PSM */ 2474 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2475 macctl &= ~B43_MACCTL_PSM_JMP0; 2476 macctl |= B43_MACCTL_PSM_RUN; 2477 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2478 2479 /* Wait for the microcode to load and respond */ 2480 i = 0; 2481 while (1) { 2482 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2483 if (tmp == B43_IRQ_MAC_SUSPENDED) 2484 break; 2485 i++; 2486 if (i >= 20) { 2487 b43err(dev->wl, "Microcode not responding\n"); 2488 b43_print_fw_helptext(dev->wl, 1); 2489 err = -ENODEV; 2490 goto error; 2491 } 2492 msleep(50); 2493 } 2494 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 2495 2496 /* Get and check the revisions. */ 2497 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 2498 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 2499 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 2500 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 2501 2502 if (fwrev <= 0x128) { 2503 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 2504 "binary drivers older than version 4.x is unsupported. " 2505 "You must upgrade your firmware files.\n"); 2506 b43_print_fw_helptext(dev->wl, 1); 2507 err = -EOPNOTSUPP; 2508 goto error; 2509 } 2510 dev->fw.rev = fwrev; 2511 dev->fw.patch = fwpatch; 2512 dev->fw.opensource = (fwdate == 0xFFFF); 2513 2514 /* Default to use-all-queues. */ 2515 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues; 2516 dev->qos_enabled = !!modparam_qos; 2517 /* Default to firmware/hardware crypto acceleration. */ 2518 dev->hwcrypto_enabled = 1; 2519 2520 if (dev->fw.opensource) { 2521 u16 fwcapa; 2522 2523 /* Patchlevel info is encoded in the "time" field. */ 2524 dev->fw.patch = fwtime; 2525 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n", 2526 dev->fw.rev, dev->fw.patch); 2527 2528 fwcapa = b43_fwcapa_read(dev); 2529 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) { 2530 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n"); 2531 /* Disable hardware crypto and fall back to software crypto. */ 2532 dev->hwcrypto_enabled = 0; 2533 } 2534 if (!(fwcapa & B43_FWCAPA_QOS)) { 2535 b43info(dev->wl, "QoS not supported by firmware\n"); 2536 /* Disable QoS. Tweak hw->queues to 1. It will be restored before 2537 * ieee80211_unregister to make sure the networking core can 2538 * properly free possible resources. */ 2539 dev->wl->hw->queues = 1; 2540 dev->qos_enabled = 0; 2541 } 2542 } else { 2543 b43info(dev->wl, "Loading firmware version %u.%u " 2544 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 2545 fwrev, fwpatch, 2546 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 2547 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 2548 if (dev->fw.pcm_request_failed) { 2549 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. " 2550 "Hardware accelerated cryptography is disabled.\n"); 2551 b43_print_fw_helptext(dev->wl, 0); 2552 } 2553 } 2554 2555 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", 2556 dev->fw.rev, dev->fw.patch); 2557 wiphy->hw_version = dev->dev->core_id; 2558 2559 if (b43_is_old_txhdr_format(dev)) { 2560 /* We're over the deadline, but we keep support for old fw 2561 * until it turns out to be in major conflict with something new. */ 2562 b43warn(dev->wl, "You are using an old firmware image. " 2563 "Support for old firmware will be removed soon " 2564 "(official deadline was July 2008).\n"); 2565 b43_print_fw_helptext(dev->wl, 0); 2566 } 2567 2568 return 0; 2569 2570error: 2571 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2572 macctl &= ~B43_MACCTL_PSM_RUN; 2573 macctl |= B43_MACCTL_PSM_JMP0; 2574 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2575 2576 return err; 2577} 2578 2579static int b43_write_initvals(struct b43_wldev *dev, 2580 const struct b43_iv *ivals, 2581 size_t count, 2582 size_t array_size) 2583{ 2584 const struct b43_iv *iv; 2585 u16 offset; 2586 size_t i; 2587 bool bit32; 2588 2589 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 2590 iv = ivals; 2591 for (i = 0; i < count; i++) { 2592 if (array_size < sizeof(iv->offset_size)) 2593 goto err_format; 2594 array_size -= sizeof(iv->offset_size); 2595 offset = be16_to_cpu(iv->offset_size); 2596 bit32 = !!(offset & B43_IV_32BIT); 2597 offset &= B43_IV_OFFSET_MASK; 2598 if (offset >= 0x1000) 2599 goto err_format; 2600 if (bit32) { 2601 u32 value; 2602 2603 if (array_size < sizeof(iv->data.d32)) 2604 goto err_format; 2605 array_size -= sizeof(iv->data.d32); 2606 2607 value = get_unaligned_be32(&iv->data.d32); 2608 b43_write32(dev, offset, value); 2609 2610 iv = (const struct b43_iv *)((const uint8_t *)iv + 2611 sizeof(__be16) + 2612 sizeof(__be32)); 2613 } else { 2614 u16 value; 2615 2616 if (array_size < sizeof(iv->data.d16)) 2617 goto err_format; 2618 array_size -= sizeof(iv->data.d16); 2619 2620 value = be16_to_cpu(iv->data.d16); 2621 b43_write16(dev, offset, value); 2622 2623 iv = (const struct b43_iv *)((const uint8_t *)iv + 2624 sizeof(__be16) + 2625 sizeof(__be16)); 2626 } 2627 } 2628 if (array_size) 2629 goto err_format; 2630 2631 return 0; 2632 2633err_format: 2634 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 2635 b43_print_fw_helptext(dev->wl, 1); 2636 2637 return -EPROTO; 2638} 2639 2640static int b43_upload_initvals(struct b43_wldev *dev) 2641{ 2642 const size_t hdr_len = sizeof(struct b43_fw_header); 2643 const struct b43_fw_header *hdr; 2644 struct b43_firmware *fw = &dev->fw; 2645 const struct b43_iv *ivals; 2646 size_t count; 2647 int err; 2648 2649 hdr = (const struct b43_fw_header *)(fw->initvals.data->data); 2650 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); 2651 count = be32_to_cpu(hdr->size); 2652 err = b43_write_initvals(dev, ivals, count, 2653 fw->initvals.data->size - hdr_len); 2654 if (err) 2655 goto out; 2656 if (fw->initvals_band.data) { 2657 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); 2658 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); 2659 count = be32_to_cpu(hdr->size); 2660 err = b43_write_initvals(dev, ivals, count, 2661 fw->initvals_band.data->size - hdr_len); 2662 if (err) 2663 goto out; 2664 } 2665out: 2666 2667 return err; 2668} 2669 2670/* Initialize the GPIOs 2671 * http://bcm-specs.sipsolutions.net/GPIO 2672 */ 2673static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev) 2674{ 2675 struct ssb_bus *bus = dev->dev->sdev->bus; 2676 2677#ifdef CONFIG_SSB_DRIVER_PCICORE 2678 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev); 2679#else 2680 return bus->chipco.dev; 2681#endif 2682} 2683 2684static int b43_gpio_init(struct b43_wldev *dev) 2685{ 2686 struct ssb_device *gpiodev; 2687 u32 mask, set; 2688 2689 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2690 & ~B43_MACCTL_GPOUTSMSK); 2691 2692 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 2693 | 0x000F); 2694 2695 mask = 0x0000001F; 2696 set = 0x0000000F; 2697 if (dev->dev->chip_id == 0x4301) { 2698 mask |= 0x0060; 2699 set |= 0x0060; 2700 } 2701 if (0 /* FIXME: conditional unknown */ ) { 2702 b43_write16(dev, B43_MMIO_GPIO_MASK, 2703 b43_read16(dev, B43_MMIO_GPIO_MASK) 2704 | 0x0100); 2705 mask |= 0x0180; 2706 set |= 0x0180; 2707 } 2708 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) { 2709 b43_write16(dev, B43_MMIO_GPIO_MASK, 2710 b43_read16(dev, B43_MMIO_GPIO_MASK) 2711 | 0x0200); 2712 mask |= 0x0200; 2713 set |= 0x0200; 2714 } 2715 if (dev->dev->core_rev >= 2) 2716 mask |= 0x0010; /* FIXME: This is redundant. */ 2717 2718 switch (dev->dev->bus_type) { 2719#ifdef CONFIG_B43_BCMA 2720 case B43_BUS_BCMA: 2721 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL, 2722 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc, 2723 BCMA_CC_GPIOCTL) & mask) | set); 2724 break; 2725#endif 2726#ifdef CONFIG_B43_SSB 2727 case B43_BUS_SSB: 2728 gpiodev = b43_ssb_gpio_dev(dev); 2729 if (gpiodev) 2730 ssb_write32(gpiodev, B43_GPIO_CONTROL, 2731 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2732 & mask) | set); 2733 break; 2734#endif 2735 } 2736 2737 return 0; 2738} 2739 2740/* Turn off all GPIO stuff. Call this on module unload, for example. */ 2741static void b43_gpio_cleanup(struct b43_wldev *dev) 2742{ 2743 struct ssb_device *gpiodev; 2744 2745 switch (dev->dev->bus_type) { 2746#ifdef CONFIG_B43_BCMA 2747 case B43_BUS_BCMA: 2748 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL, 2749 0); 2750 break; 2751#endif 2752#ifdef CONFIG_B43_SSB 2753 case B43_BUS_SSB: 2754 gpiodev = b43_ssb_gpio_dev(dev); 2755 if (gpiodev) 2756 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2757 break; 2758#endif 2759 } 2760} 2761 2762/* http://bcm-specs.sipsolutions.net/EnableMac */ 2763void b43_mac_enable(struct b43_wldev *dev) 2764{ 2765 if (b43_debug(dev, B43_DBG_FIRMWARE)) { 2766 u16 fwstate; 2767 2768 fwstate = b43_shm_read16(dev, B43_SHM_SHARED, 2769 B43_SHM_SH_UCODESTAT); 2770 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) && 2771 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) { 2772 b43err(dev->wl, "b43_mac_enable(): The firmware " 2773 "should be suspended, but current state is %u\n", 2774 fwstate); 2775 } 2776 } 2777 2778 dev->mac_suspended--; 2779 B43_WARN_ON(dev->mac_suspended < 0); 2780 if (dev->mac_suspended == 0) { 2781 b43_write32(dev, B43_MMIO_MACCTL, 2782 b43_read32(dev, B43_MMIO_MACCTL) 2783 | B43_MACCTL_ENABLED); 2784 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2785 B43_IRQ_MAC_SUSPENDED); 2786 /* Commit writes */ 2787 b43_read32(dev, B43_MMIO_MACCTL); 2788 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2789 b43_power_saving_ctl_bits(dev, 0); 2790 } 2791} 2792 2793/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2794void b43_mac_suspend(struct b43_wldev *dev) 2795{ 2796 int i; 2797 u32 tmp; 2798 2799 might_sleep(); 2800 B43_WARN_ON(dev->mac_suspended < 0); 2801 2802 if (dev->mac_suspended == 0) { 2803 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2804 b43_write32(dev, B43_MMIO_MACCTL, 2805 b43_read32(dev, B43_MMIO_MACCTL) 2806 & ~B43_MACCTL_ENABLED); 2807 /* force pci to flush the write */ 2808 b43_read32(dev, B43_MMIO_MACCTL); 2809 for (i = 35; i; i--) { 2810 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2811 if (tmp & B43_IRQ_MAC_SUSPENDED) 2812 goto out; 2813 udelay(10); 2814 } 2815 /* Hm, it seems this will take some time. Use msleep(). */ 2816 for (i = 40; i; i--) { 2817 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2818 if (tmp & B43_IRQ_MAC_SUSPENDED) 2819 goto out; 2820 msleep(1); 2821 } 2822 b43err(dev->wl, "MAC suspend failed\n"); 2823 } 2824out: 2825 dev->mac_suspended++; 2826} 2827 2828/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 2829void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on) 2830{ 2831 u32 tmp; 2832 2833 switch (dev->dev->bus_type) { 2834#ifdef CONFIG_B43_BCMA 2835 case B43_BUS_BCMA: 2836 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 2837 if (on) 2838 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN; 2839 else 2840 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN; 2841 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); 2842 break; 2843#endif 2844#ifdef CONFIG_B43_SSB 2845 case B43_BUS_SSB: 2846 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 2847 if (on) 2848 tmp |= B43_TMSLOW_MACPHYCLKEN; 2849 else 2850 tmp &= ~B43_TMSLOW_MACPHYCLKEN; 2851 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 2852 break; 2853#endif 2854 } 2855} 2856 2857static void b43_adjust_opmode(struct b43_wldev *dev) 2858{ 2859 struct b43_wl *wl = dev->wl; 2860 u32 ctl; 2861 u16 cfp_pretbtt; 2862 2863 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2864 /* Reset status to STA infrastructure mode. */ 2865 ctl &= ~B43_MACCTL_AP; 2866 ctl &= ~B43_MACCTL_KEEP_CTL; 2867 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2868 ctl &= ~B43_MACCTL_KEEP_BAD; 2869 ctl &= ~B43_MACCTL_PROMISC; 2870 ctl &= ~B43_MACCTL_BEACPROMISC; 2871 ctl |= B43_MACCTL_INFRA; 2872 2873 if (b43_is_mode(wl, NL80211_IFTYPE_AP) || 2874 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 2875 ctl |= B43_MACCTL_AP; 2876 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 2877 ctl &= ~B43_MACCTL_INFRA; 2878 2879 if (wl->filter_flags & FIF_CONTROL) 2880 ctl |= B43_MACCTL_KEEP_CTL; 2881 if (wl->filter_flags & FIF_FCSFAIL) 2882 ctl |= B43_MACCTL_KEEP_BAD; 2883 if (wl->filter_flags & FIF_PLCPFAIL) 2884 ctl |= B43_MACCTL_KEEP_BADPLCP; 2885 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2886 ctl |= B43_MACCTL_PROMISC; 2887 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2888 ctl |= B43_MACCTL_BEACPROMISC; 2889 2890 /* Workaround: On old hardware the HW-MAC-address-filter 2891 * doesn't work properly, so always run promisc in filter 2892 * it in software. */ 2893 if (dev->dev->core_rev <= 4) 2894 ctl |= B43_MACCTL_PROMISC; 2895 2896 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2897 2898 cfp_pretbtt = 2; 2899 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2900 if (dev->dev->chip_id == 0x4306 && 2901 dev->dev->chip_rev == 3) 2902 cfp_pretbtt = 100; 2903 else 2904 cfp_pretbtt = 50; 2905 } 2906 b43_write16(dev, 0x612, cfp_pretbtt); 2907 2908 /* FIXME: We don't currently implement the PMQ mechanism, 2909 * so always disable it. If we want to implement PMQ, 2910 * we need to enable it here (clear DISCPMQ) in AP mode. 2911 */ 2912 if (0 /* ctl & B43_MACCTL_AP */) { 2913 b43_write32(dev, B43_MMIO_MACCTL, 2914 b43_read32(dev, B43_MMIO_MACCTL) 2915 & ~B43_MACCTL_DISCPMQ); 2916 } else { 2917 b43_write32(dev, B43_MMIO_MACCTL, 2918 b43_read32(dev, B43_MMIO_MACCTL) 2919 | B43_MACCTL_DISCPMQ); 2920 } 2921} 2922 2923static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2924{ 2925 u16 offset; 2926 2927 if (is_ofdm) { 2928 offset = 0x480; 2929 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2930 } else { 2931 offset = 0x4C0; 2932 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2933 } 2934 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2935 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2936} 2937 2938static void b43_rate_memory_init(struct b43_wldev *dev) 2939{ 2940 switch (dev->phy.type) { 2941 case B43_PHYTYPE_A: 2942 case B43_PHYTYPE_G: 2943 case B43_PHYTYPE_N: 2944 case B43_PHYTYPE_LP: 2945 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2946 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2947 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2948 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2949 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2950 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2951 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2952 if (dev->phy.type == B43_PHYTYPE_A) 2953 break; 2954 /* fallthrough */ 2955 case B43_PHYTYPE_B: 2956 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2957 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2958 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2959 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2960 break; 2961 default: 2962 B43_WARN_ON(1); 2963 } 2964} 2965 2966/* Set the default values for the PHY TX Control Words. */ 2967static void b43_set_phytxctl_defaults(struct b43_wldev *dev) 2968{ 2969 u16 ctl = 0; 2970 2971 ctl |= B43_TXH_PHY_ENC_CCK; 2972 ctl |= B43_TXH_PHY_ANT01AUTO; 2973 ctl |= B43_TXH_PHY_TXPWR; 2974 2975 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 2976 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); 2977 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); 2978} 2979 2980/* Set the TX-Antenna for management frames sent by firmware. */ 2981static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2982{ 2983 u16 ant; 2984 u16 tmp; 2985 2986 ant = b43_antenna_to_phyctl(antenna); 2987 2988 /* For ACK/CTS */ 2989 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2990 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2991 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2992 /* For Probe Resposes */ 2993 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2994 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2995 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2996} 2997 2998/* This is the opposite of b43_chip_init() */ 2999static void b43_chip_exit(struct b43_wldev *dev) 3000{ 3001 b43_phy_exit(dev); 3002 b43_gpio_cleanup(dev); 3003 /* firmware is released later */ 3004} 3005 3006/* Initialize the chip 3007 * http://bcm-specs.sipsolutions.net/ChipInit 3008 */ 3009static int b43_chip_init(struct b43_wldev *dev) 3010{ 3011 struct b43_phy *phy = &dev->phy; 3012 int err; 3013 u32 macctl; 3014 u16 value16; 3015 3016 /* Initialize the MAC control */ 3017 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; 3018 if (dev->phy.gmode) 3019 macctl |= B43_MACCTL_GMODE; 3020 macctl |= B43_MACCTL_INFRA; 3021 b43_write32(dev, B43_MMIO_MACCTL, macctl); 3022 3023 err = b43_request_firmware(dev); 3024 if (err) 3025 goto out; 3026 err = b43_upload_microcode(dev); 3027 if (err) 3028 goto out; /* firmware is released later */ 3029 3030 err = b43_gpio_init(dev); 3031 if (err) 3032 goto out; /* firmware is released later */ 3033 3034 err = b43_upload_initvals(dev); 3035 if (err) 3036 goto err_gpio_clean; 3037 3038 /* Turn the Analog on and initialize the PHY. */ 3039 phy->ops->switch_analog(dev, 1); 3040 err = b43_phy_init(dev); 3041 if (err) 3042 goto err_gpio_clean; 3043 3044 /* Disable Interference Mitigation. */ 3045 if (phy->ops->interf_mitigation) 3046 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); 3047 3048 /* Select the antennae */ 3049 if (phy->ops->set_rx_antenna) 3050 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 3051 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 3052 3053 if (phy->type == B43_PHYTYPE_B) { 3054 value16 = b43_read16(dev, 0x005E); 3055 value16 |= 0x0004; 3056 b43_write16(dev, 0x005E, value16); 3057 } 3058 b43_write32(dev, 0x0100, 0x01000000); 3059 if (dev->dev->core_rev < 5) 3060 b43_write32(dev, 0x010C, 0x01000000); 3061 3062 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 3063 & ~B43_MACCTL_INFRA); 3064 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 3065 | B43_MACCTL_INFRA); 3066 3067 /* Probe Response Timeout value */ 3068 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 3069 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 3070 3071 /* Initially set the wireless operation mode. */ 3072 b43_adjust_opmode(dev); 3073 3074 if (dev->dev->core_rev < 3) { 3075 b43_write16(dev, 0x060E, 0x0000); 3076 b43_write16(dev, 0x0610, 0x8000); 3077 b43_write16(dev, 0x0604, 0x0000); 3078 b43_write16(dev, 0x0606, 0x0200); 3079 } else { 3080 b43_write32(dev, 0x0188, 0x80000000); 3081 b43_write32(dev, 0x018C, 0x02000000); 3082 } 3083 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 3084 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 3085 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 3086 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 3087 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 3088 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 3089 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 3090 3091 b43_mac_phy_clock_set(dev, true); 3092 3093 switch (dev->dev->bus_type) { 3094#ifdef CONFIG_B43_BCMA 3095 case B43_BUS_BCMA: 3096 /* FIXME: 0xE74 is quite common, but should be read from CC */ 3097 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74); 3098 break; 3099#endif 3100#ifdef CONFIG_B43_SSB 3101 case B43_BUS_SSB: 3102 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 3103 dev->dev->sdev->bus->chipco.fast_pwrup_delay); 3104 break; 3105#endif 3106 } 3107 3108 err = 0; 3109 b43dbg(dev->wl, "Chip initialized\n"); 3110out: 3111 return err; 3112 3113err_gpio_clean: 3114 b43_gpio_cleanup(dev); 3115 return err; 3116} 3117 3118static void b43_periodic_every60sec(struct b43_wldev *dev) 3119{ 3120 const struct b43_phy_operations *ops = dev->phy.ops; 3121 3122 if (ops->pwork_60sec) 3123 ops->pwork_60sec(dev); 3124 3125 /* Force check the TX power emission now. */ 3126 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME); 3127} 3128 3129static void b43_periodic_every30sec(struct b43_wldev *dev) 3130{ 3131 /* Update device statistics. */ 3132 b43_calculate_link_quality(dev); 3133} 3134 3135static void b43_periodic_every15sec(struct b43_wldev *dev) 3136{ 3137 struct b43_phy *phy = &dev->phy; 3138 u16 wdr; 3139 3140 if (dev->fw.opensource) { 3141 /* Check if the firmware is still alive. 3142 * It will reset the watchdog counter to 0 in its idle loop. */ 3143 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG); 3144 if (unlikely(wdr)) { 3145 b43err(dev->wl, "Firmware watchdog: The firmware died!\n"); 3146 b43_controller_restart(dev, "Firmware watchdog"); 3147 return; 3148 } else { 3149 b43_shm_write16(dev, B43_SHM_SCRATCH, 3150 B43_WATCHDOG_REG, 1); 3151 } 3152 } 3153 3154 if (phy->ops->pwork_15sec) 3155 phy->ops->pwork_15sec(dev); 3156 3157 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3158 wmb(); 3159 3160#if B43_DEBUG 3161 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 3162 unsigned int i; 3163 3164 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n", 3165 dev->irq_count / 15, 3166 dev->tx_count / 15, 3167 dev->rx_count / 15); 3168 dev->irq_count = 0; 3169 dev->tx_count = 0; 3170 dev->rx_count = 0; 3171 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 3172 if (dev->irq_bit_count[i]) { 3173 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", 3174 dev->irq_bit_count[i] / 15, i, (1 << i)); 3175 dev->irq_bit_count[i] = 0; 3176 } 3177 } 3178 } 3179#endif 3180} 3181 3182static void do_periodic_work(struct b43_wldev *dev) 3183{ 3184 unsigned int state; 3185 3186 state = dev->periodic_state; 3187 if (state % 4 == 0) 3188 b43_periodic_every60sec(dev); 3189 if (state % 2 == 0) 3190 b43_periodic_every30sec(dev); 3191 b43_periodic_every15sec(dev); 3192} 3193 3194/* Periodic work locking policy: 3195 * The whole periodic work handler is protected by 3196 * wl->mutex. If another lock is needed somewhere in the 3197 * pwork callchain, it's acquired in-place, where it's needed. 3198 */ 3199static void b43_periodic_work_handler(struct work_struct *work) 3200{ 3201 struct b43_wldev *dev = container_of(work, struct b43_wldev, 3202 periodic_work.work); 3203 struct b43_wl *wl = dev->wl; 3204 unsigned long delay; 3205 3206 mutex_lock(&wl->mutex); 3207 3208 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 3209 goto out; 3210 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 3211 goto out_requeue; 3212 3213 do_periodic_work(dev); 3214 3215 dev->periodic_state++; 3216out_requeue: 3217 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 3218 delay = msecs_to_jiffies(50); 3219 else 3220 delay = round_jiffies_relative(HZ * 15); 3221 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); 3222out: 3223 mutex_unlock(&wl->mutex); 3224} 3225 3226static void b43_periodic_tasks_setup(struct b43_wldev *dev) 3227{ 3228 struct delayed_work *work = &dev->periodic_work; 3229 3230 dev->periodic_state = 0; 3231 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 3232 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); 3233} 3234 3235/* Check if communication with the device works correctly. */ 3236static int b43_validate_chipaccess(struct b43_wldev *dev) 3237{ 3238 u32 v, backup0, backup4; 3239 3240 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); 3241 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4); 3242 3243 /* Check for read/write and endianness problems. */ 3244 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 3245 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 3246 goto error; 3247 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 3248 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 3249 goto error; 3250 3251 /* Check if unaligned 32bit SHM_SHARED access works properly. 3252 * However, don't bail out on failure, because it's noncritical. */ 3253 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); 3254 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); 3255 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); 3256 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); 3257 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) 3258 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n"); 3259 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); 3260 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || 3261 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || 3262 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || 3263 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) 3264 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n"); 3265 3266 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); 3267 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); 3268 3269 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) { 3270 /* The 32bit register shadows the two 16bit registers 3271 * with update sideeffects. Validate this. */ 3272 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 3273 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 3274 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 3275 goto error; 3276 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 3277 goto error; 3278 } 3279 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 3280 3281 v = b43_read32(dev, B43_MMIO_MACCTL); 3282 v |= B43_MACCTL_GMODE; 3283 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 3284 goto error; 3285 3286 return 0; 3287error: 3288 b43err(dev->wl, "Failed to validate the chipaccess\n"); 3289 return -ENODEV; 3290} 3291 3292static void b43_security_init(struct b43_wldev *dev) 3293{ 3294 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 3295 /* KTP is a word address, but we address SHM bytewise. 3296 * So multiply by two. 3297 */ 3298 dev->ktp *= 2; 3299 /* Number of RCMTA address slots */ 3300 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS); 3301 /* Clear the key memory. */ 3302 b43_clear_keys(dev); 3303} 3304 3305#ifdef CONFIG_B43_HWRNG 3306static int b43_rng_read(struct hwrng *rng, u32 *data) 3307{ 3308 struct b43_wl *wl = (struct b43_wl *)rng->priv; 3309 struct b43_wldev *dev; 3310 int count = -ENODEV; 3311 3312 mutex_lock(&wl->mutex); 3313 dev = wl->current_dev; 3314 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) { 3315 *data = b43_read16(dev, B43_MMIO_RNG); 3316 count = sizeof(u16); 3317 } 3318 mutex_unlock(&wl->mutex); 3319 3320 return count; 3321} 3322#endif /* CONFIG_B43_HWRNG */ 3323 3324static void b43_rng_exit(struct b43_wl *wl) 3325{ 3326#ifdef CONFIG_B43_HWRNG 3327 if (wl->rng_initialized) 3328 hwrng_unregister(&wl->rng); 3329#endif /* CONFIG_B43_HWRNG */ 3330} 3331 3332static int b43_rng_init(struct b43_wl *wl) 3333{ 3334 int err = 0; 3335 3336#ifdef CONFIG_B43_HWRNG 3337 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 3338 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 3339 wl->rng.name = wl->rng_name; 3340 wl->rng.data_read = b43_rng_read; 3341 wl->rng.priv = (unsigned long)wl; 3342 wl->rng_initialized = 1; 3343 err = hwrng_register(&wl->rng); 3344 if (err) { 3345 wl->rng_initialized = 0; 3346 b43err(wl, "Failed to register the random " 3347 "number generator (%d)\n", err); 3348 } 3349#endif /* CONFIG_B43_HWRNG */ 3350 3351 return err; 3352} 3353 3354static void b43_tx_work(struct work_struct *work) 3355{ 3356 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work); 3357 struct b43_wldev *dev; 3358 struct sk_buff *skb; 3359 int err = 0; 3360 3361 mutex_lock(&wl->mutex); 3362 dev = wl->current_dev; 3363 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) { 3364 mutex_unlock(&wl->mutex); 3365 return; 3366 } 3367 3368 while (skb_queue_len(&wl->tx_queue)) { 3369 skb = skb_dequeue(&wl->tx_queue); 3370 3371 if (b43_using_pio_transfers(dev)) 3372 err = b43_pio_tx(dev, skb); 3373 else 3374 err = b43_dma_tx(dev, skb); 3375 if (unlikely(err)) 3376 dev_kfree_skb(skb); /* Drop it */ 3377 } 3378 3379#if B43_DEBUG 3380 dev->tx_count++; 3381#endif 3382 mutex_unlock(&wl->mutex); 3383} 3384 3385static void b43_op_tx(struct ieee80211_hw *hw, 3386 struct sk_buff *skb) 3387{ 3388 struct b43_wl *wl = hw_to_b43_wl(hw); 3389 3390 if (unlikely(skb->len < 2 + 2 + 6)) { 3391 /* Too short, this can't be a valid frame. */ 3392 dev_kfree_skb_any(skb); 3393 return; 3394 } 3395 B43_WARN_ON(skb_shinfo(skb)->nr_frags); 3396 3397 skb_queue_tail(&wl->tx_queue, skb); 3398 ieee80211_queue_work(wl->hw, &wl->tx_work); 3399} 3400 3401static void b43_qos_params_upload(struct b43_wldev *dev, 3402 const struct ieee80211_tx_queue_params *p, 3403 u16 shm_offset) 3404{ 3405 u16 params[B43_NR_QOSPARAMS]; 3406 int bslots, tmp; 3407 unsigned int i; 3408 3409 if (!dev->qos_enabled) 3410 return; 3411 3412 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min; 3413 3414 memset(¶ms, 0, sizeof(params)); 3415 3416 params[B43_QOSPARAM_TXOP] = p->txop * 32; 3417 params[B43_QOSPARAM_CWMIN] = p->cw_min; 3418 params[B43_QOSPARAM_CWMAX] = p->cw_max; 3419 params[B43_QOSPARAM_CWCUR] = p->cw_min; 3420 params[B43_QOSPARAM_AIFS] = p->aifs; 3421 params[B43_QOSPARAM_BSLOTS] = bslots; 3422 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs; 3423 3424 for (i = 0; i < ARRAY_SIZE(params); i++) { 3425 if (i == B43_QOSPARAM_STATUS) { 3426 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 3427 shm_offset + (i * 2)); 3428 /* Mark the parameters as updated. */ 3429 tmp |= 0x100; 3430 b43_shm_write16(dev, B43_SHM_SHARED, 3431 shm_offset + (i * 2), 3432 tmp); 3433 } else { 3434 b43_shm_write16(dev, B43_SHM_SHARED, 3435 shm_offset + (i * 2), 3436 params[i]); 3437 } 3438 } 3439} 3440 3441/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */ 3442static const u16 b43_qos_shm_offsets[] = { 3443 /* [mac80211-queue-nr] = SHM_OFFSET, */ 3444 [0] = B43_QOS_VOICE, 3445 [1] = B43_QOS_VIDEO, 3446 [2] = B43_QOS_BESTEFFORT, 3447 [3] = B43_QOS_BACKGROUND, 3448}; 3449 3450/* Update all QOS parameters in hardware. */ 3451static void b43_qos_upload_all(struct b43_wldev *dev) 3452{ 3453 struct b43_wl *wl = dev->wl; 3454 struct b43_qos_params *params; 3455 unsigned int i; 3456 3457 if (!dev->qos_enabled) 3458 return; 3459 3460 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3461 ARRAY_SIZE(wl->qos_params)); 3462 3463 b43_mac_suspend(dev); 3464 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3465 params = &(wl->qos_params[i]); 3466 b43_qos_params_upload(dev, &(params->p), 3467 b43_qos_shm_offsets[i]); 3468 } 3469 b43_mac_enable(dev); 3470} 3471 3472static void b43_qos_clear(struct b43_wl *wl) 3473{ 3474 struct b43_qos_params *params; 3475 unsigned int i; 3476 3477 /* Initialize QoS parameters to sane defaults. */ 3478 3479 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3480 ARRAY_SIZE(wl->qos_params)); 3481 3482 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3483 params = &(wl->qos_params[i]); 3484 3485 switch (b43_qos_shm_offsets[i]) { 3486 case B43_QOS_VOICE: 3487 params->p.txop = 0; 3488 params->p.aifs = 2; 3489 params->p.cw_min = 0x0001; 3490 params->p.cw_max = 0x0001; 3491 break; 3492 case B43_QOS_VIDEO: 3493 params->p.txop = 0; 3494 params->p.aifs = 2; 3495 params->p.cw_min = 0x0001; 3496 params->p.cw_max = 0x0001; 3497 break; 3498 case B43_QOS_BESTEFFORT: 3499 params->p.txop = 0; 3500 params->p.aifs = 3; 3501 params->p.cw_min = 0x0001; 3502 params->p.cw_max = 0x03FF; 3503 break; 3504 case B43_QOS_BACKGROUND: 3505 params->p.txop = 0; 3506 params->p.aifs = 7; 3507 params->p.cw_min = 0x0001; 3508 params->p.cw_max = 0x03FF; 3509 break; 3510 default: 3511 B43_WARN_ON(1); 3512 } 3513 } 3514} 3515 3516/* Initialize the core's QOS capabilities */ 3517static void b43_qos_init(struct b43_wldev *dev) 3518{ 3519 if (!dev->qos_enabled) { 3520 /* Disable QOS support. */ 3521 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF); 3522 b43_write16(dev, B43_MMIO_IFSCTL, 3523 b43_read16(dev, B43_MMIO_IFSCTL) 3524 & ~B43_MMIO_IFSCTL_USE_EDCF); 3525 b43dbg(dev->wl, "QoS disabled\n"); 3526 return; 3527 } 3528 3529 /* Upload the current QOS parameters. */ 3530 b43_qos_upload_all(dev); 3531 3532 /* Enable QOS support. */ 3533 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); 3534 b43_write16(dev, B43_MMIO_IFSCTL, 3535 b43_read16(dev, B43_MMIO_IFSCTL) 3536 | B43_MMIO_IFSCTL_USE_EDCF); 3537 b43dbg(dev->wl, "QoS enabled\n"); 3538} 3539 3540static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue, 3541 const struct ieee80211_tx_queue_params *params) 3542{ 3543 struct b43_wl *wl = hw_to_b43_wl(hw); 3544 struct b43_wldev *dev; 3545 unsigned int queue = (unsigned int)_queue; 3546 int err = -ENODEV; 3547 3548 if (queue >= ARRAY_SIZE(wl->qos_params)) { 3549 /* Queue not available or don't support setting 3550 * params on this queue. Return success to not 3551 * confuse mac80211. */ 3552 return 0; 3553 } 3554 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3555 ARRAY_SIZE(wl->qos_params)); 3556 3557 mutex_lock(&wl->mutex); 3558 dev = wl->current_dev; 3559 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) 3560 goto out_unlock; 3561 3562 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params)); 3563 b43_mac_suspend(dev); 3564 b43_qos_params_upload(dev, &(wl->qos_params[queue].p), 3565 b43_qos_shm_offsets[queue]); 3566 b43_mac_enable(dev); 3567 err = 0; 3568 3569out_unlock: 3570 mutex_unlock(&wl->mutex); 3571 3572 return err; 3573} 3574 3575static int b43_op_get_stats(struct ieee80211_hw *hw, 3576 struct ieee80211_low_level_stats *stats) 3577{ 3578 struct b43_wl *wl = hw_to_b43_wl(hw); 3579 3580 mutex_lock(&wl->mutex); 3581 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 3582 mutex_unlock(&wl->mutex); 3583 3584 return 0; 3585} 3586 3587static u64 b43_op_get_tsf(struct ieee80211_hw *hw) 3588{ 3589 struct b43_wl *wl = hw_to_b43_wl(hw); 3590 struct b43_wldev *dev; 3591 u64 tsf; 3592 3593 mutex_lock(&wl->mutex); 3594 dev = wl->current_dev; 3595 3596 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3597 b43_tsf_read(dev, &tsf); 3598 else 3599 tsf = 0; 3600 3601 mutex_unlock(&wl->mutex); 3602 3603 return tsf; 3604} 3605 3606static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3607{ 3608 struct b43_wl *wl = hw_to_b43_wl(hw); 3609 struct b43_wldev *dev; 3610 3611 mutex_lock(&wl->mutex); 3612 dev = wl->current_dev; 3613 3614 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3615 b43_tsf_write(dev, tsf); 3616 3617 mutex_unlock(&wl->mutex); 3618} 3619 3620static void b43_put_phy_into_reset(struct b43_wldev *dev) 3621{ 3622 u32 tmp; 3623 3624 switch (dev->dev->bus_type) { 3625#ifdef CONFIG_B43_BCMA 3626 case B43_BUS_BCMA: 3627 b43err(dev->wl, 3628 "Putting PHY into reset not supported on BCMA\n"); 3629 break; 3630#endif 3631#ifdef CONFIG_B43_SSB 3632 case B43_BUS_SSB: 3633 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 3634 tmp &= ~B43_TMSLOW_GMODE; 3635 tmp |= B43_TMSLOW_PHYRESET; 3636 tmp |= SSB_TMSLOW_FGC; 3637 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 3638 msleep(1); 3639 3640 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 3641 tmp &= ~SSB_TMSLOW_FGC; 3642 tmp |= B43_TMSLOW_PHYRESET; 3643 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 3644 msleep(1); 3645 3646 break; 3647#endif 3648 } 3649} 3650 3651static const char *band_to_string(enum ieee80211_band band) 3652{ 3653 switch (band) { 3654 case IEEE80211_BAND_5GHZ: 3655 return "5"; 3656 case IEEE80211_BAND_2GHZ: 3657 return "2.4"; 3658 default: 3659 break; 3660 } 3661 B43_WARN_ON(1); 3662 return ""; 3663} 3664 3665/* Expects wl->mutex locked */ 3666static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan) 3667{ 3668 struct b43_wldev *up_dev = NULL; 3669 struct b43_wldev *down_dev; 3670 struct b43_wldev *d; 3671 int err; 3672 bool uninitialized_var(gmode); 3673 int prev_status; 3674 3675 /* Find a device and PHY which supports the band. */ 3676 list_for_each_entry(d, &wl->devlist, list) { 3677 switch (chan->band) { 3678 case IEEE80211_BAND_5GHZ: 3679 if (d->phy.supports_5ghz) { 3680 up_dev = d; 3681 gmode = 0; 3682 } 3683 break; 3684 case IEEE80211_BAND_2GHZ: 3685 if (d->phy.supports_2ghz) { 3686 up_dev = d; 3687 gmode = 1; 3688 } 3689 break; 3690 default: 3691 B43_WARN_ON(1); 3692 return -EINVAL; 3693 } 3694 if (up_dev) 3695 break; 3696 } 3697 if (!up_dev) { 3698 b43err(wl, "Could not find a device for %s-GHz band operation\n", 3699 band_to_string(chan->band)); 3700 return -ENODEV; 3701 } 3702 if ((up_dev == wl->current_dev) && 3703 (!!wl->current_dev->phy.gmode == !!gmode)) { 3704 /* This device is already running. */ 3705 return 0; 3706 } 3707 b43dbg(wl, "Switching to %s-GHz band\n", 3708 band_to_string(chan->band)); 3709 down_dev = wl->current_dev; 3710 3711 prev_status = b43_status(down_dev); 3712 /* Shutdown the currently running core. */ 3713 if (prev_status >= B43_STAT_STARTED) 3714 down_dev = b43_wireless_core_stop(down_dev); 3715 if (prev_status >= B43_STAT_INITIALIZED) 3716 b43_wireless_core_exit(down_dev); 3717 3718 if (down_dev != up_dev) { 3719 /* We switch to a different core, so we put PHY into 3720 * RESET on the old core. */ 3721 b43_put_phy_into_reset(down_dev); 3722 } 3723 3724 /* Now start the new core. */ 3725 up_dev->phy.gmode = gmode; 3726 if (prev_status >= B43_STAT_INITIALIZED) { 3727 err = b43_wireless_core_init(up_dev); 3728 if (err) { 3729 b43err(wl, "Fatal: Could not initialize device for " 3730 "selected %s-GHz band\n", 3731 band_to_string(chan->band)); 3732 goto init_failure; 3733 } 3734 } 3735 if (prev_status >= B43_STAT_STARTED) { 3736 err = b43_wireless_core_start(up_dev); 3737 if (err) { 3738 b43err(wl, "Fatal: Coult not start device for " 3739 "selected %s-GHz band\n", 3740 band_to_string(chan->band)); 3741 b43_wireless_core_exit(up_dev); 3742 goto init_failure; 3743 } 3744 } 3745 B43_WARN_ON(b43_status(up_dev) != prev_status); 3746 3747 wl->current_dev = up_dev; 3748 3749 return 0; 3750init_failure: 3751 /* Whoops, failed to init the new core. No core is operating now. */ 3752 wl->current_dev = NULL; 3753 return err; 3754} 3755 3756/* Write the short and long frame retry limit values. */ 3757static void b43_set_retry_limits(struct b43_wldev *dev, 3758 unsigned int short_retry, 3759 unsigned int long_retry) 3760{ 3761 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3762 * the chip-internal counter. */ 3763 short_retry = min(short_retry, (unsigned int)0xF); 3764 long_retry = min(long_retry, (unsigned int)0xF); 3765 3766 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3767 short_retry); 3768 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3769 long_retry); 3770} 3771 3772static int b43_op_config(struct ieee80211_hw *hw, u32 changed) 3773{ 3774 struct b43_wl *wl = hw_to_b43_wl(hw); 3775 struct b43_wldev *dev; 3776 struct b43_phy *phy; 3777 struct ieee80211_conf *conf = &hw->conf; 3778 int antenna; 3779 int err = 0; 3780 3781 mutex_lock(&wl->mutex); 3782 3783 /* Switch the band (if necessary). This might change the active core. */ 3784 err = b43_switch_band(wl, conf->channel); 3785 if (err) 3786 goto out_unlock_mutex; 3787 dev = wl->current_dev; 3788 phy = &dev->phy; 3789 3790 if (conf_is_ht(conf)) 3791 phy->is_40mhz = 3792 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf)); 3793 else 3794 phy->is_40mhz = false; 3795 3796 b43_mac_suspend(dev); 3797 3798 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 3799 b43_set_retry_limits(dev, conf->short_frame_max_tx_count, 3800 conf->long_frame_max_tx_count); 3801 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; 3802 if (!changed) 3803 goto out_mac_enable; 3804 3805 /* Switch to the requested channel. 3806 * The firmware takes care of races with the TX handler. */ 3807 if (conf->channel->hw_value != phy->channel) 3808 b43_switch_channel(dev, conf->channel->hw_value); 3809 3810 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 3811 3812 /* Adjust the desired TX power level. */ 3813 if (conf->power_level != 0) { 3814 if (conf->power_level != phy->desired_txpower) { 3815 phy->desired_txpower = conf->power_level; 3816 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME | 3817 B43_TXPWR_IGNORE_TSSI); 3818 } 3819 } 3820 3821 /* Antennas for RX and management frame TX. */ 3822 antenna = B43_ANTENNA_DEFAULT; 3823 b43_mgmtframe_txantenna(dev, antenna); 3824 antenna = B43_ANTENNA_DEFAULT; 3825 if (phy->ops->set_rx_antenna) 3826 phy->ops->set_rx_antenna(dev, antenna); 3827 3828 if (wl->radio_enabled != phy->radio_on) { 3829 if (wl->radio_enabled) { 3830 b43_software_rfkill(dev, false); 3831 b43info(dev->wl, "Radio turned on by software\n"); 3832 if (!dev->radio_hw_enable) { 3833 b43info(dev->wl, "The hardware RF-kill button " 3834 "still turns the radio physically off. " 3835 "Press the button to turn it on.\n"); 3836 } 3837 } else { 3838 b43_software_rfkill(dev, true); 3839 b43info(dev->wl, "Radio turned off by software\n"); 3840 } 3841 } 3842 3843out_mac_enable: 3844 b43_mac_enable(dev); 3845out_unlock_mutex: 3846 mutex_unlock(&wl->mutex); 3847 3848 return err; 3849} 3850 3851static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates) 3852{ 3853 struct ieee80211_supported_band *sband = 3854 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)]; 3855 struct ieee80211_rate *rate; 3856 int i; 3857 u16 basic, direct, offset, basic_offset, rateptr; 3858 3859 for (i = 0; i < sband->n_bitrates; i++) { 3860 rate = &sband->bitrates[i]; 3861 3862 if (b43_is_cck_rate(rate->hw_value)) { 3863 direct = B43_SHM_SH_CCKDIRECT; 3864 basic = B43_SHM_SH_CCKBASIC; 3865 offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3866 offset &= 0xF; 3867 } else { 3868 direct = B43_SHM_SH_OFDMDIRECT; 3869 basic = B43_SHM_SH_OFDMBASIC; 3870 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3871 offset &= 0xF; 3872 } 3873 3874 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); 3875 3876 if (b43_is_cck_rate(rate->hw_value)) { 3877 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3878 basic_offset &= 0xF; 3879 } else { 3880 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3881 basic_offset &= 0xF; 3882 } 3883 3884 /* 3885 * Get the pointer that we need to point to 3886 * from the direct map 3887 */ 3888 rateptr = b43_shm_read16(dev, B43_SHM_SHARED, 3889 direct + 2 * basic_offset); 3890 /* and write it to the basic map */ 3891 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset, 3892 rateptr); 3893 } 3894} 3895 3896static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 3897 struct ieee80211_vif *vif, 3898 struct ieee80211_bss_conf *conf, 3899 u32 changed) 3900{ 3901 struct b43_wl *wl = hw_to_b43_wl(hw); 3902 struct b43_wldev *dev; 3903 3904 mutex_lock(&wl->mutex); 3905 3906 dev = wl->current_dev; 3907 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3908 goto out_unlock_mutex; 3909 3910 B43_WARN_ON(wl->vif != vif); 3911 3912 if (changed & BSS_CHANGED_BSSID) { 3913 if (conf->bssid) 3914 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3915 else 3916 memset(wl->bssid, 0, ETH_ALEN); 3917 } 3918 3919 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3920 if (changed & BSS_CHANGED_BEACON && 3921 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3922 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3923 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3924 b43_update_templates(wl); 3925 3926 if (changed & BSS_CHANGED_BSSID) 3927 b43_write_mac_bssid_templates(dev); 3928 } 3929 3930 b43_mac_suspend(dev); 3931 3932 /* Update templates for AP/mesh mode. */ 3933 if (changed & BSS_CHANGED_BEACON_INT && 3934 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3935 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3936 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3937 b43_set_beacon_int(dev, conf->beacon_int); 3938 3939 if (changed & BSS_CHANGED_BASIC_RATES) 3940 b43_update_basic_rates(dev, conf->basic_rates); 3941 3942 if (changed & BSS_CHANGED_ERP_SLOT) { 3943 if (conf->use_short_slot) 3944 b43_short_slot_timing_enable(dev); 3945 else 3946 b43_short_slot_timing_disable(dev); 3947 } 3948 3949 b43_mac_enable(dev); 3950out_unlock_mutex: 3951 mutex_unlock(&wl->mutex); 3952} 3953 3954static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3955 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3956 struct ieee80211_key_conf *key) 3957{ 3958 struct b43_wl *wl = hw_to_b43_wl(hw); 3959 struct b43_wldev *dev; 3960 u8 algorithm; 3961 u8 index; 3962 int err; 3963 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3964 3965 if (modparam_nohwcrypt) 3966 return -ENOSPC; /* User disabled HW-crypto */ 3967 3968 mutex_lock(&wl->mutex); 3969 3970 dev = wl->current_dev; 3971 err = -ENODEV; 3972 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 3973 goto out_unlock; 3974 3975 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) { 3976 /* We don't have firmware for the crypto engine. 3977 * Must use software-crypto. */ 3978 err = -EOPNOTSUPP; 3979 goto out_unlock; 3980 } 3981 3982 err = -EINVAL; 3983 switch (key->cipher) { 3984 case WLAN_CIPHER_SUITE_WEP40: 3985 algorithm = B43_SEC_ALGO_WEP40; 3986 break; 3987 case WLAN_CIPHER_SUITE_WEP104: 3988 algorithm = B43_SEC_ALGO_WEP104; 3989 break; 3990 case WLAN_CIPHER_SUITE_TKIP: 3991 algorithm = B43_SEC_ALGO_TKIP; 3992 break; 3993 case WLAN_CIPHER_SUITE_CCMP: 3994 algorithm = B43_SEC_ALGO_AES; 3995 break; 3996 default: 3997 B43_WARN_ON(1); 3998 goto out_unlock; 3999 } 4000 index = (u8) (key->keyidx); 4001 if (index > 3) 4002 goto out_unlock; 4003 4004 switch (cmd) { 4005 case SET_KEY: 4006 if (algorithm == B43_SEC_ALGO_TKIP && 4007 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) || 4008 !modparam_hwtkip)) { 4009 /* We support only pairwise key */ 4010 err = -EOPNOTSUPP; 4011 goto out_unlock; 4012 } 4013 4014 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 4015 if (WARN_ON(!sta)) { 4016 err = -EOPNOTSUPP; 4017 goto out_unlock; 4018 } 4019 /* Pairwise key with an assigned MAC address. */ 4020 err = b43_key_write(dev, -1, algorithm, 4021 key->key, key->keylen, 4022 sta->addr, key); 4023 } else { 4024 /* Group key */ 4025 err = b43_key_write(dev, index, algorithm, 4026 key->key, key->keylen, NULL, key); 4027 } 4028 if (err) 4029 goto out_unlock; 4030 4031 if (algorithm == B43_SEC_ALGO_WEP40 || 4032 algorithm == B43_SEC_ALGO_WEP104) { 4033 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 4034 } else { 4035 b43_hf_write(dev, 4036 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 4037 } 4038 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 4039 if (algorithm == B43_SEC_ALGO_TKIP) 4040 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 4041 break; 4042 case DISABLE_KEY: { 4043 err = b43_key_clear(dev, key->hw_key_idx); 4044 if (err) 4045 goto out_unlock; 4046 break; 4047 } 4048 default: 4049 B43_WARN_ON(1); 4050 } 4051 4052out_unlock: 4053 if (!err) { 4054 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 4055 "mac: %pM\n", 4056 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 4057 sta ? sta->addr : bcast_addr); 4058 b43_dump_keymemory(dev); 4059 } 4060 mutex_unlock(&wl->mutex); 4061 4062 return err; 4063} 4064 4065static void b43_op_configure_filter(struct ieee80211_hw *hw, 4066 unsigned int changed, unsigned int *fflags, 4067 u64 multicast) 4068{ 4069 struct b43_wl *wl = hw_to_b43_wl(hw); 4070 struct b43_wldev *dev; 4071 4072 mutex_lock(&wl->mutex); 4073 dev = wl->current_dev; 4074 if (!dev) { 4075 *fflags = 0; 4076 goto out_unlock; 4077 } 4078 4079 *fflags &= FIF_PROMISC_IN_BSS | 4080 FIF_ALLMULTI | 4081 FIF_FCSFAIL | 4082 FIF_PLCPFAIL | 4083 FIF_CONTROL | 4084 FIF_OTHER_BSS | 4085 FIF_BCN_PRBRESP_PROMISC; 4086 4087 changed &= FIF_PROMISC_IN_BSS | 4088 FIF_ALLMULTI | 4089 FIF_FCSFAIL | 4090 FIF_PLCPFAIL | 4091 FIF_CONTROL | 4092 FIF_OTHER_BSS | 4093 FIF_BCN_PRBRESP_PROMISC; 4094 4095 wl->filter_flags = *fflags; 4096 4097 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 4098 b43_adjust_opmode(dev); 4099 4100out_unlock: 4101 mutex_unlock(&wl->mutex); 4102} 4103 4104/* Locking: wl->mutex 4105 * Returns the current dev. This might be different from the passed in dev, 4106 * because the core might be gone away while we unlocked the mutex. */ 4107static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev) 4108{ 4109 struct b43_wl *wl = dev->wl; 4110 struct b43_wldev *orig_dev; 4111 u32 mask; 4112 4113redo: 4114 if (!dev || b43_status(dev) < B43_STAT_STARTED) 4115 return dev; 4116 4117 /* Cancel work. Unlock to avoid deadlocks. */ 4118 mutex_unlock(&wl->mutex); 4119 cancel_delayed_work_sync(&dev->periodic_work); 4120 cancel_work_sync(&wl->tx_work); 4121 mutex_lock(&wl->mutex); 4122 dev = wl->current_dev; 4123 if (!dev || b43_status(dev) < B43_STAT_STARTED) { 4124 /* Whoops, aliens ate up the device while we were unlocked. */ 4125 return dev; 4126 } 4127 4128 /* Disable interrupts on the device. */ 4129 b43_set_status(dev, B43_STAT_INITIALIZED); 4130 if (b43_bus_host_is_sdio(dev->dev)) { 4131 /* wl->mutex is locked. That is enough. */ 4132 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4133 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4134 } else { 4135 spin_lock_irq(&wl->hardirq_lock); 4136 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4137 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4138 spin_unlock_irq(&wl->hardirq_lock); 4139 } 4140 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ 4141 orig_dev = dev; 4142 mutex_unlock(&wl->mutex); 4143 if (b43_bus_host_is_sdio(dev->dev)) { 4144 b43_sdio_free_irq(dev); 4145 } else { 4146 synchronize_irq(dev->dev->irq); 4147 free_irq(dev->dev->irq, dev); 4148 } 4149 mutex_lock(&wl->mutex); 4150 dev = wl->current_dev; 4151 if (!dev) 4152 return dev; 4153 if (dev != orig_dev) { 4154 if (b43_status(dev) >= B43_STAT_STARTED) 4155 goto redo; 4156 return dev; 4157 } 4158 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 4159 B43_WARN_ON(mask != 0xFFFFFFFF && mask); 4160 4161 /* Drain the TX queue */ 4162 while (skb_queue_len(&wl->tx_queue)) 4163 dev_kfree_skb(skb_dequeue(&wl->tx_queue)); 4164 4165 b43_mac_suspend(dev); 4166 b43_leds_exit(dev); 4167 b43dbg(wl, "Wireless interface stopped\n"); 4168 4169 return dev; 4170} 4171 4172/* Locking: wl->mutex */ 4173static int b43_wireless_core_start(struct b43_wldev *dev) 4174{ 4175 int err; 4176 4177 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 4178 4179 drain_txstatus_queue(dev); 4180 if (b43_bus_host_is_sdio(dev->dev)) { 4181 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); 4182 if (err) { 4183 b43err(dev->wl, "Cannot request SDIO IRQ\n"); 4184 goto out; 4185 } 4186 } else { 4187 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler, 4188 b43_interrupt_thread_handler, 4189 IRQF_SHARED, KBUILD_MODNAME, dev); 4190 if (err) { 4191 b43err(dev->wl, "Cannot request IRQ-%d\n", 4192 dev->dev->irq); 4193 goto out; 4194 } 4195 } 4196 4197 /* We are ready to run. */ 4198 ieee80211_wake_queues(dev->wl->hw); 4199 b43_set_status(dev, B43_STAT_STARTED); 4200 4201 /* Start data flow (TX/RX). */ 4202 b43_mac_enable(dev); 4203 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 4204 4205 /* Start maintenance work */ 4206 b43_periodic_tasks_setup(dev); 4207 4208 b43_leds_init(dev); 4209 4210 b43dbg(dev->wl, "Wireless interface started\n"); 4211out: 4212 return err; 4213} 4214 4215/* Get PHY and RADIO versioning numbers */ 4216static int b43_phy_versioning(struct b43_wldev *dev) 4217{ 4218 struct b43_phy *phy = &dev->phy; 4219 u32 tmp; 4220 u8 analog_type; 4221 u8 phy_type; 4222 u8 phy_rev; 4223 u16 radio_manuf; 4224 u16 radio_ver; 4225 u16 radio_rev; 4226 int unsupported = 0; 4227 4228 /* Get PHY versioning */ 4229 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 4230 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 4231 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 4232 phy_rev = (tmp & B43_PHYVER_VERSION); 4233 switch (phy_type) { 4234 case B43_PHYTYPE_A: 4235 if (phy_rev >= 4) 4236 unsupported = 1; 4237 break; 4238 case B43_PHYTYPE_B: 4239 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 4240 && phy_rev != 7) 4241 unsupported = 1; 4242 break; 4243 case B43_PHYTYPE_G: 4244 if (phy_rev > 9) 4245 unsupported = 1; 4246 break; 4247#ifdef CONFIG_B43_PHY_N 4248 case B43_PHYTYPE_N: 4249 if (phy_rev > 9) 4250 unsupported = 1; 4251 break; 4252#endif 4253#ifdef CONFIG_B43_PHY_LP 4254 case B43_PHYTYPE_LP: 4255 if (phy_rev > 2) 4256 unsupported = 1; 4257 break; 4258#endif 4259#ifdef CONFIG_B43_PHY_HT 4260 case B43_PHYTYPE_HT: 4261 if (phy_rev > 1) 4262 unsupported = 1; 4263 break; 4264#endif 4265#ifdef CONFIG_B43_PHY_LCN 4266 case B43_PHYTYPE_LCN: 4267 if (phy_rev > 1) 4268 unsupported = 1; 4269 break; 4270#endif 4271 default: 4272 unsupported = 1; 4273 } 4274 if (unsupported) { 4275 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 4276 "(Analog %u, Type %u, Revision %u)\n", 4277 analog_type, phy_type, phy_rev); 4278 return -EOPNOTSUPP; 4279 } 4280 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 4281 analog_type, phy_type, phy_rev); 4282 4283 /* Get RADIO versioning */ 4284 if (dev->dev->core_rev >= 24) { 4285 u16 radio24[3]; 4286 4287 for (tmp = 0; tmp < 3; tmp++) { 4288 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp); 4289 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4290 } 4291 4292 /* Broadcom uses "id" for our "ver" and has separated "ver" */ 4293 /* radio_ver = (radio24[0] & 0xF0) >> 4; */ 4294 4295 radio_manuf = 0x17F; 4296 radio_ver = (radio24[2] << 8) | radio24[1]; 4297 radio_rev = (radio24[0] & 0xF); 4298 } else { 4299 if (dev->dev->chip_id == 0x4317) { 4300 if (dev->dev->chip_rev == 0) 4301 tmp = 0x3205017F; 4302 else if (dev->dev->chip_rev == 1) 4303 tmp = 0x4205017F; 4304 else 4305 tmp = 0x5205017F; 4306 } else { 4307 b43_write16(dev, B43_MMIO_RADIO_CONTROL, 4308 B43_RADIOCTL_ID); 4309 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 4310 b43_write16(dev, B43_MMIO_RADIO_CONTROL, 4311 B43_RADIOCTL_ID); 4312 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) 4313 << 16; 4314 } 4315 radio_manuf = (tmp & 0x00000FFF); 4316 radio_ver = (tmp & 0x0FFFF000) >> 12; 4317 radio_rev = (tmp & 0xF0000000) >> 28; 4318 } 4319 4320 if (radio_manuf != 0x17F /* Broadcom */) 4321 unsupported = 1; 4322 switch (phy_type) { 4323 case B43_PHYTYPE_A: 4324 if (radio_ver != 0x2060) 4325 unsupported = 1; 4326 if (radio_rev != 1) 4327 unsupported = 1; 4328 if (radio_manuf != 0x17F) 4329 unsupported = 1; 4330 break; 4331 case B43_PHYTYPE_B: 4332 if ((radio_ver & 0xFFF0) != 0x2050) 4333 unsupported = 1; 4334 break; 4335 case B43_PHYTYPE_G: 4336 if (radio_ver != 0x2050) 4337 unsupported = 1; 4338 break; 4339 case B43_PHYTYPE_N: 4340 if (radio_ver != 0x2055 && radio_ver != 0x2056) 4341 unsupported = 1; 4342 break; 4343 case B43_PHYTYPE_LP: 4344 if (radio_ver != 0x2062 && radio_ver != 0x2063) 4345 unsupported = 1; 4346 break; 4347 case B43_PHYTYPE_HT: 4348 if (radio_ver != 0x2059) 4349 unsupported = 1; 4350 break; 4351 case B43_PHYTYPE_LCN: 4352 if (radio_ver != 0x2064) 4353 unsupported = 1; 4354 break; 4355 default: 4356 B43_WARN_ON(1); 4357 } 4358 if (unsupported) { 4359 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 4360 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 4361 radio_manuf, radio_ver, radio_rev); 4362 return -EOPNOTSUPP; 4363 } 4364 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 4365 radio_manuf, radio_ver, radio_rev); 4366 4367 phy->radio_manuf = radio_manuf; 4368 phy->radio_ver = radio_ver; 4369 phy->radio_rev = radio_rev; 4370 4371 phy->analog = analog_type; 4372 phy->type = phy_type; 4373 phy->rev = phy_rev; 4374 4375 return 0; 4376} 4377 4378static void setup_struct_phy_for_init(struct b43_wldev *dev, 4379 struct b43_phy *phy) 4380{ 4381 phy->hardware_power_control = !!modparam_hwpctl; 4382 phy->next_txpwr_check_time = jiffies; 4383 /* PHY TX errors counter. */ 4384 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 4385 4386#if B43_DEBUG 4387 phy->phy_locked = 0; 4388 phy->radio_locked = 0; 4389#endif 4390} 4391 4392static void setup_struct_wldev_for_init(struct b43_wldev *dev) 4393{ 4394 dev->dfq_valid = 0; 4395 4396 /* Assume the radio is enabled. If it's not enabled, the state will 4397 * immediately get fixed on the first periodic work run. */ 4398 dev->radio_hw_enable = 1; 4399 4400 /* Stats */ 4401 memset(&dev->stats, 0, sizeof(dev->stats)); 4402 4403 setup_struct_phy_for_init(dev, &dev->phy); 4404 4405 /* IRQ related flags */ 4406 dev->irq_reason = 0; 4407 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 4408 dev->irq_mask = B43_IRQ_MASKTEMPLATE; 4409 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 4410 dev->irq_mask &= ~B43_IRQ_PHY_TXERR; 4411 4412 dev->mac_suspended = 1; 4413 4414 /* Noise calculation context */ 4415 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 4416} 4417 4418static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 4419{ 4420 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4421 u64 hf; 4422 4423 if (!modparam_btcoex) 4424 return; 4425 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 4426 return; 4427 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 4428 return; 4429 4430 hf = b43_hf_read(dev); 4431 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 4432 hf |= B43_HF_BTCOEXALT; 4433 else 4434 hf |= B43_HF_BTCOEX; 4435 b43_hf_write(dev, hf); 4436} 4437 4438static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 4439{ 4440 if (!modparam_btcoex) 4441 return; 4442 //TODO 4443} 4444 4445static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 4446{ 4447 struct ssb_bus *bus; 4448 u32 tmp; 4449 4450 if (dev->dev->bus_type != B43_BUS_SSB) 4451 return; 4452 4453 bus = dev->dev->sdev->bus; 4454 4455 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || 4456 (bus->chip_id == 0x4312)) { 4457 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO); 4458 tmp &= ~SSB_IMCFGLO_REQTO; 4459 tmp &= ~SSB_IMCFGLO_SERTO; 4460 tmp |= 0x3; 4461 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp); 4462 ssb_commit_settings(bus); 4463 } 4464} 4465 4466static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) 4467{ 4468 u16 pu_delay; 4469 4470 /* The time value is in microseconds. */ 4471 if (dev->phy.type == B43_PHYTYPE_A) 4472 pu_delay = 3700; 4473 else 4474 pu_delay = 1050; 4475 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) 4476 pu_delay = 500; 4477 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) 4478 pu_delay = max(pu_delay, (u16)2400); 4479 4480 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); 4481} 4482 4483/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ 4484static void b43_set_pretbtt(struct b43_wldev *dev) 4485{ 4486 u16 pretbtt; 4487 4488 /* The time value is in microseconds. */ 4489 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) { 4490 pretbtt = 2; 4491 } else { 4492 if (dev->phy.type == B43_PHYTYPE_A) 4493 pretbtt = 120; 4494 else 4495 pretbtt = 250; 4496 } 4497 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); 4498 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); 4499} 4500 4501/* Shutdown a wireless core */ 4502/* Locking: wl->mutex */ 4503static void b43_wireless_core_exit(struct b43_wldev *dev) 4504{ 4505 u32 macctl; 4506 4507 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED); 4508 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED) 4509 return; 4510 4511 /* Unregister HW RNG driver */ 4512 b43_rng_exit(dev->wl); 4513 4514 b43_set_status(dev, B43_STAT_UNINIT); 4515 4516 /* Stop the microcode PSM. */ 4517 macctl = b43_read32(dev, B43_MMIO_MACCTL); 4518 macctl &= ~B43_MACCTL_PSM_RUN; 4519 macctl |= B43_MACCTL_PSM_JMP0; 4520 b43_write32(dev, B43_MMIO_MACCTL, macctl); 4521 4522 b43_dma_free(dev); 4523 b43_pio_free(dev); 4524 b43_chip_exit(dev); 4525 dev->phy.ops->switch_analog(dev, 0); 4526 if (dev->wl->current_beacon) { 4527 dev_kfree_skb_any(dev->wl->current_beacon); 4528 dev->wl->current_beacon = NULL; 4529 } 4530 4531 b43_device_disable(dev, 0); 4532 b43_bus_may_powerdown(dev); 4533} 4534 4535/* Initialize a wireless core */ 4536static int b43_wireless_core_init(struct b43_wldev *dev) 4537{ 4538 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4539 struct b43_phy *phy = &dev->phy; 4540 int err; 4541 u64 hf; 4542 4543 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4544 4545 err = b43_bus_powerup(dev, 0); 4546 if (err) 4547 goto out; 4548 if (!b43_device_is_enabled(dev)) 4549 b43_wireless_core_reset(dev, phy->gmode); 4550 4551 /* Reset all data structures. */ 4552 setup_struct_wldev_for_init(dev); 4553 phy->ops->prepare_structs(dev); 4554 4555 /* Enable IRQ routing to this device. */ 4556 switch (dev->dev->bus_type) { 4557#ifdef CONFIG_B43_BCMA 4558 case B43_BUS_BCMA: 4559 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci, 4560 dev->dev->bdev, true); 4561 break; 4562#endif 4563#ifdef CONFIG_B43_SSB 4564 case B43_BUS_SSB: 4565 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore, 4566 dev->dev->sdev); 4567 break; 4568#endif 4569 } 4570 4571 b43_imcfglo_timeouts_workaround(dev); 4572 b43_bluetooth_coext_disable(dev); 4573 if (phy->ops->prepare_hardware) { 4574 err = phy->ops->prepare_hardware(dev); 4575 if (err) 4576 goto err_busdown; 4577 } 4578 err = b43_chip_init(dev); 4579 if (err) 4580 goto err_busdown; 4581 b43_shm_write16(dev, B43_SHM_SHARED, 4582 B43_SHM_SH_WLCOREREV, dev->dev->core_rev); 4583 hf = b43_hf_read(dev); 4584 if (phy->type == B43_PHYTYPE_G) { 4585 hf |= B43_HF_SYMW; 4586 if (phy->rev == 1) 4587 hf |= B43_HF_GDCW; 4588 if (sprom->boardflags_lo & B43_BFL_PACTRL) 4589 hf |= B43_HF_OFDMPABOOST; 4590 } 4591 if (phy->radio_ver == 0x2050) { 4592 if (phy->radio_rev == 6) 4593 hf |= B43_HF_4318TSSI; 4594 if (phy->radio_rev < 6) 4595 hf |= B43_HF_VCORECALC; 4596 } 4597 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) 4598 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ 4599#ifdef CONFIG_SSB_DRIVER_PCICORE 4600 if (dev->dev->bus_type == B43_BUS_SSB && 4601 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI && 4602 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10) 4603 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ 4604#endif 4605 hf &= ~B43_HF_SKCFPUP; 4606 b43_hf_write(dev, hf); 4607 4608 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 4609 B43_DEFAULT_LONG_RETRY_LIMIT); 4610 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 4611 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 4612 4613 /* Disable sending probe responses from firmware. 4614 * Setting the MaxTime to one usec will always trigger 4615 * a timeout, so we never send any probe resp. 4616 * A timeout of zero is infinite. */ 4617 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 4618 4619 b43_rate_memory_init(dev); 4620 b43_set_phytxctl_defaults(dev); 4621 4622 /* Minimum Contention Window */ 4623 if (phy->type == B43_PHYTYPE_B) 4624 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 4625 else 4626 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 4627 /* Maximum Contention Window */ 4628 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 4629 4630 if (b43_bus_host_is_pcmcia(dev->dev) || 4631 b43_bus_host_is_sdio(dev->dev) || 4632 dev->use_pio) { 4633 dev->__using_pio_transfers = 1; 4634 err = b43_pio_init(dev); 4635 } else { 4636 dev->__using_pio_transfers = 0; 4637 err = b43_dma_init(dev); 4638 } 4639 if (err) 4640 goto err_chip_exit; 4641 b43_qos_init(dev); 4642 b43_set_synth_pu_delay(dev, 1); 4643 b43_bluetooth_coext_enable(dev); 4644 4645 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); 4646 b43_upload_card_macaddress(dev); 4647 b43_security_init(dev); 4648 4649 ieee80211_wake_queues(dev->wl->hw); 4650 4651 b43_set_status(dev, B43_STAT_INITIALIZED); 4652 4653 /* Register HW RNG driver */ 4654 b43_rng_init(dev->wl); 4655 4656out: 4657 return err; 4658 4659err_chip_exit: 4660 b43_chip_exit(dev); 4661err_busdown: 4662 b43_bus_may_powerdown(dev); 4663 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4664 return err; 4665} 4666 4667static int b43_op_add_interface(struct ieee80211_hw *hw, 4668 struct ieee80211_vif *vif) 4669{ 4670 struct b43_wl *wl = hw_to_b43_wl(hw); 4671 struct b43_wldev *dev; 4672 int err = -EOPNOTSUPP; 4673 4674 /* TODO: allow WDS/AP devices to coexist */ 4675 4676 if (vif->type != NL80211_IFTYPE_AP && 4677 vif->type != NL80211_IFTYPE_MESH_POINT && 4678 vif->type != NL80211_IFTYPE_STATION && 4679 vif->type != NL80211_IFTYPE_WDS && 4680 vif->type != NL80211_IFTYPE_ADHOC) 4681 return -EOPNOTSUPP; 4682 4683 mutex_lock(&wl->mutex); 4684 if (wl->operating) 4685 goto out_mutex_unlock; 4686 4687 b43dbg(wl, "Adding Interface type %d\n", vif->type); 4688 4689 dev = wl->current_dev; 4690 wl->operating = 1; 4691 wl->vif = vif; 4692 wl->if_type = vif->type; 4693 memcpy(wl->mac_addr, vif->addr, ETH_ALEN); 4694 4695 b43_adjust_opmode(dev); 4696 b43_set_pretbtt(dev); 4697 b43_set_synth_pu_delay(dev, 0); 4698 b43_upload_card_macaddress(dev); 4699 4700 err = 0; 4701 out_mutex_unlock: 4702 mutex_unlock(&wl->mutex); 4703 4704 return err; 4705} 4706 4707static void b43_op_remove_interface(struct ieee80211_hw *hw, 4708 struct ieee80211_vif *vif) 4709{ 4710 struct b43_wl *wl = hw_to_b43_wl(hw); 4711 struct b43_wldev *dev = wl->current_dev; 4712 4713 b43dbg(wl, "Removing Interface type %d\n", vif->type); 4714 4715 mutex_lock(&wl->mutex); 4716 4717 B43_WARN_ON(!wl->operating); 4718 B43_WARN_ON(wl->vif != vif); 4719 wl->vif = NULL; 4720 4721 wl->operating = 0; 4722 4723 b43_adjust_opmode(dev); 4724 memset(wl->mac_addr, 0, ETH_ALEN); 4725 b43_upload_card_macaddress(dev); 4726 4727 mutex_unlock(&wl->mutex); 4728} 4729 4730static int b43_op_start(struct ieee80211_hw *hw) 4731{ 4732 struct b43_wl *wl = hw_to_b43_wl(hw); 4733 struct b43_wldev *dev = wl->current_dev; 4734 int did_init = 0; 4735 int err = 0; 4736 4737 /* Kill all old instance specific information to make sure 4738 * the card won't use it in the short timeframe between start 4739 * and mac80211 reconfiguring it. */ 4740 memset(wl->bssid, 0, ETH_ALEN); 4741 memset(wl->mac_addr, 0, ETH_ALEN); 4742 wl->filter_flags = 0; 4743 wl->radiotap_enabled = 0; 4744 b43_qos_clear(wl); 4745 wl->beacon0_uploaded = 0; 4746 wl->beacon1_uploaded = 0; 4747 wl->beacon_templates_virgin = 1; 4748 wl->radio_enabled = 1; 4749 4750 mutex_lock(&wl->mutex); 4751 4752 if (b43_status(dev) < B43_STAT_INITIALIZED) { 4753 err = b43_wireless_core_init(dev); 4754 if (err) 4755 goto out_mutex_unlock; 4756 did_init = 1; 4757 } 4758 4759 if (b43_status(dev) < B43_STAT_STARTED) { 4760 err = b43_wireless_core_start(dev); 4761 if (err) { 4762 if (did_init) 4763 b43_wireless_core_exit(dev); 4764 goto out_mutex_unlock; 4765 } 4766 } 4767 4768 /* XXX: only do if device doesn't support rfkill irq */ 4769 wiphy_rfkill_start_polling(hw->wiphy); 4770 4771 out_mutex_unlock: 4772 mutex_unlock(&wl->mutex); 4773 4774 return err; 4775} 4776 4777static void b43_op_stop(struct ieee80211_hw *hw) 4778{ 4779 struct b43_wl *wl = hw_to_b43_wl(hw); 4780 struct b43_wldev *dev = wl->current_dev; 4781 4782 cancel_work_sync(&(wl->beacon_update_trigger)); 4783 4784 mutex_lock(&wl->mutex); 4785 if (b43_status(dev) >= B43_STAT_STARTED) { 4786 dev = b43_wireless_core_stop(dev); 4787 if (!dev) 4788 goto out_unlock; 4789 } 4790 b43_wireless_core_exit(dev); 4791 wl->radio_enabled = 0; 4792 4793out_unlock: 4794 mutex_unlock(&wl->mutex); 4795 4796 cancel_work_sync(&(wl->txpower_adjust_work)); 4797} 4798 4799static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, 4800 struct ieee80211_sta *sta, bool set) 4801{ 4802 struct b43_wl *wl = hw_to_b43_wl(hw); 4803 4804 /* FIXME: add locking */ 4805 b43_update_templates(wl); 4806 4807 return 0; 4808} 4809 4810static void b43_op_sta_notify(struct ieee80211_hw *hw, 4811 struct ieee80211_vif *vif, 4812 enum sta_notify_cmd notify_cmd, 4813 struct ieee80211_sta *sta) 4814{ 4815 struct b43_wl *wl = hw_to_b43_wl(hw); 4816 4817 B43_WARN_ON(!vif || wl->vif != vif); 4818} 4819 4820static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw) 4821{ 4822 struct b43_wl *wl = hw_to_b43_wl(hw); 4823 struct b43_wldev *dev; 4824 4825 mutex_lock(&wl->mutex); 4826 dev = wl->current_dev; 4827 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4828 /* Disable CFP update during scan on other channels. */ 4829 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP); 4830 } 4831 mutex_unlock(&wl->mutex); 4832} 4833 4834static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw) 4835{ 4836 struct b43_wl *wl = hw_to_b43_wl(hw); 4837 struct b43_wldev *dev; 4838 4839 mutex_lock(&wl->mutex); 4840 dev = wl->current_dev; 4841 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4842 /* Re-enable CFP update. */ 4843 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP); 4844 } 4845 mutex_unlock(&wl->mutex); 4846} 4847 4848static int b43_op_get_survey(struct ieee80211_hw *hw, int idx, 4849 struct survey_info *survey) 4850{ 4851 struct b43_wl *wl = hw_to_b43_wl(hw); 4852 struct b43_wldev *dev = wl->current_dev; 4853 struct ieee80211_conf *conf = &hw->conf; 4854 4855 if (idx != 0) 4856 return -ENOENT; 4857 4858 survey->channel = conf->channel; 4859 survey->filled = SURVEY_INFO_NOISE_DBM; 4860 survey->noise = dev->stats.link_noise; 4861 4862 return 0; 4863} 4864 4865static const struct ieee80211_ops b43_hw_ops = { 4866 .tx = b43_op_tx, 4867 .conf_tx = b43_op_conf_tx, 4868 .add_interface = b43_op_add_interface, 4869 .remove_interface = b43_op_remove_interface, 4870 .config = b43_op_config, 4871 .bss_info_changed = b43_op_bss_info_changed, 4872 .configure_filter = b43_op_configure_filter, 4873 .set_key = b43_op_set_key, 4874 .update_tkip_key = b43_op_update_tkip_key, 4875 .get_stats = b43_op_get_stats, 4876 .get_tsf = b43_op_get_tsf, 4877 .set_tsf = b43_op_set_tsf, 4878 .start = b43_op_start, 4879 .stop = b43_op_stop, 4880 .set_tim = b43_op_beacon_set_tim, 4881 .sta_notify = b43_op_sta_notify, 4882 .sw_scan_start = b43_op_sw_scan_start_notifier, 4883 .sw_scan_complete = b43_op_sw_scan_complete_notifier, 4884 .get_survey = b43_op_get_survey, 4885 .rfkill_poll = b43_rfkill_poll, 4886}; 4887 4888/* Hard-reset the chip. Do not call this directly. 4889 * Use b43_controller_restart() 4890 */ 4891static void b43_chip_reset(struct work_struct *work) 4892{ 4893 struct b43_wldev *dev = 4894 container_of(work, struct b43_wldev, restart_work); 4895 struct b43_wl *wl = dev->wl; 4896 int err = 0; 4897 int prev_status; 4898 4899 mutex_lock(&wl->mutex); 4900 4901 prev_status = b43_status(dev); 4902 /* Bring the device down... */ 4903 if (prev_status >= B43_STAT_STARTED) { 4904 dev = b43_wireless_core_stop(dev); 4905 if (!dev) { 4906 err = -ENODEV; 4907 goto out; 4908 } 4909 } 4910 if (prev_status >= B43_STAT_INITIALIZED) 4911 b43_wireless_core_exit(dev); 4912 4913 /* ...and up again. */ 4914 if (prev_status >= B43_STAT_INITIALIZED) { 4915 err = b43_wireless_core_init(dev); 4916 if (err) 4917 goto out; 4918 } 4919 if (prev_status >= B43_STAT_STARTED) { 4920 err = b43_wireless_core_start(dev); 4921 if (err) { 4922 b43_wireless_core_exit(dev); 4923 goto out; 4924 } 4925 } 4926out: 4927 if (err) 4928 wl->current_dev = NULL; /* Failed to init the dev. */ 4929 mutex_unlock(&wl->mutex); 4930 if (err) 4931 b43err(wl, "Controller restart FAILED\n"); 4932 else 4933 b43info(wl, "Controller restarted\n"); 4934} 4935 4936static int b43_setup_bands(struct b43_wldev *dev, 4937 bool have_2ghz_phy, bool have_5ghz_phy) 4938{ 4939 struct ieee80211_hw *hw = dev->wl->hw; 4940 4941 if (have_2ghz_phy) 4942 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz; 4943 if (dev->phy.type == B43_PHYTYPE_N) { 4944 if (have_5ghz_phy) 4945 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy; 4946 } else { 4947 if (have_5ghz_phy) 4948 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy; 4949 } 4950 4951 dev->phy.supports_2ghz = have_2ghz_phy; 4952 dev->phy.supports_5ghz = have_5ghz_phy; 4953 4954 return 0; 4955} 4956 4957static void b43_wireless_core_detach(struct b43_wldev *dev) 4958{ 4959 /* We release firmware that late to not be required to re-request 4960 * is all the time when we reinit the core. */ 4961 b43_release_firmware(dev); 4962 b43_phy_free(dev); 4963} 4964 4965static int b43_wireless_core_attach(struct b43_wldev *dev) 4966{ 4967 struct b43_wl *wl = dev->wl; 4968 struct pci_dev *pdev = NULL; 4969 int err; 4970 u32 tmp; 4971 bool have_2ghz_phy = 0, have_5ghz_phy = 0; 4972 4973 /* Do NOT do any device initialization here. 4974 * Do it in wireless_core_init() instead. 4975 * This function is for gathering basic information about the HW, only. 4976 * Also some structs may be set up here. But most likely you want to have 4977 * that in core_init(), too. 4978 */ 4979 4980#ifdef CONFIG_B43_SSB 4981 if (dev->dev->bus_type == B43_BUS_SSB && 4982 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) 4983 pdev = dev->dev->sdev->bus->host_pci; 4984#endif 4985 4986 err = b43_bus_powerup(dev, 0); 4987 if (err) { 4988 b43err(wl, "Bus powerup failed\n"); 4989 goto out; 4990 } 4991 4992 /* Get the PHY type. */ 4993 switch (dev->dev->bus_type) { 4994#ifdef CONFIG_B43_BCMA 4995 case B43_BUS_BCMA: 4996 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST); 4997 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY); 4998 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY); 4999 break; 5000#endif 5001#ifdef CONFIG_B43_SSB 5002 case B43_BUS_SSB: 5003 if (dev->dev->core_rev >= 5) { 5004 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 5005 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY); 5006 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY); 5007 } else 5008 B43_WARN_ON(1); 5009 break; 5010#endif 5011 } 5012 5013 dev->phy.gmode = have_2ghz_phy; 5014 dev->phy.radio_on = 1; 5015 b43_wireless_core_reset(dev, dev->phy.gmode); 5016 5017 err = b43_phy_versioning(dev); 5018 if (err) 5019 goto err_powerdown; 5020 /* Check if this device supports multiband. */ 5021 if (!pdev || 5022 (pdev->device != 0x4312 && 5023 pdev->device != 0x4319 && pdev->device != 0x4324)) { 5024 /* No multiband support. */ 5025 have_2ghz_phy = 0; 5026 have_5ghz_phy = 0; 5027 switch (dev->phy.type) { 5028 case B43_PHYTYPE_A: 5029 have_5ghz_phy = 1; 5030 break; 5031 case B43_PHYTYPE_LP: //FIXME not always! 5032#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference 5033 have_5ghz_phy = 1; 5034#endif 5035 case B43_PHYTYPE_G: 5036 case B43_PHYTYPE_N: 5037 case B43_PHYTYPE_HT: 5038 case B43_PHYTYPE_LCN: 5039 have_2ghz_phy = 1; 5040 break; 5041 default: 5042 B43_WARN_ON(1); 5043 } 5044 } 5045 if (dev->phy.type == B43_PHYTYPE_A) { 5046 /* FIXME */ 5047 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 5048 err = -EOPNOTSUPP; 5049 goto err_powerdown; 5050 } 5051 if (1 /* disable A-PHY */) { 5052 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */ 5053 if (dev->phy.type != B43_PHYTYPE_N && 5054 dev->phy.type != B43_PHYTYPE_LP) { 5055 have_2ghz_phy = 1; 5056 have_5ghz_phy = 0; 5057 } 5058 } 5059 5060 err = b43_phy_allocate(dev); 5061 if (err) 5062 goto err_powerdown; 5063 5064 dev->phy.gmode = have_2ghz_phy; 5065 b43_wireless_core_reset(dev, dev->phy.gmode); 5066 5067 err = b43_validate_chipaccess(dev); 5068 if (err) 5069 goto err_phy_free; 5070 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); 5071 if (err) 5072 goto err_phy_free; 5073 5074 /* Now set some default "current_dev" */ 5075 if (!wl->current_dev) 5076 wl->current_dev = dev; 5077 INIT_WORK(&dev->restart_work, b43_chip_reset); 5078 5079 dev->phy.ops->switch_analog(dev, 0); 5080 b43_device_disable(dev, 0); 5081 b43_bus_may_powerdown(dev); 5082 5083out: 5084 return err; 5085 5086err_phy_free: 5087 b43_phy_free(dev); 5088err_powerdown: 5089 b43_bus_may_powerdown(dev); 5090 return err; 5091} 5092 5093static void b43_one_core_detach(struct b43_bus_dev *dev) 5094{ 5095 struct b43_wldev *wldev; 5096 struct b43_wl *wl; 5097 5098 /* Do not cancel ieee80211-workqueue based work here. 5099 * See comment in b43_remove(). */ 5100 5101 wldev = b43_bus_get_wldev(dev); 5102 wl = wldev->wl; 5103 b43_debugfs_remove_device(wldev); 5104 b43_wireless_core_detach(wldev); 5105 list_del(&wldev->list); 5106 wl->nr_devs--; 5107 b43_bus_set_wldev(dev, NULL); 5108 kfree(wldev); 5109} 5110 5111static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl) 5112{ 5113 struct b43_wldev *wldev; 5114 int err = -ENOMEM; 5115 5116 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 5117 if (!wldev) 5118 goto out; 5119 5120 wldev->use_pio = b43_modparam_pio; 5121 wldev->dev = dev; 5122 wldev->wl = wl; 5123 b43_set_status(wldev, B43_STAT_UNINIT); 5124 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 5125 INIT_LIST_HEAD(&wldev->list); 5126 5127 err = b43_wireless_core_attach(wldev); 5128 if (err) 5129 goto err_kfree_wldev; 5130 5131 list_add(&wldev->list, &wl->devlist); 5132 wl->nr_devs++; 5133 b43_bus_set_wldev(dev, wldev); 5134 b43_debugfs_add_device(wldev); 5135 5136 out: 5137 return err; 5138 5139 err_kfree_wldev: 5140 kfree(wldev); 5141 return err; 5142} 5143 5144#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ 5145 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ 5146 (pdev->device == _device) && \ 5147 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ 5148 (pdev->subsystem_device == _subdevice) ) 5149 5150static void b43_sprom_fixup(struct ssb_bus *bus) 5151{ 5152 struct pci_dev *pdev; 5153 5154 /* boardflags workarounds */ 5155 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 5156 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 5157 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 5158 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 5159 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 5160 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 5161 if (bus->bustype == SSB_BUSTYPE_PCI) { 5162 pdev = bus->host_pci; 5163 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || 5164 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || 5165 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || 5166 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || 5167 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || 5168 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || 5169 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) 5170 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; 5171 } 5172} 5173 5174static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl) 5175{ 5176 struct ieee80211_hw *hw = wl->hw; 5177 5178 ssb_set_devtypedata(dev->sdev, NULL); 5179 ieee80211_free_hw(hw); 5180} 5181 5182static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev) 5183{ 5184 struct ssb_sprom *sprom = dev->bus_sprom; 5185 struct ieee80211_hw *hw; 5186 struct b43_wl *wl; 5187 char chip_name[6]; 5188 5189 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 5190 if (!hw) { 5191 b43err(NULL, "Could not allocate ieee80211 device\n"); 5192 return ERR_PTR(-ENOMEM); 5193 } 5194 wl = hw_to_b43_wl(hw); 5195 5196 /* fill hw info */ 5197 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 5198 IEEE80211_HW_SIGNAL_DBM; 5199 5200 hw->wiphy->interface_modes = 5201 BIT(NL80211_IFTYPE_AP) | 5202 BIT(NL80211_IFTYPE_MESH_POINT) | 5203 BIT(NL80211_IFTYPE_STATION) | 5204 BIT(NL80211_IFTYPE_WDS) | 5205 BIT(NL80211_IFTYPE_ADHOC); 5206 5207 hw->queues = modparam_qos ? 4 : 1; 5208 wl->mac80211_initially_registered_queues = hw->queues; 5209 hw->max_rates = 2; 5210 SET_IEEE80211_DEV(hw, dev->dev); 5211 if (is_valid_ether_addr(sprom->et1mac)) 5212 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 5213 else 5214 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 5215 5216 /* Initialize struct b43_wl */ 5217 wl->hw = hw; 5218 mutex_init(&wl->mutex); 5219 spin_lock_init(&wl->hardirq_lock); 5220 INIT_LIST_HEAD(&wl->devlist); 5221 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); 5222 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work); 5223 INIT_WORK(&wl->tx_work, b43_tx_work); 5224 skb_queue_head_init(&wl->tx_queue); 5225 5226 snprintf(chip_name, ARRAY_SIZE(chip_name), 5227 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id); 5228 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name, 5229 dev->core_rev); 5230 return wl; 5231} 5232 5233#ifdef CONFIG_B43_BCMA 5234static int b43_bcma_probe(struct bcma_device *core) 5235{ 5236 struct b43_bus_dev *dev; 5237 struct b43_wl *wl; 5238 int err; 5239 5240 dev = b43_bus_dev_bcma_init(core); 5241 if (!dev) 5242 return -ENODEV; 5243 5244 wl = b43_wireless_init(dev); 5245 if (IS_ERR(wl)) { 5246 err = PTR_ERR(wl); 5247 goto bcma_out; 5248 } 5249 5250 err = b43_one_core_attach(dev, wl); 5251 if (err) 5252 goto bcma_err_wireless_exit; 5253 5254 err = ieee80211_register_hw(wl->hw); 5255 if (err) 5256 goto bcma_err_one_core_detach; 5257 b43_leds_register(wl->current_dev); 5258 5259bcma_out: 5260 return err; 5261 5262bcma_err_one_core_detach: 5263 b43_one_core_detach(dev); 5264bcma_err_wireless_exit: 5265 ieee80211_free_hw(wl->hw); 5266 return err; 5267} 5268 5269static void b43_bcma_remove(struct bcma_device *core) 5270{ 5271 struct b43_wldev *wldev = bcma_get_drvdata(core); 5272 struct b43_wl *wl = wldev->wl; 5273 5274 /* We must cancel any work here before unregistering from ieee80211, 5275 * as the ieee80211 unreg will destroy the workqueue. */ 5276 cancel_work_sync(&wldev->restart_work); 5277 5278 /* Restore the queues count before unregistering, because firmware detect 5279 * might have modified it. Restoring is important, so the networking 5280 * stack can properly free resources. */ 5281 wl->hw->queues = wl->mac80211_initially_registered_queues; 5282 b43_leds_stop(wldev); 5283 ieee80211_unregister_hw(wl->hw); 5284 5285 b43_one_core_detach(wldev->dev); 5286 5287 b43_leds_unregister(wl); 5288 5289 ieee80211_free_hw(wl->hw); 5290} 5291 5292static struct bcma_driver b43_bcma_driver = { 5293 .name = KBUILD_MODNAME, 5294 .id_table = b43_bcma_tbl, 5295 .probe = b43_bcma_probe, 5296 .remove = b43_bcma_remove, 5297}; 5298#endif 5299 5300#ifdef CONFIG_B43_SSB 5301static 5302int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id) 5303{ 5304 struct b43_bus_dev *dev; 5305 struct b43_wl *wl; 5306 int err; 5307 int first = 0; 5308 5309 dev = b43_bus_dev_ssb_init(sdev); 5310 if (!dev) 5311 return -ENOMEM; 5312 5313 wl = ssb_get_devtypedata(sdev); 5314 if (!wl) { 5315 /* Probing the first core. Must setup common struct b43_wl */ 5316 first = 1; 5317 b43_sprom_fixup(sdev->bus); 5318 wl = b43_wireless_init(dev); 5319 if (IS_ERR(wl)) { 5320 err = PTR_ERR(wl); 5321 goto out; 5322 } 5323 ssb_set_devtypedata(sdev, wl); 5324 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl); 5325 } 5326 err = b43_one_core_attach(dev, wl); 5327 if (err) 5328 goto err_wireless_exit; 5329 5330 if (first) { 5331 err = ieee80211_register_hw(wl->hw); 5332 if (err) 5333 goto err_one_core_detach; 5334 b43_leds_register(wl->current_dev); 5335 } 5336 5337 out: 5338 return err; 5339 5340 err_one_core_detach: 5341 b43_one_core_detach(dev); 5342 err_wireless_exit: 5343 if (first) 5344 b43_wireless_exit(dev, wl); 5345 return err; 5346} 5347 5348static void b43_ssb_remove(struct ssb_device *sdev) 5349{ 5350 struct b43_wl *wl = ssb_get_devtypedata(sdev); 5351 struct b43_wldev *wldev = ssb_get_drvdata(sdev); 5352 struct b43_bus_dev *dev = wldev->dev; 5353 5354 /* We must cancel any work here before unregistering from ieee80211, 5355 * as the ieee80211 unreg will destroy the workqueue. */ 5356 cancel_work_sync(&wldev->restart_work); 5357 5358 B43_WARN_ON(!wl); 5359 if (wl->current_dev == wldev) { 5360 /* Restore the queues count before unregistering, because firmware detect 5361 * might have modified it. Restoring is important, so the networking 5362 * stack can properly free resources. */ 5363 wl->hw->queues = wl->mac80211_initially_registered_queues; 5364 b43_leds_stop(wldev); 5365 ieee80211_unregister_hw(wl->hw); 5366 } 5367 5368 b43_one_core_detach(dev); 5369 5370 if (list_empty(&wl->devlist)) { 5371 b43_leds_unregister(wl); 5372 /* Last core on the chip unregistered. 5373 * We can destroy common struct b43_wl. 5374 */ 5375 b43_wireless_exit(dev, wl); 5376 } 5377} 5378 5379static struct ssb_driver b43_ssb_driver = { 5380 .name = KBUILD_MODNAME, 5381 .id_table = b43_ssb_tbl, 5382 .probe = b43_ssb_probe, 5383 .remove = b43_ssb_remove, 5384}; 5385#endif /* CONFIG_B43_SSB */ 5386 5387/* Perform a hardware reset. This can be called from any context. */ 5388void b43_controller_restart(struct b43_wldev *dev, const char *reason) 5389{ 5390 /* Must avoid requeueing, if we are in shutdown. */ 5391 if (b43_status(dev) < B43_STAT_INITIALIZED) 5392 return; 5393 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 5394 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 5395} 5396 5397static void b43_print_driverinfo(void) 5398{ 5399 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", 5400 *feat_leds = "", *feat_sdio = ""; 5401 5402#ifdef CONFIG_B43_PCI_AUTOSELECT 5403 feat_pci = "P"; 5404#endif 5405#ifdef CONFIG_B43_PCMCIA 5406 feat_pcmcia = "M"; 5407#endif 5408#ifdef CONFIG_B43_PHY_N 5409 feat_nphy = "N"; 5410#endif 5411#ifdef CONFIG_B43_LEDS 5412 feat_leds = "L"; 5413#endif 5414#ifdef CONFIG_B43_SDIO 5415 feat_sdio = "S"; 5416#endif 5417 printk(KERN_INFO "Broadcom 43xx driver loaded " 5418 "[ Features: %s%s%s%s%s, Firmware-ID: " 5419 B43_SUPPORTED_FIRMWARE_ID " ]\n", 5420 feat_pci, feat_pcmcia, feat_nphy, 5421 feat_leds, feat_sdio); 5422} 5423 5424static int __init b43_init(void) 5425{ 5426 int err; 5427 5428 b43_debugfs_init(); 5429 err = b43_pcmcia_init(); 5430 if (err) 5431 goto err_dfs_exit; 5432 err = b43_sdio_init(); 5433 if (err) 5434 goto err_pcmcia_exit; 5435#ifdef CONFIG_B43_BCMA 5436 err = bcma_driver_register(&b43_bcma_driver); 5437 if (err) 5438 goto err_sdio_exit; 5439#endif 5440#ifdef CONFIG_B43_SSB 5441 err = ssb_driver_register(&b43_ssb_driver); 5442 if (err) 5443 goto err_bcma_driver_exit; 5444#endif 5445 b43_print_driverinfo(); 5446 5447 return err; 5448 5449#ifdef CONFIG_B43_SSB 5450err_bcma_driver_exit: 5451#endif 5452#ifdef CONFIG_B43_BCMA 5453 bcma_driver_unregister(&b43_bcma_driver); 5454err_sdio_exit: 5455#endif 5456 b43_sdio_exit(); 5457err_pcmcia_exit: 5458 b43_pcmcia_exit(); 5459err_dfs_exit: 5460 b43_debugfs_exit(); 5461 return err; 5462} 5463 5464static void __exit b43_exit(void) 5465{ 5466#ifdef CONFIG_B43_SSB 5467 ssb_driver_unregister(&b43_ssb_driver); 5468#endif 5469#ifdef CONFIG_B43_BCMA 5470 bcma_driver_unregister(&b43_bcma_driver); 5471#endif 5472 b43_sdio_exit(); 5473 b43_pcmcia_exit(); 5474 b43_debugfs_exit(); 5475} 5476 5477module_init(b43_init) 5478module_exit(b43_exit) 5479