main.c revision b3fbdcf49f940d0703c356441e0daf045e64e076
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 SDIO support 12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> 13 14 Some parts of the code in this file are derived from the ipw2200 15 driver Copyright(c) 2003 - 2004 Intel Corporation. 16 17 This program is free software; you can redistribute it and/or modify 18 it under the terms of the GNU General Public License as published by 19 the Free Software Foundation; either version 2 of the License, or 20 (at your option) any later version. 21 22 This program is distributed in the hope that it will be useful, 23 but WITHOUT ANY WARRANTY; without even the implied warranty of 24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 GNU General Public License for more details. 26 27 You should have received a copy of the GNU General Public License 28 along with this program; see the file COPYING. If not, write to 29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 30 Boston, MA 02110-1301, USA. 31 32*/ 33 34#include <linux/delay.h> 35#include <linux/init.h> 36#include <linux/moduleparam.h> 37#include <linux/if_arp.h> 38#include <linux/etherdevice.h> 39#include <linux/firmware.h> 40#include <linux/wireless.h> 41#include <linux/workqueue.h> 42#include <linux/skbuff.h> 43#include <linux/io.h> 44#include <linux/dma-mapping.h> 45#include <asm/unaligned.h> 46 47#include "b43.h" 48#include "main.h" 49#include "debugfs.h" 50#include "phy_common.h" 51#include "phy_g.h" 52#include "phy_n.h" 53#include "dma.h" 54#include "pio.h" 55#include "sysfs.h" 56#include "xmit.h" 57#include "lo.h" 58#include "pcmcia.h" 59#include "sdio.h" 60#include <linux/mmc/sdio_func.h> 61 62MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 63MODULE_AUTHOR("Martin Langer"); 64MODULE_AUTHOR("Stefano Brivio"); 65MODULE_AUTHOR("Michael Buesch"); 66MODULE_AUTHOR("Gábor Stefanik"); 67MODULE_LICENSE("GPL"); 68 69MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID); 70MODULE_FIRMWARE("b43/ucode11.fw"); 71MODULE_FIRMWARE("b43/ucode13.fw"); 72MODULE_FIRMWARE("b43/ucode14.fw"); 73MODULE_FIRMWARE("b43/ucode15.fw"); 74MODULE_FIRMWARE("b43/ucode5.fw"); 75MODULE_FIRMWARE("b43/ucode9.fw"); 76 77static int modparam_bad_frames_preempt; 78module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 79MODULE_PARM_DESC(bad_frames_preempt, 80 "enable(1) / disable(0) Bad Frames Preemption"); 81 82static char modparam_fwpostfix[16]; 83module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 84MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 85 86static int modparam_hwpctl; 87module_param_named(hwpctl, modparam_hwpctl, int, 0444); 88MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 89 90static int modparam_nohwcrypt; 91module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 92MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 93 94static int modparam_hwtkip; 95module_param_named(hwtkip, modparam_hwtkip, int, 0444); 96MODULE_PARM_DESC(hwtkip, "Enable hardware tkip."); 97 98static int modparam_qos = 1; 99module_param_named(qos, modparam_qos, int, 0444); 100MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); 101 102static int modparam_btcoex = 1; 103module_param_named(btcoex, modparam_btcoex, int, 0444); 104MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)"); 105 106int b43_modparam_verbose = B43_VERBOSITY_DEFAULT; 107module_param_named(verbose, b43_modparam_verbose, int, 0644); 108MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug"); 109 110static int modparam_pio; 111module_param_named(pio, modparam_pio, int, 0444); 112MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode"); 113 114static const struct ssb_device_id b43_ssb_tbl[] = { 115 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 116 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 119 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12), 122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 123 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15), 124 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), 125 SSB_DEVTABLE_END 126}; 127 128MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 129 130/* Channel and ratetables are shared for all devices. 131 * They can't be const, because ieee80211 puts some precalculated 132 * data in there. This data is the same for all devices, so we don't 133 * get concurrency issues */ 134#define RATETAB_ENT(_rateid, _flags) \ 135 { \ 136 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ 137 .hw_value = (_rateid), \ 138 .flags = (_flags), \ 139 } 140 141/* 142 * NOTE: When changing this, sync with xmit.c's 143 * b43_plcp_get_bitrate_idx_* functions! 144 */ 145static struct ieee80211_rate __b43_ratetable[] = { 146 RATETAB_ENT(B43_CCK_RATE_1MB, 0), 147 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), 148 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), 149 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), 150 RATETAB_ENT(B43_OFDM_RATE_6MB, 0), 151 RATETAB_ENT(B43_OFDM_RATE_9MB, 0), 152 RATETAB_ENT(B43_OFDM_RATE_12MB, 0), 153 RATETAB_ENT(B43_OFDM_RATE_18MB, 0), 154 RATETAB_ENT(B43_OFDM_RATE_24MB, 0), 155 RATETAB_ENT(B43_OFDM_RATE_36MB, 0), 156 RATETAB_ENT(B43_OFDM_RATE_48MB, 0), 157 RATETAB_ENT(B43_OFDM_RATE_54MB, 0), 158}; 159 160#define b43_a_ratetable (__b43_ratetable + 4) 161#define b43_a_ratetable_size 8 162#define b43_b_ratetable (__b43_ratetable + 0) 163#define b43_b_ratetable_size 4 164#define b43_g_ratetable (__b43_ratetable + 0) 165#define b43_g_ratetable_size 12 166 167#define CHAN4G(_channel, _freq, _flags) { \ 168 .band = IEEE80211_BAND_2GHZ, \ 169 .center_freq = (_freq), \ 170 .hw_value = (_channel), \ 171 .flags = (_flags), \ 172 .max_antenna_gain = 0, \ 173 .max_power = 30, \ 174} 175static struct ieee80211_channel b43_2ghz_chantable[] = { 176 CHAN4G(1, 2412, 0), 177 CHAN4G(2, 2417, 0), 178 CHAN4G(3, 2422, 0), 179 CHAN4G(4, 2427, 0), 180 CHAN4G(5, 2432, 0), 181 CHAN4G(6, 2437, 0), 182 CHAN4G(7, 2442, 0), 183 CHAN4G(8, 2447, 0), 184 CHAN4G(9, 2452, 0), 185 CHAN4G(10, 2457, 0), 186 CHAN4G(11, 2462, 0), 187 CHAN4G(12, 2467, 0), 188 CHAN4G(13, 2472, 0), 189 CHAN4G(14, 2484, 0), 190}; 191#undef CHAN4G 192 193#define CHAN5G(_channel, _flags) { \ 194 .band = IEEE80211_BAND_5GHZ, \ 195 .center_freq = 5000 + (5 * (_channel)), \ 196 .hw_value = (_channel), \ 197 .flags = (_flags), \ 198 .max_antenna_gain = 0, \ 199 .max_power = 30, \ 200} 201static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { 202 CHAN5G(32, 0), CHAN5G(34, 0), 203 CHAN5G(36, 0), CHAN5G(38, 0), 204 CHAN5G(40, 0), CHAN5G(42, 0), 205 CHAN5G(44, 0), CHAN5G(46, 0), 206 CHAN5G(48, 0), CHAN5G(50, 0), 207 CHAN5G(52, 0), CHAN5G(54, 0), 208 CHAN5G(56, 0), CHAN5G(58, 0), 209 CHAN5G(60, 0), CHAN5G(62, 0), 210 CHAN5G(64, 0), CHAN5G(66, 0), 211 CHAN5G(68, 0), CHAN5G(70, 0), 212 CHAN5G(72, 0), CHAN5G(74, 0), 213 CHAN5G(76, 0), CHAN5G(78, 0), 214 CHAN5G(80, 0), CHAN5G(82, 0), 215 CHAN5G(84, 0), CHAN5G(86, 0), 216 CHAN5G(88, 0), CHAN5G(90, 0), 217 CHAN5G(92, 0), CHAN5G(94, 0), 218 CHAN5G(96, 0), CHAN5G(98, 0), 219 CHAN5G(100, 0), CHAN5G(102, 0), 220 CHAN5G(104, 0), CHAN5G(106, 0), 221 CHAN5G(108, 0), CHAN5G(110, 0), 222 CHAN5G(112, 0), CHAN5G(114, 0), 223 CHAN5G(116, 0), CHAN5G(118, 0), 224 CHAN5G(120, 0), CHAN5G(122, 0), 225 CHAN5G(124, 0), CHAN5G(126, 0), 226 CHAN5G(128, 0), CHAN5G(130, 0), 227 CHAN5G(132, 0), CHAN5G(134, 0), 228 CHAN5G(136, 0), CHAN5G(138, 0), 229 CHAN5G(140, 0), CHAN5G(142, 0), 230 CHAN5G(144, 0), CHAN5G(145, 0), 231 CHAN5G(146, 0), CHAN5G(147, 0), 232 CHAN5G(148, 0), CHAN5G(149, 0), 233 CHAN5G(150, 0), CHAN5G(151, 0), 234 CHAN5G(152, 0), CHAN5G(153, 0), 235 CHAN5G(154, 0), CHAN5G(155, 0), 236 CHAN5G(156, 0), CHAN5G(157, 0), 237 CHAN5G(158, 0), CHAN5G(159, 0), 238 CHAN5G(160, 0), CHAN5G(161, 0), 239 CHAN5G(162, 0), CHAN5G(163, 0), 240 CHAN5G(164, 0), CHAN5G(165, 0), 241 CHAN5G(166, 0), CHAN5G(168, 0), 242 CHAN5G(170, 0), CHAN5G(172, 0), 243 CHAN5G(174, 0), CHAN5G(176, 0), 244 CHAN5G(178, 0), CHAN5G(180, 0), 245 CHAN5G(182, 0), CHAN5G(184, 0), 246 CHAN5G(186, 0), CHAN5G(188, 0), 247 CHAN5G(190, 0), CHAN5G(192, 0), 248 CHAN5G(194, 0), CHAN5G(196, 0), 249 CHAN5G(198, 0), CHAN5G(200, 0), 250 CHAN5G(202, 0), CHAN5G(204, 0), 251 CHAN5G(206, 0), CHAN5G(208, 0), 252 CHAN5G(210, 0), CHAN5G(212, 0), 253 CHAN5G(214, 0), CHAN5G(216, 0), 254 CHAN5G(218, 0), CHAN5G(220, 0), 255 CHAN5G(222, 0), CHAN5G(224, 0), 256 CHAN5G(226, 0), CHAN5G(228, 0), 257}; 258 259static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { 260 CHAN5G(34, 0), CHAN5G(36, 0), 261 CHAN5G(38, 0), CHAN5G(40, 0), 262 CHAN5G(42, 0), CHAN5G(44, 0), 263 CHAN5G(46, 0), CHAN5G(48, 0), 264 CHAN5G(52, 0), CHAN5G(56, 0), 265 CHAN5G(60, 0), CHAN5G(64, 0), 266 CHAN5G(100, 0), CHAN5G(104, 0), 267 CHAN5G(108, 0), CHAN5G(112, 0), 268 CHAN5G(116, 0), CHAN5G(120, 0), 269 CHAN5G(124, 0), CHAN5G(128, 0), 270 CHAN5G(132, 0), CHAN5G(136, 0), 271 CHAN5G(140, 0), CHAN5G(149, 0), 272 CHAN5G(153, 0), CHAN5G(157, 0), 273 CHAN5G(161, 0), CHAN5G(165, 0), 274 CHAN5G(184, 0), CHAN5G(188, 0), 275 CHAN5G(192, 0), CHAN5G(196, 0), 276 CHAN5G(200, 0), CHAN5G(204, 0), 277 CHAN5G(208, 0), CHAN5G(212, 0), 278 CHAN5G(216, 0), 279}; 280#undef CHAN5G 281 282static struct ieee80211_supported_band b43_band_5GHz_nphy = { 283 .band = IEEE80211_BAND_5GHZ, 284 .channels = b43_5ghz_nphy_chantable, 285 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), 286 .bitrates = b43_a_ratetable, 287 .n_bitrates = b43_a_ratetable_size, 288}; 289 290static struct ieee80211_supported_band b43_band_5GHz_aphy = { 291 .band = IEEE80211_BAND_5GHZ, 292 .channels = b43_5ghz_aphy_chantable, 293 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), 294 .bitrates = b43_a_ratetable, 295 .n_bitrates = b43_a_ratetable_size, 296}; 297 298static struct ieee80211_supported_band b43_band_2GHz = { 299 .band = IEEE80211_BAND_2GHZ, 300 .channels = b43_2ghz_chantable, 301 .n_channels = ARRAY_SIZE(b43_2ghz_chantable), 302 .bitrates = b43_g_ratetable, 303 .n_bitrates = b43_g_ratetable_size, 304}; 305 306static void b43_wireless_core_exit(struct b43_wldev *dev); 307static int b43_wireless_core_init(struct b43_wldev *dev); 308static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev); 309static int b43_wireless_core_start(struct b43_wldev *dev); 310 311static int b43_ratelimit(struct b43_wl *wl) 312{ 313 if (!wl || !wl->current_dev) 314 return 1; 315 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 316 return 1; 317 /* We are up and running. 318 * Ratelimit the messages to avoid DoS over the net. */ 319 return net_ratelimit(); 320} 321 322void b43info(struct b43_wl *wl, const char *fmt, ...) 323{ 324 va_list args; 325 326 if (b43_modparam_verbose < B43_VERBOSITY_INFO) 327 return; 328 if (!b43_ratelimit(wl)) 329 return; 330 va_start(args, fmt); 331 printk(KERN_INFO "b43-%s: ", 332 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 333 vprintk(fmt, args); 334 va_end(args); 335} 336 337void b43err(struct b43_wl *wl, const char *fmt, ...) 338{ 339 va_list args; 340 341 if (b43_modparam_verbose < B43_VERBOSITY_ERROR) 342 return; 343 if (!b43_ratelimit(wl)) 344 return; 345 va_start(args, fmt); 346 printk(KERN_ERR "b43-%s ERROR: ", 347 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 348 vprintk(fmt, args); 349 va_end(args); 350} 351 352void b43warn(struct b43_wl *wl, const char *fmt, ...) 353{ 354 va_list args; 355 356 if (b43_modparam_verbose < B43_VERBOSITY_WARN) 357 return; 358 if (!b43_ratelimit(wl)) 359 return; 360 va_start(args, fmt); 361 printk(KERN_WARNING "b43-%s warning: ", 362 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 363 vprintk(fmt, args); 364 va_end(args); 365} 366 367void b43dbg(struct b43_wl *wl, const char *fmt, ...) 368{ 369 va_list args; 370 371 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 372 return; 373 va_start(args, fmt); 374 printk(KERN_DEBUG "b43-%s debug: ", 375 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 376 vprintk(fmt, args); 377 va_end(args); 378} 379 380static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 381{ 382 u32 macctl; 383 384 B43_WARN_ON(offset % 4 != 0); 385 386 macctl = b43_read32(dev, B43_MMIO_MACCTL); 387 if (macctl & B43_MACCTL_BE) 388 val = swab32(val); 389 390 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 391 mmiowb(); 392 b43_write32(dev, B43_MMIO_RAM_DATA, val); 393} 394 395static inline void b43_shm_control_word(struct b43_wldev *dev, 396 u16 routing, u16 offset) 397{ 398 u32 control; 399 400 /* "offset" is the WORD offset. */ 401 control = routing; 402 control <<= 16; 403 control |= offset; 404 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 405} 406 407u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 408{ 409 u32 ret; 410 411 if (routing == B43_SHM_SHARED) { 412 B43_WARN_ON(offset & 0x0001); 413 if (offset & 0x0003) { 414 /* Unaligned access */ 415 b43_shm_control_word(dev, routing, offset >> 2); 416 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 417 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 418 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16; 419 420 goto out; 421 } 422 offset >>= 2; 423 } 424 b43_shm_control_word(dev, routing, offset); 425 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 426out: 427 return ret; 428} 429 430u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset) 431{ 432 u16 ret; 433 434 if (routing == B43_SHM_SHARED) { 435 B43_WARN_ON(offset & 0x0001); 436 if (offset & 0x0003) { 437 /* Unaligned access */ 438 b43_shm_control_word(dev, routing, offset >> 2); 439 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 440 441 goto out; 442 } 443 offset >>= 2; 444 } 445 b43_shm_control_word(dev, routing, offset); 446 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 447out: 448 return ret; 449} 450 451void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 452{ 453 if (routing == B43_SHM_SHARED) { 454 B43_WARN_ON(offset & 0x0001); 455 if (offset & 0x0003) { 456 /* Unaligned access */ 457 b43_shm_control_word(dev, routing, offset >> 2); 458 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 459 value & 0xFFFF); 460 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 461 b43_write16(dev, B43_MMIO_SHM_DATA, 462 (value >> 16) & 0xFFFF); 463 return; 464 } 465 offset >>= 2; 466 } 467 b43_shm_control_word(dev, routing, offset); 468 b43_write32(dev, B43_MMIO_SHM_DATA, value); 469} 470 471void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 472{ 473 if (routing == B43_SHM_SHARED) { 474 B43_WARN_ON(offset & 0x0001); 475 if (offset & 0x0003) { 476 /* Unaligned access */ 477 b43_shm_control_word(dev, routing, offset >> 2); 478 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 479 return; 480 } 481 offset >>= 2; 482 } 483 b43_shm_control_word(dev, routing, offset); 484 b43_write16(dev, B43_MMIO_SHM_DATA, value); 485} 486 487/* Read HostFlags */ 488u64 b43_hf_read(struct b43_wldev *dev) 489{ 490 u64 ret; 491 492 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 493 ret <<= 16; 494 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI); 495 ret <<= 16; 496 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 497 498 return ret; 499} 500 501/* Write HostFlags */ 502void b43_hf_write(struct b43_wldev *dev, u64 value) 503{ 504 u16 lo, mi, hi; 505 506 lo = (value & 0x00000000FFFFULL); 507 mi = (value & 0x0000FFFF0000ULL) >> 16; 508 hi = (value & 0xFFFF00000000ULL) >> 32; 509 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo); 510 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi); 511 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi); 512} 513 514/* Read the firmware capabilities bitmask (Opensource firmware only) */ 515static u16 b43_fwcapa_read(struct b43_wldev *dev) 516{ 517 B43_WARN_ON(!dev->fw.opensource); 518 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA); 519} 520 521void b43_tsf_read(struct b43_wldev *dev, u64 *tsf) 522{ 523 u32 low, high; 524 525 B43_WARN_ON(dev->dev->id.revision < 3); 526 527 /* The hardware guarantees us an atomic read, if we 528 * read the low register first. */ 529 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 530 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 531 532 *tsf = high; 533 *tsf <<= 32; 534 *tsf |= low; 535} 536 537static void b43_time_lock(struct b43_wldev *dev) 538{ 539 u32 macctl; 540 541 macctl = b43_read32(dev, B43_MMIO_MACCTL); 542 macctl |= B43_MACCTL_TBTTHOLD; 543 b43_write32(dev, B43_MMIO_MACCTL, macctl); 544 /* Commit the write */ 545 b43_read32(dev, B43_MMIO_MACCTL); 546} 547 548static void b43_time_unlock(struct b43_wldev *dev) 549{ 550 u32 macctl; 551 552 macctl = b43_read32(dev, B43_MMIO_MACCTL); 553 macctl &= ~B43_MACCTL_TBTTHOLD; 554 b43_write32(dev, B43_MMIO_MACCTL, macctl); 555 /* Commit the write */ 556 b43_read32(dev, B43_MMIO_MACCTL); 557} 558 559static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 560{ 561 u32 low, high; 562 563 B43_WARN_ON(dev->dev->id.revision < 3); 564 565 low = tsf; 566 high = (tsf >> 32); 567 /* The hardware guarantees us an atomic write, if we 568 * write the low register first. */ 569 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low); 570 mmiowb(); 571 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high); 572 mmiowb(); 573} 574 575void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 576{ 577 b43_time_lock(dev); 578 b43_tsf_write_locked(dev, tsf); 579 b43_time_unlock(dev); 580} 581 582static 583void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac) 584{ 585 static const u8 zero_addr[ETH_ALEN] = { 0 }; 586 u16 data; 587 588 if (!mac) 589 mac = zero_addr; 590 591 offset |= 0x0020; 592 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 593 594 data = mac[0]; 595 data |= mac[1] << 8; 596 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 597 data = mac[2]; 598 data |= mac[3] << 8; 599 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 600 data = mac[4]; 601 data |= mac[5] << 8; 602 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 603} 604 605static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 606{ 607 const u8 *mac; 608 const u8 *bssid; 609 u8 mac_bssid[ETH_ALEN * 2]; 610 int i; 611 u32 tmp; 612 613 bssid = dev->wl->bssid; 614 mac = dev->wl->mac_addr; 615 616 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 617 618 memcpy(mac_bssid, mac, ETH_ALEN); 619 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 620 621 /* Write our MAC address and BSSID to template ram */ 622 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 623 tmp = (u32) (mac_bssid[i + 0]); 624 tmp |= (u32) (mac_bssid[i + 1]) << 8; 625 tmp |= (u32) (mac_bssid[i + 2]) << 16; 626 tmp |= (u32) (mac_bssid[i + 3]) << 24; 627 b43_ram_write(dev, 0x20 + i, tmp); 628 } 629} 630 631static void b43_upload_card_macaddress(struct b43_wldev *dev) 632{ 633 b43_write_mac_bssid_templates(dev); 634 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 635} 636 637static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 638{ 639 /* slot_time is in usec. */ 640 if (dev->phy.type != B43_PHYTYPE_G) 641 return; 642 b43_write16(dev, 0x684, 510 + slot_time); 643 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 644} 645 646static void b43_short_slot_timing_enable(struct b43_wldev *dev) 647{ 648 b43_set_slot_time(dev, 9); 649} 650 651static void b43_short_slot_timing_disable(struct b43_wldev *dev) 652{ 653 b43_set_slot_time(dev, 20); 654} 655 656/* DummyTransmission function, as documented on 657 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission 658 */ 659void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) 660{ 661 struct b43_phy *phy = &dev->phy; 662 unsigned int i, max_loop; 663 u16 value; 664 u32 buffer[5] = { 665 0x00000000, 666 0x00D40000, 667 0x00000000, 668 0x01000000, 669 0x00000000, 670 }; 671 672 if (ofdm) { 673 max_loop = 0x1E; 674 buffer[0] = 0x000201CC; 675 } else { 676 max_loop = 0xFA; 677 buffer[0] = 0x000B846E; 678 } 679 680 for (i = 0; i < 5; i++) 681 b43_ram_write(dev, i * 4, buffer[i]); 682 683 b43_write16(dev, 0x0568, 0x0000); 684 if (dev->dev->id.revision < 11) 685 b43_write16(dev, 0x07C0, 0x0000); 686 else 687 b43_write16(dev, 0x07C0, 0x0100); 688 value = (ofdm ? 0x41 : 0x40); 689 b43_write16(dev, 0x050C, value); 690 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP)) 691 b43_write16(dev, 0x0514, 0x1A02); 692 b43_write16(dev, 0x0508, 0x0000); 693 b43_write16(dev, 0x050A, 0x0000); 694 b43_write16(dev, 0x054C, 0x0000); 695 b43_write16(dev, 0x056A, 0x0014); 696 b43_write16(dev, 0x0568, 0x0826); 697 b43_write16(dev, 0x0500, 0x0000); 698 if (!pa_on && (phy->type == B43_PHYTYPE_N)) { 699 //SPEC TODO 700 } 701 702 switch (phy->type) { 703 case B43_PHYTYPE_N: 704 b43_write16(dev, 0x0502, 0x00D0); 705 break; 706 case B43_PHYTYPE_LP: 707 b43_write16(dev, 0x0502, 0x0050); 708 break; 709 default: 710 b43_write16(dev, 0x0502, 0x0030); 711 } 712 713 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 714 b43_radio_write16(dev, 0x0051, 0x0017); 715 for (i = 0x00; i < max_loop; i++) { 716 value = b43_read16(dev, 0x050E); 717 if (value & 0x0080) 718 break; 719 udelay(10); 720 } 721 for (i = 0x00; i < 0x0A; i++) { 722 value = b43_read16(dev, 0x050E); 723 if (value & 0x0400) 724 break; 725 udelay(10); 726 } 727 for (i = 0x00; i < 0x19; i++) { 728 value = b43_read16(dev, 0x0690); 729 if (!(value & 0x0100)) 730 break; 731 udelay(10); 732 } 733 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 734 b43_radio_write16(dev, 0x0051, 0x0037); 735} 736 737static void key_write(struct b43_wldev *dev, 738 u8 index, u8 algorithm, const u8 *key) 739{ 740 unsigned int i; 741 u32 offset; 742 u16 value; 743 u16 kidx; 744 745 /* Key index/algo block */ 746 kidx = b43_kidx_to_fw(dev, index); 747 value = ((kidx << 4) | algorithm); 748 b43_shm_write16(dev, B43_SHM_SHARED, 749 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 750 751 /* Write the key to the Key Table Pointer offset */ 752 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 753 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 754 value = key[i]; 755 value |= (u16) (key[i + 1]) << 8; 756 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 757 } 758} 759 760static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr) 761{ 762 u32 addrtmp[2] = { 0, 0, }; 763 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 764 765 if (b43_new_kidx_api(dev)) 766 pairwise_keys_start = B43_NR_GROUP_KEYS; 767 768 B43_WARN_ON(index < pairwise_keys_start); 769 /* We have four default TX keys and possibly four default RX keys. 770 * Physical mac 0 is mapped to physical key 4 or 8, depending 771 * on the firmware version. 772 * So we must adjust the index here. 773 */ 774 index -= pairwise_keys_start; 775 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 776 777 if (addr) { 778 addrtmp[0] = addr[0]; 779 addrtmp[0] |= ((u32) (addr[1]) << 8); 780 addrtmp[0] |= ((u32) (addr[2]) << 16); 781 addrtmp[0] |= ((u32) (addr[3]) << 24); 782 addrtmp[1] = addr[4]; 783 addrtmp[1] |= ((u32) (addr[5]) << 8); 784 } 785 786 /* Receive match transmitter address (RCMTA) mechanism */ 787 b43_shm_write32(dev, B43_SHM_RCMTA, 788 (index * 2) + 0, addrtmp[0]); 789 b43_shm_write16(dev, B43_SHM_RCMTA, 790 (index * 2) + 1, addrtmp[1]); 791} 792 793/* The ucode will use phase1 key with TEK key to decrypt rx packets. 794 * When a packet is received, the iv32 is checked. 795 * - if it doesn't the packet is returned without modification (and software 796 * decryption can be done). That's what happen when iv16 wrap. 797 * - if it does, the rc4 key is computed, and decryption is tried. 798 * Either it will success and B43_RX_MAC_DEC is returned, 799 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned 800 * and the packet is not usable (it got modified by the ucode). 801 * So in order to never have B43_RX_MAC_DECERR, we should provide 802 * a iv32 and phase1key that match. Because we drop packets in case of 803 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all 804 * packets will be lost without higher layer knowing (ie no resync possible 805 * until next wrap). 806 * 807 * NOTE : this should support 50 key like RCMTA because 808 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50 809 */ 810static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32, 811 u16 *phase1key) 812{ 813 unsigned int i; 814 u32 offset; 815 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 816 817 if (!modparam_hwtkip) 818 return; 819 820 if (b43_new_kidx_api(dev)) 821 pairwise_keys_start = B43_NR_GROUP_KEYS; 822 823 B43_WARN_ON(index < pairwise_keys_start); 824 /* We have four default TX keys and possibly four default RX keys. 825 * Physical mac 0 is mapped to physical key 4 or 8, depending 826 * on the firmware version. 827 * So we must adjust the index here. 828 */ 829 index -= pairwise_keys_start; 830 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 831 832 if (b43_debug(dev, B43_DBG_KEYS)) { 833 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", 834 index, iv32); 835 } 836 /* Write the key to the RX tkip shared mem */ 837 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4); 838 for (i = 0; i < 10; i += 2) { 839 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, 840 phase1key ? phase1key[i / 2] : 0); 841 } 842 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32); 843 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16); 844} 845 846static void b43_op_update_tkip_key(struct ieee80211_hw *hw, 847 struct ieee80211_vif *vif, 848 struct ieee80211_key_conf *keyconf, 849 struct ieee80211_sta *sta, 850 u32 iv32, u16 *phase1key) 851{ 852 struct b43_wl *wl = hw_to_b43_wl(hw); 853 struct b43_wldev *dev; 854 int index = keyconf->hw_key_idx; 855 856 if (B43_WARN_ON(!modparam_hwtkip)) 857 return; 858 859 mutex_lock(&wl->mutex); 860 861 dev = wl->current_dev; 862 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 863 goto out_unlock; 864 865 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */ 866 867 rx_tkip_phase1_write(dev, index, iv32, phase1key); 868 /* only pairwise TKIP keys are supported right now */ 869 if (WARN_ON(!sta)) 870 goto out_unlock; 871 keymac_write(dev, index, sta->addr); 872 873out_unlock: 874 mutex_unlock(&wl->mutex); 875} 876 877static void do_key_write(struct b43_wldev *dev, 878 u8 index, u8 algorithm, 879 const u8 *key, size_t key_len, const u8 *mac_addr) 880{ 881 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 882 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 883 884 if (b43_new_kidx_api(dev)) 885 pairwise_keys_start = B43_NR_GROUP_KEYS; 886 887 B43_WARN_ON(index >= ARRAY_SIZE(dev->key)); 888 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 889 890 if (index >= pairwise_keys_start) 891 keymac_write(dev, index, NULL); /* First zero out mac. */ 892 if (algorithm == B43_SEC_ALGO_TKIP) { 893 /* 894 * We should provide an initial iv32, phase1key pair. 895 * We could start with iv32=0 and compute the corresponding 896 * phase1key, but this means calling ieee80211_get_tkip_key 897 * with a fake skb (or export other tkip function). 898 * Because we are lazy we hope iv32 won't start with 899 * 0xffffffff and let's b43_op_update_tkip_key provide a 900 * correct pair. 901 */ 902 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); 903 } else if (index >= pairwise_keys_start) /* clear it */ 904 rx_tkip_phase1_write(dev, index, 0, NULL); 905 if (key) 906 memcpy(buf, key, key_len); 907 key_write(dev, index, algorithm, buf); 908 if (index >= pairwise_keys_start) 909 keymac_write(dev, index, mac_addr); 910 911 dev->key[index].algorithm = algorithm; 912} 913 914static int b43_key_write(struct b43_wldev *dev, 915 int index, u8 algorithm, 916 const u8 *key, size_t key_len, 917 const u8 *mac_addr, 918 struct ieee80211_key_conf *keyconf) 919{ 920 int i; 921 int pairwise_keys_start; 922 923 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block: 924 * - Temporal Encryption Key (128 bits) 925 * - Temporal Authenticator Tx MIC Key (64 bits) 926 * - Temporal Authenticator Rx MIC Key (64 bits) 927 * 928 * Hardware only store TEK 929 */ 930 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32) 931 key_len = 16; 932 if (key_len > B43_SEC_KEYSIZE) 933 return -EINVAL; 934 for (i = 0; i < ARRAY_SIZE(dev->key); i++) { 935 /* Check that we don't already have this key. */ 936 B43_WARN_ON(dev->key[i].keyconf == keyconf); 937 } 938 if (index < 0) { 939 /* Pairwise key. Get an empty slot for the key. */ 940 if (b43_new_kidx_api(dev)) 941 pairwise_keys_start = B43_NR_GROUP_KEYS; 942 else 943 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 944 for (i = pairwise_keys_start; 945 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS; 946 i++) { 947 B43_WARN_ON(i >= ARRAY_SIZE(dev->key)); 948 if (!dev->key[i].keyconf) { 949 /* found empty */ 950 index = i; 951 break; 952 } 953 } 954 if (index < 0) { 955 b43warn(dev->wl, "Out of hardware key memory\n"); 956 return -ENOSPC; 957 } 958 } else 959 B43_WARN_ON(index > 3); 960 961 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 962 if ((index <= 3) && !b43_new_kidx_api(dev)) { 963 /* Default RX key */ 964 B43_WARN_ON(mac_addr); 965 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 966 } 967 keyconf->hw_key_idx = index; 968 dev->key[index].keyconf = keyconf; 969 970 return 0; 971} 972 973static int b43_key_clear(struct b43_wldev *dev, int index) 974{ 975 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) 976 return -EINVAL; 977 do_key_write(dev, index, B43_SEC_ALGO_NONE, 978 NULL, B43_SEC_KEYSIZE, NULL); 979 if ((index <= 3) && !b43_new_kidx_api(dev)) { 980 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 981 NULL, B43_SEC_KEYSIZE, NULL); 982 } 983 dev->key[index].keyconf = NULL; 984 985 return 0; 986} 987 988static void b43_clear_keys(struct b43_wldev *dev) 989{ 990 int i, count; 991 992 if (b43_new_kidx_api(dev)) 993 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 994 else 995 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 996 for (i = 0; i < count; i++) 997 b43_key_clear(dev, i); 998} 999 1000static void b43_dump_keymemory(struct b43_wldev *dev) 1001{ 1002 unsigned int i, index, count, offset, pairwise_keys_start; 1003 u8 mac[ETH_ALEN]; 1004 u16 algo; 1005 u32 rcmta0; 1006 u16 rcmta1; 1007 u64 hf; 1008 struct b43_key *key; 1009 1010 if (!b43_debug(dev, B43_DBG_KEYS)) 1011 return; 1012 1013 hf = b43_hf_read(dev); 1014 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n", 1015 !!(hf & B43_HF_USEDEFKEYS)); 1016 if (b43_new_kidx_api(dev)) { 1017 pairwise_keys_start = B43_NR_GROUP_KEYS; 1018 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1019 } else { 1020 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 1021 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1022 } 1023 for (index = 0; index < count; index++) { 1024 key = &(dev->key[index]); 1025 printk(KERN_DEBUG "Key slot %02u: %s", 1026 index, (key->keyconf == NULL) ? " " : "*"); 1027 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 1028 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 1029 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1030 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1031 } 1032 1033 algo = b43_shm_read16(dev, B43_SHM_SHARED, 1034 B43_SHM_SH_KEYIDXBLOCK + (index * 2)); 1035 printk(" Algo: %04X/%02X", algo, key->algorithm); 1036 1037 if (index >= pairwise_keys_start) { 1038 if (key->algorithm == B43_SEC_ALGO_TKIP) { 1039 printk(" TKIP: "); 1040 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4); 1041 for (i = 0; i < 14; i += 2) { 1042 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1043 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1044 } 1045 } 1046 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA, 1047 ((index - pairwise_keys_start) * 2) + 0); 1048 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA, 1049 ((index - pairwise_keys_start) * 2) + 1); 1050 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); 1051 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1); 1052 printk(" MAC: %pM", mac); 1053 } else 1054 printk(" DEFAULT KEY"); 1055 printk("\n"); 1056 } 1057} 1058 1059void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 1060{ 1061 u32 macctl; 1062 u16 ucstat; 1063 bool hwps; 1064 bool awake; 1065 int i; 1066 1067 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 1068 (ps_flags & B43_PS_DISABLED)); 1069 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 1070 1071 if (ps_flags & B43_PS_ENABLED) { 1072 hwps = 1; 1073 } else if (ps_flags & B43_PS_DISABLED) { 1074 hwps = 0; 1075 } else { 1076 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 1077 // and thus is not an AP and we are associated, set bit 25 1078 } 1079 if (ps_flags & B43_PS_AWAKE) { 1080 awake = 1; 1081 } else if (ps_flags & B43_PS_ASLEEP) { 1082 awake = 0; 1083 } else { 1084 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 1085 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 1086 // successful, set bit26 1087 } 1088 1089/* FIXME: For now we force awake-on and hwps-off */ 1090 hwps = 0; 1091 awake = 1; 1092 1093 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1094 if (hwps) 1095 macctl |= B43_MACCTL_HWPS; 1096 else 1097 macctl &= ~B43_MACCTL_HWPS; 1098 if (awake) 1099 macctl |= B43_MACCTL_AWAKE; 1100 else 1101 macctl &= ~B43_MACCTL_AWAKE; 1102 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1103 /* Commit write */ 1104 b43_read32(dev, B43_MMIO_MACCTL); 1105 if (awake && dev->dev->id.revision >= 5) { 1106 /* Wait for the microcode to wake up. */ 1107 for (i = 0; i < 100; i++) { 1108 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 1109 B43_SHM_SH_UCODESTAT); 1110 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 1111 break; 1112 udelay(10); 1113 } 1114 } 1115} 1116 1117void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 1118{ 1119 u32 tmslow; 1120 u32 macctl; 1121 1122 flags |= B43_TMSLOW_PHYCLKEN; 1123 flags |= B43_TMSLOW_PHYRESET; 1124 ssb_device_enable(dev->dev, flags); 1125 msleep(2); /* Wait for the PLL to turn on. */ 1126 1127 /* Now take the PHY out of Reset again */ 1128 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 1129 tmslow |= SSB_TMSLOW_FGC; 1130 tmslow &= ~B43_TMSLOW_PHYRESET; 1131 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 1132 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 1133 msleep(1); 1134 tmslow &= ~SSB_TMSLOW_FGC; 1135 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 1136 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 1137 msleep(1); 1138 1139 /* Turn Analog ON, but only if we already know the PHY-type. 1140 * This protects against very early setup where we don't know the 1141 * PHY-type, yet. wireless_core_reset will be called once again later, 1142 * when we know the PHY-type. */ 1143 if (dev->phy.ops) 1144 dev->phy.ops->switch_analog(dev, 1); 1145 1146 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1147 macctl &= ~B43_MACCTL_GMODE; 1148 if (flags & B43_TMSLOW_GMODE) 1149 macctl |= B43_MACCTL_GMODE; 1150 macctl |= B43_MACCTL_IHR_ENABLED; 1151 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1152} 1153 1154static void handle_irq_transmit_status(struct b43_wldev *dev) 1155{ 1156 u32 v0, v1; 1157 u16 tmp; 1158 struct b43_txstatus stat; 1159 1160 while (1) { 1161 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1162 if (!(v0 & 0x00000001)) 1163 break; 1164 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1165 1166 stat.cookie = (v0 >> 16); 1167 stat.seq = (v1 & 0x0000FFFF); 1168 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 1169 tmp = (v0 & 0x0000FFFF); 1170 stat.frame_count = ((tmp & 0xF000) >> 12); 1171 stat.rts_count = ((tmp & 0x0F00) >> 8); 1172 stat.supp_reason = ((tmp & 0x001C) >> 2); 1173 stat.pm_indicated = !!(tmp & 0x0080); 1174 stat.intermediate = !!(tmp & 0x0040); 1175 stat.for_ampdu = !!(tmp & 0x0020); 1176 stat.acked = !!(tmp & 0x0002); 1177 1178 b43_handle_txstatus(dev, &stat); 1179 } 1180} 1181 1182static void drain_txstatus_queue(struct b43_wldev *dev) 1183{ 1184 u32 dummy; 1185 1186 if (dev->dev->id.revision < 5) 1187 return; 1188 /* Read all entries from the microcode TXstatus FIFO 1189 * and throw them away. 1190 */ 1191 while (1) { 1192 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1193 if (!(dummy & 0x00000001)) 1194 break; 1195 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1196 } 1197} 1198 1199static u32 b43_jssi_read(struct b43_wldev *dev) 1200{ 1201 u32 val = 0; 1202 1203 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 1204 val <<= 16; 1205 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1206 1207 return val; 1208} 1209 1210static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1211{ 1212 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1213 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1214} 1215 1216static void b43_generate_noise_sample(struct b43_wldev *dev) 1217{ 1218 b43_jssi_write(dev, 0x7F7F7F7F); 1219 b43_write32(dev, B43_MMIO_MACCMD, 1220 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1221} 1222 1223static void b43_calculate_link_quality(struct b43_wldev *dev) 1224{ 1225 /* Top half of Link Quality calculation. */ 1226 1227 if (dev->phy.type != B43_PHYTYPE_G) 1228 return; 1229 if (dev->noisecalc.calculation_running) 1230 return; 1231 dev->noisecalc.calculation_running = 1; 1232 dev->noisecalc.nr_samples = 0; 1233 1234 b43_generate_noise_sample(dev); 1235} 1236 1237static void handle_irq_noise(struct b43_wldev *dev) 1238{ 1239 struct b43_phy_g *phy = dev->phy.g; 1240 u16 tmp; 1241 u8 noise[4]; 1242 u8 i, j; 1243 s32 average; 1244 1245 /* Bottom half of Link Quality calculation. */ 1246 1247 if (dev->phy.type != B43_PHYTYPE_G) 1248 return; 1249 1250 /* Possible race condition: It might be possible that the user 1251 * changed to a different channel in the meantime since we 1252 * started the calculation. We ignore that fact, since it's 1253 * not really that much of a problem. The background noise is 1254 * an estimation only anyway. Slightly wrong results will get damped 1255 * by the averaging of the 8 sample rounds. Additionally the 1256 * value is shortlived. So it will be replaced by the next noise 1257 * calculation round soon. */ 1258 1259 B43_WARN_ON(!dev->noisecalc.calculation_running); 1260 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1261 if (noise[0] == 0x7F || noise[1] == 0x7F || 1262 noise[2] == 0x7F || noise[3] == 0x7F) 1263 goto generate_new; 1264 1265 /* Get the noise samples. */ 1266 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1267 i = dev->noisecalc.nr_samples; 1268 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1269 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1270 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1271 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1272 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1273 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1274 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1275 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1276 dev->noisecalc.nr_samples++; 1277 if (dev->noisecalc.nr_samples == 8) { 1278 /* Calculate the Link Quality by the noise samples. */ 1279 average = 0; 1280 for (i = 0; i < 8; i++) { 1281 for (j = 0; j < 4; j++) 1282 average += dev->noisecalc.samples[i][j]; 1283 } 1284 average /= (8 * 4); 1285 average *= 125; 1286 average += 64; 1287 average /= 128; 1288 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1289 tmp = (tmp / 128) & 0x1F; 1290 if (tmp >= 8) 1291 average += 2; 1292 else 1293 average -= 25; 1294 if (tmp == 8) 1295 average -= 72; 1296 else 1297 average -= 48; 1298 1299 dev->stats.link_noise = average; 1300 dev->noisecalc.calculation_running = 0; 1301 return; 1302 } 1303generate_new: 1304 b43_generate_noise_sample(dev); 1305} 1306 1307static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1308{ 1309 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) { 1310 ///TODO: PS TBTT 1311 } else { 1312 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1313 b43_power_saving_ctl_bits(dev, 0); 1314 } 1315 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 1316 dev->dfq_valid = 1; 1317} 1318 1319static void handle_irq_atim_end(struct b43_wldev *dev) 1320{ 1321 if (dev->dfq_valid) { 1322 b43_write32(dev, B43_MMIO_MACCMD, 1323 b43_read32(dev, B43_MMIO_MACCMD) 1324 | B43_MACCMD_DFQ_VALID); 1325 dev->dfq_valid = 0; 1326 } 1327} 1328 1329static void handle_irq_pmq(struct b43_wldev *dev) 1330{ 1331 u32 tmp; 1332 1333 //TODO: AP mode. 1334 1335 while (1) { 1336 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1337 if (!(tmp & 0x00000008)) 1338 break; 1339 } 1340 /* 16bit write is odd, but correct. */ 1341 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1342} 1343 1344static void b43_write_template_common(struct b43_wldev *dev, 1345 const u8 *data, u16 size, 1346 u16 ram_offset, 1347 u16 shm_size_offset, u8 rate) 1348{ 1349 u32 i, tmp; 1350 struct b43_plcp_hdr4 plcp; 1351 1352 plcp.data = 0; 1353 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1354 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1355 ram_offset += sizeof(u32); 1356 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1357 * So leave the first two bytes of the next write blank. 1358 */ 1359 tmp = (u32) (data[0]) << 16; 1360 tmp |= (u32) (data[1]) << 24; 1361 b43_ram_write(dev, ram_offset, tmp); 1362 ram_offset += sizeof(u32); 1363 for (i = 2; i < size; i += sizeof(u32)) { 1364 tmp = (u32) (data[i + 0]); 1365 if (i + 1 < size) 1366 tmp |= (u32) (data[i + 1]) << 8; 1367 if (i + 2 < size) 1368 tmp |= (u32) (data[i + 2]) << 16; 1369 if (i + 3 < size) 1370 tmp |= (u32) (data[i + 3]) << 24; 1371 b43_ram_write(dev, ram_offset + i - 2, tmp); 1372 } 1373 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1374 size + sizeof(struct b43_plcp_hdr6)); 1375} 1376 1377/* Check if the use of the antenna that ieee80211 told us to 1378 * use is possible. This will fall back to DEFAULT. 1379 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 1380u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 1381 u8 antenna_nr) 1382{ 1383 u8 antenna_mask; 1384 1385 if (antenna_nr == 0) { 1386 /* Zero means "use default antenna". That's always OK. */ 1387 return 0; 1388 } 1389 1390 /* Get the mask of available antennas. */ 1391 if (dev->phy.gmode) 1392 antenna_mask = dev->dev->bus->sprom.ant_available_bg; 1393 else 1394 antenna_mask = dev->dev->bus->sprom.ant_available_a; 1395 1396 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 1397 /* This antenna is not available. Fall back to default. */ 1398 return 0; 1399 } 1400 1401 return antenna_nr; 1402} 1403 1404/* Convert a b43 antenna number value to the PHY TX control value. */ 1405static u16 b43_antenna_to_phyctl(int antenna) 1406{ 1407 switch (antenna) { 1408 case B43_ANTENNA0: 1409 return B43_TXH_PHY_ANT0; 1410 case B43_ANTENNA1: 1411 return B43_TXH_PHY_ANT1; 1412 case B43_ANTENNA2: 1413 return B43_TXH_PHY_ANT2; 1414 case B43_ANTENNA3: 1415 return B43_TXH_PHY_ANT3; 1416 case B43_ANTENNA_AUTO0: 1417 case B43_ANTENNA_AUTO1: 1418 return B43_TXH_PHY_ANT01AUTO; 1419 } 1420 B43_WARN_ON(1); 1421 return 0; 1422} 1423 1424static void b43_write_beacon_template(struct b43_wldev *dev, 1425 u16 ram_offset, 1426 u16 shm_size_offset) 1427{ 1428 unsigned int i, len, variable_len; 1429 const struct ieee80211_mgmt *bcn; 1430 const u8 *ie; 1431 bool tim_found = 0; 1432 unsigned int rate; 1433 u16 ctl; 1434 int antenna; 1435 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon); 1436 1437 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1438 len = min((size_t) dev->wl->current_beacon->len, 1439 0x200 - sizeof(struct b43_plcp_hdr6)); 1440 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; 1441 1442 b43_write_template_common(dev, (const u8 *)bcn, 1443 len, ram_offset, shm_size_offset, rate); 1444 1445 /* Write the PHY TX control parameters. */ 1446 antenna = B43_ANTENNA_DEFAULT; 1447 antenna = b43_antenna_to_phyctl(antenna); 1448 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 1449 /* We can't send beacons with short preamble. Would get PHY errors. */ 1450 ctl &= ~B43_TXH_PHY_SHORTPRMBL; 1451 ctl &= ~B43_TXH_PHY_ANT; 1452 ctl &= ~B43_TXH_PHY_ENC; 1453 ctl |= antenna; 1454 if (b43_is_cck_rate(rate)) 1455 ctl |= B43_TXH_PHY_ENC_CCK; 1456 else 1457 ctl |= B43_TXH_PHY_ENC_OFDM; 1458 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 1459 1460 /* Find the position of the TIM and the DTIM_period value 1461 * and write them to SHM. */ 1462 ie = bcn->u.beacon.variable; 1463 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1464 for (i = 0; i < variable_len - 2; ) { 1465 uint8_t ie_id, ie_len; 1466 1467 ie_id = ie[i]; 1468 ie_len = ie[i + 1]; 1469 if (ie_id == 5) { 1470 u16 tim_position; 1471 u16 dtim_period; 1472 /* This is the TIM Information Element */ 1473 1474 /* Check whether the ie_len is in the beacon data range. */ 1475 if (variable_len < ie_len + 2 + i) 1476 break; 1477 /* A valid TIM is at least 4 bytes long. */ 1478 if (ie_len < 4) 1479 break; 1480 tim_found = 1; 1481 1482 tim_position = sizeof(struct b43_plcp_hdr6); 1483 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1484 tim_position += i; 1485 1486 dtim_period = ie[i + 3]; 1487 1488 b43_shm_write16(dev, B43_SHM_SHARED, 1489 B43_SHM_SH_TIMBPOS, tim_position); 1490 b43_shm_write16(dev, B43_SHM_SHARED, 1491 B43_SHM_SH_DTIMPER, dtim_period); 1492 break; 1493 } 1494 i += ie_len + 2; 1495 } 1496 if (!tim_found) { 1497 /* 1498 * If ucode wants to modify TIM do it behind the beacon, this 1499 * will happen, for example, when doing mesh networking. 1500 */ 1501 b43_shm_write16(dev, B43_SHM_SHARED, 1502 B43_SHM_SH_TIMBPOS, 1503 len + sizeof(struct b43_plcp_hdr6)); 1504 b43_shm_write16(dev, B43_SHM_SHARED, 1505 B43_SHM_SH_DTIMPER, 0); 1506 } 1507 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); 1508} 1509 1510static void b43_upload_beacon0(struct b43_wldev *dev) 1511{ 1512 struct b43_wl *wl = dev->wl; 1513 1514 if (wl->beacon0_uploaded) 1515 return; 1516 b43_write_beacon_template(dev, 0x68, 0x18); 1517 wl->beacon0_uploaded = 1; 1518} 1519 1520static void b43_upload_beacon1(struct b43_wldev *dev) 1521{ 1522 struct b43_wl *wl = dev->wl; 1523 1524 if (wl->beacon1_uploaded) 1525 return; 1526 b43_write_beacon_template(dev, 0x468, 0x1A); 1527 wl->beacon1_uploaded = 1; 1528} 1529 1530static void handle_irq_beacon(struct b43_wldev *dev) 1531{ 1532 struct b43_wl *wl = dev->wl; 1533 u32 cmd, beacon0_valid, beacon1_valid; 1534 1535 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && 1536 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 1537 return; 1538 1539 /* This is the bottom half of the asynchronous beacon update. */ 1540 1541 /* Ignore interrupt in the future. */ 1542 dev->irq_mask &= ~B43_IRQ_BEACON; 1543 1544 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1545 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); 1546 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); 1547 1548 /* Schedule interrupt manually, if busy. */ 1549 if (beacon0_valid && beacon1_valid) { 1550 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1551 dev->irq_mask |= B43_IRQ_BEACON; 1552 return; 1553 } 1554 1555 if (unlikely(wl->beacon_templates_virgin)) { 1556 /* We never uploaded a beacon before. 1557 * Upload both templates now, but only mark one valid. */ 1558 wl->beacon_templates_virgin = 0; 1559 b43_upload_beacon0(dev); 1560 b43_upload_beacon1(dev); 1561 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1562 cmd |= B43_MACCMD_BEACON0_VALID; 1563 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1564 } else { 1565 if (!beacon0_valid) { 1566 b43_upload_beacon0(dev); 1567 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1568 cmd |= B43_MACCMD_BEACON0_VALID; 1569 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1570 } else if (!beacon1_valid) { 1571 b43_upload_beacon1(dev); 1572 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1573 cmd |= B43_MACCMD_BEACON1_VALID; 1574 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1575 } 1576 } 1577} 1578 1579static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev) 1580{ 1581 u32 old_irq_mask = dev->irq_mask; 1582 1583 /* update beacon right away or defer to irq */ 1584 handle_irq_beacon(dev); 1585 if (old_irq_mask != dev->irq_mask) { 1586 /* The handler updated the IRQ mask. */ 1587 B43_WARN_ON(!dev->irq_mask); 1588 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) { 1589 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1590 } else { 1591 /* Device interrupts are currently disabled. That means 1592 * we just ran the hardirq handler and scheduled the 1593 * IRQ thread. The thread will write the IRQ mask when 1594 * it finished, so there's nothing to do here. Writing 1595 * the mask _here_ would incorrectly re-enable IRQs. */ 1596 } 1597 } 1598} 1599 1600static void b43_beacon_update_trigger_work(struct work_struct *work) 1601{ 1602 struct b43_wl *wl = container_of(work, struct b43_wl, 1603 beacon_update_trigger); 1604 struct b43_wldev *dev; 1605 1606 mutex_lock(&wl->mutex); 1607 dev = wl->current_dev; 1608 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { 1609 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) { 1610 /* wl->mutex is enough. */ 1611 b43_do_beacon_update_trigger_work(dev); 1612 mmiowb(); 1613 } else { 1614 spin_lock_irq(&wl->hardirq_lock); 1615 b43_do_beacon_update_trigger_work(dev); 1616 mmiowb(); 1617 spin_unlock_irq(&wl->hardirq_lock); 1618 } 1619 } 1620 mutex_unlock(&wl->mutex); 1621} 1622 1623/* Asynchronously update the packet templates in template RAM. 1624 * Locking: Requires wl->mutex to be locked. */ 1625static void b43_update_templates(struct b43_wl *wl) 1626{ 1627 struct sk_buff *beacon; 1628 1629 /* This is the top half of the ansynchronous beacon update. 1630 * The bottom half is the beacon IRQ. 1631 * Beacon update must be asynchronous to avoid sending an 1632 * invalid beacon. This can happen for example, if the firmware 1633 * transmits a beacon while we are updating it. */ 1634 1635 /* We could modify the existing beacon and set the aid bit in 1636 * the TIM field, but that would probably require resizing and 1637 * moving of data within the beacon template. 1638 * Simply request a new beacon and let mac80211 do the hard work. */ 1639 beacon = ieee80211_beacon_get(wl->hw, wl->vif); 1640 if (unlikely(!beacon)) 1641 return; 1642 1643 if (wl->current_beacon) 1644 dev_kfree_skb_any(wl->current_beacon); 1645 wl->current_beacon = beacon; 1646 wl->beacon0_uploaded = 0; 1647 wl->beacon1_uploaded = 0; 1648 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); 1649} 1650 1651static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1652{ 1653 b43_time_lock(dev); 1654 if (dev->dev->id.revision >= 3) { 1655 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); 1656 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); 1657 } else { 1658 b43_write16(dev, 0x606, (beacon_int >> 6)); 1659 b43_write16(dev, 0x610, beacon_int); 1660 } 1661 b43_time_unlock(dev); 1662 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1663} 1664 1665static void b43_handle_firmware_panic(struct b43_wldev *dev) 1666{ 1667 u16 reason; 1668 1669 /* Read the register that contains the reason code for the panic. */ 1670 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG); 1671 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason); 1672 1673 switch (reason) { 1674 default: 1675 b43dbg(dev->wl, "The panic reason is unknown.\n"); 1676 /* fallthrough */ 1677 case B43_FWPANIC_DIE: 1678 /* Do not restart the controller or firmware. 1679 * The device is nonfunctional from now on. 1680 * Restarting would result in this panic to trigger again, 1681 * so we avoid that recursion. */ 1682 break; 1683 case B43_FWPANIC_RESTART: 1684 b43_controller_restart(dev, "Microcode panic"); 1685 break; 1686 } 1687} 1688 1689static void handle_irq_ucode_debug(struct b43_wldev *dev) 1690{ 1691 unsigned int i, cnt; 1692 u16 reason, marker_id, marker_line; 1693 __le16 *buf; 1694 1695 /* The proprietary firmware doesn't have this IRQ. */ 1696 if (!dev->fw.opensource) 1697 return; 1698 1699 /* Read the register that contains the reason code for this IRQ. */ 1700 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG); 1701 1702 switch (reason) { 1703 case B43_DEBUGIRQ_PANIC: 1704 b43_handle_firmware_panic(dev); 1705 break; 1706 case B43_DEBUGIRQ_DUMP_SHM: 1707 if (!B43_DEBUG) 1708 break; /* Only with driver debugging enabled. */ 1709 buf = kmalloc(4096, GFP_ATOMIC); 1710 if (!buf) { 1711 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n"); 1712 goto out; 1713 } 1714 for (i = 0; i < 4096; i += 2) { 1715 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i); 1716 buf[i / 2] = cpu_to_le16(tmp); 1717 } 1718 b43info(dev->wl, "Shared memory dump:\n"); 1719 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 1720 16, 2, buf, 4096, 1); 1721 kfree(buf); 1722 break; 1723 case B43_DEBUGIRQ_DUMP_REGS: 1724 if (!B43_DEBUG) 1725 break; /* Only with driver debugging enabled. */ 1726 b43info(dev->wl, "Microcode register dump:\n"); 1727 for (i = 0, cnt = 0; i < 64; i++) { 1728 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i); 1729 if (cnt == 0) 1730 printk(KERN_INFO); 1731 printk("r%02u: 0x%04X ", i, tmp); 1732 cnt++; 1733 if (cnt == 6) { 1734 printk("\n"); 1735 cnt = 0; 1736 } 1737 } 1738 printk("\n"); 1739 break; 1740 case B43_DEBUGIRQ_MARKER: 1741 if (!B43_DEBUG) 1742 break; /* Only with driver debugging enabled. */ 1743 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH, 1744 B43_MARKER_ID_REG); 1745 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH, 1746 B43_MARKER_LINE_REG); 1747 b43info(dev->wl, "The firmware just executed the MARKER(%u) " 1748 "at line number %u\n", 1749 marker_id, marker_line); 1750 break; 1751 default: 1752 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n", 1753 reason); 1754 } 1755out: 1756 /* Acknowledge the debug-IRQ, so the firmware can continue. */ 1757 b43_shm_write16(dev, B43_SHM_SCRATCH, 1758 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK); 1759} 1760 1761static void b43_do_interrupt_thread(struct b43_wldev *dev) 1762{ 1763 u32 reason; 1764 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1765 u32 merged_dma_reason = 0; 1766 int i; 1767 1768 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 1769 return; 1770 1771 reason = dev->irq_reason; 1772 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1773 dma_reason[i] = dev->dma_reason[i]; 1774 merged_dma_reason |= dma_reason[i]; 1775 } 1776 1777 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1778 b43err(dev->wl, "MAC transmission error\n"); 1779 1780 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1781 b43err(dev->wl, "PHY transmission error\n"); 1782 rmb(); 1783 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1784 atomic_set(&dev->phy.txerr_cnt, 1785 B43_PHY_TX_BADNESS_LIMIT); 1786 b43err(dev->wl, "Too many PHY TX errors, " 1787 "restarting the controller\n"); 1788 b43_controller_restart(dev, "PHY TX errors"); 1789 } 1790 } 1791 1792 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1793 B43_DMAIRQ_NONFATALMASK))) { 1794 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1795 b43err(dev->wl, "Fatal DMA error: " 1796 "0x%08X, 0x%08X, 0x%08X, " 1797 "0x%08X, 0x%08X, 0x%08X\n", 1798 dma_reason[0], dma_reason[1], 1799 dma_reason[2], dma_reason[3], 1800 dma_reason[4], dma_reason[5]); 1801 b43err(dev->wl, "This device does not support DMA " 1802 "on your system. Please use PIO instead.\n"); 1803 b43err(dev->wl, "Unload the b43 module and reload " 1804 "with 'pio=1'\n"); 1805 return; 1806 } 1807 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1808 b43err(dev->wl, "DMA error: " 1809 "0x%08X, 0x%08X, 0x%08X, " 1810 "0x%08X, 0x%08X, 0x%08X\n", 1811 dma_reason[0], dma_reason[1], 1812 dma_reason[2], dma_reason[3], 1813 dma_reason[4], dma_reason[5]); 1814 } 1815 } 1816 1817 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1818 handle_irq_ucode_debug(dev); 1819 if (reason & B43_IRQ_TBTT_INDI) 1820 handle_irq_tbtt_indication(dev); 1821 if (reason & B43_IRQ_ATIM_END) 1822 handle_irq_atim_end(dev); 1823 if (reason & B43_IRQ_BEACON) 1824 handle_irq_beacon(dev); 1825 if (reason & B43_IRQ_PMQ) 1826 handle_irq_pmq(dev); 1827 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1828 ;/* TODO */ 1829 if (reason & B43_IRQ_NOISESAMPLE_OK) 1830 handle_irq_noise(dev); 1831 1832 /* Check the DMA reason registers for received data. */ 1833 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 1834 if (b43_using_pio_transfers(dev)) 1835 b43_pio_rx(dev->pio.rx_queue); 1836 else 1837 b43_dma_rx(dev->dma.rx_ring); 1838 } 1839 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1840 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1841 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); 1842 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1843 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1844 1845 if (reason & B43_IRQ_TX_OK) 1846 handle_irq_transmit_status(dev); 1847 1848 /* Re-enable interrupts on the device by restoring the current interrupt mask. */ 1849 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1850 1851#if B43_DEBUG 1852 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 1853 dev->irq_count++; 1854 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 1855 if (reason & (1 << i)) 1856 dev->irq_bit_count[i]++; 1857 } 1858 } 1859#endif 1860} 1861 1862/* Interrupt thread handler. Handles device interrupts in thread context. */ 1863static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id) 1864{ 1865 struct b43_wldev *dev = dev_id; 1866 1867 mutex_lock(&dev->wl->mutex); 1868 b43_do_interrupt_thread(dev); 1869 mmiowb(); 1870 mutex_unlock(&dev->wl->mutex); 1871 1872 return IRQ_HANDLED; 1873} 1874 1875static irqreturn_t b43_do_interrupt(struct b43_wldev *dev) 1876{ 1877 u32 reason; 1878 1879 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses. 1880 * On SDIO, this runs under wl->mutex. */ 1881 1882 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1883 if (reason == 0xffffffff) /* shared IRQ */ 1884 return IRQ_NONE; 1885 reason &= dev->irq_mask; 1886 if (!reason) 1887 return IRQ_HANDLED; 1888 1889 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1890 & 0x0001DC00; 1891 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1892 & 0x0000DC00; 1893 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1894 & 0x0000DC00; 1895 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1896 & 0x0001DC00; 1897 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1898 & 0x0000DC00; 1899/* Unused ring 1900 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1901 & 0x0000DC00; 1902*/ 1903 1904 /* ACK the interrupt. */ 1905 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1906 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1907 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1908 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1909 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1910 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1911/* Unused ring 1912 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1913*/ 1914 1915 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */ 1916 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 1917 /* Save the reason bitmasks for the IRQ thread handler. */ 1918 dev->irq_reason = reason; 1919 1920 return IRQ_WAKE_THREAD; 1921} 1922 1923/* Interrupt handler top-half. This runs with interrupts disabled. */ 1924static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1925{ 1926 struct b43_wldev *dev = dev_id; 1927 irqreturn_t ret; 1928 1929 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 1930 return IRQ_NONE; 1931 1932 spin_lock(&dev->wl->hardirq_lock); 1933 ret = b43_do_interrupt(dev); 1934 mmiowb(); 1935 spin_unlock(&dev->wl->hardirq_lock); 1936 1937 return ret; 1938} 1939 1940/* SDIO interrupt handler. This runs in process context. */ 1941static void b43_sdio_interrupt_handler(struct b43_wldev *dev) 1942{ 1943 struct b43_wl *wl = dev->wl; 1944 irqreturn_t ret; 1945 1946 mutex_lock(&wl->mutex); 1947 1948 ret = b43_do_interrupt(dev); 1949 if (ret == IRQ_WAKE_THREAD) 1950 b43_do_interrupt_thread(dev); 1951 1952 mutex_unlock(&wl->mutex); 1953} 1954 1955void b43_do_release_fw(struct b43_firmware_file *fw) 1956{ 1957 release_firmware(fw->data); 1958 fw->data = NULL; 1959 fw->filename = NULL; 1960} 1961 1962static void b43_release_firmware(struct b43_wldev *dev) 1963{ 1964 b43_do_release_fw(&dev->fw.ucode); 1965 b43_do_release_fw(&dev->fw.pcm); 1966 b43_do_release_fw(&dev->fw.initvals); 1967 b43_do_release_fw(&dev->fw.initvals_band); 1968} 1969 1970static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 1971{ 1972 const char text[] = 1973 "You must go to " \ 1974 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \ 1975 "and download the correct firmware for this driver version. " \ 1976 "Please carefully read all instructions on this website.\n"; 1977 1978 if (error) 1979 b43err(wl, text); 1980 else 1981 b43warn(wl, text); 1982} 1983 1984int b43_do_request_fw(struct b43_request_fw_context *ctx, 1985 const char *name, 1986 struct b43_firmware_file *fw) 1987{ 1988 const struct firmware *blob; 1989 struct b43_fw_header *hdr; 1990 u32 size; 1991 int err; 1992 1993 if (!name) { 1994 /* Don't fetch anything. Free possibly cached firmware. */ 1995 /* FIXME: We should probably keep it anyway, to save some headache 1996 * on suspend/resume with multiband devices. */ 1997 b43_do_release_fw(fw); 1998 return 0; 1999 } 2000 if (fw->filename) { 2001 if ((fw->type == ctx->req_type) && 2002 (strcmp(fw->filename, name) == 0)) 2003 return 0; /* Already have this fw. */ 2004 /* Free the cached firmware first. */ 2005 /* FIXME: We should probably do this later after we successfully 2006 * got the new fw. This could reduce headache with multiband devices. 2007 * We could also redesign this to cache the firmware for all possible 2008 * bands all the time. */ 2009 b43_do_release_fw(fw); 2010 } 2011 2012 switch (ctx->req_type) { 2013 case B43_FWTYPE_PROPRIETARY: 2014 snprintf(ctx->fwname, sizeof(ctx->fwname), 2015 "b43%s/%s.fw", 2016 modparam_fwpostfix, name); 2017 break; 2018 case B43_FWTYPE_OPENSOURCE: 2019 snprintf(ctx->fwname, sizeof(ctx->fwname), 2020 "b43-open%s/%s.fw", 2021 modparam_fwpostfix, name); 2022 break; 2023 default: 2024 B43_WARN_ON(1); 2025 return -ENOSYS; 2026 } 2027 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev); 2028 if (err == -ENOENT) { 2029 snprintf(ctx->errors[ctx->req_type], 2030 sizeof(ctx->errors[ctx->req_type]), 2031 "Firmware file \"%s\" not found\n", ctx->fwname); 2032 return err; 2033 } else if (err) { 2034 snprintf(ctx->errors[ctx->req_type], 2035 sizeof(ctx->errors[ctx->req_type]), 2036 "Firmware file \"%s\" request failed (err=%d)\n", 2037 ctx->fwname, err); 2038 return err; 2039 } 2040 if (blob->size < sizeof(struct b43_fw_header)) 2041 goto err_format; 2042 hdr = (struct b43_fw_header *)(blob->data); 2043 switch (hdr->type) { 2044 case B43_FW_TYPE_UCODE: 2045 case B43_FW_TYPE_PCM: 2046 size = be32_to_cpu(hdr->size); 2047 if (size != blob->size - sizeof(struct b43_fw_header)) 2048 goto err_format; 2049 /* fallthrough */ 2050 case B43_FW_TYPE_IV: 2051 if (hdr->ver != 1) 2052 goto err_format; 2053 break; 2054 default: 2055 goto err_format; 2056 } 2057 2058 fw->data = blob; 2059 fw->filename = name; 2060 fw->type = ctx->req_type; 2061 2062 return 0; 2063 2064err_format: 2065 snprintf(ctx->errors[ctx->req_type], 2066 sizeof(ctx->errors[ctx->req_type]), 2067 "Firmware file \"%s\" format error.\n", ctx->fwname); 2068 release_firmware(blob); 2069 2070 return -EPROTO; 2071} 2072 2073static int b43_try_request_fw(struct b43_request_fw_context *ctx) 2074{ 2075 struct b43_wldev *dev = ctx->dev; 2076 struct b43_firmware *fw = &ctx->dev->fw; 2077 const u8 rev = ctx->dev->dev->id.revision; 2078 const char *filename; 2079 u32 tmshigh; 2080 int err; 2081 2082 /* Get microcode */ 2083 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 2084 if ((rev >= 5) && (rev <= 10)) 2085 filename = "ucode5"; 2086 else if ((rev >= 11) && (rev <= 12)) 2087 filename = "ucode11"; 2088 else if (rev == 13) 2089 filename = "ucode13"; 2090 else if (rev == 14) 2091 filename = "ucode14"; 2092 else if (rev >= 15) 2093 filename = "ucode15"; 2094 else 2095 goto err_no_ucode; 2096 err = b43_do_request_fw(ctx, filename, &fw->ucode); 2097 if (err) 2098 goto err_load; 2099 2100 /* Get PCM code */ 2101 if ((rev >= 5) && (rev <= 10)) 2102 filename = "pcm5"; 2103 else if (rev >= 11) 2104 filename = NULL; 2105 else 2106 goto err_no_pcm; 2107 fw->pcm_request_failed = 0; 2108 err = b43_do_request_fw(ctx, filename, &fw->pcm); 2109 if (err == -ENOENT) { 2110 /* We did not find a PCM file? Not fatal, but 2111 * core rev <= 10 must do without hwcrypto then. */ 2112 fw->pcm_request_failed = 1; 2113 } else if (err) 2114 goto err_load; 2115 2116 /* Get initvals */ 2117 switch (dev->phy.type) { 2118 case B43_PHYTYPE_A: 2119 if ((rev >= 5) && (rev <= 10)) { 2120 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2121 filename = "a0g1initvals5"; 2122 else 2123 filename = "a0g0initvals5"; 2124 } else 2125 goto err_no_initvals; 2126 break; 2127 case B43_PHYTYPE_G: 2128 if ((rev >= 5) && (rev <= 10)) 2129 filename = "b0g0initvals5"; 2130 else if (rev >= 13) 2131 filename = "b0g0initvals13"; 2132 else 2133 goto err_no_initvals; 2134 break; 2135 case B43_PHYTYPE_N: 2136 if ((rev >= 11) && (rev <= 12)) 2137 filename = "n0initvals11"; 2138 else 2139 goto err_no_initvals; 2140 break; 2141 case B43_PHYTYPE_LP: 2142 if (rev == 13) 2143 filename = "lp0initvals13"; 2144 else if (rev == 14) 2145 filename = "lp0initvals14"; 2146 else if (rev >= 15) 2147 filename = "lp0initvals15"; 2148 else 2149 goto err_no_initvals; 2150 break; 2151 default: 2152 goto err_no_initvals; 2153 } 2154 err = b43_do_request_fw(ctx, filename, &fw->initvals); 2155 if (err) 2156 goto err_load; 2157 2158 /* Get bandswitch initvals */ 2159 switch (dev->phy.type) { 2160 case B43_PHYTYPE_A: 2161 if ((rev >= 5) && (rev <= 10)) { 2162 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2163 filename = "a0g1bsinitvals5"; 2164 else 2165 filename = "a0g0bsinitvals5"; 2166 } else if (rev >= 11) 2167 filename = NULL; 2168 else 2169 goto err_no_initvals; 2170 break; 2171 case B43_PHYTYPE_G: 2172 if ((rev >= 5) && (rev <= 10)) 2173 filename = "b0g0bsinitvals5"; 2174 else if (rev >= 11) 2175 filename = NULL; 2176 else 2177 goto err_no_initvals; 2178 break; 2179 case B43_PHYTYPE_N: 2180 if ((rev >= 11) && (rev <= 12)) 2181 filename = "n0bsinitvals11"; 2182 else 2183 goto err_no_initvals; 2184 break; 2185 case B43_PHYTYPE_LP: 2186 if (rev == 13) 2187 filename = "lp0bsinitvals13"; 2188 else if (rev == 14) 2189 filename = "lp0bsinitvals14"; 2190 else if (rev >= 15) 2191 filename = "lp0bsinitvals15"; 2192 else 2193 goto err_no_initvals; 2194 break; 2195 default: 2196 goto err_no_initvals; 2197 } 2198 err = b43_do_request_fw(ctx, filename, &fw->initvals_band); 2199 if (err) 2200 goto err_load; 2201 2202 return 0; 2203 2204err_no_ucode: 2205 err = ctx->fatal_failure = -EOPNOTSUPP; 2206 b43err(dev->wl, "The driver does not know which firmware (ucode) " 2207 "is required for your device (wl-core rev %u)\n", rev); 2208 goto error; 2209 2210err_no_pcm: 2211 err = ctx->fatal_failure = -EOPNOTSUPP; 2212 b43err(dev->wl, "The driver does not know which firmware (PCM) " 2213 "is required for your device (wl-core rev %u)\n", rev); 2214 goto error; 2215 2216err_no_initvals: 2217 err = ctx->fatal_failure = -EOPNOTSUPP; 2218 b43err(dev->wl, "The driver does not know which firmware (initvals) " 2219 "is required for your device (wl-core rev %u)\n", rev); 2220 goto error; 2221 2222err_load: 2223 /* We failed to load this firmware image. The error message 2224 * already is in ctx->errors. Return and let our caller decide 2225 * what to do. */ 2226 goto error; 2227 2228error: 2229 b43_release_firmware(dev); 2230 return err; 2231} 2232 2233static int b43_request_firmware(struct b43_wldev *dev) 2234{ 2235 struct b43_request_fw_context *ctx; 2236 unsigned int i; 2237 int err; 2238 const char *errmsg; 2239 2240 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2241 if (!ctx) 2242 return -ENOMEM; 2243 ctx->dev = dev; 2244 2245 ctx->req_type = B43_FWTYPE_PROPRIETARY; 2246 err = b43_try_request_fw(ctx); 2247 if (!err) 2248 goto out; /* Successfully loaded it. */ 2249 err = ctx->fatal_failure; 2250 if (err) 2251 goto out; 2252 2253 ctx->req_type = B43_FWTYPE_OPENSOURCE; 2254 err = b43_try_request_fw(ctx); 2255 if (!err) 2256 goto out; /* Successfully loaded it. */ 2257 err = ctx->fatal_failure; 2258 if (err) 2259 goto out; 2260 2261 /* Could not find a usable firmware. Print the errors. */ 2262 for (i = 0; i < B43_NR_FWTYPES; i++) { 2263 errmsg = ctx->errors[i]; 2264 if (strlen(errmsg)) 2265 b43err(dev->wl, errmsg); 2266 } 2267 b43_print_fw_helptext(dev->wl, 1); 2268 err = -ENOENT; 2269 2270out: 2271 kfree(ctx); 2272 return err; 2273} 2274 2275static int b43_upload_microcode(struct b43_wldev *dev) 2276{ 2277 const size_t hdr_len = sizeof(struct b43_fw_header); 2278 const __be32 *data; 2279 unsigned int i, len; 2280 u16 fwrev, fwpatch, fwdate, fwtime; 2281 u32 tmp, macctl; 2282 int err = 0; 2283 2284 /* Jump the microcode PSM to offset 0 */ 2285 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2286 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); 2287 macctl |= B43_MACCTL_PSM_JMP0; 2288 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2289 /* Zero out all microcode PSM registers and shared memory. */ 2290 for (i = 0; i < 64; i++) 2291 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); 2292 for (i = 0; i < 4096; i += 2) 2293 b43_shm_write16(dev, B43_SHM_SHARED, i, 0); 2294 2295 /* Upload Microcode. */ 2296 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); 2297 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); 2298 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 2299 for (i = 0; i < len; i++) { 2300 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2301 udelay(10); 2302 } 2303 2304 if (dev->fw.pcm.data) { 2305 /* Upload PCM data. */ 2306 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); 2307 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); 2308 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 2309 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 2310 /* No need for autoinc bit in SHM_HW */ 2311 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 2312 for (i = 0; i < len; i++) { 2313 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2314 udelay(10); 2315 } 2316 } 2317 2318 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 2319 2320 /* Start the microcode PSM */ 2321 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2322 macctl &= ~B43_MACCTL_PSM_JMP0; 2323 macctl |= B43_MACCTL_PSM_RUN; 2324 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2325 2326 /* Wait for the microcode to load and respond */ 2327 i = 0; 2328 while (1) { 2329 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2330 if (tmp == B43_IRQ_MAC_SUSPENDED) 2331 break; 2332 i++; 2333 if (i >= 20) { 2334 b43err(dev->wl, "Microcode not responding\n"); 2335 b43_print_fw_helptext(dev->wl, 1); 2336 err = -ENODEV; 2337 goto error; 2338 } 2339 msleep(50); 2340 } 2341 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 2342 2343 /* Get and check the revisions. */ 2344 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 2345 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 2346 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 2347 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 2348 2349 if (fwrev <= 0x128) { 2350 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 2351 "binary drivers older than version 4.x is unsupported. " 2352 "You must upgrade your firmware files.\n"); 2353 b43_print_fw_helptext(dev->wl, 1); 2354 err = -EOPNOTSUPP; 2355 goto error; 2356 } 2357 dev->fw.rev = fwrev; 2358 dev->fw.patch = fwpatch; 2359 dev->fw.opensource = (fwdate == 0xFFFF); 2360 2361 /* Default to use-all-queues. */ 2362 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues; 2363 dev->qos_enabled = !!modparam_qos; 2364 /* Default to firmware/hardware crypto acceleration. */ 2365 dev->hwcrypto_enabled = 1; 2366 2367 if (dev->fw.opensource) { 2368 u16 fwcapa; 2369 2370 /* Patchlevel info is encoded in the "time" field. */ 2371 dev->fw.patch = fwtime; 2372 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n", 2373 dev->fw.rev, dev->fw.patch); 2374 2375 fwcapa = b43_fwcapa_read(dev); 2376 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) { 2377 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n"); 2378 /* Disable hardware crypto and fall back to software crypto. */ 2379 dev->hwcrypto_enabled = 0; 2380 } 2381 if (!(fwcapa & B43_FWCAPA_QOS)) { 2382 b43info(dev->wl, "QoS not supported by firmware\n"); 2383 /* Disable QoS. Tweak hw->queues to 1. It will be restored before 2384 * ieee80211_unregister to make sure the networking core can 2385 * properly free possible resources. */ 2386 dev->wl->hw->queues = 1; 2387 dev->qos_enabled = 0; 2388 } 2389 } else { 2390 b43info(dev->wl, "Loading firmware version %u.%u " 2391 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 2392 fwrev, fwpatch, 2393 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 2394 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 2395 if (dev->fw.pcm_request_failed) { 2396 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. " 2397 "Hardware accelerated cryptography is disabled.\n"); 2398 b43_print_fw_helptext(dev->wl, 0); 2399 } 2400 } 2401 2402 if (b43_is_old_txhdr_format(dev)) { 2403 /* We're over the deadline, but we keep support for old fw 2404 * until it turns out to be in major conflict with something new. */ 2405 b43warn(dev->wl, "You are using an old firmware image. " 2406 "Support for old firmware will be removed soon " 2407 "(official deadline was July 2008).\n"); 2408 b43_print_fw_helptext(dev->wl, 0); 2409 } 2410 2411 return 0; 2412 2413error: 2414 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2415 macctl &= ~B43_MACCTL_PSM_RUN; 2416 macctl |= B43_MACCTL_PSM_JMP0; 2417 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2418 2419 return err; 2420} 2421 2422static int b43_write_initvals(struct b43_wldev *dev, 2423 const struct b43_iv *ivals, 2424 size_t count, 2425 size_t array_size) 2426{ 2427 const struct b43_iv *iv; 2428 u16 offset; 2429 size_t i; 2430 bool bit32; 2431 2432 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 2433 iv = ivals; 2434 for (i = 0; i < count; i++) { 2435 if (array_size < sizeof(iv->offset_size)) 2436 goto err_format; 2437 array_size -= sizeof(iv->offset_size); 2438 offset = be16_to_cpu(iv->offset_size); 2439 bit32 = !!(offset & B43_IV_32BIT); 2440 offset &= B43_IV_OFFSET_MASK; 2441 if (offset >= 0x1000) 2442 goto err_format; 2443 if (bit32) { 2444 u32 value; 2445 2446 if (array_size < sizeof(iv->data.d32)) 2447 goto err_format; 2448 array_size -= sizeof(iv->data.d32); 2449 2450 value = get_unaligned_be32(&iv->data.d32); 2451 b43_write32(dev, offset, value); 2452 2453 iv = (const struct b43_iv *)((const uint8_t *)iv + 2454 sizeof(__be16) + 2455 sizeof(__be32)); 2456 } else { 2457 u16 value; 2458 2459 if (array_size < sizeof(iv->data.d16)) 2460 goto err_format; 2461 array_size -= sizeof(iv->data.d16); 2462 2463 value = be16_to_cpu(iv->data.d16); 2464 b43_write16(dev, offset, value); 2465 2466 iv = (const struct b43_iv *)((const uint8_t *)iv + 2467 sizeof(__be16) + 2468 sizeof(__be16)); 2469 } 2470 } 2471 if (array_size) 2472 goto err_format; 2473 2474 return 0; 2475 2476err_format: 2477 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 2478 b43_print_fw_helptext(dev->wl, 1); 2479 2480 return -EPROTO; 2481} 2482 2483static int b43_upload_initvals(struct b43_wldev *dev) 2484{ 2485 const size_t hdr_len = sizeof(struct b43_fw_header); 2486 const struct b43_fw_header *hdr; 2487 struct b43_firmware *fw = &dev->fw; 2488 const struct b43_iv *ivals; 2489 size_t count; 2490 int err; 2491 2492 hdr = (const struct b43_fw_header *)(fw->initvals.data->data); 2493 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); 2494 count = be32_to_cpu(hdr->size); 2495 err = b43_write_initvals(dev, ivals, count, 2496 fw->initvals.data->size - hdr_len); 2497 if (err) 2498 goto out; 2499 if (fw->initvals_band.data) { 2500 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); 2501 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); 2502 count = be32_to_cpu(hdr->size); 2503 err = b43_write_initvals(dev, ivals, count, 2504 fw->initvals_band.data->size - hdr_len); 2505 if (err) 2506 goto out; 2507 } 2508out: 2509 2510 return err; 2511} 2512 2513/* Initialize the GPIOs 2514 * http://bcm-specs.sipsolutions.net/GPIO 2515 */ 2516static int b43_gpio_init(struct b43_wldev *dev) 2517{ 2518 struct ssb_bus *bus = dev->dev->bus; 2519 struct ssb_device *gpiodev, *pcidev = NULL; 2520 u32 mask, set; 2521 2522 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2523 & ~B43_MACCTL_GPOUTSMSK); 2524 2525 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 2526 | 0x000F); 2527 2528 mask = 0x0000001F; 2529 set = 0x0000000F; 2530 if (dev->dev->bus->chip_id == 0x4301) { 2531 mask |= 0x0060; 2532 set |= 0x0060; 2533 } 2534 if (0 /* FIXME: conditional unknown */ ) { 2535 b43_write16(dev, B43_MMIO_GPIO_MASK, 2536 b43_read16(dev, B43_MMIO_GPIO_MASK) 2537 | 0x0100); 2538 mask |= 0x0180; 2539 set |= 0x0180; 2540 } 2541 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) { 2542 b43_write16(dev, B43_MMIO_GPIO_MASK, 2543 b43_read16(dev, B43_MMIO_GPIO_MASK) 2544 | 0x0200); 2545 mask |= 0x0200; 2546 set |= 0x0200; 2547 } 2548 if (dev->dev->id.revision >= 2) 2549 mask |= 0x0010; /* FIXME: This is redundant. */ 2550 2551#ifdef CONFIG_SSB_DRIVER_PCICORE 2552 pcidev = bus->pcicore.dev; 2553#endif 2554 gpiodev = bus->chipco.dev ? : pcidev; 2555 if (!gpiodev) 2556 return 0; 2557 ssb_write32(gpiodev, B43_GPIO_CONTROL, 2558 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2559 & mask) | set); 2560 2561 return 0; 2562} 2563 2564/* Turn off all GPIO stuff. Call this on module unload, for example. */ 2565static void b43_gpio_cleanup(struct b43_wldev *dev) 2566{ 2567 struct ssb_bus *bus = dev->dev->bus; 2568 struct ssb_device *gpiodev, *pcidev = NULL; 2569 2570#ifdef CONFIG_SSB_DRIVER_PCICORE 2571 pcidev = bus->pcicore.dev; 2572#endif 2573 gpiodev = bus->chipco.dev ? : pcidev; 2574 if (!gpiodev) 2575 return; 2576 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2577} 2578 2579/* http://bcm-specs.sipsolutions.net/EnableMac */ 2580void b43_mac_enable(struct b43_wldev *dev) 2581{ 2582 if (b43_debug(dev, B43_DBG_FIRMWARE)) { 2583 u16 fwstate; 2584 2585 fwstate = b43_shm_read16(dev, B43_SHM_SHARED, 2586 B43_SHM_SH_UCODESTAT); 2587 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) && 2588 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) { 2589 b43err(dev->wl, "b43_mac_enable(): The firmware " 2590 "should be suspended, but current state is %u\n", 2591 fwstate); 2592 } 2593 } 2594 2595 dev->mac_suspended--; 2596 B43_WARN_ON(dev->mac_suspended < 0); 2597 if (dev->mac_suspended == 0) { 2598 b43_write32(dev, B43_MMIO_MACCTL, 2599 b43_read32(dev, B43_MMIO_MACCTL) 2600 | B43_MACCTL_ENABLED); 2601 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2602 B43_IRQ_MAC_SUSPENDED); 2603 /* Commit writes */ 2604 b43_read32(dev, B43_MMIO_MACCTL); 2605 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2606 b43_power_saving_ctl_bits(dev, 0); 2607 } 2608} 2609 2610/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2611void b43_mac_suspend(struct b43_wldev *dev) 2612{ 2613 int i; 2614 u32 tmp; 2615 2616 might_sleep(); 2617 B43_WARN_ON(dev->mac_suspended < 0); 2618 2619 if (dev->mac_suspended == 0) { 2620 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2621 b43_write32(dev, B43_MMIO_MACCTL, 2622 b43_read32(dev, B43_MMIO_MACCTL) 2623 & ~B43_MACCTL_ENABLED); 2624 /* force pci to flush the write */ 2625 b43_read32(dev, B43_MMIO_MACCTL); 2626 for (i = 35; i; i--) { 2627 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2628 if (tmp & B43_IRQ_MAC_SUSPENDED) 2629 goto out; 2630 udelay(10); 2631 } 2632 /* Hm, it seems this will take some time. Use msleep(). */ 2633 for (i = 40; i; i--) { 2634 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2635 if (tmp & B43_IRQ_MAC_SUSPENDED) 2636 goto out; 2637 msleep(1); 2638 } 2639 b43err(dev->wl, "MAC suspend failed\n"); 2640 } 2641out: 2642 dev->mac_suspended++; 2643} 2644 2645static void b43_adjust_opmode(struct b43_wldev *dev) 2646{ 2647 struct b43_wl *wl = dev->wl; 2648 u32 ctl; 2649 u16 cfp_pretbtt; 2650 2651 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2652 /* Reset status to STA infrastructure mode. */ 2653 ctl &= ~B43_MACCTL_AP; 2654 ctl &= ~B43_MACCTL_KEEP_CTL; 2655 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2656 ctl &= ~B43_MACCTL_KEEP_BAD; 2657 ctl &= ~B43_MACCTL_PROMISC; 2658 ctl &= ~B43_MACCTL_BEACPROMISC; 2659 ctl |= B43_MACCTL_INFRA; 2660 2661 if (b43_is_mode(wl, NL80211_IFTYPE_AP) || 2662 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 2663 ctl |= B43_MACCTL_AP; 2664 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 2665 ctl &= ~B43_MACCTL_INFRA; 2666 2667 if (wl->filter_flags & FIF_CONTROL) 2668 ctl |= B43_MACCTL_KEEP_CTL; 2669 if (wl->filter_flags & FIF_FCSFAIL) 2670 ctl |= B43_MACCTL_KEEP_BAD; 2671 if (wl->filter_flags & FIF_PLCPFAIL) 2672 ctl |= B43_MACCTL_KEEP_BADPLCP; 2673 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2674 ctl |= B43_MACCTL_PROMISC; 2675 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2676 ctl |= B43_MACCTL_BEACPROMISC; 2677 2678 /* Workaround: On old hardware the HW-MAC-address-filter 2679 * doesn't work properly, so always run promisc in filter 2680 * it in software. */ 2681 if (dev->dev->id.revision <= 4) 2682 ctl |= B43_MACCTL_PROMISC; 2683 2684 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2685 2686 cfp_pretbtt = 2; 2687 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2688 if (dev->dev->bus->chip_id == 0x4306 && 2689 dev->dev->bus->chip_rev == 3) 2690 cfp_pretbtt = 100; 2691 else 2692 cfp_pretbtt = 50; 2693 } 2694 b43_write16(dev, 0x612, cfp_pretbtt); 2695 2696 /* FIXME: We don't currently implement the PMQ mechanism, 2697 * so always disable it. If we want to implement PMQ, 2698 * we need to enable it here (clear DISCPMQ) in AP mode. 2699 */ 2700 if (0 /* ctl & B43_MACCTL_AP */) { 2701 b43_write32(dev, B43_MMIO_MACCTL, 2702 b43_read32(dev, B43_MMIO_MACCTL) 2703 & ~B43_MACCTL_DISCPMQ); 2704 } else { 2705 b43_write32(dev, B43_MMIO_MACCTL, 2706 b43_read32(dev, B43_MMIO_MACCTL) 2707 | B43_MACCTL_DISCPMQ); 2708 } 2709} 2710 2711static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2712{ 2713 u16 offset; 2714 2715 if (is_ofdm) { 2716 offset = 0x480; 2717 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2718 } else { 2719 offset = 0x4C0; 2720 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2721 } 2722 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2723 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2724} 2725 2726static void b43_rate_memory_init(struct b43_wldev *dev) 2727{ 2728 switch (dev->phy.type) { 2729 case B43_PHYTYPE_A: 2730 case B43_PHYTYPE_G: 2731 case B43_PHYTYPE_N: 2732 case B43_PHYTYPE_LP: 2733 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2734 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2735 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2736 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2737 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2738 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2739 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2740 if (dev->phy.type == B43_PHYTYPE_A) 2741 break; 2742 /* fallthrough */ 2743 case B43_PHYTYPE_B: 2744 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2745 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2746 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2747 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2748 break; 2749 default: 2750 B43_WARN_ON(1); 2751 } 2752} 2753 2754/* Set the default values for the PHY TX Control Words. */ 2755static void b43_set_phytxctl_defaults(struct b43_wldev *dev) 2756{ 2757 u16 ctl = 0; 2758 2759 ctl |= B43_TXH_PHY_ENC_CCK; 2760 ctl |= B43_TXH_PHY_ANT01AUTO; 2761 ctl |= B43_TXH_PHY_TXPWR; 2762 2763 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 2764 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); 2765 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); 2766} 2767 2768/* Set the TX-Antenna for management frames sent by firmware. */ 2769static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2770{ 2771 u16 ant; 2772 u16 tmp; 2773 2774 ant = b43_antenna_to_phyctl(antenna); 2775 2776 /* For ACK/CTS */ 2777 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2778 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2779 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2780 /* For Probe Resposes */ 2781 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2782 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2783 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2784} 2785 2786/* This is the opposite of b43_chip_init() */ 2787static void b43_chip_exit(struct b43_wldev *dev) 2788{ 2789 b43_phy_exit(dev); 2790 b43_gpio_cleanup(dev); 2791 /* firmware is released later */ 2792} 2793 2794/* Initialize the chip 2795 * http://bcm-specs.sipsolutions.net/ChipInit 2796 */ 2797static int b43_chip_init(struct b43_wldev *dev) 2798{ 2799 struct b43_phy *phy = &dev->phy; 2800 int err; 2801 u32 value32, macctl; 2802 u16 value16; 2803 2804 /* Initialize the MAC control */ 2805 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; 2806 if (dev->phy.gmode) 2807 macctl |= B43_MACCTL_GMODE; 2808 macctl |= B43_MACCTL_INFRA; 2809 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2810 2811 err = b43_request_firmware(dev); 2812 if (err) 2813 goto out; 2814 err = b43_upload_microcode(dev); 2815 if (err) 2816 goto out; /* firmware is released later */ 2817 2818 err = b43_gpio_init(dev); 2819 if (err) 2820 goto out; /* firmware is released later */ 2821 2822 err = b43_upload_initvals(dev); 2823 if (err) 2824 goto err_gpio_clean; 2825 2826 /* Turn the Analog on and initialize the PHY. */ 2827 phy->ops->switch_analog(dev, 1); 2828 err = b43_phy_init(dev); 2829 if (err) 2830 goto err_gpio_clean; 2831 2832 /* Disable Interference Mitigation. */ 2833 if (phy->ops->interf_mitigation) 2834 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); 2835 2836 /* Select the antennae */ 2837 if (phy->ops->set_rx_antenna) 2838 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2839 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2840 2841 if (phy->type == B43_PHYTYPE_B) { 2842 value16 = b43_read16(dev, 0x005E); 2843 value16 |= 0x0004; 2844 b43_write16(dev, 0x005E, value16); 2845 } 2846 b43_write32(dev, 0x0100, 0x01000000); 2847 if (dev->dev->id.revision < 5) 2848 b43_write32(dev, 0x010C, 0x01000000); 2849 2850 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2851 & ~B43_MACCTL_INFRA); 2852 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2853 | B43_MACCTL_INFRA); 2854 2855 /* Probe Response Timeout value */ 2856 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2857 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2858 2859 /* Initially set the wireless operation mode. */ 2860 b43_adjust_opmode(dev); 2861 2862 if (dev->dev->id.revision < 3) { 2863 b43_write16(dev, 0x060E, 0x0000); 2864 b43_write16(dev, 0x0610, 0x8000); 2865 b43_write16(dev, 0x0604, 0x0000); 2866 b43_write16(dev, 0x0606, 0x0200); 2867 } else { 2868 b43_write32(dev, 0x0188, 0x80000000); 2869 b43_write32(dev, 0x018C, 0x02000000); 2870 } 2871 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2872 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2873 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2874 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2875 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2876 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2877 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2878 2879 value32 = ssb_read32(dev->dev, SSB_TMSLOW); 2880 value32 |= 0x00100000; 2881 ssb_write32(dev->dev, SSB_TMSLOW, value32); 2882 2883 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2884 dev->dev->bus->chipco.fast_pwrup_delay); 2885 2886 err = 0; 2887 b43dbg(dev->wl, "Chip initialized\n"); 2888out: 2889 return err; 2890 2891err_gpio_clean: 2892 b43_gpio_cleanup(dev); 2893 return err; 2894} 2895 2896static void b43_periodic_every60sec(struct b43_wldev *dev) 2897{ 2898 const struct b43_phy_operations *ops = dev->phy.ops; 2899 2900 if (ops->pwork_60sec) 2901 ops->pwork_60sec(dev); 2902 2903 /* Force check the TX power emission now. */ 2904 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME); 2905} 2906 2907static void b43_periodic_every30sec(struct b43_wldev *dev) 2908{ 2909 /* Update device statistics. */ 2910 b43_calculate_link_quality(dev); 2911} 2912 2913static void b43_periodic_every15sec(struct b43_wldev *dev) 2914{ 2915 struct b43_phy *phy = &dev->phy; 2916 u16 wdr; 2917 2918 if (dev->fw.opensource) { 2919 /* Check if the firmware is still alive. 2920 * It will reset the watchdog counter to 0 in its idle loop. */ 2921 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG); 2922 if (unlikely(wdr)) { 2923 b43err(dev->wl, "Firmware watchdog: The firmware died!\n"); 2924 b43_controller_restart(dev, "Firmware watchdog"); 2925 return; 2926 } else { 2927 b43_shm_write16(dev, B43_SHM_SCRATCH, 2928 B43_WATCHDOG_REG, 1); 2929 } 2930 } 2931 2932 if (phy->ops->pwork_15sec) 2933 phy->ops->pwork_15sec(dev); 2934 2935 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 2936 wmb(); 2937 2938#if B43_DEBUG 2939 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 2940 unsigned int i; 2941 2942 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n", 2943 dev->irq_count / 15, 2944 dev->tx_count / 15, 2945 dev->rx_count / 15); 2946 dev->irq_count = 0; 2947 dev->tx_count = 0; 2948 dev->rx_count = 0; 2949 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 2950 if (dev->irq_bit_count[i]) { 2951 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", 2952 dev->irq_bit_count[i] / 15, i, (1 << i)); 2953 dev->irq_bit_count[i] = 0; 2954 } 2955 } 2956 } 2957#endif 2958} 2959 2960static void do_periodic_work(struct b43_wldev *dev) 2961{ 2962 unsigned int state; 2963 2964 state = dev->periodic_state; 2965 if (state % 4 == 0) 2966 b43_periodic_every60sec(dev); 2967 if (state % 2 == 0) 2968 b43_periodic_every30sec(dev); 2969 b43_periodic_every15sec(dev); 2970} 2971 2972/* Periodic work locking policy: 2973 * The whole periodic work handler is protected by 2974 * wl->mutex. If another lock is needed somewhere in the 2975 * pwork callchain, it's aquired in-place, where it's needed. 2976 */ 2977static void b43_periodic_work_handler(struct work_struct *work) 2978{ 2979 struct b43_wldev *dev = container_of(work, struct b43_wldev, 2980 periodic_work.work); 2981 struct b43_wl *wl = dev->wl; 2982 unsigned long delay; 2983 2984 mutex_lock(&wl->mutex); 2985 2986 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 2987 goto out; 2988 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 2989 goto out_requeue; 2990 2991 do_periodic_work(dev); 2992 2993 dev->periodic_state++; 2994out_requeue: 2995 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 2996 delay = msecs_to_jiffies(50); 2997 else 2998 delay = round_jiffies_relative(HZ * 15); 2999 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); 3000out: 3001 mutex_unlock(&wl->mutex); 3002} 3003 3004static void b43_periodic_tasks_setup(struct b43_wldev *dev) 3005{ 3006 struct delayed_work *work = &dev->periodic_work; 3007 3008 dev->periodic_state = 0; 3009 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 3010 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); 3011} 3012 3013/* Check if communication with the device works correctly. */ 3014static int b43_validate_chipaccess(struct b43_wldev *dev) 3015{ 3016 u32 v, backup0, backup4; 3017 3018 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); 3019 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4); 3020 3021 /* Check for read/write and endianness problems. */ 3022 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 3023 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 3024 goto error; 3025 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 3026 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 3027 goto error; 3028 3029 /* Check if unaligned 32bit SHM_SHARED access works properly. 3030 * However, don't bail out on failure, because it's noncritical. */ 3031 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); 3032 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); 3033 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); 3034 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); 3035 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) 3036 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n"); 3037 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); 3038 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || 3039 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || 3040 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || 3041 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) 3042 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n"); 3043 3044 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); 3045 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); 3046 3047 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) { 3048 /* The 32bit register shadows the two 16bit registers 3049 * with update sideeffects. Validate this. */ 3050 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 3051 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 3052 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 3053 goto error; 3054 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 3055 goto error; 3056 } 3057 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 3058 3059 v = b43_read32(dev, B43_MMIO_MACCTL); 3060 v |= B43_MACCTL_GMODE; 3061 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 3062 goto error; 3063 3064 return 0; 3065error: 3066 b43err(dev->wl, "Failed to validate the chipaccess\n"); 3067 return -ENODEV; 3068} 3069 3070static void b43_security_init(struct b43_wldev *dev) 3071{ 3072 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 3073 /* KTP is a word address, but we address SHM bytewise. 3074 * So multiply by two. 3075 */ 3076 dev->ktp *= 2; 3077 /* Number of RCMTA address slots */ 3078 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS); 3079 /* Clear the key memory. */ 3080 b43_clear_keys(dev); 3081} 3082 3083#ifdef CONFIG_B43_HWRNG 3084static int b43_rng_read(struct hwrng *rng, u32 *data) 3085{ 3086 struct b43_wl *wl = (struct b43_wl *)rng->priv; 3087 struct b43_wldev *dev; 3088 int count = -ENODEV; 3089 3090 mutex_lock(&wl->mutex); 3091 dev = wl->current_dev; 3092 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) { 3093 *data = b43_read16(dev, B43_MMIO_RNG); 3094 count = sizeof(u16); 3095 } 3096 mutex_unlock(&wl->mutex); 3097 3098 return count; 3099} 3100#endif /* CONFIG_B43_HWRNG */ 3101 3102static void b43_rng_exit(struct b43_wl *wl) 3103{ 3104#ifdef CONFIG_B43_HWRNG 3105 if (wl->rng_initialized) 3106 hwrng_unregister(&wl->rng); 3107#endif /* CONFIG_B43_HWRNG */ 3108} 3109 3110static int b43_rng_init(struct b43_wl *wl) 3111{ 3112 int err = 0; 3113 3114#ifdef CONFIG_B43_HWRNG 3115 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 3116 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 3117 wl->rng.name = wl->rng_name; 3118 wl->rng.data_read = b43_rng_read; 3119 wl->rng.priv = (unsigned long)wl; 3120 wl->rng_initialized = 1; 3121 err = hwrng_register(&wl->rng); 3122 if (err) { 3123 wl->rng_initialized = 0; 3124 b43err(wl, "Failed to register the random " 3125 "number generator (%d)\n", err); 3126 } 3127#endif /* CONFIG_B43_HWRNG */ 3128 3129 return err; 3130} 3131 3132static void b43_tx_work(struct work_struct *work) 3133{ 3134 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work); 3135 struct b43_wldev *dev; 3136 struct sk_buff *skb; 3137 int err = 0; 3138 3139 mutex_lock(&wl->mutex); 3140 dev = wl->current_dev; 3141 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) { 3142 mutex_unlock(&wl->mutex); 3143 return; 3144 } 3145 3146 while (skb_queue_len(&wl->tx_queue)) { 3147 skb = skb_dequeue(&wl->tx_queue); 3148 3149 if (b43_using_pio_transfers(dev)) 3150 err = b43_pio_tx(dev, skb); 3151 else 3152 err = b43_dma_tx(dev, skb); 3153 if (unlikely(err)) 3154 dev_kfree_skb(skb); /* Drop it */ 3155 } 3156 3157#if B43_DEBUG 3158 dev->tx_count++; 3159#endif 3160 mutex_unlock(&wl->mutex); 3161} 3162 3163static int b43_op_tx(struct ieee80211_hw *hw, 3164 struct sk_buff *skb) 3165{ 3166 struct b43_wl *wl = hw_to_b43_wl(hw); 3167 3168 if (unlikely(skb->len < 2 + 2 + 6)) { 3169 /* Too short, this can't be a valid frame. */ 3170 dev_kfree_skb_any(skb); 3171 return NETDEV_TX_OK; 3172 } 3173 B43_WARN_ON(skb_shinfo(skb)->nr_frags); 3174 3175 skb_queue_tail(&wl->tx_queue, skb); 3176 ieee80211_queue_work(wl->hw, &wl->tx_work); 3177 3178 return NETDEV_TX_OK; 3179} 3180 3181static void b43_qos_params_upload(struct b43_wldev *dev, 3182 const struct ieee80211_tx_queue_params *p, 3183 u16 shm_offset) 3184{ 3185 u16 params[B43_NR_QOSPARAMS]; 3186 int bslots, tmp; 3187 unsigned int i; 3188 3189 if (!dev->qos_enabled) 3190 return; 3191 3192 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min; 3193 3194 memset(¶ms, 0, sizeof(params)); 3195 3196 params[B43_QOSPARAM_TXOP] = p->txop * 32; 3197 params[B43_QOSPARAM_CWMIN] = p->cw_min; 3198 params[B43_QOSPARAM_CWMAX] = p->cw_max; 3199 params[B43_QOSPARAM_CWCUR] = p->cw_min; 3200 params[B43_QOSPARAM_AIFS] = p->aifs; 3201 params[B43_QOSPARAM_BSLOTS] = bslots; 3202 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs; 3203 3204 for (i = 0; i < ARRAY_SIZE(params); i++) { 3205 if (i == B43_QOSPARAM_STATUS) { 3206 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 3207 shm_offset + (i * 2)); 3208 /* Mark the parameters as updated. */ 3209 tmp |= 0x100; 3210 b43_shm_write16(dev, B43_SHM_SHARED, 3211 shm_offset + (i * 2), 3212 tmp); 3213 } else { 3214 b43_shm_write16(dev, B43_SHM_SHARED, 3215 shm_offset + (i * 2), 3216 params[i]); 3217 } 3218 } 3219} 3220 3221/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */ 3222static const u16 b43_qos_shm_offsets[] = { 3223 /* [mac80211-queue-nr] = SHM_OFFSET, */ 3224 [0] = B43_QOS_VOICE, 3225 [1] = B43_QOS_VIDEO, 3226 [2] = B43_QOS_BESTEFFORT, 3227 [3] = B43_QOS_BACKGROUND, 3228}; 3229 3230/* Update all QOS parameters in hardware. */ 3231static void b43_qos_upload_all(struct b43_wldev *dev) 3232{ 3233 struct b43_wl *wl = dev->wl; 3234 struct b43_qos_params *params; 3235 unsigned int i; 3236 3237 if (!dev->qos_enabled) 3238 return; 3239 3240 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3241 ARRAY_SIZE(wl->qos_params)); 3242 3243 b43_mac_suspend(dev); 3244 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3245 params = &(wl->qos_params[i]); 3246 b43_qos_params_upload(dev, &(params->p), 3247 b43_qos_shm_offsets[i]); 3248 } 3249 b43_mac_enable(dev); 3250} 3251 3252static void b43_qos_clear(struct b43_wl *wl) 3253{ 3254 struct b43_qos_params *params; 3255 unsigned int i; 3256 3257 /* Initialize QoS parameters to sane defaults. */ 3258 3259 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3260 ARRAY_SIZE(wl->qos_params)); 3261 3262 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3263 params = &(wl->qos_params[i]); 3264 3265 switch (b43_qos_shm_offsets[i]) { 3266 case B43_QOS_VOICE: 3267 params->p.txop = 0; 3268 params->p.aifs = 2; 3269 params->p.cw_min = 0x0001; 3270 params->p.cw_max = 0x0001; 3271 break; 3272 case B43_QOS_VIDEO: 3273 params->p.txop = 0; 3274 params->p.aifs = 2; 3275 params->p.cw_min = 0x0001; 3276 params->p.cw_max = 0x0001; 3277 break; 3278 case B43_QOS_BESTEFFORT: 3279 params->p.txop = 0; 3280 params->p.aifs = 3; 3281 params->p.cw_min = 0x0001; 3282 params->p.cw_max = 0x03FF; 3283 break; 3284 case B43_QOS_BACKGROUND: 3285 params->p.txop = 0; 3286 params->p.aifs = 7; 3287 params->p.cw_min = 0x0001; 3288 params->p.cw_max = 0x03FF; 3289 break; 3290 default: 3291 B43_WARN_ON(1); 3292 } 3293 } 3294} 3295 3296/* Initialize the core's QOS capabilities */ 3297static void b43_qos_init(struct b43_wldev *dev) 3298{ 3299 if (!dev->qos_enabled) { 3300 /* Disable QOS support. */ 3301 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF); 3302 b43_write16(dev, B43_MMIO_IFSCTL, 3303 b43_read16(dev, B43_MMIO_IFSCTL) 3304 & ~B43_MMIO_IFSCTL_USE_EDCF); 3305 b43dbg(dev->wl, "QoS disabled\n"); 3306 return; 3307 } 3308 3309 /* Upload the current QOS parameters. */ 3310 b43_qos_upload_all(dev); 3311 3312 /* Enable QOS support. */ 3313 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); 3314 b43_write16(dev, B43_MMIO_IFSCTL, 3315 b43_read16(dev, B43_MMIO_IFSCTL) 3316 | B43_MMIO_IFSCTL_USE_EDCF); 3317 b43dbg(dev->wl, "QoS enabled\n"); 3318} 3319 3320static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue, 3321 const struct ieee80211_tx_queue_params *params) 3322{ 3323 struct b43_wl *wl = hw_to_b43_wl(hw); 3324 struct b43_wldev *dev; 3325 unsigned int queue = (unsigned int)_queue; 3326 int err = -ENODEV; 3327 3328 if (queue >= ARRAY_SIZE(wl->qos_params)) { 3329 /* Queue not available or don't support setting 3330 * params on this queue. Return success to not 3331 * confuse mac80211. */ 3332 return 0; 3333 } 3334 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3335 ARRAY_SIZE(wl->qos_params)); 3336 3337 mutex_lock(&wl->mutex); 3338 dev = wl->current_dev; 3339 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) 3340 goto out_unlock; 3341 3342 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params)); 3343 b43_mac_suspend(dev); 3344 b43_qos_params_upload(dev, &(wl->qos_params[queue].p), 3345 b43_qos_shm_offsets[queue]); 3346 b43_mac_enable(dev); 3347 err = 0; 3348 3349out_unlock: 3350 mutex_unlock(&wl->mutex); 3351 3352 return err; 3353} 3354 3355static int b43_op_get_tx_stats(struct ieee80211_hw *hw, 3356 struct ieee80211_tx_queue_stats *stats) 3357{ 3358 struct b43_wl *wl = hw_to_b43_wl(hw); 3359 struct b43_wldev *dev; 3360 int err = -ENODEV; 3361 3362 mutex_lock(&wl->mutex); 3363 dev = wl->current_dev; 3364 if (dev && b43_status(dev) >= B43_STAT_STARTED) { 3365 if (b43_using_pio_transfers(dev)) 3366 b43_pio_get_tx_stats(dev, stats); 3367 else 3368 b43_dma_get_tx_stats(dev, stats); 3369 err = 0; 3370 } 3371 mutex_unlock(&wl->mutex); 3372 3373 return err; 3374} 3375 3376static int b43_op_get_stats(struct ieee80211_hw *hw, 3377 struct ieee80211_low_level_stats *stats) 3378{ 3379 struct b43_wl *wl = hw_to_b43_wl(hw); 3380 3381 mutex_lock(&wl->mutex); 3382 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 3383 mutex_unlock(&wl->mutex); 3384 3385 return 0; 3386} 3387 3388static u64 b43_op_get_tsf(struct ieee80211_hw *hw) 3389{ 3390 struct b43_wl *wl = hw_to_b43_wl(hw); 3391 struct b43_wldev *dev; 3392 u64 tsf; 3393 3394 mutex_lock(&wl->mutex); 3395 dev = wl->current_dev; 3396 3397 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3398 b43_tsf_read(dev, &tsf); 3399 else 3400 tsf = 0; 3401 3402 mutex_unlock(&wl->mutex); 3403 3404 return tsf; 3405} 3406 3407static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3408{ 3409 struct b43_wl *wl = hw_to_b43_wl(hw); 3410 struct b43_wldev *dev; 3411 3412 mutex_lock(&wl->mutex); 3413 dev = wl->current_dev; 3414 3415 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3416 b43_tsf_write(dev, tsf); 3417 3418 mutex_unlock(&wl->mutex); 3419} 3420 3421static void b43_put_phy_into_reset(struct b43_wldev *dev) 3422{ 3423 struct ssb_device *sdev = dev->dev; 3424 u32 tmslow; 3425 3426 tmslow = ssb_read32(sdev, SSB_TMSLOW); 3427 tmslow &= ~B43_TMSLOW_GMODE; 3428 tmslow |= B43_TMSLOW_PHYRESET; 3429 tmslow |= SSB_TMSLOW_FGC; 3430 ssb_write32(sdev, SSB_TMSLOW, tmslow); 3431 msleep(1); 3432 3433 tmslow = ssb_read32(sdev, SSB_TMSLOW); 3434 tmslow &= ~SSB_TMSLOW_FGC; 3435 tmslow |= B43_TMSLOW_PHYRESET; 3436 ssb_write32(sdev, SSB_TMSLOW, tmslow); 3437 msleep(1); 3438} 3439 3440static const char *band_to_string(enum ieee80211_band band) 3441{ 3442 switch (band) { 3443 case IEEE80211_BAND_5GHZ: 3444 return "5"; 3445 case IEEE80211_BAND_2GHZ: 3446 return "2.4"; 3447 default: 3448 break; 3449 } 3450 B43_WARN_ON(1); 3451 return ""; 3452} 3453 3454/* Expects wl->mutex locked */ 3455static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan) 3456{ 3457 struct b43_wldev *up_dev = NULL; 3458 struct b43_wldev *down_dev; 3459 struct b43_wldev *d; 3460 int err; 3461 bool uninitialized_var(gmode); 3462 int prev_status; 3463 3464 /* Find a device and PHY which supports the band. */ 3465 list_for_each_entry(d, &wl->devlist, list) { 3466 switch (chan->band) { 3467 case IEEE80211_BAND_5GHZ: 3468 if (d->phy.supports_5ghz) { 3469 up_dev = d; 3470 gmode = 0; 3471 } 3472 break; 3473 case IEEE80211_BAND_2GHZ: 3474 if (d->phy.supports_2ghz) { 3475 up_dev = d; 3476 gmode = 1; 3477 } 3478 break; 3479 default: 3480 B43_WARN_ON(1); 3481 return -EINVAL; 3482 } 3483 if (up_dev) 3484 break; 3485 } 3486 if (!up_dev) { 3487 b43err(wl, "Could not find a device for %s-GHz band operation\n", 3488 band_to_string(chan->band)); 3489 return -ENODEV; 3490 } 3491 if ((up_dev == wl->current_dev) && 3492 (!!wl->current_dev->phy.gmode == !!gmode)) { 3493 /* This device is already running. */ 3494 return 0; 3495 } 3496 b43dbg(wl, "Switching to %s-GHz band\n", 3497 band_to_string(chan->band)); 3498 down_dev = wl->current_dev; 3499 3500 prev_status = b43_status(down_dev); 3501 /* Shutdown the currently running core. */ 3502 if (prev_status >= B43_STAT_STARTED) 3503 down_dev = b43_wireless_core_stop(down_dev); 3504 if (prev_status >= B43_STAT_INITIALIZED) 3505 b43_wireless_core_exit(down_dev); 3506 3507 if (down_dev != up_dev) { 3508 /* We switch to a different core, so we put PHY into 3509 * RESET on the old core. */ 3510 b43_put_phy_into_reset(down_dev); 3511 } 3512 3513 /* Now start the new core. */ 3514 up_dev->phy.gmode = gmode; 3515 if (prev_status >= B43_STAT_INITIALIZED) { 3516 err = b43_wireless_core_init(up_dev); 3517 if (err) { 3518 b43err(wl, "Fatal: Could not initialize device for " 3519 "selected %s-GHz band\n", 3520 band_to_string(chan->band)); 3521 goto init_failure; 3522 } 3523 } 3524 if (prev_status >= B43_STAT_STARTED) { 3525 err = b43_wireless_core_start(up_dev); 3526 if (err) { 3527 b43err(wl, "Fatal: Coult not start device for " 3528 "selected %s-GHz band\n", 3529 band_to_string(chan->band)); 3530 b43_wireless_core_exit(up_dev); 3531 goto init_failure; 3532 } 3533 } 3534 B43_WARN_ON(b43_status(up_dev) != prev_status); 3535 3536 wl->current_dev = up_dev; 3537 3538 return 0; 3539init_failure: 3540 /* Whoops, failed to init the new core. No core is operating now. */ 3541 wl->current_dev = NULL; 3542 return err; 3543} 3544 3545/* Write the short and long frame retry limit values. */ 3546static void b43_set_retry_limits(struct b43_wldev *dev, 3547 unsigned int short_retry, 3548 unsigned int long_retry) 3549{ 3550 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3551 * the chip-internal counter. */ 3552 short_retry = min(short_retry, (unsigned int)0xF); 3553 long_retry = min(long_retry, (unsigned int)0xF); 3554 3555 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3556 short_retry); 3557 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3558 long_retry); 3559} 3560 3561static int b43_op_config(struct ieee80211_hw *hw, u32 changed) 3562{ 3563 struct b43_wl *wl = hw_to_b43_wl(hw); 3564 struct b43_wldev *dev; 3565 struct b43_phy *phy; 3566 struct ieee80211_conf *conf = &hw->conf; 3567 int antenna; 3568 int err = 0; 3569 3570 mutex_lock(&wl->mutex); 3571 3572 /* Switch the band (if necessary). This might change the active core. */ 3573 err = b43_switch_band(wl, conf->channel); 3574 if (err) 3575 goto out_unlock_mutex; 3576 dev = wl->current_dev; 3577 phy = &dev->phy; 3578 3579 b43_mac_suspend(dev); 3580 3581 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 3582 b43_set_retry_limits(dev, conf->short_frame_max_tx_count, 3583 conf->long_frame_max_tx_count); 3584 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; 3585 if (!changed) 3586 goto out_mac_enable; 3587 3588 /* Switch to the requested channel. 3589 * The firmware takes care of races with the TX handler. */ 3590 if (conf->channel->hw_value != phy->channel) 3591 b43_switch_channel(dev, conf->channel->hw_value); 3592 3593 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 3594 3595 /* Adjust the desired TX power level. */ 3596 if (conf->power_level != 0) { 3597 if (conf->power_level != phy->desired_txpower) { 3598 phy->desired_txpower = conf->power_level; 3599 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME | 3600 B43_TXPWR_IGNORE_TSSI); 3601 } 3602 } 3603 3604 /* Antennas for RX and management frame TX. */ 3605 antenna = B43_ANTENNA_DEFAULT; 3606 b43_mgmtframe_txantenna(dev, antenna); 3607 antenna = B43_ANTENNA_DEFAULT; 3608 if (phy->ops->set_rx_antenna) 3609 phy->ops->set_rx_antenna(dev, antenna); 3610 3611 if (wl->radio_enabled != phy->radio_on) { 3612 if (wl->radio_enabled) { 3613 b43_software_rfkill(dev, false); 3614 b43info(dev->wl, "Radio turned on by software\n"); 3615 if (!dev->radio_hw_enable) { 3616 b43info(dev->wl, "The hardware RF-kill button " 3617 "still turns the radio physically off. " 3618 "Press the button to turn it on.\n"); 3619 } 3620 } else { 3621 b43_software_rfkill(dev, true); 3622 b43info(dev->wl, "Radio turned off by software\n"); 3623 } 3624 } 3625 3626out_mac_enable: 3627 b43_mac_enable(dev); 3628out_unlock_mutex: 3629 mutex_unlock(&wl->mutex); 3630 3631 return err; 3632} 3633 3634static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates) 3635{ 3636 struct ieee80211_supported_band *sband = 3637 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)]; 3638 struct ieee80211_rate *rate; 3639 int i; 3640 u16 basic, direct, offset, basic_offset, rateptr; 3641 3642 for (i = 0; i < sband->n_bitrates; i++) { 3643 rate = &sband->bitrates[i]; 3644 3645 if (b43_is_cck_rate(rate->hw_value)) { 3646 direct = B43_SHM_SH_CCKDIRECT; 3647 basic = B43_SHM_SH_CCKBASIC; 3648 offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3649 offset &= 0xF; 3650 } else { 3651 direct = B43_SHM_SH_OFDMDIRECT; 3652 basic = B43_SHM_SH_OFDMBASIC; 3653 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3654 offset &= 0xF; 3655 } 3656 3657 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); 3658 3659 if (b43_is_cck_rate(rate->hw_value)) { 3660 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3661 basic_offset &= 0xF; 3662 } else { 3663 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3664 basic_offset &= 0xF; 3665 } 3666 3667 /* 3668 * Get the pointer that we need to point to 3669 * from the direct map 3670 */ 3671 rateptr = b43_shm_read16(dev, B43_SHM_SHARED, 3672 direct + 2 * basic_offset); 3673 /* and write it to the basic map */ 3674 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset, 3675 rateptr); 3676 } 3677} 3678 3679static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 3680 struct ieee80211_vif *vif, 3681 struct ieee80211_bss_conf *conf, 3682 u32 changed) 3683{ 3684 struct b43_wl *wl = hw_to_b43_wl(hw); 3685 struct b43_wldev *dev; 3686 3687 mutex_lock(&wl->mutex); 3688 3689 dev = wl->current_dev; 3690 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3691 goto out_unlock_mutex; 3692 3693 B43_WARN_ON(wl->vif != vif); 3694 3695 if (changed & BSS_CHANGED_BSSID) { 3696 if (conf->bssid) 3697 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3698 else 3699 memset(wl->bssid, 0, ETH_ALEN); 3700 } 3701 3702 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3703 if (changed & BSS_CHANGED_BEACON && 3704 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3705 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3706 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3707 b43_update_templates(wl); 3708 3709 if (changed & BSS_CHANGED_BSSID) 3710 b43_write_mac_bssid_templates(dev); 3711 } 3712 3713 b43_mac_suspend(dev); 3714 3715 /* Update templates for AP/mesh mode. */ 3716 if (changed & BSS_CHANGED_BEACON_INT && 3717 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3718 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3719 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3720 b43_set_beacon_int(dev, conf->beacon_int); 3721 3722 if (changed & BSS_CHANGED_BASIC_RATES) 3723 b43_update_basic_rates(dev, conf->basic_rates); 3724 3725 if (changed & BSS_CHANGED_ERP_SLOT) { 3726 if (conf->use_short_slot) 3727 b43_short_slot_timing_enable(dev); 3728 else 3729 b43_short_slot_timing_disable(dev); 3730 } 3731 3732 b43_mac_enable(dev); 3733out_unlock_mutex: 3734 mutex_unlock(&wl->mutex); 3735} 3736 3737static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3738 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3739 struct ieee80211_key_conf *key) 3740{ 3741 struct b43_wl *wl = hw_to_b43_wl(hw); 3742 struct b43_wldev *dev; 3743 u8 algorithm; 3744 u8 index; 3745 int err; 3746 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3747 3748 if (modparam_nohwcrypt) 3749 return -ENOSPC; /* User disabled HW-crypto */ 3750 3751 mutex_lock(&wl->mutex); 3752 3753 dev = wl->current_dev; 3754 err = -ENODEV; 3755 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 3756 goto out_unlock; 3757 3758 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) { 3759 /* We don't have firmware for the crypto engine. 3760 * Must use software-crypto. */ 3761 err = -EOPNOTSUPP; 3762 goto out_unlock; 3763 } 3764 3765 err = -EINVAL; 3766 switch (key->alg) { 3767 case ALG_WEP: 3768 if (key->keylen == WLAN_KEY_LEN_WEP40) 3769 algorithm = B43_SEC_ALGO_WEP40; 3770 else 3771 algorithm = B43_SEC_ALGO_WEP104; 3772 break; 3773 case ALG_TKIP: 3774 algorithm = B43_SEC_ALGO_TKIP; 3775 break; 3776 case ALG_CCMP: 3777 algorithm = B43_SEC_ALGO_AES; 3778 break; 3779 default: 3780 B43_WARN_ON(1); 3781 goto out_unlock; 3782 } 3783 index = (u8) (key->keyidx); 3784 if (index > 3) 3785 goto out_unlock; 3786 3787 switch (cmd) { 3788 case SET_KEY: 3789 if (algorithm == B43_SEC_ALGO_TKIP && 3790 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) || 3791 !modparam_hwtkip)) { 3792 /* We support only pairwise key */ 3793 err = -EOPNOTSUPP; 3794 goto out_unlock; 3795 } 3796 3797 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 3798 if (WARN_ON(!sta)) { 3799 err = -EOPNOTSUPP; 3800 goto out_unlock; 3801 } 3802 /* Pairwise key with an assigned MAC address. */ 3803 err = b43_key_write(dev, -1, algorithm, 3804 key->key, key->keylen, 3805 sta->addr, key); 3806 } else { 3807 /* Group key */ 3808 err = b43_key_write(dev, index, algorithm, 3809 key->key, key->keylen, NULL, key); 3810 } 3811 if (err) 3812 goto out_unlock; 3813 3814 if (algorithm == B43_SEC_ALGO_WEP40 || 3815 algorithm == B43_SEC_ALGO_WEP104) { 3816 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 3817 } else { 3818 b43_hf_write(dev, 3819 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 3820 } 3821 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 3822 if (algorithm == B43_SEC_ALGO_TKIP) 3823 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 3824 break; 3825 case DISABLE_KEY: { 3826 err = b43_key_clear(dev, key->hw_key_idx); 3827 if (err) 3828 goto out_unlock; 3829 break; 3830 } 3831 default: 3832 B43_WARN_ON(1); 3833 } 3834 3835out_unlock: 3836 if (!err) { 3837 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 3838 "mac: %pM\n", 3839 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 3840 sta ? sta->addr : bcast_addr); 3841 b43_dump_keymemory(dev); 3842 } 3843 mutex_unlock(&wl->mutex); 3844 3845 return err; 3846} 3847 3848static void b43_op_configure_filter(struct ieee80211_hw *hw, 3849 unsigned int changed, unsigned int *fflags, 3850 u64 multicast) 3851{ 3852 struct b43_wl *wl = hw_to_b43_wl(hw); 3853 struct b43_wldev *dev; 3854 3855 mutex_lock(&wl->mutex); 3856 dev = wl->current_dev; 3857 if (!dev) { 3858 *fflags = 0; 3859 goto out_unlock; 3860 } 3861 3862 *fflags &= FIF_PROMISC_IN_BSS | 3863 FIF_ALLMULTI | 3864 FIF_FCSFAIL | 3865 FIF_PLCPFAIL | 3866 FIF_CONTROL | 3867 FIF_OTHER_BSS | 3868 FIF_BCN_PRBRESP_PROMISC; 3869 3870 changed &= FIF_PROMISC_IN_BSS | 3871 FIF_ALLMULTI | 3872 FIF_FCSFAIL | 3873 FIF_PLCPFAIL | 3874 FIF_CONTROL | 3875 FIF_OTHER_BSS | 3876 FIF_BCN_PRBRESP_PROMISC; 3877 3878 wl->filter_flags = *fflags; 3879 3880 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 3881 b43_adjust_opmode(dev); 3882 3883out_unlock: 3884 mutex_unlock(&wl->mutex); 3885} 3886 3887/* Locking: wl->mutex 3888 * Returns the current dev. This might be different from the passed in dev, 3889 * because the core might be gone away while we unlocked the mutex. */ 3890static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev) 3891{ 3892 struct b43_wl *wl = dev->wl; 3893 struct b43_wldev *orig_dev; 3894 u32 mask; 3895 3896redo: 3897 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3898 return dev; 3899 3900 /* Cancel work. Unlock to avoid deadlocks. */ 3901 mutex_unlock(&wl->mutex); 3902 cancel_delayed_work_sync(&dev->periodic_work); 3903 cancel_work_sync(&wl->tx_work); 3904 mutex_lock(&wl->mutex); 3905 dev = wl->current_dev; 3906 if (!dev || b43_status(dev) < B43_STAT_STARTED) { 3907 /* Whoops, aliens ate up the device while we were unlocked. */ 3908 return dev; 3909 } 3910 3911 /* Disable interrupts on the device. */ 3912 b43_set_status(dev, B43_STAT_INITIALIZED); 3913 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) { 3914 /* wl->mutex is locked. That is enough. */ 3915 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 3916 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 3917 } else { 3918 spin_lock_irq(&wl->hardirq_lock); 3919 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 3920 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 3921 spin_unlock_irq(&wl->hardirq_lock); 3922 } 3923 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ 3924 orig_dev = dev; 3925 mutex_unlock(&wl->mutex); 3926 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) { 3927 b43_sdio_free_irq(dev); 3928 } else { 3929 synchronize_irq(dev->dev->irq); 3930 free_irq(dev->dev->irq, dev); 3931 } 3932 mutex_lock(&wl->mutex); 3933 dev = wl->current_dev; 3934 if (!dev) 3935 return dev; 3936 if (dev != orig_dev) { 3937 if (b43_status(dev) >= B43_STAT_STARTED) 3938 goto redo; 3939 return dev; 3940 } 3941 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 3942 B43_WARN_ON(mask != 0xFFFFFFFF && mask); 3943 3944 /* Drain the TX queue */ 3945 while (skb_queue_len(&wl->tx_queue)) 3946 dev_kfree_skb(skb_dequeue(&wl->tx_queue)); 3947 3948 b43_mac_suspend(dev); 3949 b43_leds_exit(dev); 3950 b43dbg(wl, "Wireless interface stopped\n"); 3951 3952 return dev; 3953} 3954 3955/* Locking: wl->mutex */ 3956static int b43_wireless_core_start(struct b43_wldev *dev) 3957{ 3958 int err; 3959 3960 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 3961 3962 drain_txstatus_queue(dev); 3963 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) { 3964 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); 3965 if (err) { 3966 b43err(dev->wl, "Cannot request SDIO IRQ\n"); 3967 goto out; 3968 } 3969 } else { 3970 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler, 3971 b43_interrupt_thread_handler, 3972 IRQF_SHARED, KBUILD_MODNAME, dev); 3973 if (err) { 3974 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); 3975 goto out; 3976 } 3977 } 3978 3979 /* We are ready to run. */ 3980 b43_set_status(dev, B43_STAT_STARTED); 3981 3982 /* Start data flow (TX/RX). */ 3983 b43_mac_enable(dev); 3984 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 3985 3986 /* Start maintainance work */ 3987 b43_periodic_tasks_setup(dev); 3988 3989 b43_leds_init(dev); 3990 3991 b43dbg(dev->wl, "Wireless interface started\n"); 3992out: 3993 return err; 3994} 3995 3996/* Get PHY and RADIO versioning numbers */ 3997static int b43_phy_versioning(struct b43_wldev *dev) 3998{ 3999 struct b43_phy *phy = &dev->phy; 4000 u32 tmp; 4001 u8 analog_type; 4002 u8 phy_type; 4003 u8 phy_rev; 4004 u16 radio_manuf; 4005 u16 radio_ver; 4006 u16 radio_rev; 4007 int unsupported = 0; 4008 4009 /* Get PHY versioning */ 4010 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 4011 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 4012 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 4013 phy_rev = (tmp & B43_PHYVER_VERSION); 4014 switch (phy_type) { 4015 case B43_PHYTYPE_A: 4016 if (phy_rev >= 4) 4017 unsupported = 1; 4018 break; 4019 case B43_PHYTYPE_B: 4020 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 4021 && phy_rev != 7) 4022 unsupported = 1; 4023 break; 4024 case B43_PHYTYPE_G: 4025 if (phy_rev > 9) 4026 unsupported = 1; 4027 break; 4028#ifdef CONFIG_B43_NPHY 4029 case B43_PHYTYPE_N: 4030 if (phy_rev > 4) 4031 unsupported = 1; 4032 break; 4033#endif 4034#ifdef CONFIG_B43_PHY_LP 4035 case B43_PHYTYPE_LP: 4036 if (phy_rev > 2) 4037 unsupported = 1; 4038 break; 4039#endif 4040 default: 4041 unsupported = 1; 4042 }; 4043 if (unsupported) { 4044 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 4045 "(Analog %u, Type %u, Revision %u)\n", 4046 analog_type, phy_type, phy_rev); 4047 return -EOPNOTSUPP; 4048 } 4049 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 4050 analog_type, phy_type, phy_rev); 4051 4052 /* Get RADIO versioning */ 4053 if (dev->dev->bus->chip_id == 0x4317) { 4054 if (dev->dev->bus->chip_rev == 0) 4055 tmp = 0x3205017F; 4056 else if (dev->dev->bus->chip_rev == 1) 4057 tmp = 0x4205017F; 4058 else 4059 tmp = 0x5205017F; 4060 } else { 4061 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 4062 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 4063 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 4064 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; 4065 } 4066 radio_manuf = (tmp & 0x00000FFF); 4067 radio_ver = (tmp & 0x0FFFF000) >> 12; 4068 radio_rev = (tmp & 0xF0000000) >> 28; 4069 if (radio_manuf != 0x17F /* Broadcom */) 4070 unsupported = 1; 4071 switch (phy_type) { 4072 case B43_PHYTYPE_A: 4073 if (radio_ver != 0x2060) 4074 unsupported = 1; 4075 if (radio_rev != 1) 4076 unsupported = 1; 4077 if (radio_manuf != 0x17F) 4078 unsupported = 1; 4079 break; 4080 case B43_PHYTYPE_B: 4081 if ((radio_ver & 0xFFF0) != 0x2050) 4082 unsupported = 1; 4083 break; 4084 case B43_PHYTYPE_G: 4085 if (radio_ver != 0x2050) 4086 unsupported = 1; 4087 break; 4088 case B43_PHYTYPE_N: 4089 if (radio_ver != 0x2055 && radio_ver != 0x2056) 4090 unsupported = 1; 4091 break; 4092 case B43_PHYTYPE_LP: 4093 if (radio_ver != 0x2062 && radio_ver != 0x2063) 4094 unsupported = 1; 4095 break; 4096 default: 4097 B43_WARN_ON(1); 4098 } 4099 if (unsupported) { 4100 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 4101 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 4102 radio_manuf, radio_ver, radio_rev); 4103 return -EOPNOTSUPP; 4104 } 4105 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 4106 radio_manuf, radio_ver, radio_rev); 4107 4108 phy->radio_manuf = radio_manuf; 4109 phy->radio_ver = radio_ver; 4110 phy->radio_rev = radio_rev; 4111 4112 phy->analog = analog_type; 4113 phy->type = phy_type; 4114 phy->rev = phy_rev; 4115 4116 return 0; 4117} 4118 4119static void setup_struct_phy_for_init(struct b43_wldev *dev, 4120 struct b43_phy *phy) 4121{ 4122 phy->hardware_power_control = !!modparam_hwpctl; 4123 phy->next_txpwr_check_time = jiffies; 4124 /* PHY TX errors counter. */ 4125 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 4126 4127#if B43_DEBUG 4128 phy->phy_locked = 0; 4129 phy->radio_locked = 0; 4130#endif 4131} 4132 4133static void setup_struct_wldev_for_init(struct b43_wldev *dev) 4134{ 4135 dev->dfq_valid = 0; 4136 4137 /* Assume the radio is enabled. If it's not enabled, the state will 4138 * immediately get fixed on the first periodic work run. */ 4139 dev->radio_hw_enable = 1; 4140 4141 /* Stats */ 4142 memset(&dev->stats, 0, sizeof(dev->stats)); 4143 4144 setup_struct_phy_for_init(dev, &dev->phy); 4145 4146 /* IRQ related flags */ 4147 dev->irq_reason = 0; 4148 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 4149 dev->irq_mask = B43_IRQ_MASKTEMPLATE; 4150 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 4151 dev->irq_mask &= ~B43_IRQ_PHY_TXERR; 4152 4153 dev->mac_suspended = 1; 4154 4155 /* Noise calculation context */ 4156 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 4157} 4158 4159static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 4160{ 4161 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 4162 u64 hf; 4163 4164 if (!modparam_btcoex) 4165 return; 4166 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 4167 return; 4168 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 4169 return; 4170 4171 hf = b43_hf_read(dev); 4172 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 4173 hf |= B43_HF_BTCOEXALT; 4174 else 4175 hf |= B43_HF_BTCOEX; 4176 b43_hf_write(dev, hf); 4177} 4178 4179static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 4180{ 4181 if (!modparam_btcoex) 4182 return; 4183 //TODO 4184} 4185 4186static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 4187{ 4188#ifdef CONFIG_SSB_DRIVER_PCICORE 4189 struct ssb_bus *bus = dev->dev->bus; 4190 u32 tmp; 4191 4192 if (bus->pcicore.dev && 4193 bus->pcicore.dev->id.coreid == SSB_DEV_PCI && 4194 bus->pcicore.dev->id.revision <= 5) { 4195 /* IMCFGLO timeouts workaround. */ 4196 tmp = ssb_read32(dev->dev, SSB_IMCFGLO); 4197 switch (bus->bustype) { 4198 case SSB_BUSTYPE_PCI: 4199 case SSB_BUSTYPE_PCMCIA: 4200 tmp &= ~SSB_IMCFGLO_REQTO; 4201 tmp &= ~SSB_IMCFGLO_SERTO; 4202 tmp |= 0x32; 4203 break; 4204 case SSB_BUSTYPE_SSB: 4205 tmp &= ~SSB_IMCFGLO_REQTO; 4206 tmp &= ~SSB_IMCFGLO_SERTO; 4207 tmp |= 0x53; 4208 break; 4209 default: 4210 break; 4211 } 4212 ssb_write32(dev->dev, SSB_IMCFGLO, tmp); 4213 } 4214#endif /* CONFIG_SSB_DRIVER_PCICORE */ 4215} 4216 4217static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) 4218{ 4219 u16 pu_delay; 4220 4221 /* The time value is in microseconds. */ 4222 if (dev->phy.type == B43_PHYTYPE_A) 4223 pu_delay = 3700; 4224 else 4225 pu_delay = 1050; 4226 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) 4227 pu_delay = 500; 4228 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) 4229 pu_delay = max(pu_delay, (u16)2400); 4230 4231 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); 4232} 4233 4234/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ 4235static void b43_set_pretbtt(struct b43_wldev *dev) 4236{ 4237 u16 pretbtt; 4238 4239 /* The time value is in microseconds. */ 4240 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) { 4241 pretbtt = 2; 4242 } else { 4243 if (dev->phy.type == B43_PHYTYPE_A) 4244 pretbtt = 120; 4245 else 4246 pretbtt = 250; 4247 } 4248 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); 4249 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); 4250} 4251 4252/* Shutdown a wireless core */ 4253/* Locking: wl->mutex */ 4254static void b43_wireless_core_exit(struct b43_wldev *dev) 4255{ 4256 u32 macctl; 4257 4258 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED); 4259 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED) 4260 return; 4261 b43_set_status(dev, B43_STAT_UNINIT); 4262 4263 /* Stop the microcode PSM. */ 4264 macctl = b43_read32(dev, B43_MMIO_MACCTL); 4265 macctl &= ~B43_MACCTL_PSM_RUN; 4266 macctl |= B43_MACCTL_PSM_JMP0; 4267 b43_write32(dev, B43_MMIO_MACCTL, macctl); 4268 4269 b43_dma_free(dev); 4270 b43_pio_free(dev); 4271 b43_chip_exit(dev); 4272 dev->phy.ops->switch_analog(dev, 0); 4273 if (dev->wl->current_beacon) { 4274 dev_kfree_skb_any(dev->wl->current_beacon); 4275 dev->wl->current_beacon = NULL; 4276 } 4277 4278 ssb_device_disable(dev->dev, 0); 4279 ssb_bus_may_powerdown(dev->dev->bus); 4280} 4281 4282/* Initialize a wireless core */ 4283static int b43_wireless_core_init(struct b43_wldev *dev) 4284{ 4285 struct ssb_bus *bus = dev->dev->bus; 4286 struct ssb_sprom *sprom = &bus->sprom; 4287 struct b43_phy *phy = &dev->phy; 4288 int err; 4289 u64 hf; 4290 u32 tmp; 4291 4292 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4293 4294 err = ssb_bus_powerup(bus, 0); 4295 if (err) 4296 goto out; 4297 if (!ssb_device_is_enabled(dev->dev)) { 4298 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 4299 b43_wireless_core_reset(dev, tmp); 4300 } 4301 4302 /* Reset all data structures. */ 4303 setup_struct_wldev_for_init(dev); 4304 phy->ops->prepare_structs(dev); 4305 4306 /* Enable IRQ routing to this device. */ 4307 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 4308 4309 b43_imcfglo_timeouts_workaround(dev); 4310 b43_bluetooth_coext_disable(dev); 4311 if (phy->ops->prepare_hardware) { 4312 err = phy->ops->prepare_hardware(dev); 4313 if (err) 4314 goto err_busdown; 4315 } 4316 err = b43_chip_init(dev); 4317 if (err) 4318 goto err_busdown; 4319 b43_shm_write16(dev, B43_SHM_SHARED, 4320 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 4321 hf = b43_hf_read(dev); 4322 if (phy->type == B43_PHYTYPE_G) { 4323 hf |= B43_HF_SYMW; 4324 if (phy->rev == 1) 4325 hf |= B43_HF_GDCW; 4326 if (sprom->boardflags_lo & B43_BFL_PACTRL) 4327 hf |= B43_HF_OFDMPABOOST; 4328 } 4329 if (phy->radio_ver == 0x2050) { 4330 if (phy->radio_rev == 6) 4331 hf |= B43_HF_4318TSSI; 4332 if (phy->radio_rev < 6) 4333 hf |= B43_HF_VCORECALC; 4334 } 4335 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) 4336 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ 4337#ifdef CONFIG_SSB_DRIVER_PCICORE 4338 if ((bus->bustype == SSB_BUSTYPE_PCI) && 4339 (bus->pcicore.dev->id.revision <= 10)) 4340 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ 4341#endif 4342 hf &= ~B43_HF_SKCFPUP; 4343 b43_hf_write(dev, hf); 4344 4345 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 4346 B43_DEFAULT_LONG_RETRY_LIMIT); 4347 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 4348 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 4349 4350 /* Disable sending probe responses from firmware. 4351 * Setting the MaxTime to one usec will always trigger 4352 * a timeout, so we never send any probe resp. 4353 * A timeout of zero is infinite. */ 4354 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 4355 4356 b43_rate_memory_init(dev); 4357 b43_set_phytxctl_defaults(dev); 4358 4359 /* Minimum Contention Window */ 4360 if (phy->type == B43_PHYTYPE_B) { 4361 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 4362 } else { 4363 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 4364 } 4365 /* Maximum Contention Window */ 4366 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 4367 4368 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || 4369 (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) || 4370 modparam_pio) { 4371 dev->__using_pio_transfers = 1; 4372 err = b43_pio_init(dev); 4373 } else { 4374 dev->__using_pio_transfers = 0; 4375 err = b43_dma_init(dev); 4376 } 4377 if (err) 4378 goto err_chip_exit; 4379 b43_qos_init(dev); 4380 b43_set_synth_pu_delay(dev, 1); 4381 b43_bluetooth_coext_enable(dev); 4382 4383 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); 4384 b43_upload_card_macaddress(dev); 4385 b43_security_init(dev); 4386 4387 ieee80211_wake_queues(dev->wl->hw); 4388 4389 ieee80211_wake_queues(dev->wl->hw); 4390 4391 b43_set_status(dev, B43_STAT_INITIALIZED); 4392 4393out: 4394 return err; 4395 4396err_chip_exit: 4397 b43_chip_exit(dev); 4398err_busdown: 4399 ssb_bus_may_powerdown(bus); 4400 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4401 return err; 4402} 4403 4404static int b43_op_add_interface(struct ieee80211_hw *hw, 4405 struct ieee80211_vif *vif) 4406{ 4407 struct b43_wl *wl = hw_to_b43_wl(hw); 4408 struct b43_wldev *dev; 4409 int err = -EOPNOTSUPP; 4410 4411 /* TODO: allow WDS/AP devices to coexist */ 4412 4413 if (vif->type != NL80211_IFTYPE_AP && 4414 vif->type != NL80211_IFTYPE_MESH_POINT && 4415 vif->type != NL80211_IFTYPE_STATION && 4416 vif->type != NL80211_IFTYPE_WDS && 4417 vif->type != NL80211_IFTYPE_ADHOC) 4418 return -EOPNOTSUPP; 4419 4420 mutex_lock(&wl->mutex); 4421 if (wl->operating) 4422 goto out_mutex_unlock; 4423 4424 b43dbg(wl, "Adding Interface type %d\n", vif->type); 4425 4426 dev = wl->current_dev; 4427 wl->operating = 1; 4428 wl->vif = vif; 4429 wl->if_type = vif->type; 4430 memcpy(wl->mac_addr, vif->addr, ETH_ALEN); 4431 4432 b43_adjust_opmode(dev); 4433 b43_set_pretbtt(dev); 4434 b43_set_synth_pu_delay(dev, 0); 4435 b43_upload_card_macaddress(dev); 4436 4437 err = 0; 4438 out_mutex_unlock: 4439 mutex_unlock(&wl->mutex); 4440 4441 return err; 4442} 4443 4444static void b43_op_remove_interface(struct ieee80211_hw *hw, 4445 struct ieee80211_vif *vif) 4446{ 4447 struct b43_wl *wl = hw_to_b43_wl(hw); 4448 struct b43_wldev *dev = wl->current_dev; 4449 4450 b43dbg(wl, "Removing Interface type %d\n", vif->type); 4451 4452 mutex_lock(&wl->mutex); 4453 4454 B43_WARN_ON(!wl->operating); 4455 B43_WARN_ON(wl->vif != vif); 4456 wl->vif = NULL; 4457 4458 wl->operating = 0; 4459 4460 b43_adjust_opmode(dev); 4461 memset(wl->mac_addr, 0, ETH_ALEN); 4462 b43_upload_card_macaddress(dev); 4463 4464 mutex_unlock(&wl->mutex); 4465} 4466 4467static int b43_op_start(struct ieee80211_hw *hw) 4468{ 4469 struct b43_wl *wl = hw_to_b43_wl(hw); 4470 struct b43_wldev *dev = wl->current_dev; 4471 int did_init = 0; 4472 int err = 0; 4473 4474 /* Kill all old instance specific information to make sure 4475 * the card won't use it in the short timeframe between start 4476 * and mac80211 reconfiguring it. */ 4477 memset(wl->bssid, 0, ETH_ALEN); 4478 memset(wl->mac_addr, 0, ETH_ALEN); 4479 wl->filter_flags = 0; 4480 wl->radiotap_enabled = 0; 4481 b43_qos_clear(wl); 4482 wl->beacon0_uploaded = 0; 4483 wl->beacon1_uploaded = 0; 4484 wl->beacon_templates_virgin = 1; 4485 wl->radio_enabled = 1; 4486 4487 mutex_lock(&wl->mutex); 4488 4489 if (b43_status(dev) < B43_STAT_INITIALIZED) { 4490 err = b43_wireless_core_init(dev); 4491 if (err) 4492 goto out_mutex_unlock; 4493 did_init = 1; 4494 } 4495 4496 if (b43_status(dev) < B43_STAT_STARTED) { 4497 err = b43_wireless_core_start(dev); 4498 if (err) { 4499 if (did_init) 4500 b43_wireless_core_exit(dev); 4501 goto out_mutex_unlock; 4502 } 4503 } 4504 4505 /* XXX: only do if device doesn't support rfkill irq */ 4506 wiphy_rfkill_start_polling(hw->wiphy); 4507 4508 out_mutex_unlock: 4509 mutex_unlock(&wl->mutex); 4510 4511 return err; 4512} 4513 4514static void b43_op_stop(struct ieee80211_hw *hw) 4515{ 4516 struct b43_wl *wl = hw_to_b43_wl(hw); 4517 struct b43_wldev *dev = wl->current_dev; 4518 4519 cancel_work_sync(&(wl->beacon_update_trigger)); 4520 4521 mutex_lock(&wl->mutex); 4522 if (b43_status(dev) >= B43_STAT_STARTED) { 4523 dev = b43_wireless_core_stop(dev); 4524 if (!dev) 4525 goto out_unlock; 4526 } 4527 b43_wireless_core_exit(dev); 4528 wl->radio_enabled = 0; 4529 4530out_unlock: 4531 mutex_unlock(&wl->mutex); 4532 4533 cancel_work_sync(&(wl->txpower_adjust_work)); 4534} 4535 4536static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, 4537 struct ieee80211_sta *sta, bool set) 4538{ 4539 struct b43_wl *wl = hw_to_b43_wl(hw); 4540 4541 /* FIXME: add locking */ 4542 b43_update_templates(wl); 4543 4544 return 0; 4545} 4546 4547static void b43_op_sta_notify(struct ieee80211_hw *hw, 4548 struct ieee80211_vif *vif, 4549 enum sta_notify_cmd notify_cmd, 4550 struct ieee80211_sta *sta) 4551{ 4552 struct b43_wl *wl = hw_to_b43_wl(hw); 4553 4554 B43_WARN_ON(!vif || wl->vif != vif); 4555} 4556 4557static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw) 4558{ 4559 struct b43_wl *wl = hw_to_b43_wl(hw); 4560 struct b43_wldev *dev; 4561 4562 mutex_lock(&wl->mutex); 4563 dev = wl->current_dev; 4564 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4565 /* Disable CFP update during scan on other channels. */ 4566 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP); 4567 } 4568 mutex_unlock(&wl->mutex); 4569} 4570 4571static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw) 4572{ 4573 struct b43_wl *wl = hw_to_b43_wl(hw); 4574 struct b43_wldev *dev; 4575 4576 mutex_lock(&wl->mutex); 4577 dev = wl->current_dev; 4578 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4579 /* Re-enable CFP update. */ 4580 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP); 4581 } 4582 mutex_unlock(&wl->mutex); 4583} 4584 4585static const struct ieee80211_ops b43_hw_ops = { 4586 .tx = b43_op_tx, 4587 .conf_tx = b43_op_conf_tx, 4588 .add_interface = b43_op_add_interface, 4589 .remove_interface = b43_op_remove_interface, 4590 .config = b43_op_config, 4591 .bss_info_changed = b43_op_bss_info_changed, 4592 .configure_filter = b43_op_configure_filter, 4593 .set_key = b43_op_set_key, 4594 .update_tkip_key = b43_op_update_tkip_key, 4595 .get_stats = b43_op_get_stats, 4596 .get_tx_stats = b43_op_get_tx_stats, 4597 .get_tsf = b43_op_get_tsf, 4598 .set_tsf = b43_op_set_tsf, 4599 .start = b43_op_start, 4600 .stop = b43_op_stop, 4601 .set_tim = b43_op_beacon_set_tim, 4602 .sta_notify = b43_op_sta_notify, 4603 .sw_scan_start = b43_op_sw_scan_start_notifier, 4604 .sw_scan_complete = b43_op_sw_scan_complete_notifier, 4605 .rfkill_poll = b43_rfkill_poll, 4606}; 4607 4608/* Hard-reset the chip. Do not call this directly. 4609 * Use b43_controller_restart() 4610 */ 4611static void b43_chip_reset(struct work_struct *work) 4612{ 4613 struct b43_wldev *dev = 4614 container_of(work, struct b43_wldev, restart_work); 4615 struct b43_wl *wl = dev->wl; 4616 int err = 0; 4617 int prev_status; 4618 4619 mutex_lock(&wl->mutex); 4620 4621 prev_status = b43_status(dev); 4622 /* Bring the device down... */ 4623 if (prev_status >= B43_STAT_STARTED) { 4624 dev = b43_wireless_core_stop(dev); 4625 if (!dev) { 4626 err = -ENODEV; 4627 goto out; 4628 } 4629 } 4630 if (prev_status >= B43_STAT_INITIALIZED) 4631 b43_wireless_core_exit(dev); 4632 4633 /* ...and up again. */ 4634 if (prev_status >= B43_STAT_INITIALIZED) { 4635 err = b43_wireless_core_init(dev); 4636 if (err) 4637 goto out; 4638 } 4639 if (prev_status >= B43_STAT_STARTED) { 4640 err = b43_wireless_core_start(dev); 4641 if (err) { 4642 b43_wireless_core_exit(dev); 4643 goto out; 4644 } 4645 } 4646out: 4647 if (err) 4648 wl->current_dev = NULL; /* Failed to init the dev. */ 4649 mutex_unlock(&wl->mutex); 4650 if (err) 4651 b43err(wl, "Controller restart FAILED\n"); 4652 else 4653 b43info(wl, "Controller restarted\n"); 4654} 4655 4656static int b43_setup_bands(struct b43_wldev *dev, 4657 bool have_2ghz_phy, bool have_5ghz_phy) 4658{ 4659 struct ieee80211_hw *hw = dev->wl->hw; 4660 4661 if (have_2ghz_phy) 4662 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz; 4663 if (dev->phy.type == B43_PHYTYPE_N) { 4664 if (have_5ghz_phy) 4665 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy; 4666 } else { 4667 if (have_5ghz_phy) 4668 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy; 4669 } 4670 4671 dev->phy.supports_2ghz = have_2ghz_phy; 4672 dev->phy.supports_5ghz = have_5ghz_phy; 4673 4674 return 0; 4675} 4676 4677static void b43_wireless_core_detach(struct b43_wldev *dev) 4678{ 4679 /* We release firmware that late to not be required to re-request 4680 * is all the time when we reinit the core. */ 4681 b43_release_firmware(dev); 4682 b43_phy_free(dev); 4683} 4684 4685static int b43_wireless_core_attach(struct b43_wldev *dev) 4686{ 4687 struct b43_wl *wl = dev->wl; 4688 struct ssb_bus *bus = dev->dev->bus; 4689 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL; 4690 int err; 4691 bool have_2ghz_phy = 0, have_5ghz_phy = 0; 4692 u32 tmp; 4693 4694 /* Do NOT do any device initialization here. 4695 * Do it in wireless_core_init() instead. 4696 * This function is for gathering basic information about the HW, only. 4697 * Also some structs may be set up here. But most likely you want to have 4698 * that in core_init(), too. 4699 */ 4700 4701 err = ssb_bus_powerup(bus, 0); 4702 if (err) { 4703 b43err(wl, "Bus powerup failed\n"); 4704 goto out; 4705 } 4706 /* Get the PHY type. */ 4707 if (dev->dev->id.revision >= 5) { 4708 u32 tmshigh; 4709 4710 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 4711 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY); 4712 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY); 4713 } else 4714 B43_WARN_ON(1); 4715 4716 dev->phy.gmode = have_2ghz_phy; 4717 dev->phy.radio_on = 1; 4718 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 4719 b43_wireless_core_reset(dev, tmp); 4720 4721 err = b43_phy_versioning(dev); 4722 if (err) 4723 goto err_powerdown; 4724 /* Check if this device supports multiband. */ 4725 if (!pdev || 4726 (pdev->device != 0x4312 && 4727 pdev->device != 0x4319 && pdev->device != 0x4324)) { 4728 /* No multiband support. */ 4729 have_2ghz_phy = 0; 4730 have_5ghz_phy = 0; 4731 switch (dev->phy.type) { 4732 case B43_PHYTYPE_A: 4733 have_5ghz_phy = 1; 4734 break; 4735 case B43_PHYTYPE_LP: //FIXME not always! 4736#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference 4737 have_5ghz_phy = 1; 4738#endif 4739 case B43_PHYTYPE_G: 4740 case B43_PHYTYPE_N: 4741 have_2ghz_phy = 1; 4742 break; 4743 default: 4744 B43_WARN_ON(1); 4745 } 4746 } 4747 if (dev->phy.type == B43_PHYTYPE_A) { 4748 /* FIXME */ 4749 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 4750 err = -EOPNOTSUPP; 4751 goto err_powerdown; 4752 } 4753 if (1 /* disable A-PHY */) { 4754 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */ 4755 if (dev->phy.type != B43_PHYTYPE_N && 4756 dev->phy.type != B43_PHYTYPE_LP) { 4757 have_2ghz_phy = 1; 4758 have_5ghz_phy = 0; 4759 } 4760 } 4761 4762 err = b43_phy_allocate(dev); 4763 if (err) 4764 goto err_powerdown; 4765 4766 dev->phy.gmode = have_2ghz_phy; 4767 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 4768 b43_wireless_core_reset(dev, tmp); 4769 4770 err = b43_validate_chipaccess(dev); 4771 if (err) 4772 goto err_phy_free; 4773 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); 4774 if (err) 4775 goto err_phy_free; 4776 4777 /* Now set some default "current_dev" */ 4778 if (!wl->current_dev) 4779 wl->current_dev = dev; 4780 INIT_WORK(&dev->restart_work, b43_chip_reset); 4781 4782 dev->phy.ops->switch_analog(dev, 0); 4783 ssb_device_disable(dev->dev, 0); 4784 ssb_bus_may_powerdown(bus); 4785 4786out: 4787 return err; 4788 4789err_phy_free: 4790 b43_phy_free(dev); 4791err_powerdown: 4792 ssb_bus_may_powerdown(bus); 4793 return err; 4794} 4795 4796static void b43_one_core_detach(struct ssb_device *dev) 4797{ 4798 struct b43_wldev *wldev; 4799 struct b43_wl *wl; 4800 4801 /* Do not cancel ieee80211-workqueue based work here. 4802 * See comment in b43_remove(). */ 4803 4804 wldev = ssb_get_drvdata(dev); 4805 wl = wldev->wl; 4806 b43_debugfs_remove_device(wldev); 4807 b43_wireless_core_detach(wldev); 4808 list_del(&wldev->list); 4809 wl->nr_devs--; 4810 ssb_set_drvdata(dev, NULL); 4811 kfree(wldev); 4812} 4813 4814static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 4815{ 4816 struct b43_wldev *wldev; 4817 struct pci_dev *pdev; 4818 int err = -ENOMEM; 4819 4820 if (!list_empty(&wl->devlist)) { 4821 /* We are not the first core on this chip. */ 4822 pdev = (dev->bus->bustype == SSB_BUSTYPE_PCI) ? dev->bus->host_pci : NULL; 4823 /* Only special chips support more than one wireless 4824 * core, although some of the other chips have more than 4825 * one wireless core as well. Check for this and 4826 * bail out early. 4827 */ 4828 if (!pdev || 4829 ((pdev->device != 0x4321) && 4830 (pdev->device != 0x4313) && (pdev->device != 0x431A))) { 4831 b43dbg(wl, "Ignoring unconnected 802.11 core\n"); 4832 return -ENODEV; 4833 } 4834 } 4835 4836 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 4837 if (!wldev) 4838 goto out; 4839 4840 wldev->dev = dev; 4841 wldev->wl = wl; 4842 b43_set_status(wldev, B43_STAT_UNINIT); 4843 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 4844 INIT_LIST_HEAD(&wldev->list); 4845 4846 err = b43_wireless_core_attach(wldev); 4847 if (err) 4848 goto err_kfree_wldev; 4849 4850 list_add(&wldev->list, &wl->devlist); 4851 wl->nr_devs++; 4852 ssb_set_drvdata(dev, wldev); 4853 b43_debugfs_add_device(wldev); 4854 4855 out: 4856 return err; 4857 4858 err_kfree_wldev: 4859 kfree(wldev); 4860 return err; 4861} 4862 4863#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ 4864 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ 4865 (pdev->device == _device) && \ 4866 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ 4867 (pdev->subsystem_device == _subdevice) ) 4868 4869static void b43_sprom_fixup(struct ssb_bus *bus) 4870{ 4871 struct pci_dev *pdev; 4872 4873 /* boardflags workarounds */ 4874 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 4875 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 4876 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 4877 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 4878 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 4879 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 4880 if (bus->bustype == SSB_BUSTYPE_PCI) { 4881 pdev = bus->host_pci; 4882 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || 4883 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || 4884 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || 4885 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || 4886 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || 4887 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || 4888 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) 4889 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; 4890 } 4891} 4892 4893static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 4894{ 4895 struct ieee80211_hw *hw = wl->hw; 4896 4897 ssb_set_devtypedata(dev, NULL); 4898 ieee80211_free_hw(hw); 4899} 4900 4901static int b43_wireless_init(struct ssb_device *dev) 4902{ 4903 struct ssb_sprom *sprom = &dev->bus->sprom; 4904 struct ieee80211_hw *hw; 4905 struct b43_wl *wl; 4906 int err = -ENOMEM; 4907 4908 b43_sprom_fixup(dev->bus); 4909 4910 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 4911 if (!hw) { 4912 b43err(NULL, "Could not allocate ieee80211 device\n"); 4913 goto out; 4914 } 4915 wl = hw_to_b43_wl(hw); 4916 4917 /* fill hw info */ 4918 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 4919 IEEE80211_HW_SIGNAL_DBM | 4920 IEEE80211_HW_NOISE_DBM; 4921 4922 hw->wiphy->interface_modes = 4923 BIT(NL80211_IFTYPE_AP) | 4924 BIT(NL80211_IFTYPE_MESH_POINT) | 4925 BIT(NL80211_IFTYPE_STATION) | 4926 BIT(NL80211_IFTYPE_WDS) | 4927 BIT(NL80211_IFTYPE_ADHOC); 4928 4929 hw->queues = modparam_qos ? 4 : 1; 4930 wl->mac80211_initially_registered_queues = hw->queues; 4931 hw->max_rates = 2; 4932 SET_IEEE80211_DEV(hw, dev->dev); 4933 if (is_valid_ether_addr(sprom->et1mac)) 4934 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 4935 else 4936 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 4937 4938 /* Initialize struct b43_wl */ 4939 wl->hw = hw; 4940 mutex_init(&wl->mutex); 4941 spin_lock_init(&wl->hardirq_lock); 4942 INIT_LIST_HEAD(&wl->devlist); 4943 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); 4944 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work); 4945 INIT_WORK(&wl->tx_work, b43_tx_work); 4946 skb_queue_head_init(&wl->tx_queue); 4947 4948 ssb_set_devtypedata(dev, wl); 4949 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n", 4950 dev->bus->chip_id, dev->id.revision); 4951 err = 0; 4952out: 4953 return err; 4954} 4955 4956static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id) 4957{ 4958 struct b43_wl *wl; 4959 int err; 4960 int first = 0; 4961 4962 wl = ssb_get_devtypedata(dev); 4963 if (!wl) { 4964 /* Probing the first core. Must setup common struct b43_wl */ 4965 first = 1; 4966 err = b43_wireless_init(dev); 4967 if (err) 4968 goto out; 4969 wl = ssb_get_devtypedata(dev); 4970 B43_WARN_ON(!wl); 4971 } 4972 err = b43_one_core_attach(dev, wl); 4973 if (err) 4974 goto err_wireless_exit; 4975 4976 if (first) { 4977 err = ieee80211_register_hw(wl->hw); 4978 if (err) 4979 goto err_one_core_detach; 4980 b43_leds_register(wl->current_dev); 4981 b43_rng_init(wl); 4982 } 4983 4984 out: 4985 return err; 4986 4987 err_one_core_detach: 4988 b43_one_core_detach(dev); 4989 err_wireless_exit: 4990 if (first) 4991 b43_wireless_exit(dev, wl); 4992 return err; 4993} 4994 4995static void b43_remove(struct ssb_device *dev) 4996{ 4997 struct b43_wl *wl = ssb_get_devtypedata(dev); 4998 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4999 5000 /* We must cancel any work here before unregistering from ieee80211, 5001 * as the ieee80211 unreg will destroy the workqueue. */ 5002 cancel_work_sync(&wldev->restart_work); 5003 5004 B43_WARN_ON(!wl); 5005 if (wl->current_dev == wldev) { 5006 /* Restore the queues count before unregistering, because firmware detect 5007 * might have modified it. Restoring is important, so the networking 5008 * stack can properly free resources. */ 5009 wl->hw->queues = wl->mac80211_initially_registered_queues; 5010 b43_leds_stop(wldev); 5011 ieee80211_unregister_hw(wl->hw); 5012 } 5013 5014 b43_one_core_detach(dev); 5015 5016 if (list_empty(&wl->devlist)) { 5017 b43_rng_exit(wl); 5018 b43_leds_unregister(wl); 5019 /* Last core on the chip unregistered. 5020 * We can destroy common struct b43_wl. 5021 */ 5022 b43_wireless_exit(dev, wl); 5023 } 5024} 5025 5026/* Perform a hardware reset. This can be called from any context. */ 5027void b43_controller_restart(struct b43_wldev *dev, const char *reason) 5028{ 5029 /* Must avoid requeueing, if we are in shutdown. */ 5030 if (b43_status(dev) < B43_STAT_INITIALIZED) 5031 return; 5032 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 5033 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 5034} 5035 5036static struct ssb_driver b43_ssb_driver = { 5037 .name = KBUILD_MODNAME, 5038 .id_table = b43_ssb_tbl, 5039 .probe = b43_probe, 5040 .remove = b43_remove, 5041}; 5042 5043static void b43_print_driverinfo(void) 5044{ 5045 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", 5046 *feat_leds = "", *feat_sdio = ""; 5047 5048#ifdef CONFIG_B43_PCI_AUTOSELECT 5049 feat_pci = "P"; 5050#endif 5051#ifdef CONFIG_B43_PCMCIA 5052 feat_pcmcia = "M"; 5053#endif 5054#ifdef CONFIG_B43_NPHY 5055 feat_nphy = "N"; 5056#endif 5057#ifdef CONFIG_B43_LEDS 5058 feat_leds = "L"; 5059#endif 5060#ifdef CONFIG_B43_SDIO 5061 feat_sdio = "S"; 5062#endif 5063 printk(KERN_INFO "Broadcom 43xx driver loaded " 5064 "[ Features: %s%s%s%s%s, Firmware-ID: " 5065 B43_SUPPORTED_FIRMWARE_ID " ]\n", 5066 feat_pci, feat_pcmcia, feat_nphy, 5067 feat_leds, feat_sdio); 5068} 5069 5070static int __init b43_init(void) 5071{ 5072 int err; 5073 5074 b43_debugfs_init(); 5075 err = b43_pcmcia_init(); 5076 if (err) 5077 goto err_dfs_exit; 5078 err = b43_sdio_init(); 5079 if (err) 5080 goto err_pcmcia_exit; 5081 err = ssb_driver_register(&b43_ssb_driver); 5082 if (err) 5083 goto err_sdio_exit; 5084 b43_print_driverinfo(); 5085 5086 return err; 5087 5088err_sdio_exit: 5089 b43_sdio_exit(); 5090err_pcmcia_exit: 5091 b43_pcmcia_exit(); 5092err_dfs_exit: 5093 b43_debugfs_exit(); 5094 return err; 5095} 5096 5097static void __exit b43_exit(void) 5098{ 5099 ssb_driver_unregister(&b43_ssb_driver); 5100 b43_sdio_exit(); 5101 b43_pcmcia_exit(); 5102 b43_debugfs_exit(); 5103} 5104 5105module_init(b43_init) 5106module_exit(b43_exit) 5107