main.c revision e00cf3b9eb7839b952e434a75bff6b99e47337ac
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 SDIO support 12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> 13 14 Some parts of the code in this file are derived from the ipw2200 15 driver Copyright(c) 2003 - 2004 Intel Corporation. 16 17 This program is free software; you can redistribute it and/or modify 18 it under the terms of the GNU General Public License as published by 19 the Free Software Foundation; either version 2 of the License, or 20 (at your option) any later version. 21 22 This program is distributed in the hope that it will be useful, 23 but WITHOUT ANY WARRANTY; without even the implied warranty of 24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 GNU General Public License for more details. 26 27 You should have received a copy of the GNU General Public License 28 along with this program; see the file COPYING. If not, write to 29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 30 Boston, MA 02110-1301, USA. 31 32*/ 33 34#include <linux/delay.h> 35#include <linux/init.h> 36#include <linux/moduleparam.h> 37#include <linux/if_arp.h> 38#include <linux/etherdevice.h> 39#include <linux/firmware.h> 40#include <linux/wireless.h> 41#include <linux/workqueue.h> 42#include <linux/skbuff.h> 43#include <linux/io.h> 44#include <linux/dma-mapping.h> 45#include <linux/slab.h> 46#include <asm/unaligned.h> 47 48#include "b43.h" 49#include "main.h" 50#include "debugfs.h" 51#include "phy_common.h" 52#include "phy_g.h" 53#include "phy_n.h" 54#include "dma.h" 55#include "pio.h" 56#include "sysfs.h" 57#include "xmit.h" 58#include "lo.h" 59#include "pcmcia.h" 60#include "sdio.h" 61#include <linux/mmc/sdio_func.h> 62 63MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 64MODULE_AUTHOR("Martin Langer"); 65MODULE_AUTHOR("Stefano Brivio"); 66MODULE_AUTHOR("Michael Buesch"); 67MODULE_AUTHOR("Gábor Stefanik"); 68MODULE_LICENSE("GPL"); 69 70MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID); 71MODULE_FIRMWARE("b43/ucode11.fw"); 72MODULE_FIRMWARE("b43/ucode13.fw"); 73MODULE_FIRMWARE("b43/ucode14.fw"); 74MODULE_FIRMWARE("b43/ucode15.fw"); 75MODULE_FIRMWARE("b43/ucode16_mimo.fw"); 76MODULE_FIRMWARE("b43/ucode5.fw"); 77MODULE_FIRMWARE("b43/ucode9.fw"); 78 79static int modparam_bad_frames_preempt; 80module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 81MODULE_PARM_DESC(bad_frames_preempt, 82 "enable(1) / disable(0) Bad Frames Preemption"); 83 84static char modparam_fwpostfix[16]; 85module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 86MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 87 88static int modparam_hwpctl; 89module_param_named(hwpctl, modparam_hwpctl, int, 0444); 90MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 91 92static int modparam_nohwcrypt; 93module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 94MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 95 96static int modparam_hwtkip; 97module_param_named(hwtkip, modparam_hwtkip, int, 0444); 98MODULE_PARM_DESC(hwtkip, "Enable hardware tkip."); 99 100static int modparam_qos = 1; 101module_param_named(qos, modparam_qos, int, 0444); 102MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); 103 104static int modparam_btcoex = 1; 105module_param_named(btcoex, modparam_btcoex, int, 0444); 106MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)"); 107 108int b43_modparam_verbose = B43_VERBOSITY_DEFAULT; 109module_param_named(verbose, b43_modparam_verbose, int, 0644); 110MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug"); 111 112static int b43_modparam_pio = B43_PIO_DEFAULT; 113module_param_named(pio, b43_modparam_pio, int, 0644); 114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO"); 115 116static const struct ssb_device_id b43_ssb_tbl[] = { 117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 119 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 123 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12), 124 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 125 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15), 126 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), 127 SSB_DEVTABLE_END 128}; 129 130MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 131 132/* Channel and ratetables are shared for all devices. 133 * They can't be const, because ieee80211 puts some precalculated 134 * data in there. This data is the same for all devices, so we don't 135 * get concurrency issues */ 136#define RATETAB_ENT(_rateid, _flags) \ 137 { \ 138 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ 139 .hw_value = (_rateid), \ 140 .flags = (_flags), \ 141 } 142 143/* 144 * NOTE: When changing this, sync with xmit.c's 145 * b43_plcp_get_bitrate_idx_* functions! 146 */ 147static struct ieee80211_rate __b43_ratetable[] = { 148 RATETAB_ENT(B43_CCK_RATE_1MB, 0), 149 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), 150 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), 151 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), 152 RATETAB_ENT(B43_OFDM_RATE_6MB, 0), 153 RATETAB_ENT(B43_OFDM_RATE_9MB, 0), 154 RATETAB_ENT(B43_OFDM_RATE_12MB, 0), 155 RATETAB_ENT(B43_OFDM_RATE_18MB, 0), 156 RATETAB_ENT(B43_OFDM_RATE_24MB, 0), 157 RATETAB_ENT(B43_OFDM_RATE_36MB, 0), 158 RATETAB_ENT(B43_OFDM_RATE_48MB, 0), 159 RATETAB_ENT(B43_OFDM_RATE_54MB, 0), 160}; 161 162#define b43_a_ratetable (__b43_ratetable + 4) 163#define b43_a_ratetable_size 8 164#define b43_b_ratetable (__b43_ratetable + 0) 165#define b43_b_ratetable_size 4 166#define b43_g_ratetable (__b43_ratetable + 0) 167#define b43_g_ratetable_size 12 168 169#define CHAN4G(_channel, _freq, _flags) { \ 170 .band = IEEE80211_BAND_2GHZ, \ 171 .center_freq = (_freq), \ 172 .hw_value = (_channel), \ 173 .flags = (_flags), \ 174 .max_antenna_gain = 0, \ 175 .max_power = 30, \ 176} 177static struct ieee80211_channel b43_2ghz_chantable[] = { 178 CHAN4G(1, 2412, 0), 179 CHAN4G(2, 2417, 0), 180 CHAN4G(3, 2422, 0), 181 CHAN4G(4, 2427, 0), 182 CHAN4G(5, 2432, 0), 183 CHAN4G(6, 2437, 0), 184 CHAN4G(7, 2442, 0), 185 CHAN4G(8, 2447, 0), 186 CHAN4G(9, 2452, 0), 187 CHAN4G(10, 2457, 0), 188 CHAN4G(11, 2462, 0), 189 CHAN4G(12, 2467, 0), 190 CHAN4G(13, 2472, 0), 191 CHAN4G(14, 2484, 0), 192}; 193#undef CHAN4G 194 195#define CHAN5G(_channel, _flags) { \ 196 .band = IEEE80211_BAND_5GHZ, \ 197 .center_freq = 5000 + (5 * (_channel)), \ 198 .hw_value = (_channel), \ 199 .flags = (_flags), \ 200 .max_antenna_gain = 0, \ 201 .max_power = 30, \ 202} 203static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { 204 CHAN5G(32, 0), CHAN5G(34, 0), 205 CHAN5G(36, 0), CHAN5G(38, 0), 206 CHAN5G(40, 0), CHAN5G(42, 0), 207 CHAN5G(44, 0), CHAN5G(46, 0), 208 CHAN5G(48, 0), CHAN5G(50, 0), 209 CHAN5G(52, 0), CHAN5G(54, 0), 210 CHAN5G(56, 0), CHAN5G(58, 0), 211 CHAN5G(60, 0), CHAN5G(62, 0), 212 CHAN5G(64, 0), CHAN5G(66, 0), 213 CHAN5G(68, 0), CHAN5G(70, 0), 214 CHAN5G(72, 0), CHAN5G(74, 0), 215 CHAN5G(76, 0), CHAN5G(78, 0), 216 CHAN5G(80, 0), CHAN5G(82, 0), 217 CHAN5G(84, 0), CHAN5G(86, 0), 218 CHAN5G(88, 0), CHAN5G(90, 0), 219 CHAN5G(92, 0), CHAN5G(94, 0), 220 CHAN5G(96, 0), CHAN5G(98, 0), 221 CHAN5G(100, 0), CHAN5G(102, 0), 222 CHAN5G(104, 0), CHAN5G(106, 0), 223 CHAN5G(108, 0), CHAN5G(110, 0), 224 CHAN5G(112, 0), CHAN5G(114, 0), 225 CHAN5G(116, 0), CHAN5G(118, 0), 226 CHAN5G(120, 0), CHAN5G(122, 0), 227 CHAN5G(124, 0), CHAN5G(126, 0), 228 CHAN5G(128, 0), CHAN5G(130, 0), 229 CHAN5G(132, 0), CHAN5G(134, 0), 230 CHAN5G(136, 0), CHAN5G(138, 0), 231 CHAN5G(140, 0), CHAN5G(142, 0), 232 CHAN5G(144, 0), CHAN5G(145, 0), 233 CHAN5G(146, 0), CHAN5G(147, 0), 234 CHAN5G(148, 0), CHAN5G(149, 0), 235 CHAN5G(150, 0), CHAN5G(151, 0), 236 CHAN5G(152, 0), CHAN5G(153, 0), 237 CHAN5G(154, 0), CHAN5G(155, 0), 238 CHAN5G(156, 0), CHAN5G(157, 0), 239 CHAN5G(158, 0), CHAN5G(159, 0), 240 CHAN5G(160, 0), CHAN5G(161, 0), 241 CHAN5G(162, 0), CHAN5G(163, 0), 242 CHAN5G(164, 0), CHAN5G(165, 0), 243 CHAN5G(166, 0), CHAN5G(168, 0), 244 CHAN5G(170, 0), CHAN5G(172, 0), 245 CHAN5G(174, 0), CHAN5G(176, 0), 246 CHAN5G(178, 0), CHAN5G(180, 0), 247 CHAN5G(182, 0), CHAN5G(184, 0), 248 CHAN5G(186, 0), CHAN5G(188, 0), 249 CHAN5G(190, 0), CHAN5G(192, 0), 250 CHAN5G(194, 0), CHAN5G(196, 0), 251 CHAN5G(198, 0), CHAN5G(200, 0), 252 CHAN5G(202, 0), CHAN5G(204, 0), 253 CHAN5G(206, 0), CHAN5G(208, 0), 254 CHAN5G(210, 0), CHAN5G(212, 0), 255 CHAN5G(214, 0), CHAN5G(216, 0), 256 CHAN5G(218, 0), CHAN5G(220, 0), 257 CHAN5G(222, 0), CHAN5G(224, 0), 258 CHAN5G(226, 0), CHAN5G(228, 0), 259}; 260 261static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { 262 CHAN5G(34, 0), CHAN5G(36, 0), 263 CHAN5G(38, 0), CHAN5G(40, 0), 264 CHAN5G(42, 0), CHAN5G(44, 0), 265 CHAN5G(46, 0), CHAN5G(48, 0), 266 CHAN5G(52, 0), CHAN5G(56, 0), 267 CHAN5G(60, 0), CHAN5G(64, 0), 268 CHAN5G(100, 0), CHAN5G(104, 0), 269 CHAN5G(108, 0), CHAN5G(112, 0), 270 CHAN5G(116, 0), CHAN5G(120, 0), 271 CHAN5G(124, 0), CHAN5G(128, 0), 272 CHAN5G(132, 0), CHAN5G(136, 0), 273 CHAN5G(140, 0), CHAN5G(149, 0), 274 CHAN5G(153, 0), CHAN5G(157, 0), 275 CHAN5G(161, 0), CHAN5G(165, 0), 276 CHAN5G(184, 0), CHAN5G(188, 0), 277 CHAN5G(192, 0), CHAN5G(196, 0), 278 CHAN5G(200, 0), CHAN5G(204, 0), 279 CHAN5G(208, 0), CHAN5G(212, 0), 280 CHAN5G(216, 0), 281}; 282#undef CHAN5G 283 284static struct ieee80211_supported_band b43_band_5GHz_nphy = { 285 .band = IEEE80211_BAND_5GHZ, 286 .channels = b43_5ghz_nphy_chantable, 287 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), 288 .bitrates = b43_a_ratetable, 289 .n_bitrates = b43_a_ratetable_size, 290}; 291 292static struct ieee80211_supported_band b43_band_5GHz_aphy = { 293 .band = IEEE80211_BAND_5GHZ, 294 .channels = b43_5ghz_aphy_chantable, 295 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), 296 .bitrates = b43_a_ratetable, 297 .n_bitrates = b43_a_ratetable_size, 298}; 299 300static struct ieee80211_supported_band b43_band_2GHz = { 301 .band = IEEE80211_BAND_2GHZ, 302 .channels = b43_2ghz_chantable, 303 .n_channels = ARRAY_SIZE(b43_2ghz_chantable), 304 .bitrates = b43_g_ratetable, 305 .n_bitrates = b43_g_ratetable_size, 306}; 307 308static void b43_wireless_core_exit(struct b43_wldev *dev); 309static int b43_wireless_core_init(struct b43_wldev *dev); 310static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev); 311static int b43_wireless_core_start(struct b43_wldev *dev); 312 313static int b43_ratelimit(struct b43_wl *wl) 314{ 315 if (!wl || !wl->current_dev) 316 return 1; 317 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 318 return 1; 319 /* We are up and running. 320 * Ratelimit the messages to avoid DoS over the net. */ 321 return net_ratelimit(); 322} 323 324void b43info(struct b43_wl *wl, const char *fmt, ...) 325{ 326 struct va_format vaf; 327 va_list args; 328 329 if (b43_modparam_verbose < B43_VERBOSITY_INFO) 330 return; 331 if (!b43_ratelimit(wl)) 332 return; 333 334 va_start(args, fmt); 335 336 vaf.fmt = fmt; 337 vaf.va = &args; 338 339 printk(KERN_INFO "b43-%s: %pV", 340 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 341 342 va_end(args); 343} 344 345void b43err(struct b43_wl *wl, const char *fmt, ...) 346{ 347 struct va_format vaf; 348 va_list args; 349 350 if (b43_modparam_verbose < B43_VERBOSITY_ERROR) 351 return; 352 if (!b43_ratelimit(wl)) 353 return; 354 355 va_start(args, fmt); 356 357 vaf.fmt = fmt; 358 vaf.va = &args; 359 360 printk(KERN_ERR "b43-%s ERROR: %pV", 361 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 362 363 va_end(args); 364} 365 366void b43warn(struct b43_wl *wl, const char *fmt, ...) 367{ 368 struct va_format vaf; 369 va_list args; 370 371 if (b43_modparam_verbose < B43_VERBOSITY_WARN) 372 return; 373 if (!b43_ratelimit(wl)) 374 return; 375 376 va_start(args, fmt); 377 378 vaf.fmt = fmt; 379 vaf.va = &args; 380 381 printk(KERN_WARNING "b43-%s warning: %pV", 382 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 383 384 va_end(args); 385} 386 387void b43dbg(struct b43_wl *wl, const char *fmt, ...) 388{ 389 struct va_format vaf; 390 va_list args; 391 392 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 393 return; 394 395 va_start(args, fmt); 396 397 vaf.fmt = fmt; 398 vaf.va = &args; 399 400 printk(KERN_DEBUG "b43-%s debug: %pV", 401 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 402 403 va_end(args); 404} 405 406static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 407{ 408 u32 macctl; 409 410 B43_WARN_ON(offset % 4 != 0); 411 412 macctl = b43_read32(dev, B43_MMIO_MACCTL); 413 if (macctl & B43_MACCTL_BE) 414 val = swab32(val); 415 416 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 417 mmiowb(); 418 b43_write32(dev, B43_MMIO_RAM_DATA, val); 419} 420 421static inline void b43_shm_control_word(struct b43_wldev *dev, 422 u16 routing, u16 offset) 423{ 424 u32 control; 425 426 /* "offset" is the WORD offset. */ 427 control = routing; 428 control <<= 16; 429 control |= offset; 430 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 431} 432 433u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 434{ 435 u32 ret; 436 437 if (routing == B43_SHM_SHARED) { 438 B43_WARN_ON(offset & 0x0001); 439 if (offset & 0x0003) { 440 /* Unaligned access */ 441 b43_shm_control_word(dev, routing, offset >> 2); 442 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 443 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 444 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16; 445 446 goto out; 447 } 448 offset >>= 2; 449 } 450 b43_shm_control_word(dev, routing, offset); 451 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 452out: 453 return ret; 454} 455 456u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset) 457{ 458 u16 ret; 459 460 if (routing == B43_SHM_SHARED) { 461 B43_WARN_ON(offset & 0x0001); 462 if (offset & 0x0003) { 463 /* Unaligned access */ 464 b43_shm_control_word(dev, routing, offset >> 2); 465 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 466 467 goto out; 468 } 469 offset >>= 2; 470 } 471 b43_shm_control_word(dev, routing, offset); 472 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 473out: 474 return ret; 475} 476 477void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 478{ 479 if (routing == B43_SHM_SHARED) { 480 B43_WARN_ON(offset & 0x0001); 481 if (offset & 0x0003) { 482 /* Unaligned access */ 483 b43_shm_control_word(dev, routing, offset >> 2); 484 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 485 value & 0xFFFF); 486 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 487 b43_write16(dev, B43_MMIO_SHM_DATA, 488 (value >> 16) & 0xFFFF); 489 return; 490 } 491 offset >>= 2; 492 } 493 b43_shm_control_word(dev, routing, offset); 494 b43_write32(dev, B43_MMIO_SHM_DATA, value); 495} 496 497void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 498{ 499 if (routing == B43_SHM_SHARED) { 500 B43_WARN_ON(offset & 0x0001); 501 if (offset & 0x0003) { 502 /* Unaligned access */ 503 b43_shm_control_word(dev, routing, offset >> 2); 504 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 505 return; 506 } 507 offset >>= 2; 508 } 509 b43_shm_control_word(dev, routing, offset); 510 b43_write16(dev, B43_MMIO_SHM_DATA, value); 511} 512 513/* Read HostFlags */ 514u64 b43_hf_read(struct b43_wldev *dev) 515{ 516 u64 ret; 517 518 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 519 ret <<= 16; 520 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI); 521 ret <<= 16; 522 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 523 524 return ret; 525} 526 527/* Write HostFlags */ 528void b43_hf_write(struct b43_wldev *dev, u64 value) 529{ 530 u16 lo, mi, hi; 531 532 lo = (value & 0x00000000FFFFULL); 533 mi = (value & 0x0000FFFF0000ULL) >> 16; 534 hi = (value & 0xFFFF00000000ULL) >> 32; 535 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo); 536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi); 537 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi); 538} 539 540/* Read the firmware capabilities bitmask (Opensource firmware only) */ 541static u16 b43_fwcapa_read(struct b43_wldev *dev) 542{ 543 B43_WARN_ON(!dev->fw.opensource); 544 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA); 545} 546 547void b43_tsf_read(struct b43_wldev *dev, u64 *tsf) 548{ 549 u32 low, high; 550 551 B43_WARN_ON(dev->dev->id.revision < 3); 552 553 /* The hardware guarantees us an atomic read, if we 554 * read the low register first. */ 555 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 556 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 557 558 *tsf = high; 559 *tsf <<= 32; 560 *tsf |= low; 561} 562 563static void b43_time_lock(struct b43_wldev *dev) 564{ 565 u32 macctl; 566 567 macctl = b43_read32(dev, B43_MMIO_MACCTL); 568 macctl |= B43_MACCTL_TBTTHOLD; 569 b43_write32(dev, B43_MMIO_MACCTL, macctl); 570 /* Commit the write */ 571 b43_read32(dev, B43_MMIO_MACCTL); 572} 573 574static void b43_time_unlock(struct b43_wldev *dev) 575{ 576 u32 macctl; 577 578 macctl = b43_read32(dev, B43_MMIO_MACCTL); 579 macctl &= ~B43_MACCTL_TBTTHOLD; 580 b43_write32(dev, B43_MMIO_MACCTL, macctl); 581 /* Commit the write */ 582 b43_read32(dev, B43_MMIO_MACCTL); 583} 584 585static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 586{ 587 u32 low, high; 588 589 B43_WARN_ON(dev->dev->id.revision < 3); 590 591 low = tsf; 592 high = (tsf >> 32); 593 /* The hardware guarantees us an atomic write, if we 594 * write the low register first. */ 595 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low); 596 mmiowb(); 597 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high); 598 mmiowb(); 599} 600 601void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 602{ 603 b43_time_lock(dev); 604 b43_tsf_write_locked(dev, tsf); 605 b43_time_unlock(dev); 606} 607 608static 609void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac) 610{ 611 static const u8 zero_addr[ETH_ALEN] = { 0 }; 612 u16 data; 613 614 if (!mac) 615 mac = zero_addr; 616 617 offset |= 0x0020; 618 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 619 620 data = mac[0]; 621 data |= mac[1] << 8; 622 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 623 data = mac[2]; 624 data |= mac[3] << 8; 625 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 626 data = mac[4]; 627 data |= mac[5] << 8; 628 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 629} 630 631static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 632{ 633 const u8 *mac; 634 const u8 *bssid; 635 u8 mac_bssid[ETH_ALEN * 2]; 636 int i; 637 u32 tmp; 638 639 bssid = dev->wl->bssid; 640 mac = dev->wl->mac_addr; 641 642 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 643 644 memcpy(mac_bssid, mac, ETH_ALEN); 645 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 646 647 /* Write our MAC address and BSSID to template ram */ 648 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 649 tmp = (u32) (mac_bssid[i + 0]); 650 tmp |= (u32) (mac_bssid[i + 1]) << 8; 651 tmp |= (u32) (mac_bssid[i + 2]) << 16; 652 tmp |= (u32) (mac_bssid[i + 3]) << 24; 653 b43_ram_write(dev, 0x20 + i, tmp); 654 } 655} 656 657static void b43_upload_card_macaddress(struct b43_wldev *dev) 658{ 659 b43_write_mac_bssid_templates(dev); 660 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 661} 662 663static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 664{ 665 /* slot_time is in usec. */ 666 /* This test used to exit for all but a G PHY. */ 667 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 668 return; 669 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time); 670 /* Shared memory location 0x0010 is the slot time and should be 671 * set to slot_time; however, this register is initially 0 and changing 672 * the value adversely affects the transmit rate for BCM4311 673 * devices. Until this behavior is unterstood, delete this step 674 * 675 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 676 */ 677} 678 679static void b43_short_slot_timing_enable(struct b43_wldev *dev) 680{ 681 b43_set_slot_time(dev, 9); 682} 683 684static void b43_short_slot_timing_disable(struct b43_wldev *dev) 685{ 686 b43_set_slot_time(dev, 20); 687} 688 689/* DummyTransmission function, as documented on 690 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission 691 */ 692void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) 693{ 694 struct b43_phy *phy = &dev->phy; 695 unsigned int i, max_loop; 696 u16 value; 697 u32 buffer[5] = { 698 0x00000000, 699 0x00D40000, 700 0x00000000, 701 0x01000000, 702 0x00000000, 703 }; 704 705 if (ofdm) { 706 max_loop = 0x1E; 707 buffer[0] = 0x000201CC; 708 } else { 709 max_loop = 0xFA; 710 buffer[0] = 0x000B846E; 711 } 712 713 for (i = 0; i < 5; i++) 714 b43_ram_write(dev, i * 4, buffer[i]); 715 716 b43_write16(dev, 0x0568, 0x0000); 717 if (dev->dev->id.revision < 11) 718 b43_write16(dev, 0x07C0, 0x0000); 719 else 720 b43_write16(dev, 0x07C0, 0x0100); 721 value = (ofdm ? 0x41 : 0x40); 722 b43_write16(dev, 0x050C, value); 723 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP)) 724 b43_write16(dev, 0x0514, 0x1A02); 725 b43_write16(dev, 0x0508, 0x0000); 726 b43_write16(dev, 0x050A, 0x0000); 727 b43_write16(dev, 0x054C, 0x0000); 728 b43_write16(dev, 0x056A, 0x0014); 729 b43_write16(dev, 0x0568, 0x0826); 730 b43_write16(dev, 0x0500, 0x0000); 731 if (!pa_on && (phy->type == B43_PHYTYPE_N)) { 732 //SPEC TODO 733 } 734 735 switch (phy->type) { 736 case B43_PHYTYPE_N: 737 b43_write16(dev, 0x0502, 0x00D0); 738 break; 739 case B43_PHYTYPE_LP: 740 b43_write16(dev, 0x0502, 0x0050); 741 break; 742 default: 743 b43_write16(dev, 0x0502, 0x0030); 744 } 745 746 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 747 b43_radio_write16(dev, 0x0051, 0x0017); 748 for (i = 0x00; i < max_loop; i++) { 749 value = b43_read16(dev, 0x050E); 750 if (value & 0x0080) 751 break; 752 udelay(10); 753 } 754 for (i = 0x00; i < 0x0A; i++) { 755 value = b43_read16(dev, 0x050E); 756 if (value & 0x0400) 757 break; 758 udelay(10); 759 } 760 for (i = 0x00; i < 0x19; i++) { 761 value = b43_read16(dev, 0x0690); 762 if (!(value & 0x0100)) 763 break; 764 udelay(10); 765 } 766 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 767 b43_radio_write16(dev, 0x0051, 0x0037); 768} 769 770static void key_write(struct b43_wldev *dev, 771 u8 index, u8 algorithm, const u8 *key) 772{ 773 unsigned int i; 774 u32 offset; 775 u16 value; 776 u16 kidx; 777 778 /* Key index/algo block */ 779 kidx = b43_kidx_to_fw(dev, index); 780 value = ((kidx << 4) | algorithm); 781 b43_shm_write16(dev, B43_SHM_SHARED, 782 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 783 784 /* Write the key to the Key Table Pointer offset */ 785 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 786 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 787 value = key[i]; 788 value |= (u16) (key[i + 1]) << 8; 789 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 790 } 791} 792 793static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr) 794{ 795 u32 addrtmp[2] = { 0, 0, }; 796 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 797 798 if (b43_new_kidx_api(dev)) 799 pairwise_keys_start = B43_NR_GROUP_KEYS; 800 801 B43_WARN_ON(index < pairwise_keys_start); 802 /* We have four default TX keys and possibly four default RX keys. 803 * Physical mac 0 is mapped to physical key 4 or 8, depending 804 * on the firmware version. 805 * So we must adjust the index here. 806 */ 807 index -= pairwise_keys_start; 808 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 809 810 if (addr) { 811 addrtmp[0] = addr[0]; 812 addrtmp[0] |= ((u32) (addr[1]) << 8); 813 addrtmp[0] |= ((u32) (addr[2]) << 16); 814 addrtmp[0] |= ((u32) (addr[3]) << 24); 815 addrtmp[1] = addr[4]; 816 addrtmp[1] |= ((u32) (addr[5]) << 8); 817 } 818 819 /* Receive match transmitter address (RCMTA) mechanism */ 820 b43_shm_write32(dev, B43_SHM_RCMTA, 821 (index * 2) + 0, addrtmp[0]); 822 b43_shm_write16(dev, B43_SHM_RCMTA, 823 (index * 2) + 1, addrtmp[1]); 824} 825 826/* The ucode will use phase1 key with TEK key to decrypt rx packets. 827 * When a packet is received, the iv32 is checked. 828 * - if it doesn't the packet is returned without modification (and software 829 * decryption can be done). That's what happen when iv16 wrap. 830 * - if it does, the rc4 key is computed, and decryption is tried. 831 * Either it will success and B43_RX_MAC_DEC is returned, 832 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned 833 * and the packet is not usable (it got modified by the ucode). 834 * So in order to never have B43_RX_MAC_DECERR, we should provide 835 * a iv32 and phase1key that match. Because we drop packets in case of 836 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all 837 * packets will be lost without higher layer knowing (ie no resync possible 838 * until next wrap). 839 * 840 * NOTE : this should support 50 key like RCMTA because 841 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50 842 */ 843static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32, 844 u16 *phase1key) 845{ 846 unsigned int i; 847 u32 offset; 848 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 849 850 if (!modparam_hwtkip) 851 return; 852 853 if (b43_new_kidx_api(dev)) 854 pairwise_keys_start = B43_NR_GROUP_KEYS; 855 856 B43_WARN_ON(index < pairwise_keys_start); 857 /* We have four default TX keys and possibly four default RX keys. 858 * Physical mac 0 is mapped to physical key 4 or 8, depending 859 * on the firmware version. 860 * So we must adjust the index here. 861 */ 862 index -= pairwise_keys_start; 863 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 864 865 if (b43_debug(dev, B43_DBG_KEYS)) { 866 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", 867 index, iv32); 868 } 869 /* Write the key to the RX tkip shared mem */ 870 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4); 871 for (i = 0; i < 10; i += 2) { 872 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, 873 phase1key ? phase1key[i / 2] : 0); 874 } 875 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32); 876 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16); 877} 878 879static void b43_op_update_tkip_key(struct ieee80211_hw *hw, 880 struct ieee80211_vif *vif, 881 struct ieee80211_key_conf *keyconf, 882 struct ieee80211_sta *sta, 883 u32 iv32, u16 *phase1key) 884{ 885 struct b43_wl *wl = hw_to_b43_wl(hw); 886 struct b43_wldev *dev; 887 int index = keyconf->hw_key_idx; 888 889 if (B43_WARN_ON(!modparam_hwtkip)) 890 return; 891 892 /* This is only called from the RX path through mac80211, where 893 * our mutex is already locked. */ 894 B43_WARN_ON(!mutex_is_locked(&wl->mutex)); 895 dev = wl->current_dev; 896 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED); 897 898 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */ 899 900 rx_tkip_phase1_write(dev, index, iv32, phase1key); 901 /* only pairwise TKIP keys are supported right now */ 902 if (WARN_ON(!sta)) 903 return; 904 keymac_write(dev, index, sta->addr); 905} 906 907static void do_key_write(struct b43_wldev *dev, 908 u8 index, u8 algorithm, 909 const u8 *key, size_t key_len, const u8 *mac_addr) 910{ 911 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 912 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 913 914 if (b43_new_kidx_api(dev)) 915 pairwise_keys_start = B43_NR_GROUP_KEYS; 916 917 B43_WARN_ON(index >= ARRAY_SIZE(dev->key)); 918 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 919 920 if (index >= pairwise_keys_start) 921 keymac_write(dev, index, NULL); /* First zero out mac. */ 922 if (algorithm == B43_SEC_ALGO_TKIP) { 923 /* 924 * We should provide an initial iv32, phase1key pair. 925 * We could start with iv32=0 and compute the corresponding 926 * phase1key, but this means calling ieee80211_get_tkip_key 927 * with a fake skb (or export other tkip function). 928 * Because we are lazy we hope iv32 won't start with 929 * 0xffffffff and let's b43_op_update_tkip_key provide a 930 * correct pair. 931 */ 932 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); 933 } else if (index >= pairwise_keys_start) /* clear it */ 934 rx_tkip_phase1_write(dev, index, 0, NULL); 935 if (key) 936 memcpy(buf, key, key_len); 937 key_write(dev, index, algorithm, buf); 938 if (index >= pairwise_keys_start) 939 keymac_write(dev, index, mac_addr); 940 941 dev->key[index].algorithm = algorithm; 942} 943 944static int b43_key_write(struct b43_wldev *dev, 945 int index, u8 algorithm, 946 const u8 *key, size_t key_len, 947 const u8 *mac_addr, 948 struct ieee80211_key_conf *keyconf) 949{ 950 int i; 951 int pairwise_keys_start; 952 953 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block: 954 * - Temporal Encryption Key (128 bits) 955 * - Temporal Authenticator Tx MIC Key (64 bits) 956 * - Temporal Authenticator Rx MIC Key (64 bits) 957 * 958 * Hardware only store TEK 959 */ 960 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32) 961 key_len = 16; 962 if (key_len > B43_SEC_KEYSIZE) 963 return -EINVAL; 964 for (i = 0; i < ARRAY_SIZE(dev->key); i++) { 965 /* Check that we don't already have this key. */ 966 B43_WARN_ON(dev->key[i].keyconf == keyconf); 967 } 968 if (index < 0) { 969 /* Pairwise key. Get an empty slot for the key. */ 970 if (b43_new_kidx_api(dev)) 971 pairwise_keys_start = B43_NR_GROUP_KEYS; 972 else 973 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 974 for (i = pairwise_keys_start; 975 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS; 976 i++) { 977 B43_WARN_ON(i >= ARRAY_SIZE(dev->key)); 978 if (!dev->key[i].keyconf) { 979 /* found empty */ 980 index = i; 981 break; 982 } 983 } 984 if (index < 0) { 985 b43warn(dev->wl, "Out of hardware key memory\n"); 986 return -ENOSPC; 987 } 988 } else 989 B43_WARN_ON(index > 3); 990 991 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 992 if ((index <= 3) && !b43_new_kidx_api(dev)) { 993 /* Default RX key */ 994 B43_WARN_ON(mac_addr); 995 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 996 } 997 keyconf->hw_key_idx = index; 998 dev->key[index].keyconf = keyconf; 999 1000 return 0; 1001} 1002 1003static int b43_key_clear(struct b43_wldev *dev, int index) 1004{ 1005 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) 1006 return -EINVAL; 1007 do_key_write(dev, index, B43_SEC_ALGO_NONE, 1008 NULL, B43_SEC_KEYSIZE, NULL); 1009 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1010 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 1011 NULL, B43_SEC_KEYSIZE, NULL); 1012 } 1013 dev->key[index].keyconf = NULL; 1014 1015 return 0; 1016} 1017 1018static void b43_clear_keys(struct b43_wldev *dev) 1019{ 1020 int i, count; 1021 1022 if (b43_new_kidx_api(dev)) 1023 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1024 else 1025 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1026 for (i = 0; i < count; i++) 1027 b43_key_clear(dev, i); 1028} 1029 1030static void b43_dump_keymemory(struct b43_wldev *dev) 1031{ 1032 unsigned int i, index, count, offset, pairwise_keys_start; 1033 u8 mac[ETH_ALEN]; 1034 u16 algo; 1035 u32 rcmta0; 1036 u16 rcmta1; 1037 u64 hf; 1038 struct b43_key *key; 1039 1040 if (!b43_debug(dev, B43_DBG_KEYS)) 1041 return; 1042 1043 hf = b43_hf_read(dev); 1044 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n", 1045 !!(hf & B43_HF_USEDEFKEYS)); 1046 if (b43_new_kidx_api(dev)) { 1047 pairwise_keys_start = B43_NR_GROUP_KEYS; 1048 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1049 } else { 1050 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 1051 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1052 } 1053 for (index = 0; index < count; index++) { 1054 key = &(dev->key[index]); 1055 printk(KERN_DEBUG "Key slot %02u: %s", 1056 index, (key->keyconf == NULL) ? " " : "*"); 1057 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 1058 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 1059 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1060 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1061 } 1062 1063 algo = b43_shm_read16(dev, B43_SHM_SHARED, 1064 B43_SHM_SH_KEYIDXBLOCK + (index * 2)); 1065 printk(" Algo: %04X/%02X", algo, key->algorithm); 1066 1067 if (index >= pairwise_keys_start) { 1068 if (key->algorithm == B43_SEC_ALGO_TKIP) { 1069 printk(" TKIP: "); 1070 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4); 1071 for (i = 0; i < 14; i += 2) { 1072 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1073 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1074 } 1075 } 1076 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA, 1077 ((index - pairwise_keys_start) * 2) + 0); 1078 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA, 1079 ((index - pairwise_keys_start) * 2) + 1); 1080 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); 1081 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1); 1082 printk(" MAC: %pM", mac); 1083 } else 1084 printk(" DEFAULT KEY"); 1085 printk("\n"); 1086 } 1087} 1088 1089void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 1090{ 1091 u32 macctl; 1092 u16 ucstat; 1093 bool hwps; 1094 bool awake; 1095 int i; 1096 1097 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 1098 (ps_flags & B43_PS_DISABLED)); 1099 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 1100 1101 if (ps_flags & B43_PS_ENABLED) { 1102 hwps = 1; 1103 } else if (ps_flags & B43_PS_DISABLED) { 1104 hwps = 0; 1105 } else { 1106 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 1107 // and thus is not an AP and we are associated, set bit 25 1108 } 1109 if (ps_flags & B43_PS_AWAKE) { 1110 awake = 1; 1111 } else if (ps_flags & B43_PS_ASLEEP) { 1112 awake = 0; 1113 } else { 1114 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 1115 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 1116 // successful, set bit26 1117 } 1118 1119/* FIXME: For now we force awake-on and hwps-off */ 1120 hwps = 0; 1121 awake = 1; 1122 1123 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1124 if (hwps) 1125 macctl |= B43_MACCTL_HWPS; 1126 else 1127 macctl &= ~B43_MACCTL_HWPS; 1128 if (awake) 1129 macctl |= B43_MACCTL_AWAKE; 1130 else 1131 macctl &= ~B43_MACCTL_AWAKE; 1132 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1133 /* Commit write */ 1134 b43_read32(dev, B43_MMIO_MACCTL); 1135 if (awake && dev->dev->id.revision >= 5) { 1136 /* Wait for the microcode to wake up. */ 1137 for (i = 0; i < 100; i++) { 1138 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 1139 B43_SHM_SH_UCODESTAT); 1140 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 1141 break; 1142 udelay(10); 1143 } 1144 } 1145} 1146 1147void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 1148{ 1149 u32 tmslow; 1150 u32 macctl; 1151 1152 flags |= B43_TMSLOW_PHYCLKEN; 1153 flags |= B43_TMSLOW_PHYRESET; 1154 if (dev->phy.type == B43_PHYTYPE_N) 1155 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */ 1156 ssb_device_enable(dev->dev, flags); 1157 msleep(2); /* Wait for the PLL to turn on. */ 1158 1159 /* Now take the PHY out of Reset again */ 1160 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 1161 tmslow |= SSB_TMSLOW_FGC; 1162 tmslow &= ~B43_TMSLOW_PHYRESET; 1163 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 1164 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 1165 msleep(1); 1166 tmslow &= ~SSB_TMSLOW_FGC; 1167 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 1168 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 1169 msleep(1); 1170 1171 /* Turn Analog ON, but only if we already know the PHY-type. 1172 * This protects against very early setup where we don't know the 1173 * PHY-type, yet. wireless_core_reset will be called once again later, 1174 * when we know the PHY-type. */ 1175 if (dev->phy.ops) 1176 dev->phy.ops->switch_analog(dev, 1); 1177 1178 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1179 macctl &= ~B43_MACCTL_GMODE; 1180 if (flags & B43_TMSLOW_GMODE) 1181 macctl |= B43_MACCTL_GMODE; 1182 macctl |= B43_MACCTL_IHR_ENABLED; 1183 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1184} 1185 1186static void handle_irq_transmit_status(struct b43_wldev *dev) 1187{ 1188 u32 v0, v1; 1189 u16 tmp; 1190 struct b43_txstatus stat; 1191 1192 while (1) { 1193 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1194 if (!(v0 & 0x00000001)) 1195 break; 1196 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1197 1198 stat.cookie = (v0 >> 16); 1199 stat.seq = (v1 & 0x0000FFFF); 1200 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 1201 tmp = (v0 & 0x0000FFFF); 1202 stat.frame_count = ((tmp & 0xF000) >> 12); 1203 stat.rts_count = ((tmp & 0x0F00) >> 8); 1204 stat.supp_reason = ((tmp & 0x001C) >> 2); 1205 stat.pm_indicated = !!(tmp & 0x0080); 1206 stat.intermediate = !!(tmp & 0x0040); 1207 stat.for_ampdu = !!(tmp & 0x0020); 1208 stat.acked = !!(tmp & 0x0002); 1209 1210 b43_handle_txstatus(dev, &stat); 1211 } 1212} 1213 1214static void drain_txstatus_queue(struct b43_wldev *dev) 1215{ 1216 u32 dummy; 1217 1218 if (dev->dev->id.revision < 5) 1219 return; 1220 /* Read all entries from the microcode TXstatus FIFO 1221 * and throw them away. 1222 */ 1223 while (1) { 1224 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1225 if (!(dummy & 0x00000001)) 1226 break; 1227 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1228 } 1229} 1230 1231static u32 b43_jssi_read(struct b43_wldev *dev) 1232{ 1233 u32 val = 0; 1234 1235 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 1236 val <<= 16; 1237 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1238 1239 return val; 1240} 1241 1242static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1243{ 1244 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1245 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1246} 1247 1248static void b43_generate_noise_sample(struct b43_wldev *dev) 1249{ 1250 b43_jssi_write(dev, 0x7F7F7F7F); 1251 b43_write32(dev, B43_MMIO_MACCMD, 1252 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1253} 1254 1255static void b43_calculate_link_quality(struct b43_wldev *dev) 1256{ 1257 /* Top half of Link Quality calculation. */ 1258 1259 if (dev->phy.type != B43_PHYTYPE_G) 1260 return; 1261 if (dev->noisecalc.calculation_running) 1262 return; 1263 dev->noisecalc.calculation_running = 1; 1264 dev->noisecalc.nr_samples = 0; 1265 1266 b43_generate_noise_sample(dev); 1267} 1268 1269static void handle_irq_noise(struct b43_wldev *dev) 1270{ 1271 struct b43_phy_g *phy = dev->phy.g; 1272 u16 tmp; 1273 u8 noise[4]; 1274 u8 i, j; 1275 s32 average; 1276 1277 /* Bottom half of Link Quality calculation. */ 1278 1279 if (dev->phy.type != B43_PHYTYPE_G) 1280 return; 1281 1282 /* Possible race condition: It might be possible that the user 1283 * changed to a different channel in the meantime since we 1284 * started the calculation. We ignore that fact, since it's 1285 * not really that much of a problem. The background noise is 1286 * an estimation only anyway. Slightly wrong results will get damped 1287 * by the averaging of the 8 sample rounds. Additionally the 1288 * value is shortlived. So it will be replaced by the next noise 1289 * calculation round soon. */ 1290 1291 B43_WARN_ON(!dev->noisecalc.calculation_running); 1292 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1293 if (noise[0] == 0x7F || noise[1] == 0x7F || 1294 noise[2] == 0x7F || noise[3] == 0x7F) 1295 goto generate_new; 1296 1297 /* Get the noise samples. */ 1298 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1299 i = dev->noisecalc.nr_samples; 1300 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1301 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1302 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1303 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1304 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1305 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1306 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1307 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1308 dev->noisecalc.nr_samples++; 1309 if (dev->noisecalc.nr_samples == 8) { 1310 /* Calculate the Link Quality by the noise samples. */ 1311 average = 0; 1312 for (i = 0; i < 8; i++) { 1313 for (j = 0; j < 4; j++) 1314 average += dev->noisecalc.samples[i][j]; 1315 } 1316 average /= (8 * 4); 1317 average *= 125; 1318 average += 64; 1319 average /= 128; 1320 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1321 tmp = (tmp / 128) & 0x1F; 1322 if (tmp >= 8) 1323 average += 2; 1324 else 1325 average -= 25; 1326 if (tmp == 8) 1327 average -= 72; 1328 else 1329 average -= 48; 1330 1331 dev->stats.link_noise = average; 1332 dev->noisecalc.calculation_running = 0; 1333 return; 1334 } 1335generate_new: 1336 b43_generate_noise_sample(dev); 1337} 1338 1339static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1340{ 1341 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) { 1342 ///TODO: PS TBTT 1343 } else { 1344 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1345 b43_power_saving_ctl_bits(dev, 0); 1346 } 1347 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 1348 dev->dfq_valid = 1; 1349} 1350 1351static void handle_irq_atim_end(struct b43_wldev *dev) 1352{ 1353 if (dev->dfq_valid) { 1354 b43_write32(dev, B43_MMIO_MACCMD, 1355 b43_read32(dev, B43_MMIO_MACCMD) 1356 | B43_MACCMD_DFQ_VALID); 1357 dev->dfq_valid = 0; 1358 } 1359} 1360 1361static void handle_irq_pmq(struct b43_wldev *dev) 1362{ 1363 u32 tmp; 1364 1365 //TODO: AP mode. 1366 1367 while (1) { 1368 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1369 if (!(tmp & 0x00000008)) 1370 break; 1371 } 1372 /* 16bit write is odd, but correct. */ 1373 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1374} 1375 1376static void b43_write_template_common(struct b43_wldev *dev, 1377 const u8 *data, u16 size, 1378 u16 ram_offset, 1379 u16 shm_size_offset, u8 rate) 1380{ 1381 u32 i, tmp; 1382 struct b43_plcp_hdr4 plcp; 1383 1384 plcp.data = 0; 1385 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1386 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1387 ram_offset += sizeof(u32); 1388 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1389 * So leave the first two bytes of the next write blank. 1390 */ 1391 tmp = (u32) (data[0]) << 16; 1392 tmp |= (u32) (data[1]) << 24; 1393 b43_ram_write(dev, ram_offset, tmp); 1394 ram_offset += sizeof(u32); 1395 for (i = 2; i < size; i += sizeof(u32)) { 1396 tmp = (u32) (data[i + 0]); 1397 if (i + 1 < size) 1398 tmp |= (u32) (data[i + 1]) << 8; 1399 if (i + 2 < size) 1400 tmp |= (u32) (data[i + 2]) << 16; 1401 if (i + 3 < size) 1402 tmp |= (u32) (data[i + 3]) << 24; 1403 b43_ram_write(dev, ram_offset + i - 2, tmp); 1404 } 1405 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1406 size + sizeof(struct b43_plcp_hdr6)); 1407} 1408 1409/* Check if the use of the antenna that ieee80211 told us to 1410 * use is possible. This will fall back to DEFAULT. 1411 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 1412u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 1413 u8 antenna_nr) 1414{ 1415 u8 antenna_mask; 1416 1417 if (antenna_nr == 0) { 1418 /* Zero means "use default antenna". That's always OK. */ 1419 return 0; 1420 } 1421 1422 /* Get the mask of available antennas. */ 1423 if (dev->phy.gmode) 1424 antenna_mask = dev->dev->bus->sprom.ant_available_bg; 1425 else 1426 antenna_mask = dev->dev->bus->sprom.ant_available_a; 1427 1428 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 1429 /* This antenna is not available. Fall back to default. */ 1430 return 0; 1431 } 1432 1433 return antenna_nr; 1434} 1435 1436/* Convert a b43 antenna number value to the PHY TX control value. */ 1437static u16 b43_antenna_to_phyctl(int antenna) 1438{ 1439 switch (antenna) { 1440 case B43_ANTENNA0: 1441 return B43_TXH_PHY_ANT0; 1442 case B43_ANTENNA1: 1443 return B43_TXH_PHY_ANT1; 1444 case B43_ANTENNA2: 1445 return B43_TXH_PHY_ANT2; 1446 case B43_ANTENNA3: 1447 return B43_TXH_PHY_ANT3; 1448 case B43_ANTENNA_AUTO0: 1449 case B43_ANTENNA_AUTO1: 1450 return B43_TXH_PHY_ANT01AUTO; 1451 } 1452 B43_WARN_ON(1); 1453 return 0; 1454} 1455 1456static void b43_write_beacon_template(struct b43_wldev *dev, 1457 u16 ram_offset, 1458 u16 shm_size_offset) 1459{ 1460 unsigned int i, len, variable_len; 1461 const struct ieee80211_mgmt *bcn; 1462 const u8 *ie; 1463 bool tim_found = 0; 1464 unsigned int rate; 1465 u16 ctl; 1466 int antenna; 1467 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon); 1468 1469 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1470 len = min((size_t) dev->wl->current_beacon->len, 1471 0x200 - sizeof(struct b43_plcp_hdr6)); 1472 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; 1473 1474 b43_write_template_common(dev, (const u8 *)bcn, 1475 len, ram_offset, shm_size_offset, rate); 1476 1477 /* Write the PHY TX control parameters. */ 1478 antenna = B43_ANTENNA_DEFAULT; 1479 antenna = b43_antenna_to_phyctl(antenna); 1480 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 1481 /* We can't send beacons with short preamble. Would get PHY errors. */ 1482 ctl &= ~B43_TXH_PHY_SHORTPRMBL; 1483 ctl &= ~B43_TXH_PHY_ANT; 1484 ctl &= ~B43_TXH_PHY_ENC; 1485 ctl |= antenna; 1486 if (b43_is_cck_rate(rate)) 1487 ctl |= B43_TXH_PHY_ENC_CCK; 1488 else 1489 ctl |= B43_TXH_PHY_ENC_OFDM; 1490 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 1491 1492 /* Find the position of the TIM and the DTIM_period value 1493 * and write them to SHM. */ 1494 ie = bcn->u.beacon.variable; 1495 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1496 for (i = 0; i < variable_len - 2; ) { 1497 uint8_t ie_id, ie_len; 1498 1499 ie_id = ie[i]; 1500 ie_len = ie[i + 1]; 1501 if (ie_id == 5) { 1502 u16 tim_position; 1503 u16 dtim_period; 1504 /* This is the TIM Information Element */ 1505 1506 /* Check whether the ie_len is in the beacon data range. */ 1507 if (variable_len < ie_len + 2 + i) 1508 break; 1509 /* A valid TIM is at least 4 bytes long. */ 1510 if (ie_len < 4) 1511 break; 1512 tim_found = 1; 1513 1514 tim_position = sizeof(struct b43_plcp_hdr6); 1515 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1516 tim_position += i; 1517 1518 dtim_period = ie[i + 3]; 1519 1520 b43_shm_write16(dev, B43_SHM_SHARED, 1521 B43_SHM_SH_TIMBPOS, tim_position); 1522 b43_shm_write16(dev, B43_SHM_SHARED, 1523 B43_SHM_SH_DTIMPER, dtim_period); 1524 break; 1525 } 1526 i += ie_len + 2; 1527 } 1528 if (!tim_found) { 1529 /* 1530 * If ucode wants to modify TIM do it behind the beacon, this 1531 * will happen, for example, when doing mesh networking. 1532 */ 1533 b43_shm_write16(dev, B43_SHM_SHARED, 1534 B43_SHM_SH_TIMBPOS, 1535 len + sizeof(struct b43_plcp_hdr6)); 1536 b43_shm_write16(dev, B43_SHM_SHARED, 1537 B43_SHM_SH_DTIMPER, 0); 1538 } 1539 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); 1540} 1541 1542static void b43_upload_beacon0(struct b43_wldev *dev) 1543{ 1544 struct b43_wl *wl = dev->wl; 1545 1546 if (wl->beacon0_uploaded) 1547 return; 1548 b43_write_beacon_template(dev, 0x68, 0x18); 1549 wl->beacon0_uploaded = 1; 1550} 1551 1552static void b43_upload_beacon1(struct b43_wldev *dev) 1553{ 1554 struct b43_wl *wl = dev->wl; 1555 1556 if (wl->beacon1_uploaded) 1557 return; 1558 b43_write_beacon_template(dev, 0x468, 0x1A); 1559 wl->beacon1_uploaded = 1; 1560} 1561 1562static void handle_irq_beacon(struct b43_wldev *dev) 1563{ 1564 struct b43_wl *wl = dev->wl; 1565 u32 cmd, beacon0_valid, beacon1_valid; 1566 1567 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && 1568 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 1569 return; 1570 1571 /* This is the bottom half of the asynchronous beacon update. */ 1572 1573 /* Ignore interrupt in the future. */ 1574 dev->irq_mask &= ~B43_IRQ_BEACON; 1575 1576 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1577 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); 1578 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); 1579 1580 /* Schedule interrupt manually, if busy. */ 1581 if (beacon0_valid && beacon1_valid) { 1582 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1583 dev->irq_mask |= B43_IRQ_BEACON; 1584 return; 1585 } 1586 1587 if (unlikely(wl->beacon_templates_virgin)) { 1588 /* We never uploaded a beacon before. 1589 * Upload both templates now, but only mark one valid. */ 1590 wl->beacon_templates_virgin = 0; 1591 b43_upload_beacon0(dev); 1592 b43_upload_beacon1(dev); 1593 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1594 cmd |= B43_MACCMD_BEACON0_VALID; 1595 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1596 } else { 1597 if (!beacon0_valid) { 1598 b43_upload_beacon0(dev); 1599 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1600 cmd |= B43_MACCMD_BEACON0_VALID; 1601 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1602 } else if (!beacon1_valid) { 1603 b43_upload_beacon1(dev); 1604 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1605 cmd |= B43_MACCMD_BEACON1_VALID; 1606 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1607 } 1608 } 1609} 1610 1611static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev) 1612{ 1613 u32 old_irq_mask = dev->irq_mask; 1614 1615 /* update beacon right away or defer to irq */ 1616 handle_irq_beacon(dev); 1617 if (old_irq_mask != dev->irq_mask) { 1618 /* The handler updated the IRQ mask. */ 1619 B43_WARN_ON(!dev->irq_mask); 1620 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) { 1621 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1622 } else { 1623 /* Device interrupts are currently disabled. That means 1624 * we just ran the hardirq handler and scheduled the 1625 * IRQ thread. The thread will write the IRQ mask when 1626 * it finished, so there's nothing to do here. Writing 1627 * the mask _here_ would incorrectly re-enable IRQs. */ 1628 } 1629 } 1630} 1631 1632static void b43_beacon_update_trigger_work(struct work_struct *work) 1633{ 1634 struct b43_wl *wl = container_of(work, struct b43_wl, 1635 beacon_update_trigger); 1636 struct b43_wldev *dev; 1637 1638 mutex_lock(&wl->mutex); 1639 dev = wl->current_dev; 1640 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { 1641 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) { 1642 /* wl->mutex is enough. */ 1643 b43_do_beacon_update_trigger_work(dev); 1644 mmiowb(); 1645 } else { 1646 spin_lock_irq(&wl->hardirq_lock); 1647 b43_do_beacon_update_trigger_work(dev); 1648 mmiowb(); 1649 spin_unlock_irq(&wl->hardirq_lock); 1650 } 1651 } 1652 mutex_unlock(&wl->mutex); 1653} 1654 1655/* Asynchronously update the packet templates in template RAM. 1656 * Locking: Requires wl->mutex to be locked. */ 1657static void b43_update_templates(struct b43_wl *wl) 1658{ 1659 struct sk_buff *beacon; 1660 1661 /* This is the top half of the ansynchronous beacon update. 1662 * The bottom half is the beacon IRQ. 1663 * Beacon update must be asynchronous to avoid sending an 1664 * invalid beacon. This can happen for example, if the firmware 1665 * transmits a beacon while we are updating it. */ 1666 1667 /* We could modify the existing beacon and set the aid bit in 1668 * the TIM field, but that would probably require resizing and 1669 * moving of data within the beacon template. 1670 * Simply request a new beacon and let mac80211 do the hard work. */ 1671 beacon = ieee80211_beacon_get(wl->hw, wl->vif); 1672 if (unlikely(!beacon)) 1673 return; 1674 1675 if (wl->current_beacon) 1676 dev_kfree_skb_any(wl->current_beacon); 1677 wl->current_beacon = beacon; 1678 wl->beacon0_uploaded = 0; 1679 wl->beacon1_uploaded = 0; 1680 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); 1681} 1682 1683static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1684{ 1685 b43_time_lock(dev); 1686 if (dev->dev->id.revision >= 3) { 1687 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); 1688 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); 1689 } else { 1690 b43_write16(dev, 0x606, (beacon_int >> 6)); 1691 b43_write16(dev, 0x610, beacon_int); 1692 } 1693 b43_time_unlock(dev); 1694 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1695} 1696 1697static void b43_handle_firmware_panic(struct b43_wldev *dev) 1698{ 1699 u16 reason; 1700 1701 /* Read the register that contains the reason code for the panic. */ 1702 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG); 1703 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason); 1704 1705 switch (reason) { 1706 default: 1707 b43dbg(dev->wl, "The panic reason is unknown.\n"); 1708 /* fallthrough */ 1709 case B43_FWPANIC_DIE: 1710 /* Do not restart the controller or firmware. 1711 * The device is nonfunctional from now on. 1712 * Restarting would result in this panic to trigger again, 1713 * so we avoid that recursion. */ 1714 break; 1715 case B43_FWPANIC_RESTART: 1716 b43_controller_restart(dev, "Microcode panic"); 1717 break; 1718 } 1719} 1720 1721static void handle_irq_ucode_debug(struct b43_wldev *dev) 1722{ 1723 unsigned int i, cnt; 1724 u16 reason, marker_id, marker_line; 1725 __le16 *buf; 1726 1727 /* The proprietary firmware doesn't have this IRQ. */ 1728 if (!dev->fw.opensource) 1729 return; 1730 1731 /* Read the register that contains the reason code for this IRQ. */ 1732 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG); 1733 1734 switch (reason) { 1735 case B43_DEBUGIRQ_PANIC: 1736 b43_handle_firmware_panic(dev); 1737 break; 1738 case B43_DEBUGIRQ_DUMP_SHM: 1739 if (!B43_DEBUG) 1740 break; /* Only with driver debugging enabled. */ 1741 buf = kmalloc(4096, GFP_ATOMIC); 1742 if (!buf) { 1743 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n"); 1744 goto out; 1745 } 1746 for (i = 0; i < 4096; i += 2) { 1747 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i); 1748 buf[i / 2] = cpu_to_le16(tmp); 1749 } 1750 b43info(dev->wl, "Shared memory dump:\n"); 1751 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 1752 16, 2, buf, 4096, 1); 1753 kfree(buf); 1754 break; 1755 case B43_DEBUGIRQ_DUMP_REGS: 1756 if (!B43_DEBUG) 1757 break; /* Only with driver debugging enabled. */ 1758 b43info(dev->wl, "Microcode register dump:\n"); 1759 for (i = 0, cnt = 0; i < 64; i++) { 1760 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i); 1761 if (cnt == 0) 1762 printk(KERN_INFO); 1763 printk("r%02u: 0x%04X ", i, tmp); 1764 cnt++; 1765 if (cnt == 6) { 1766 printk("\n"); 1767 cnt = 0; 1768 } 1769 } 1770 printk("\n"); 1771 break; 1772 case B43_DEBUGIRQ_MARKER: 1773 if (!B43_DEBUG) 1774 break; /* Only with driver debugging enabled. */ 1775 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH, 1776 B43_MARKER_ID_REG); 1777 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH, 1778 B43_MARKER_LINE_REG); 1779 b43info(dev->wl, "The firmware just executed the MARKER(%u) " 1780 "at line number %u\n", 1781 marker_id, marker_line); 1782 break; 1783 default: 1784 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n", 1785 reason); 1786 } 1787out: 1788 /* Acknowledge the debug-IRQ, so the firmware can continue. */ 1789 b43_shm_write16(dev, B43_SHM_SCRATCH, 1790 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK); 1791} 1792 1793static void b43_do_interrupt_thread(struct b43_wldev *dev) 1794{ 1795 u32 reason; 1796 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1797 u32 merged_dma_reason = 0; 1798 int i; 1799 1800 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 1801 return; 1802 1803 reason = dev->irq_reason; 1804 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1805 dma_reason[i] = dev->dma_reason[i]; 1806 merged_dma_reason |= dma_reason[i]; 1807 } 1808 1809 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1810 b43err(dev->wl, "MAC transmission error\n"); 1811 1812 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1813 b43err(dev->wl, "PHY transmission error\n"); 1814 rmb(); 1815 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1816 atomic_set(&dev->phy.txerr_cnt, 1817 B43_PHY_TX_BADNESS_LIMIT); 1818 b43err(dev->wl, "Too many PHY TX errors, " 1819 "restarting the controller\n"); 1820 b43_controller_restart(dev, "PHY TX errors"); 1821 } 1822 } 1823 1824 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1825 B43_DMAIRQ_NONFATALMASK))) { 1826 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1827 b43err(dev->wl, "Fatal DMA error: " 1828 "0x%08X, 0x%08X, 0x%08X, " 1829 "0x%08X, 0x%08X, 0x%08X\n", 1830 dma_reason[0], dma_reason[1], 1831 dma_reason[2], dma_reason[3], 1832 dma_reason[4], dma_reason[5]); 1833 b43err(dev->wl, "This device does not support DMA " 1834 "on your system. It will now be switched to PIO.\n"); 1835 /* Fall back to PIO transfers if we get fatal DMA errors! */ 1836 dev->use_pio = 1; 1837 b43_controller_restart(dev, "DMA error"); 1838 return; 1839 } 1840 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1841 b43err(dev->wl, "DMA error: " 1842 "0x%08X, 0x%08X, 0x%08X, " 1843 "0x%08X, 0x%08X, 0x%08X\n", 1844 dma_reason[0], dma_reason[1], 1845 dma_reason[2], dma_reason[3], 1846 dma_reason[4], dma_reason[5]); 1847 } 1848 } 1849 1850 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1851 handle_irq_ucode_debug(dev); 1852 if (reason & B43_IRQ_TBTT_INDI) 1853 handle_irq_tbtt_indication(dev); 1854 if (reason & B43_IRQ_ATIM_END) 1855 handle_irq_atim_end(dev); 1856 if (reason & B43_IRQ_BEACON) 1857 handle_irq_beacon(dev); 1858 if (reason & B43_IRQ_PMQ) 1859 handle_irq_pmq(dev); 1860 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1861 ;/* TODO */ 1862 if (reason & B43_IRQ_NOISESAMPLE_OK) 1863 handle_irq_noise(dev); 1864 1865 /* Check the DMA reason registers for received data. */ 1866 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 1867 if (b43_using_pio_transfers(dev)) 1868 b43_pio_rx(dev->pio.rx_queue); 1869 else 1870 b43_dma_rx(dev->dma.rx_ring); 1871 } 1872 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1873 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1874 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); 1875 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1876 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1877 1878 if (reason & B43_IRQ_TX_OK) 1879 handle_irq_transmit_status(dev); 1880 1881 /* Re-enable interrupts on the device by restoring the current interrupt mask. */ 1882 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1883 1884#if B43_DEBUG 1885 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 1886 dev->irq_count++; 1887 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 1888 if (reason & (1 << i)) 1889 dev->irq_bit_count[i]++; 1890 } 1891 } 1892#endif 1893} 1894 1895/* Interrupt thread handler. Handles device interrupts in thread context. */ 1896static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id) 1897{ 1898 struct b43_wldev *dev = dev_id; 1899 1900 mutex_lock(&dev->wl->mutex); 1901 b43_do_interrupt_thread(dev); 1902 mmiowb(); 1903 mutex_unlock(&dev->wl->mutex); 1904 1905 return IRQ_HANDLED; 1906} 1907 1908static irqreturn_t b43_do_interrupt(struct b43_wldev *dev) 1909{ 1910 u32 reason; 1911 1912 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses. 1913 * On SDIO, this runs under wl->mutex. */ 1914 1915 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1916 if (reason == 0xffffffff) /* shared IRQ */ 1917 return IRQ_NONE; 1918 reason &= dev->irq_mask; 1919 if (!reason) 1920 return IRQ_HANDLED; 1921 1922 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1923 & 0x0001DC00; 1924 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1925 & 0x0000DC00; 1926 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1927 & 0x0000DC00; 1928 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1929 & 0x0001DC00; 1930 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1931 & 0x0000DC00; 1932/* Unused ring 1933 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1934 & 0x0000DC00; 1935*/ 1936 1937 /* ACK the interrupt. */ 1938 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1939 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1940 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1941 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1942 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1943 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1944/* Unused ring 1945 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1946*/ 1947 1948 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */ 1949 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 1950 /* Save the reason bitmasks for the IRQ thread handler. */ 1951 dev->irq_reason = reason; 1952 1953 return IRQ_WAKE_THREAD; 1954} 1955 1956/* Interrupt handler top-half. This runs with interrupts disabled. */ 1957static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1958{ 1959 struct b43_wldev *dev = dev_id; 1960 irqreturn_t ret; 1961 1962 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 1963 return IRQ_NONE; 1964 1965 spin_lock(&dev->wl->hardirq_lock); 1966 ret = b43_do_interrupt(dev); 1967 mmiowb(); 1968 spin_unlock(&dev->wl->hardirq_lock); 1969 1970 return ret; 1971} 1972 1973/* SDIO interrupt handler. This runs in process context. */ 1974static void b43_sdio_interrupt_handler(struct b43_wldev *dev) 1975{ 1976 struct b43_wl *wl = dev->wl; 1977 irqreturn_t ret; 1978 1979 mutex_lock(&wl->mutex); 1980 1981 ret = b43_do_interrupt(dev); 1982 if (ret == IRQ_WAKE_THREAD) 1983 b43_do_interrupt_thread(dev); 1984 1985 mutex_unlock(&wl->mutex); 1986} 1987 1988void b43_do_release_fw(struct b43_firmware_file *fw) 1989{ 1990 release_firmware(fw->data); 1991 fw->data = NULL; 1992 fw->filename = NULL; 1993} 1994 1995static void b43_release_firmware(struct b43_wldev *dev) 1996{ 1997 b43_do_release_fw(&dev->fw.ucode); 1998 b43_do_release_fw(&dev->fw.pcm); 1999 b43_do_release_fw(&dev->fw.initvals); 2000 b43_do_release_fw(&dev->fw.initvals_band); 2001} 2002 2003static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 2004{ 2005 const char text[] = 2006 "You must go to " \ 2007 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \ 2008 "and download the correct firmware for this driver version. " \ 2009 "Please carefully read all instructions on this website.\n"; 2010 2011 if (error) 2012 b43err(wl, text); 2013 else 2014 b43warn(wl, text); 2015} 2016 2017int b43_do_request_fw(struct b43_request_fw_context *ctx, 2018 const char *name, 2019 struct b43_firmware_file *fw) 2020{ 2021 const struct firmware *blob; 2022 struct b43_fw_header *hdr; 2023 u32 size; 2024 int err; 2025 2026 if (!name) { 2027 /* Don't fetch anything. Free possibly cached firmware. */ 2028 /* FIXME: We should probably keep it anyway, to save some headache 2029 * on suspend/resume with multiband devices. */ 2030 b43_do_release_fw(fw); 2031 return 0; 2032 } 2033 if (fw->filename) { 2034 if ((fw->type == ctx->req_type) && 2035 (strcmp(fw->filename, name) == 0)) 2036 return 0; /* Already have this fw. */ 2037 /* Free the cached firmware first. */ 2038 /* FIXME: We should probably do this later after we successfully 2039 * got the new fw. This could reduce headache with multiband devices. 2040 * We could also redesign this to cache the firmware for all possible 2041 * bands all the time. */ 2042 b43_do_release_fw(fw); 2043 } 2044 2045 switch (ctx->req_type) { 2046 case B43_FWTYPE_PROPRIETARY: 2047 snprintf(ctx->fwname, sizeof(ctx->fwname), 2048 "b43%s/%s.fw", 2049 modparam_fwpostfix, name); 2050 break; 2051 case B43_FWTYPE_OPENSOURCE: 2052 snprintf(ctx->fwname, sizeof(ctx->fwname), 2053 "b43-open%s/%s.fw", 2054 modparam_fwpostfix, name); 2055 break; 2056 default: 2057 B43_WARN_ON(1); 2058 return -ENOSYS; 2059 } 2060 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev); 2061 if (err == -ENOENT) { 2062 snprintf(ctx->errors[ctx->req_type], 2063 sizeof(ctx->errors[ctx->req_type]), 2064 "Firmware file \"%s\" not found\n", ctx->fwname); 2065 return err; 2066 } else if (err) { 2067 snprintf(ctx->errors[ctx->req_type], 2068 sizeof(ctx->errors[ctx->req_type]), 2069 "Firmware file \"%s\" request failed (err=%d)\n", 2070 ctx->fwname, err); 2071 return err; 2072 } 2073 if (blob->size < sizeof(struct b43_fw_header)) 2074 goto err_format; 2075 hdr = (struct b43_fw_header *)(blob->data); 2076 switch (hdr->type) { 2077 case B43_FW_TYPE_UCODE: 2078 case B43_FW_TYPE_PCM: 2079 size = be32_to_cpu(hdr->size); 2080 if (size != blob->size - sizeof(struct b43_fw_header)) 2081 goto err_format; 2082 /* fallthrough */ 2083 case B43_FW_TYPE_IV: 2084 if (hdr->ver != 1) 2085 goto err_format; 2086 break; 2087 default: 2088 goto err_format; 2089 } 2090 2091 fw->data = blob; 2092 fw->filename = name; 2093 fw->type = ctx->req_type; 2094 2095 return 0; 2096 2097err_format: 2098 snprintf(ctx->errors[ctx->req_type], 2099 sizeof(ctx->errors[ctx->req_type]), 2100 "Firmware file \"%s\" format error.\n", ctx->fwname); 2101 release_firmware(blob); 2102 2103 return -EPROTO; 2104} 2105 2106static int b43_try_request_fw(struct b43_request_fw_context *ctx) 2107{ 2108 struct b43_wldev *dev = ctx->dev; 2109 struct b43_firmware *fw = &ctx->dev->fw; 2110 const u8 rev = ctx->dev->dev->id.revision; 2111 const char *filename; 2112 u32 tmshigh; 2113 int err; 2114 2115 /* Get microcode */ 2116 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 2117 if ((rev >= 5) && (rev <= 10)) 2118 filename = "ucode5"; 2119 else if ((rev >= 11) && (rev <= 12)) 2120 filename = "ucode11"; 2121 else if (rev == 13) 2122 filename = "ucode13"; 2123 else if (rev == 14) 2124 filename = "ucode14"; 2125 else if (rev == 15) 2126 filename = "ucode15"; 2127 else if ((rev >= 16) && (rev <= 20)) 2128 filename = "ucode16_mimo"; 2129 else 2130 goto err_no_ucode; 2131 err = b43_do_request_fw(ctx, filename, &fw->ucode); 2132 if (err) 2133 goto err_load; 2134 2135 /* Get PCM code */ 2136 if ((rev >= 5) && (rev <= 10)) 2137 filename = "pcm5"; 2138 else if (rev >= 11) 2139 filename = NULL; 2140 else 2141 goto err_no_pcm; 2142 fw->pcm_request_failed = 0; 2143 err = b43_do_request_fw(ctx, filename, &fw->pcm); 2144 if (err == -ENOENT) { 2145 /* We did not find a PCM file? Not fatal, but 2146 * core rev <= 10 must do without hwcrypto then. */ 2147 fw->pcm_request_failed = 1; 2148 } else if (err) 2149 goto err_load; 2150 2151 /* Get initvals */ 2152 switch (dev->phy.type) { 2153 case B43_PHYTYPE_A: 2154 if ((rev >= 5) && (rev <= 10)) { 2155 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2156 filename = "a0g1initvals5"; 2157 else 2158 filename = "a0g0initvals5"; 2159 } else 2160 goto err_no_initvals; 2161 break; 2162 case B43_PHYTYPE_G: 2163 if ((rev >= 5) && (rev <= 10)) 2164 filename = "b0g0initvals5"; 2165 else if (rev >= 13) 2166 filename = "b0g0initvals13"; 2167 else 2168 goto err_no_initvals; 2169 break; 2170 case B43_PHYTYPE_N: 2171 if (rev >= 16) 2172 filename = "n0initvals16"; 2173 else if ((rev >= 11) && (rev <= 12)) 2174 filename = "n0initvals11"; 2175 else 2176 goto err_no_initvals; 2177 break; 2178 case B43_PHYTYPE_LP: 2179 if (rev == 13) 2180 filename = "lp0initvals13"; 2181 else if (rev == 14) 2182 filename = "lp0initvals14"; 2183 else if (rev >= 15) 2184 filename = "lp0initvals15"; 2185 else 2186 goto err_no_initvals; 2187 break; 2188 default: 2189 goto err_no_initvals; 2190 } 2191 err = b43_do_request_fw(ctx, filename, &fw->initvals); 2192 if (err) 2193 goto err_load; 2194 2195 /* Get bandswitch initvals */ 2196 switch (dev->phy.type) { 2197 case B43_PHYTYPE_A: 2198 if ((rev >= 5) && (rev <= 10)) { 2199 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2200 filename = "a0g1bsinitvals5"; 2201 else 2202 filename = "a0g0bsinitvals5"; 2203 } else if (rev >= 11) 2204 filename = NULL; 2205 else 2206 goto err_no_initvals; 2207 break; 2208 case B43_PHYTYPE_G: 2209 if ((rev >= 5) && (rev <= 10)) 2210 filename = "b0g0bsinitvals5"; 2211 else if (rev >= 11) 2212 filename = NULL; 2213 else 2214 goto err_no_initvals; 2215 break; 2216 case B43_PHYTYPE_N: 2217 if (rev >= 16) 2218 filename = "n0bsinitvals16"; 2219 else if ((rev >= 11) && (rev <= 12)) 2220 filename = "n0bsinitvals11"; 2221 else 2222 goto err_no_initvals; 2223 break; 2224 case B43_PHYTYPE_LP: 2225 if (rev == 13) 2226 filename = "lp0bsinitvals13"; 2227 else if (rev == 14) 2228 filename = "lp0bsinitvals14"; 2229 else if (rev >= 15) 2230 filename = "lp0bsinitvals15"; 2231 else 2232 goto err_no_initvals; 2233 break; 2234 default: 2235 goto err_no_initvals; 2236 } 2237 err = b43_do_request_fw(ctx, filename, &fw->initvals_band); 2238 if (err) 2239 goto err_load; 2240 2241 return 0; 2242 2243err_no_ucode: 2244 err = ctx->fatal_failure = -EOPNOTSUPP; 2245 b43err(dev->wl, "The driver does not know which firmware (ucode) " 2246 "is required for your device (wl-core rev %u)\n", rev); 2247 goto error; 2248 2249err_no_pcm: 2250 err = ctx->fatal_failure = -EOPNOTSUPP; 2251 b43err(dev->wl, "The driver does not know which firmware (PCM) " 2252 "is required for your device (wl-core rev %u)\n", rev); 2253 goto error; 2254 2255err_no_initvals: 2256 err = ctx->fatal_failure = -EOPNOTSUPP; 2257 b43err(dev->wl, "The driver does not know which firmware (initvals) " 2258 "is required for your device (wl-core rev %u)\n", rev); 2259 goto error; 2260 2261err_load: 2262 /* We failed to load this firmware image. The error message 2263 * already is in ctx->errors. Return and let our caller decide 2264 * what to do. */ 2265 goto error; 2266 2267error: 2268 b43_release_firmware(dev); 2269 return err; 2270} 2271 2272static int b43_request_firmware(struct b43_wldev *dev) 2273{ 2274 struct b43_request_fw_context *ctx; 2275 unsigned int i; 2276 int err; 2277 const char *errmsg; 2278 2279 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2280 if (!ctx) 2281 return -ENOMEM; 2282 ctx->dev = dev; 2283 2284 ctx->req_type = B43_FWTYPE_PROPRIETARY; 2285 err = b43_try_request_fw(ctx); 2286 if (!err) 2287 goto out; /* Successfully loaded it. */ 2288 err = ctx->fatal_failure; 2289 if (err) 2290 goto out; 2291 2292 ctx->req_type = B43_FWTYPE_OPENSOURCE; 2293 err = b43_try_request_fw(ctx); 2294 if (!err) 2295 goto out; /* Successfully loaded it. */ 2296 err = ctx->fatal_failure; 2297 if (err) 2298 goto out; 2299 2300 /* Could not find a usable firmware. Print the errors. */ 2301 for (i = 0; i < B43_NR_FWTYPES; i++) { 2302 errmsg = ctx->errors[i]; 2303 if (strlen(errmsg)) 2304 b43err(dev->wl, errmsg); 2305 } 2306 b43_print_fw_helptext(dev->wl, 1); 2307 err = -ENOENT; 2308 2309out: 2310 kfree(ctx); 2311 return err; 2312} 2313 2314static int b43_upload_microcode(struct b43_wldev *dev) 2315{ 2316 struct wiphy *wiphy = dev->wl->hw->wiphy; 2317 const size_t hdr_len = sizeof(struct b43_fw_header); 2318 const __be32 *data; 2319 unsigned int i, len; 2320 u16 fwrev, fwpatch, fwdate, fwtime; 2321 u32 tmp, macctl; 2322 int err = 0; 2323 2324 /* Jump the microcode PSM to offset 0 */ 2325 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2326 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); 2327 macctl |= B43_MACCTL_PSM_JMP0; 2328 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2329 /* Zero out all microcode PSM registers and shared memory. */ 2330 for (i = 0; i < 64; i++) 2331 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); 2332 for (i = 0; i < 4096; i += 2) 2333 b43_shm_write16(dev, B43_SHM_SHARED, i, 0); 2334 2335 /* Upload Microcode. */ 2336 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); 2337 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); 2338 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 2339 for (i = 0; i < len; i++) { 2340 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2341 udelay(10); 2342 } 2343 2344 if (dev->fw.pcm.data) { 2345 /* Upload PCM data. */ 2346 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); 2347 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); 2348 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 2349 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 2350 /* No need for autoinc bit in SHM_HW */ 2351 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 2352 for (i = 0; i < len; i++) { 2353 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2354 udelay(10); 2355 } 2356 } 2357 2358 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 2359 2360 /* Start the microcode PSM */ 2361 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2362 macctl &= ~B43_MACCTL_PSM_JMP0; 2363 macctl |= B43_MACCTL_PSM_RUN; 2364 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2365 2366 /* Wait for the microcode to load and respond */ 2367 i = 0; 2368 while (1) { 2369 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2370 if (tmp == B43_IRQ_MAC_SUSPENDED) 2371 break; 2372 i++; 2373 if (i >= 20) { 2374 b43err(dev->wl, "Microcode not responding\n"); 2375 b43_print_fw_helptext(dev->wl, 1); 2376 err = -ENODEV; 2377 goto error; 2378 } 2379 msleep(50); 2380 } 2381 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 2382 2383 /* Get and check the revisions. */ 2384 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 2385 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 2386 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 2387 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 2388 2389 if (fwrev <= 0x128) { 2390 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 2391 "binary drivers older than version 4.x is unsupported. " 2392 "You must upgrade your firmware files.\n"); 2393 b43_print_fw_helptext(dev->wl, 1); 2394 err = -EOPNOTSUPP; 2395 goto error; 2396 } 2397 dev->fw.rev = fwrev; 2398 dev->fw.patch = fwpatch; 2399 dev->fw.opensource = (fwdate == 0xFFFF); 2400 2401 /* Default to use-all-queues. */ 2402 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues; 2403 dev->qos_enabled = !!modparam_qos; 2404 /* Default to firmware/hardware crypto acceleration. */ 2405 dev->hwcrypto_enabled = 1; 2406 2407 if (dev->fw.opensource) { 2408 u16 fwcapa; 2409 2410 /* Patchlevel info is encoded in the "time" field. */ 2411 dev->fw.patch = fwtime; 2412 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n", 2413 dev->fw.rev, dev->fw.patch); 2414 2415 fwcapa = b43_fwcapa_read(dev); 2416 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) { 2417 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n"); 2418 /* Disable hardware crypto and fall back to software crypto. */ 2419 dev->hwcrypto_enabled = 0; 2420 } 2421 if (!(fwcapa & B43_FWCAPA_QOS)) { 2422 b43info(dev->wl, "QoS not supported by firmware\n"); 2423 /* Disable QoS. Tweak hw->queues to 1. It will be restored before 2424 * ieee80211_unregister to make sure the networking core can 2425 * properly free possible resources. */ 2426 dev->wl->hw->queues = 1; 2427 dev->qos_enabled = 0; 2428 } 2429 } else { 2430 b43info(dev->wl, "Loading firmware version %u.%u " 2431 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 2432 fwrev, fwpatch, 2433 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 2434 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 2435 if (dev->fw.pcm_request_failed) { 2436 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. " 2437 "Hardware accelerated cryptography is disabled.\n"); 2438 b43_print_fw_helptext(dev->wl, 0); 2439 } 2440 } 2441 2442 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", 2443 dev->fw.rev, dev->fw.patch); 2444 wiphy->hw_version = dev->dev->id.coreid; 2445 2446 if (b43_is_old_txhdr_format(dev)) { 2447 /* We're over the deadline, but we keep support for old fw 2448 * until it turns out to be in major conflict with something new. */ 2449 b43warn(dev->wl, "You are using an old firmware image. " 2450 "Support for old firmware will be removed soon " 2451 "(official deadline was July 2008).\n"); 2452 b43_print_fw_helptext(dev->wl, 0); 2453 } 2454 2455 return 0; 2456 2457error: 2458 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2459 macctl &= ~B43_MACCTL_PSM_RUN; 2460 macctl |= B43_MACCTL_PSM_JMP0; 2461 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2462 2463 return err; 2464} 2465 2466static int b43_write_initvals(struct b43_wldev *dev, 2467 const struct b43_iv *ivals, 2468 size_t count, 2469 size_t array_size) 2470{ 2471 const struct b43_iv *iv; 2472 u16 offset; 2473 size_t i; 2474 bool bit32; 2475 2476 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 2477 iv = ivals; 2478 for (i = 0; i < count; i++) { 2479 if (array_size < sizeof(iv->offset_size)) 2480 goto err_format; 2481 array_size -= sizeof(iv->offset_size); 2482 offset = be16_to_cpu(iv->offset_size); 2483 bit32 = !!(offset & B43_IV_32BIT); 2484 offset &= B43_IV_OFFSET_MASK; 2485 if (offset >= 0x1000) 2486 goto err_format; 2487 if (bit32) { 2488 u32 value; 2489 2490 if (array_size < sizeof(iv->data.d32)) 2491 goto err_format; 2492 array_size -= sizeof(iv->data.d32); 2493 2494 value = get_unaligned_be32(&iv->data.d32); 2495 b43_write32(dev, offset, value); 2496 2497 iv = (const struct b43_iv *)((const uint8_t *)iv + 2498 sizeof(__be16) + 2499 sizeof(__be32)); 2500 } else { 2501 u16 value; 2502 2503 if (array_size < sizeof(iv->data.d16)) 2504 goto err_format; 2505 array_size -= sizeof(iv->data.d16); 2506 2507 value = be16_to_cpu(iv->data.d16); 2508 b43_write16(dev, offset, value); 2509 2510 iv = (const struct b43_iv *)((const uint8_t *)iv + 2511 sizeof(__be16) + 2512 sizeof(__be16)); 2513 } 2514 } 2515 if (array_size) 2516 goto err_format; 2517 2518 return 0; 2519 2520err_format: 2521 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 2522 b43_print_fw_helptext(dev->wl, 1); 2523 2524 return -EPROTO; 2525} 2526 2527static int b43_upload_initvals(struct b43_wldev *dev) 2528{ 2529 const size_t hdr_len = sizeof(struct b43_fw_header); 2530 const struct b43_fw_header *hdr; 2531 struct b43_firmware *fw = &dev->fw; 2532 const struct b43_iv *ivals; 2533 size_t count; 2534 int err; 2535 2536 hdr = (const struct b43_fw_header *)(fw->initvals.data->data); 2537 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); 2538 count = be32_to_cpu(hdr->size); 2539 err = b43_write_initvals(dev, ivals, count, 2540 fw->initvals.data->size - hdr_len); 2541 if (err) 2542 goto out; 2543 if (fw->initvals_band.data) { 2544 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); 2545 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); 2546 count = be32_to_cpu(hdr->size); 2547 err = b43_write_initvals(dev, ivals, count, 2548 fw->initvals_band.data->size - hdr_len); 2549 if (err) 2550 goto out; 2551 } 2552out: 2553 2554 return err; 2555} 2556 2557/* Initialize the GPIOs 2558 * http://bcm-specs.sipsolutions.net/GPIO 2559 */ 2560static int b43_gpio_init(struct b43_wldev *dev) 2561{ 2562 struct ssb_bus *bus = dev->dev->bus; 2563 struct ssb_device *gpiodev, *pcidev = NULL; 2564 u32 mask, set; 2565 2566 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2567 & ~B43_MACCTL_GPOUTSMSK); 2568 2569 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 2570 | 0x000F); 2571 2572 mask = 0x0000001F; 2573 set = 0x0000000F; 2574 if (dev->dev->bus->chip_id == 0x4301) { 2575 mask |= 0x0060; 2576 set |= 0x0060; 2577 } 2578 if (0 /* FIXME: conditional unknown */ ) { 2579 b43_write16(dev, B43_MMIO_GPIO_MASK, 2580 b43_read16(dev, B43_MMIO_GPIO_MASK) 2581 | 0x0100); 2582 mask |= 0x0180; 2583 set |= 0x0180; 2584 } 2585 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) { 2586 b43_write16(dev, B43_MMIO_GPIO_MASK, 2587 b43_read16(dev, B43_MMIO_GPIO_MASK) 2588 | 0x0200); 2589 mask |= 0x0200; 2590 set |= 0x0200; 2591 } 2592 if (dev->dev->id.revision >= 2) 2593 mask |= 0x0010; /* FIXME: This is redundant. */ 2594 2595#ifdef CONFIG_SSB_DRIVER_PCICORE 2596 pcidev = bus->pcicore.dev; 2597#endif 2598 gpiodev = bus->chipco.dev ? : pcidev; 2599 if (!gpiodev) 2600 return 0; 2601 ssb_write32(gpiodev, B43_GPIO_CONTROL, 2602 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2603 & mask) | set); 2604 2605 return 0; 2606} 2607 2608/* Turn off all GPIO stuff. Call this on module unload, for example. */ 2609static void b43_gpio_cleanup(struct b43_wldev *dev) 2610{ 2611 struct ssb_bus *bus = dev->dev->bus; 2612 struct ssb_device *gpiodev, *pcidev = NULL; 2613 2614#ifdef CONFIG_SSB_DRIVER_PCICORE 2615 pcidev = bus->pcicore.dev; 2616#endif 2617 gpiodev = bus->chipco.dev ? : pcidev; 2618 if (!gpiodev) 2619 return; 2620 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2621} 2622 2623/* http://bcm-specs.sipsolutions.net/EnableMac */ 2624void b43_mac_enable(struct b43_wldev *dev) 2625{ 2626 if (b43_debug(dev, B43_DBG_FIRMWARE)) { 2627 u16 fwstate; 2628 2629 fwstate = b43_shm_read16(dev, B43_SHM_SHARED, 2630 B43_SHM_SH_UCODESTAT); 2631 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) && 2632 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) { 2633 b43err(dev->wl, "b43_mac_enable(): The firmware " 2634 "should be suspended, but current state is %u\n", 2635 fwstate); 2636 } 2637 } 2638 2639 dev->mac_suspended--; 2640 B43_WARN_ON(dev->mac_suspended < 0); 2641 if (dev->mac_suspended == 0) { 2642 b43_write32(dev, B43_MMIO_MACCTL, 2643 b43_read32(dev, B43_MMIO_MACCTL) 2644 | B43_MACCTL_ENABLED); 2645 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2646 B43_IRQ_MAC_SUSPENDED); 2647 /* Commit writes */ 2648 b43_read32(dev, B43_MMIO_MACCTL); 2649 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2650 b43_power_saving_ctl_bits(dev, 0); 2651 } 2652} 2653 2654/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 2655void b43_mac_suspend(struct b43_wldev *dev) 2656{ 2657 int i; 2658 u32 tmp; 2659 2660 might_sleep(); 2661 B43_WARN_ON(dev->mac_suspended < 0); 2662 2663 if (dev->mac_suspended == 0) { 2664 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2665 b43_write32(dev, B43_MMIO_MACCTL, 2666 b43_read32(dev, B43_MMIO_MACCTL) 2667 & ~B43_MACCTL_ENABLED); 2668 /* force pci to flush the write */ 2669 b43_read32(dev, B43_MMIO_MACCTL); 2670 for (i = 35; i; i--) { 2671 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2672 if (tmp & B43_IRQ_MAC_SUSPENDED) 2673 goto out; 2674 udelay(10); 2675 } 2676 /* Hm, it seems this will take some time. Use msleep(). */ 2677 for (i = 40; i; i--) { 2678 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2679 if (tmp & B43_IRQ_MAC_SUSPENDED) 2680 goto out; 2681 msleep(1); 2682 } 2683 b43err(dev->wl, "MAC suspend failed\n"); 2684 } 2685out: 2686 dev->mac_suspended++; 2687} 2688 2689/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 2690void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on) 2691{ 2692 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 2693 if (on) 2694 tmslow |= B43_TMSLOW_MACPHYCLKEN; 2695 else 2696 tmslow &= ~B43_TMSLOW_MACPHYCLKEN; 2697 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 2698} 2699 2700static void b43_adjust_opmode(struct b43_wldev *dev) 2701{ 2702 struct b43_wl *wl = dev->wl; 2703 u32 ctl; 2704 u16 cfp_pretbtt; 2705 2706 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2707 /* Reset status to STA infrastructure mode. */ 2708 ctl &= ~B43_MACCTL_AP; 2709 ctl &= ~B43_MACCTL_KEEP_CTL; 2710 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2711 ctl &= ~B43_MACCTL_KEEP_BAD; 2712 ctl &= ~B43_MACCTL_PROMISC; 2713 ctl &= ~B43_MACCTL_BEACPROMISC; 2714 ctl |= B43_MACCTL_INFRA; 2715 2716 if (b43_is_mode(wl, NL80211_IFTYPE_AP) || 2717 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 2718 ctl |= B43_MACCTL_AP; 2719 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 2720 ctl &= ~B43_MACCTL_INFRA; 2721 2722 if (wl->filter_flags & FIF_CONTROL) 2723 ctl |= B43_MACCTL_KEEP_CTL; 2724 if (wl->filter_flags & FIF_FCSFAIL) 2725 ctl |= B43_MACCTL_KEEP_BAD; 2726 if (wl->filter_flags & FIF_PLCPFAIL) 2727 ctl |= B43_MACCTL_KEEP_BADPLCP; 2728 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2729 ctl |= B43_MACCTL_PROMISC; 2730 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2731 ctl |= B43_MACCTL_BEACPROMISC; 2732 2733 /* Workaround: On old hardware the HW-MAC-address-filter 2734 * doesn't work properly, so always run promisc in filter 2735 * it in software. */ 2736 if (dev->dev->id.revision <= 4) 2737 ctl |= B43_MACCTL_PROMISC; 2738 2739 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2740 2741 cfp_pretbtt = 2; 2742 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2743 if (dev->dev->bus->chip_id == 0x4306 && 2744 dev->dev->bus->chip_rev == 3) 2745 cfp_pretbtt = 100; 2746 else 2747 cfp_pretbtt = 50; 2748 } 2749 b43_write16(dev, 0x612, cfp_pretbtt); 2750 2751 /* FIXME: We don't currently implement the PMQ mechanism, 2752 * so always disable it. If we want to implement PMQ, 2753 * we need to enable it here (clear DISCPMQ) in AP mode. 2754 */ 2755 if (0 /* ctl & B43_MACCTL_AP */) { 2756 b43_write32(dev, B43_MMIO_MACCTL, 2757 b43_read32(dev, B43_MMIO_MACCTL) 2758 & ~B43_MACCTL_DISCPMQ); 2759 } else { 2760 b43_write32(dev, B43_MMIO_MACCTL, 2761 b43_read32(dev, B43_MMIO_MACCTL) 2762 | B43_MACCTL_DISCPMQ); 2763 } 2764} 2765 2766static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2767{ 2768 u16 offset; 2769 2770 if (is_ofdm) { 2771 offset = 0x480; 2772 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2773 } else { 2774 offset = 0x4C0; 2775 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2776 } 2777 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2778 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2779} 2780 2781static void b43_rate_memory_init(struct b43_wldev *dev) 2782{ 2783 switch (dev->phy.type) { 2784 case B43_PHYTYPE_A: 2785 case B43_PHYTYPE_G: 2786 case B43_PHYTYPE_N: 2787 case B43_PHYTYPE_LP: 2788 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2789 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2790 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2791 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2792 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2793 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2794 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2795 if (dev->phy.type == B43_PHYTYPE_A) 2796 break; 2797 /* fallthrough */ 2798 case B43_PHYTYPE_B: 2799 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2800 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2801 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2802 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2803 break; 2804 default: 2805 B43_WARN_ON(1); 2806 } 2807} 2808 2809/* Set the default values for the PHY TX Control Words. */ 2810static void b43_set_phytxctl_defaults(struct b43_wldev *dev) 2811{ 2812 u16 ctl = 0; 2813 2814 ctl |= B43_TXH_PHY_ENC_CCK; 2815 ctl |= B43_TXH_PHY_ANT01AUTO; 2816 ctl |= B43_TXH_PHY_TXPWR; 2817 2818 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 2819 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); 2820 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); 2821} 2822 2823/* Set the TX-Antenna for management frames sent by firmware. */ 2824static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2825{ 2826 u16 ant; 2827 u16 tmp; 2828 2829 ant = b43_antenna_to_phyctl(antenna); 2830 2831 /* For ACK/CTS */ 2832 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2833 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2834 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2835 /* For Probe Resposes */ 2836 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2837 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 2838 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2839} 2840 2841/* This is the opposite of b43_chip_init() */ 2842static void b43_chip_exit(struct b43_wldev *dev) 2843{ 2844 b43_phy_exit(dev); 2845 b43_gpio_cleanup(dev); 2846 /* firmware is released later */ 2847} 2848 2849/* Initialize the chip 2850 * http://bcm-specs.sipsolutions.net/ChipInit 2851 */ 2852static int b43_chip_init(struct b43_wldev *dev) 2853{ 2854 struct b43_phy *phy = &dev->phy; 2855 int err; 2856 u32 macctl; 2857 u16 value16; 2858 2859 /* Initialize the MAC control */ 2860 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; 2861 if (dev->phy.gmode) 2862 macctl |= B43_MACCTL_GMODE; 2863 macctl |= B43_MACCTL_INFRA; 2864 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2865 2866 err = b43_request_firmware(dev); 2867 if (err) 2868 goto out; 2869 err = b43_upload_microcode(dev); 2870 if (err) 2871 goto out; /* firmware is released later */ 2872 2873 err = b43_gpio_init(dev); 2874 if (err) 2875 goto out; /* firmware is released later */ 2876 2877 err = b43_upload_initvals(dev); 2878 if (err) 2879 goto err_gpio_clean; 2880 2881 /* Turn the Analog on and initialize the PHY. */ 2882 phy->ops->switch_analog(dev, 1); 2883 err = b43_phy_init(dev); 2884 if (err) 2885 goto err_gpio_clean; 2886 2887 /* Disable Interference Mitigation. */ 2888 if (phy->ops->interf_mitigation) 2889 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); 2890 2891 /* Select the antennae */ 2892 if (phy->ops->set_rx_antenna) 2893 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2894 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2895 2896 if (phy->type == B43_PHYTYPE_B) { 2897 value16 = b43_read16(dev, 0x005E); 2898 value16 |= 0x0004; 2899 b43_write16(dev, 0x005E, value16); 2900 } 2901 b43_write32(dev, 0x0100, 0x01000000); 2902 if (dev->dev->id.revision < 5) 2903 b43_write32(dev, 0x010C, 0x01000000); 2904 2905 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2906 & ~B43_MACCTL_INFRA); 2907 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2908 | B43_MACCTL_INFRA); 2909 2910 /* Probe Response Timeout value */ 2911 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2912 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2913 2914 /* Initially set the wireless operation mode. */ 2915 b43_adjust_opmode(dev); 2916 2917 if (dev->dev->id.revision < 3) { 2918 b43_write16(dev, 0x060E, 0x0000); 2919 b43_write16(dev, 0x0610, 0x8000); 2920 b43_write16(dev, 0x0604, 0x0000); 2921 b43_write16(dev, 0x0606, 0x0200); 2922 } else { 2923 b43_write32(dev, 0x0188, 0x80000000); 2924 b43_write32(dev, 0x018C, 0x02000000); 2925 } 2926 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2927 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2928 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2929 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2930 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2931 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2932 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2933 2934 b43_mac_phy_clock_set(dev, true); 2935 2936 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2937 dev->dev->bus->chipco.fast_pwrup_delay); 2938 2939 err = 0; 2940 b43dbg(dev->wl, "Chip initialized\n"); 2941out: 2942 return err; 2943 2944err_gpio_clean: 2945 b43_gpio_cleanup(dev); 2946 return err; 2947} 2948 2949static void b43_periodic_every60sec(struct b43_wldev *dev) 2950{ 2951 const struct b43_phy_operations *ops = dev->phy.ops; 2952 2953 if (ops->pwork_60sec) 2954 ops->pwork_60sec(dev); 2955 2956 /* Force check the TX power emission now. */ 2957 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME); 2958} 2959 2960static void b43_periodic_every30sec(struct b43_wldev *dev) 2961{ 2962 /* Update device statistics. */ 2963 b43_calculate_link_quality(dev); 2964} 2965 2966static void b43_periodic_every15sec(struct b43_wldev *dev) 2967{ 2968 struct b43_phy *phy = &dev->phy; 2969 u16 wdr; 2970 2971 if (dev->fw.opensource) { 2972 /* Check if the firmware is still alive. 2973 * It will reset the watchdog counter to 0 in its idle loop. */ 2974 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG); 2975 if (unlikely(wdr)) { 2976 b43err(dev->wl, "Firmware watchdog: The firmware died!\n"); 2977 b43_controller_restart(dev, "Firmware watchdog"); 2978 return; 2979 } else { 2980 b43_shm_write16(dev, B43_SHM_SCRATCH, 2981 B43_WATCHDOG_REG, 1); 2982 } 2983 } 2984 2985 if (phy->ops->pwork_15sec) 2986 phy->ops->pwork_15sec(dev); 2987 2988 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 2989 wmb(); 2990 2991#if B43_DEBUG 2992 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 2993 unsigned int i; 2994 2995 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n", 2996 dev->irq_count / 15, 2997 dev->tx_count / 15, 2998 dev->rx_count / 15); 2999 dev->irq_count = 0; 3000 dev->tx_count = 0; 3001 dev->rx_count = 0; 3002 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 3003 if (dev->irq_bit_count[i]) { 3004 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", 3005 dev->irq_bit_count[i] / 15, i, (1 << i)); 3006 dev->irq_bit_count[i] = 0; 3007 } 3008 } 3009 } 3010#endif 3011} 3012 3013static void do_periodic_work(struct b43_wldev *dev) 3014{ 3015 unsigned int state; 3016 3017 state = dev->periodic_state; 3018 if (state % 4 == 0) 3019 b43_periodic_every60sec(dev); 3020 if (state % 2 == 0) 3021 b43_periodic_every30sec(dev); 3022 b43_periodic_every15sec(dev); 3023} 3024 3025/* Periodic work locking policy: 3026 * The whole periodic work handler is protected by 3027 * wl->mutex. If another lock is needed somewhere in the 3028 * pwork callchain, it's acquired in-place, where it's needed. 3029 */ 3030static void b43_periodic_work_handler(struct work_struct *work) 3031{ 3032 struct b43_wldev *dev = container_of(work, struct b43_wldev, 3033 periodic_work.work); 3034 struct b43_wl *wl = dev->wl; 3035 unsigned long delay; 3036 3037 mutex_lock(&wl->mutex); 3038 3039 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 3040 goto out; 3041 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 3042 goto out_requeue; 3043 3044 do_periodic_work(dev); 3045 3046 dev->periodic_state++; 3047out_requeue: 3048 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 3049 delay = msecs_to_jiffies(50); 3050 else 3051 delay = round_jiffies_relative(HZ * 15); 3052 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); 3053out: 3054 mutex_unlock(&wl->mutex); 3055} 3056 3057static void b43_periodic_tasks_setup(struct b43_wldev *dev) 3058{ 3059 struct delayed_work *work = &dev->periodic_work; 3060 3061 dev->periodic_state = 0; 3062 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 3063 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); 3064} 3065 3066/* Check if communication with the device works correctly. */ 3067static int b43_validate_chipaccess(struct b43_wldev *dev) 3068{ 3069 u32 v, backup0, backup4; 3070 3071 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); 3072 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4); 3073 3074 /* Check for read/write and endianness problems. */ 3075 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 3076 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 3077 goto error; 3078 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 3079 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 3080 goto error; 3081 3082 /* Check if unaligned 32bit SHM_SHARED access works properly. 3083 * However, don't bail out on failure, because it's noncritical. */ 3084 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); 3085 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); 3086 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); 3087 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); 3088 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) 3089 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n"); 3090 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); 3091 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || 3092 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || 3093 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || 3094 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) 3095 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n"); 3096 3097 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); 3098 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); 3099 3100 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) { 3101 /* The 32bit register shadows the two 16bit registers 3102 * with update sideeffects. Validate this. */ 3103 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 3104 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 3105 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 3106 goto error; 3107 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 3108 goto error; 3109 } 3110 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 3111 3112 v = b43_read32(dev, B43_MMIO_MACCTL); 3113 v |= B43_MACCTL_GMODE; 3114 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 3115 goto error; 3116 3117 return 0; 3118error: 3119 b43err(dev->wl, "Failed to validate the chipaccess\n"); 3120 return -ENODEV; 3121} 3122 3123static void b43_security_init(struct b43_wldev *dev) 3124{ 3125 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 3126 /* KTP is a word address, but we address SHM bytewise. 3127 * So multiply by two. 3128 */ 3129 dev->ktp *= 2; 3130 /* Number of RCMTA address slots */ 3131 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS); 3132 /* Clear the key memory. */ 3133 b43_clear_keys(dev); 3134} 3135 3136#ifdef CONFIG_B43_HWRNG 3137static int b43_rng_read(struct hwrng *rng, u32 *data) 3138{ 3139 struct b43_wl *wl = (struct b43_wl *)rng->priv; 3140 struct b43_wldev *dev; 3141 int count = -ENODEV; 3142 3143 mutex_lock(&wl->mutex); 3144 dev = wl->current_dev; 3145 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) { 3146 *data = b43_read16(dev, B43_MMIO_RNG); 3147 count = sizeof(u16); 3148 } 3149 mutex_unlock(&wl->mutex); 3150 3151 return count; 3152} 3153#endif /* CONFIG_B43_HWRNG */ 3154 3155static void b43_rng_exit(struct b43_wl *wl) 3156{ 3157#ifdef CONFIG_B43_HWRNG 3158 if (wl->rng_initialized) 3159 hwrng_unregister(&wl->rng); 3160#endif /* CONFIG_B43_HWRNG */ 3161} 3162 3163static int b43_rng_init(struct b43_wl *wl) 3164{ 3165 int err = 0; 3166 3167#ifdef CONFIG_B43_HWRNG 3168 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 3169 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 3170 wl->rng.name = wl->rng_name; 3171 wl->rng.data_read = b43_rng_read; 3172 wl->rng.priv = (unsigned long)wl; 3173 wl->rng_initialized = 1; 3174 err = hwrng_register(&wl->rng); 3175 if (err) { 3176 wl->rng_initialized = 0; 3177 b43err(wl, "Failed to register the random " 3178 "number generator (%d)\n", err); 3179 } 3180#endif /* CONFIG_B43_HWRNG */ 3181 3182 return err; 3183} 3184 3185static void b43_tx_work(struct work_struct *work) 3186{ 3187 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work); 3188 struct b43_wldev *dev; 3189 struct sk_buff *skb; 3190 int err = 0; 3191 3192 mutex_lock(&wl->mutex); 3193 dev = wl->current_dev; 3194 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) { 3195 mutex_unlock(&wl->mutex); 3196 return; 3197 } 3198 3199 while (skb_queue_len(&wl->tx_queue)) { 3200 skb = skb_dequeue(&wl->tx_queue); 3201 3202 if (b43_using_pio_transfers(dev)) 3203 err = b43_pio_tx(dev, skb); 3204 else 3205 err = b43_dma_tx(dev, skb); 3206 if (unlikely(err)) 3207 dev_kfree_skb(skb); /* Drop it */ 3208 } 3209 3210#if B43_DEBUG 3211 dev->tx_count++; 3212#endif 3213 mutex_unlock(&wl->mutex); 3214} 3215 3216static void b43_op_tx(struct ieee80211_hw *hw, 3217 struct sk_buff *skb) 3218{ 3219 struct b43_wl *wl = hw_to_b43_wl(hw); 3220 3221 if (unlikely(skb->len < 2 + 2 + 6)) { 3222 /* Too short, this can't be a valid frame. */ 3223 dev_kfree_skb_any(skb); 3224 return; 3225 } 3226 B43_WARN_ON(skb_shinfo(skb)->nr_frags); 3227 3228 skb_queue_tail(&wl->tx_queue, skb); 3229 ieee80211_queue_work(wl->hw, &wl->tx_work); 3230} 3231 3232static void b43_qos_params_upload(struct b43_wldev *dev, 3233 const struct ieee80211_tx_queue_params *p, 3234 u16 shm_offset) 3235{ 3236 u16 params[B43_NR_QOSPARAMS]; 3237 int bslots, tmp; 3238 unsigned int i; 3239 3240 if (!dev->qos_enabled) 3241 return; 3242 3243 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min; 3244 3245 memset(¶ms, 0, sizeof(params)); 3246 3247 params[B43_QOSPARAM_TXOP] = p->txop * 32; 3248 params[B43_QOSPARAM_CWMIN] = p->cw_min; 3249 params[B43_QOSPARAM_CWMAX] = p->cw_max; 3250 params[B43_QOSPARAM_CWCUR] = p->cw_min; 3251 params[B43_QOSPARAM_AIFS] = p->aifs; 3252 params[B43_QOSPARAM_BSLOTS] = bslots; 3253 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs; 3254 3255 for (i = 0; i < ARRAY_SIZE(params); i++) { 3256 if (i == B43_QOSPARAM_STATUS) { 3257 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 3258 shm_offset + (i * 2)); 3259 /* Mark the parameters as updated. */ 3260 tmp |= 0x100; 3261 b43_shm_write16(dev, B43_SHM_SHARED, 3262 shm_offset + (i * 2), 3263 tmp); 3264 } else { 3265 b43_shm_write16(dev, B43_SHM_SHARED, 3266 shm_offset + (i * 2), 3267 params[i]); 3268 } 3269 } 3270} 3271 3272/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */ 3273static const u16 b43_qos_shm_offsets[] = { 3274 /* [mac80211-queue-nr] = SHM_OFFSET, */ 3275 [0] = B43_QOS_VOICE, 3276 [1] = B43_QOS_VIDEO, 3277 [2] = B43_QOS_BESTEFFORT, 3278 [3] = B43_QOS_BACKGROUND, 3279}; 3280 3281/* Update all QOS parameters in hardware. */ 3282static void b43_qos_upload_all(struct b43_wldev *dev) 3283{ 3284 struct b43_wl *wl = dev->wl; 3285 struct b43_qos_params *params; 3286 unsigned int i; 3287 3288 if (!dev->qos_enabled) 3289 return; 3290 3291 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3292 ARRAY_SIZE(wl->qos_params)); 3293 3294 b43_mac_suspend(dev); 3295 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3296 params = &(wl->qos_params[i]); 3297 b43_qos_params_upload(dev, &(params->p), 3298 b43_qos_shm_offsets[i]); 3299 } 3300 b43_mac_enable(dev); 3301} 3302 3303static void b43_qos_clear(struct b43_wl *wl) 3304{ 3305 struct b43_qos_params *params; 3306 unsigned int i; 3307 3308 /* Initialize QoS parameters to sane defaults. */ 3309 3310 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3311 ARRAY_SIZE(wl->qos_params)); 3312 3313 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3314 params = &(wl->qos_params[i]); 3315 3316 switch (b43_qos_shm_offsets[i]) { 3317 case B43_QOS_VOICE: 3318 params->p.txop = 0; 3319 params->p.aifs = 2; 3320 params->p.cw_min = 0x0001; 3321 params->p.cw_max = 0x0001; 3322 break; 3323 case B43_QOS_VIDEO: 3324 params->p.txop = 0; 3325 params->p.aifs = 2; 3326 params->p.cw_min = 0x0001; 3327 params->p.cw_max = 0x0001; 3328 break; 3329 case B43_QOS_BESTEFFORT: 3330 params->p.txop = 0; 3331 params->p.aifs = 3; 3332 params->p.cw_min = 0x0001; 3333 params->p.cw_max = 0x03FF; 3334 break; 3335 case B43_QOS_BACKGROUND: 3336 params->p.txop = 0; 3337 params->p.aifs = 7; 3338 params->p.cw_min = 0x0001; 3339 params->p.cw_max = 0x03FF; 3340 break; 3341 default: 3342 B43_WARN_ON(1); 3343 } 3344 } 3345} 3346 3347/* Initialize the core's QOS capabilities */ 3348static void b43_qos_init(struct b43_wldev *dev) 3349{ 3350 if (!dev->qos_enabled) { 3351 /* Disable QOS support. */ 3352 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF); 3353 b43_write16(dev, B43_MMIO_IFSCTL, 3354 b43_read16(dev, B43_MMIO_IFSCTL) 3355 & ~B43_MMIO_IFSCTL_USE_EDCF); 3356 b43dbg(dev->wl, "QoS disabled\n"); 3357 return; 3358 } 3359 3360 /* Upload the current QOS parameters. */ 3361 b43_qos_upload_all(dev); 3362 3363 /* Enable QOS support. */ 3364 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); 3365 b43_write16(dev, B43_MMIO_IFSCTL, 3366 b43_read16(dev, B43_MMIO_IFSCTL) 3367 | B43_MMIO_IFSCTL_USE_EDCF); 3368 b43dbg(dev->wl, "QoS enabled\n"); 3369} 3370 3371static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue, 3372 const struct ieee80211_tx_queue_params *params) 3373{ 3374 struct b43_wl *wl = hw_to_b43_wl(hw); 3375 struct b43_wldev *dev; 3376 unsigned int queue = (unsigned int)_queue; 3377 int err = -ENODEV; 3378 3379 if (queue >= ARRAY_SIZE(wl->qos_params)) { 3380 /* Queue not available or don't support setting 3381 * params on this queue. Return success to not 3382 * confuse mac80211. */ 3383 return 0; 3384 } 3385 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3386 ARRAY_SIZE(wl->qos_params)); 3387 3388 mutex_lock(&wl->mutex); 3389 dev = wl->current_dev; 3390 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) 3391 goto out_unlock; 3392 3393 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params)); 3394 b43_mac_suspend(dev); 3395 b43_qos_params_upload(dev, &(wl->qos_params[queue].p), 3396 b43_qos_shm_offsets[queue]); 3397 b43_mac_enable(dev); 3398 err = 0; 3399 3400out_unlock: 3401 mutex_unlock(&wl->mutex); 3402 3403 return err; 3404} 3405 3406static int b43_op_get_stats(struct ieee80211_hw *hw, 3407 struct ieee80211_low_level_stats *stats) 3408{ 3409 struct b43_wl *wl = hw_to_b43_wl(hw); 3410 3411 mutex_lock(&wl->mutex); 3412 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 3413 mutex_unlock(&wl->mutex); 3414 3415 return 0; 3416} 3417 3418static u64 b43_op_get_tsf(struct ieee80211_hw *hw) 3419{ 3420 struct b43_wl *wl = hw_to_b43_wl(hw); 3421 struct b43_wldev *dev; 3422 u64 tsf; 3423 3424 mutex_lock(&wl->mutex); 3425 dev = wl->current_dev; 3426 3427 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3428 b43_tsf_read(dev, &tsf); 3429 else 3430 tsf = 0; 3431 3432 mutex_unlock(&wl->mutex); 3433 3434 return tsf; 3435} 3436 3437static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3438{ 3439 struct b43_wl *wl = hw_to_b43_wl(hw); 3440 struct b43_wldev *dev; 3441 3442 mutex_lock(&wl->mutex); 3443 dev = wl->current_dev; 3444 3445 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3446 b43_tsf_write(dev, tsf); 3447 3448 mutex_unlock(&wl->mutex); 3449} 3450 3451static void b43_put_phy_into_reset(struct b43_wldev *dev) 3452{ 3453 struct ssb_device *sdev = dev->dev; 3454 u32 tmslow; 3455 3456 tmslow = ssb_read32(sdev, SSB_TMSLOW); 3457 tmslow &= ~B43_TMSLOW_GMODE; 3458 tmslow |= B43_TMSLOW_PHYRESET; 3459 tmslow |= SSB_TMSLOW_FGC; 3460 ssb_write32(sdev, SSB_TMSLOW, tmslow); 3461 msleep(1); 3462 3463 tmslow = ssb_read32(sdev, SSB_TMSLOW); 3464 tmslow &= ~SSB_TMSLOW_FGC; 3465 tmslow |= B43_TMSLOW_PHYRESET; 3466 ssb_write32(sdev, SSB_TMSLOW, tmslow); 3467 msleep(1); 3468} 3469 3470static const char *band_to_string(enum ieee80211_band band) 3471{ 3472 switch (band) { 3473 case IEEE80211_BAND_5GHZ: 3474 return "5"; 3475 case IEEE80211_BAND_2GHZ: 3476 return "2.4"; 3477 default: 3478 break; 3479 } 3480 B43_WARN_ON(1); 3481 return ""; 3482} 3483 3484/* Expects wl->mutex locked */ 3485static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan) 3486{ 3487 struct b43_wldev *up_dev = NULL; 3488 struct b43_wldev *down_dev; 3489 struct b43_wldev *d; 3490 int err; 3491 bool uninitialized_var(gmode); 3492 int prev_status; 3493 3494 /* Find a device and PHY which supports the band. */ 3495 list_for_each_entry(d, &wl->devlist, list) { 3496 switch (chan->band) { 3497 case IEEE80211_BAND_5GHZ: 3498 if (d->phy.supports_5ghz) { 3499 up_dev = d; 3500 gmode = 0; 3501 } 3502 break; 3503 case IEEE80211_BAND_2GHZ: 3504 if (d->phy.supports_2ghz) { 3505 up_dev = d; 3506 gmode = 1; 3507 } 3508 break; 3509 default: 3510 B43_WARN_ON(1); 3511 return -EINVAL; 3512 } 3513 if (up_dev) 3514 break; 3515 } 3516 if (!up_dev) { 3517 b43err(wl, "Could not find a device for %s-GHz band operation\n", 3518 band_to_string(chan->band)); 3519 return -ENODEV; 3520 } 3521 if ((up_dev == wl->current_dev) && 3522 (!!wl->current_dev->phy.gmode == !!gmode)) { 3523 /* This device is already running. */ 3524 return 0; 3525 } 3526 b43dbg(wl, "Switching to %s-GHz band\n", 3527 band_to_string(chan->band)); 3528 down_dev = wl->current_dev; 3529 3530 prev_status = b43_status(down_dev); 3531 /* Shutdown the currently running core. */ 3532 if (prev_status >= B43_STAT_STARTED) 3533 down_dev = b43_wireless_core_stop(down_dev); 3534 if (prev_status >= B43_STAT_INITIALIZED) 3535 b43_wireless_core_exit(down_dev); 3536 3537 if (down_dev != up_dev) { 3538 /* We switch to a different core, so we put PHY into 3539 * RESET on the old core. */ 3540 b43_put_phy_into_reset(down_dev); 3541 } 3542 3543 /* Now start the new core. */ 3544 up_dev->phy.gmode = gmode; 3545 if (prev_status >= B43_STAT_INITIALIZED) { 3546 err = b43_wireless_core_init(up_dev); 3547 if (err) { 3548 b43err(wl, "Fatal: Could not initialize device for " 3549 "selected %s-GHz band\n", 3550 band_to_string(chan->band)); 3551 goto init_failure; 3552 } 3553 } 3554 if (prev_status >= B43_STAT_STARTED) { 3555 err = b43_wireless_core_start(up_dev); 3556 if (err) { 3557 b43err(wl, "Fatal: Coult not start device for " 3558 "selected %s-GHz band\n", 3559 band_to_string(chan->band)); 3560 b43_wireless_core_exit(up_dev); 3561 goto init_failure; 3562 } 3563 } 3564 B43_WARN_ON(b43_status(up_dev) != prev_status); 3565 3566 wl->current_dev = up_dev; 3567 3568 return 0; 3569init_failure: 3570 /* Whoops, failed to init the new core. No core is operating now. */ 3571 wl->current_dev = NULL; 3572 return err; 3573} 3574 3575/* Write the short and long frame retry limit values. */ 3576static void b43_set_retry_limits(struct b43_wldev *dev, 3577 unsigned int short_retry, 3578 unsigned int long_retry) 3579{ 3580 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3581 * the chip-internal counter. */ 3582 short_retry = min(short_retry, (unsigned int)0xF); 3583 long_retry = min(long_retry, (unsigned int)0xF); 3584 3585 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3586 short_retry); 3587 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3588 long_retry); 3589} 3590 3591static int b43_op_config(struct ieee80211_hw *hw, u32 changed) 3592{ 3593 struct b43_wl *wl = hw_to_b43_wl(hw); 3594 struct b43_wldev *dev; 3595 struct b43_phy *phy; 3596 struct ieee80211_conf *conf = &hw->conf; 3597 int antenna; 3598 int err = 0; 3599 3600 mutex_lock(&wl->mutex); 3601 3602 /* Switch the band (if necessary). This might change the active core. */ 3603 err = b43_switch_band(wl, conf->channel); 3604 if (err) 3605 goto out_unlock_mutex; 3606 dev = wl->current_dev; 3607 phy = &dev->phy; 3608 3609 if (conf_is_ht(conf)) 3610 phy->is_40mhz = 3611 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf)); 3612 else 3613 phy->is_40mhz = false; 3614 3615 b43_mac_suspend(dev); 3616 3617 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 3618 b43_set_retry_limits(dev, conf->short_frame_max_tx_count, 3619 conf->long_frame_max_tx_count); 3620 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; 3621 if (!changed) 3622 goto out_mac_enable; 3623 3624 /* Switch to the requested channel. 3625 * The firmware takes care of races with the TX handler. */ 3626 if (conf->channel->hw_value != phy->channel) 3627 b43_switch_channel(dev, conf->channel->hw_value); 3628 3629 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 3630 3631 /* Adjust the desired TX power level. */ 3632 if (conf->power_level != 0) { 3633 if (conf->power_level != phy->desired_txpower) { 3634 phy->desired_txpower = conf->power_level; 3635 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME | 3636 B43_TXPWR_IGNORE_TSSI); 3637 } 3638 } 3639 3640 /* Antennas for RX and management frame TX. */ 3641 antenna = B43_ANTENNA_DEFAULT; 3642 b43_mgmtframe_txantenna(dev, antenna); 3643 antenna = B43_ANTENNA_DEFAULT; 3644 if (phy->ops->set_rx_antenna) 3645 phy->ops->set_rx_antenna(dev, antenna); 3646 3647 if (wl->radio_enabled != phy->radio_on) { 3648 if (wl->radio_enabled) { 3649 b43_software_rfkill(dev, false); 3650 b43info(dev->wl, "Radio turned on by software\n"); 3651 if (!dev->radio_hw_enable) { 3652 b43info(dev->wl, "The hardware RF-kill button " 3653 "still turns the radio physically off. " 3654 "Press the button to turn it on.\n"); 3655 } 3656 } else { 3657 b43_software_rfkill(dev, true); 3658 b43info(dev->wl, "Radio turned off by software\n"); 3659 } 3660 } 3661 3662out_mac_enable: 3663 b43_mac_enable(dev); 3664out_unlock_mutex: 3665 mutex_unlock(&wl->mutex); 3666 3667 return err; 3668} 3669 3670static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates) 3671{ 3672 struct ieee80211_supported_band *sband = 3673 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)]; 3674 struct ieee80211_rate *rate; 3675 int i; 3676 u16 basic, direct, offset, basic_offset, rateptr; 3677 3678 for (i = 0; i < sband->n_bitrates; i++) { 3679 rate = &sband->bitrates[i]; 3680 3681 if (b43_is_cck_rate(rate->hw_value)) { 3682 direct = B43_SHM_SH_CCKDIRECT; 3683 basic = B43_SHM_SH_CCKBASIC; 3684 offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3685 offset &= 0xF; 3686 } else { 3687 direct = B43_SHM_SH_OFDMDIRECT; 3688 basic = B43_SHM_SH_OFDMBASIC; 3689 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3690 offset &= 0xF; 3691 } 3692 3693 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); 3694 3695 if (b43_is_cck_rate(rate->hw_value)) { 3696 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value); 3697 basic_offset &= 0xF; 3698 } else { 3699 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 3700 basic_offset &= 0xF; 3701 } 3702 3703 /* 3704 * Get the pointer that we need to point to 3705 * from the direct map 3706 */ 3707 rateptr = b43_shm_read16(dev, B43_SHM_SHARED, 3708 direct + 2 * basic_offset); 3709 /* and write it to the basic map */ 3710 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset, 3711 rateptr); 3712 } 3713} 3714 3715static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 3716 struct ieee80211_vif *vif, 3717 struct ieee80211_bss_conf *conf, 3718 u32 changed) 3719{ 3720 struct b43_wl *wl = hw_to_b43_wl(hw); 3721 struct b43_wldev *dev; 3722 3723 mutex_lock(&wl->mutex); 3724 3725 dev = wl->current_dev; 3726 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3727 goto out_unlock_mutex; 3728 3729 B43_WARN_ON(wl->vif != vif); 3730 3731 if (changed & BSS_CHANGED_BSSID) { 3732 if (conf->bssid) 3733 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 3734 else 3735 memset(wl->bssid, 0, ETH_ALEN); 3736 } 3737 3738 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 3739 if (changed & BSS_CHANGED_BEACON && 3740 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3741 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3742 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3743 b43_update_templates(wl); 3744 3745 if (changed & BSS_CHANGED_BSSID) 3746 b43_write_mac_bssid_templates(dev); 3747 } 3748 3749 b43_mac_suspend(dev); 3750 3751 /* Update templates for AP/mesh mode. */ 3752 if (changed & BSS_CHANGED_BEACON_INT && 3753 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3754 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 3755 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 3756 b43_set_beacon_int(dev, conf->beacon_int); 3757 3758 if (changed & BSS_CHANGED_BASIC_RATES) 3759 b43_update_basic_rates(dev, conf->basic_rates); 3760 3761 if (changed & BSS_CHANGED_ERP_SLOT) { 3762 if (conf->use_short_slot) 3763 b43_short_slot_timing_enable(dev); 3764 else 3765 b43_short_slot_timing_disable(dev); 3766 } 3767 3768 b43_mac_enable(dev); 3769out_unlock_mutex: 3770 mutex_unlock(&wl->mutex); 3771} 3772 3773static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3774 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3775 struct ieee80211_key_conf *key) 3776{ 3777 struct b43_wl *wl = hw_to_b43_wl(hw); 3778 struct b43_wldev *dev; 3779 u8 algorithm; 3780 u8 index; 3781 int err; 3782 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3783 3784 if (modparam_nohwcrypt) 3785 return -ENOSPC; /* User disabled HW-crypto */ 3786 3787 mutex_lock(&wl->mutex); 3788 3789 dev = wl->current_dev; 3790 err = -ENODEV; 3791 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 3792 goto out_unlock; 3793 3794 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) { 3795 /* We don't have firmware for the crypto engine. 3796 * Must use software-crypto. */ 3797 err = -EOPNOTSUPP; 3798 goto out_unlock; 3799 } 3800 3801 err = -EINVAL; 3802 switch (key->cipher) { 3803 case WLAN_CIPHER_SUITE_WEP40: 3804 algorithm = B43_SEC_ALGO_WEP40; 3805 break; 3806 case WLAN_CIPHER_SUITE_WEP104: 3807 algorithm = B43_SEC_ALGO_WEP104; 3808 break; 3809 case WLAN_CIPHER_SUITE_TKIP: 3810 algorithm = B43_SEC_ALGO_TKIP; 3811 break; 3812 case WLAN_CIPHER_SUITE_CCMP: 3813 algorithm = B43_SEC_ALGO_AES; 3814 break; 3815 default: 3816 B43_WARN_ON(1); 3817 goto out_unlock; 3818 } 3819 index = (u8) (key->keyidx); 3820 if (index > 3) 3821 goto out_unlock; 3822 3823 switch (cmd) { 3824 case SET_KEY: 3825 if (algorithm == B43_SEC_ALGO_TKIP && 3826 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) || 3827 !modparam_hwtkip)) { 3828 /* We support only pairwise key */ 3829 err = -EOPNOTSUPP; 3830 goto out_unlock; 3831 } 3832 3833 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 3834 if (WARN_ON(!sta)) { 3835 err = -EOPNOTSUPP; 3836 goto out_unlock; 3837 } 3838 /* Pairwise key with an assigned MAC address. */ 3839 err = b43_key_write(dev, -1, algorithm, 3840 key->key, key->keylen, 3841 sta->addr, key); 3842 } else { 3843 /* Group key */ 3844 err = b43_key_write(dev, index, algorithm, 3845 key->key, key->keylen, NULL, key); 3846 } 3847 if (err) 3848 goto out_unlock; 3849 3850 if (algorithm == B43_SEC_ALGO_WEP40 || 3851 algorithm == B43_SEC_ALGO_WEP104) { 3852 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 3853 } else { 3854 b43_hf_write(dev, 3855 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 3856 } 3857 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 3858 if (algorithm == B43_SEC_ALGO_TKIP) 3859 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 3860 break; 3861 case DISABLE_KEY: { 3862 err = b43_key_clear(dev, key->hw_key_idx); 3863 if (err) 3864 goto out_unlock; 3865 break; 3866 } 3867 default: 3868 B43_WARN_ON(1); 3869 } 3870 3871out_unlock: 3872 if (!err) { 3873 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 3874 "mac: %pM\n", 3875 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 3876 sta ? sta->addr : bcast_addr); 3877 b43_dump_keymemory(dev); 3878 } 3879 mutex_unlock(&wl->mutex); 3880 3881 return err; 3882} 3883 3884static void b43_op_configure_filter(struct ieee80211_hw *hw, 3885 unsigned int changed, unsigned int *fflags, 3886 u64 multicast) 3887{ 3888 struct b43_wl *wl = hw_to_b43_wl(hw); 3889 struct b43_wldev *dev; 3890 3891 mutex_lock(&wl->mutex); 3892 dev = wl->current_dev; 3893 if (!dev) { 3894 *fflags = 0; 3895 goto out_unlock; 3896 } 3897 3898 *fflags &= FIF_PROMISC_IN_BSS | 3899 FIF_ALLMULTI | 3900 FIF_FCSFAIL | 3901 FIF_PLCPFAIL | 3902 FIF_CONTROL | 3903 FIF_OTHER_BSS | 3904 FIF_BCN_PRBRESP_PROMISC; 3905 3906 changed &= FIF_PROMISC_IN_BSS | 3907 FIF_ALLMULTI | 3908 FIF_FCSFAIL | 3909 FIF_PLCPFAIL | 3910 FIF_CONTROL | 3911 FIF_OTHER_BSS | 3912 FIF_BCN_PRBRESP_PROMISC; 3913 3914 wl->filter_flags = *fflags; 3915 3916 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 3917 b43_adjust_opmode(dev); 3918 3919out_unlock: 3920 mutex_unlock(&wl->mutex); 3921} 3922 3923/* Locking: wl->mutex 3924 * Returns the current dev. This might be different from the passed in dev, 3925 * because the core might be gone away while we unlocked the mutex. */ 3926static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev) 3927{ 3928 struct b43_wl *wl = dev->wl; 3929 struct b43_wldev *orig_dev; 3930 u32 mask; 3931 3932redo: 3933 if (!dev || b43_status(dev) < B43_STAT_STARTED) 3934 return dev; 3935 3936 /* Cancel work. Unlock to avoid deadlocks. */ 3937 mutex_unlock(&wl->mutex); 3938 cancel_delayed_work_sync(&dev->periodic_work); 3939 cancel_work_sync(&wl->tx_work); 3940 mutex_lock(&wl->mutex); 3941 dev = wl->current_dev; 3942 if (!dev || b43_status(dev) < B43_STAT_STARTED) { 3943 /* Whoops, aliens ate up the device while we were unlocked. */ 3944 return dev; 3945 } 3946 3947 /* Disable interrupts on the device. */ 3948 b43_set_status(dev, B43_STAT_INITIALIZED); 3949 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) { 3950 /* wl->mutex is locked. That is enough. */ 3951 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 3952 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 3953 } else { 3954 spin_lock_irq(&wl->hardirq_lock); 3955 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 3956 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 3957 spin_unlock_irq(&wl->hardirq_lock); 3958 } 3959 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ 3960 orig_dev = dev; 3961 mutex_unlock(&wl->mutex); 3962 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) { 3963 b43_sdio_free_irq(dev); 3964 } else { 3965 synchronize_irq(dev->dev->irq); 3966 free_irq(dev->dev->irq, dev); 3967 } 3968 mutex_lock(&wl->mutex); 3969 dev = wl->current_dev; 3970 if (!dev) 3971 return dev; 3972 if (dev != orig_dev) { 3973 if (b43_status(dev) >= B43_STAT_STARTED) 3974 goto redo; 3975 return dev; 3976 } 3977 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 3978 B43_WARN_ON(mask != 0xFFFFFFFF && mask); 3979 3980 /* Drain the TX queue */ 3981 while (skb_queue_len(&wl->tx_queue)) 3982 dev_kfree_skb(skb_dequeue(&wl->tx_queue)); 3983 3984 b43_mac_suspend(dev); 3985 b43_leds_exit(dev); 3986 b43dbg(wl, "Wireless interface stopped\n"); 3987 3988 return dev; 3989} 3990 3991/* Locking: wl->mutex */ 3992static int b43_wireless_core_start(struct b43_wldev *dev) 3993{ 3994 int err; 3995 3996 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 3997 3998 drain_txstatus_queue(dev); 3999 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) { 4000 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); 4001 if (err) { 4002 b43err(dev->wl, "Cannot request SDIO IRQ\n"); 4003 goto out; 4004 } 4005 } else { 4006 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler, 4007 b43_interrupt_thread_handler, 4008 IRQF_SHARED, KBUILD_MODNAME, dev); 4009 if (err) { 4010 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); 4011 goto out; 4012 } 4013 } 4014 4015 /* We are ready to run. */ 4016 ieee80211_wake_queues(dev->wl->hw); 4017 b43_set_status(dev, B43_STAT_STARTED); 4018 4019 /* Start data flow (TX/RX). */ 4020 b43_mac_enable(dev); 4021 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 4022 4023 /* Start maintenance work */ 4024 b43_periodic_tasks_setup(dev); 4025 4026 b43_leds_init(dev); 4027 4028 b43dbg(dev->wl, "Wireless interface started\n"); 4029out: 4030 return err; 4031} 4032 4033/* Get PHY and RADIO versioning numbers */ 4034static int b43_phy_versioning(struct b43_wldev *dev) 4035{ 4036 struct b43_phy *phy = &dev->phy; 4037 u32 tmp; 4038 u8 analog_type; 4039 u8 phy_type; 4040 u8 phy_rev; 4041 u16 radio_manuf; 4042 u16 radio_ver; 4043 u16 radio_rev; 4044 int unsupported = 0; 4045 4046 /* Get PHY versioning */ 4047 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 4048 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 4049 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 4050 phy_rev = (tmp & B43_PHYVER_VERSION); 4051 switch (phy_type) { 4052 case B43_PHYTYPE_A: 4053 if (phy_rev >= 4) 4054 unsupported = 1; 4055 break; 4056 case B43_PHYTYPE_B: 4057 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 4058 && phy_rev != 7) 4059 unsupported = 1; 4060 break; 4061 case B43_PHYTYPE_G: 4062 if (phy_rev > 9) 4063 unsupported = 1; 4064 break; 4065#ifdef CONFIG_B43_PHY_N 4066 case B43_PHYTYPE_N: 4067 if (phy_rev > 9) 4068 unsupported = 1; 4069 break; 4070#endif 4071#ifdef CONFIG_B43_PHY_LP 4072 case B43_PHYTYPE_LP: 4073 if (phy_rev > 2) 4074 unsupported = 1; 4075 break; 4076#endif 4077 default: 4078 unsupported = 1; 4079 }; 4080 if (unsupported) { 4081 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 4082 "(Analog %u, Type %u, Revision %u)\n", 4083 analog_type, phy_type, phy_rev); 4084 return -EOPNOTSUPP; 4085 } 4086 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 4087 analog_type, phy_type, phy_rev); 4088 4089 /* Get RADIO versioning */ 4090 if (dev->dev->bus->chip_id == 0x4317) { 4091 if (dev->dev->bus->chip_rev == 0) 4092 tmp = 0x3205017F; 4093 else if (dev->dev->bus->chip_rev == 1) 4094 tmp = 0x4205017F; 4095 else 4096 tmp = 0x5205017F; 4097 } else { 4098 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 4099 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 4100 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 4101 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; 4102 } 4103 radio_manuf = (tmp & 0x00000FFF); 4104 radio_ver = (tmp & 0x0FFFF000) >> 12; 4105 radio_rev = (tmp & 0xF0000000) >> 28; 4106 if (radio_manuf != 0x17F /* Broadcom */) 4107 unsupported = 1; 4108 switch (phy_type) { 4109 case B43_PHYTYPE_A: 4110 if (radio_ver != 0x2060) 4111 unsupported = 1; 4112 if (radio_rev != 1) 4113 unsupported = 1; 4114 if (radio_manuf != 0x17F) 4115 unsupported = 1; 4116 break; 4117 case B43_PHYTYPE_B: 4118 if ((radio_ver & 0xFFF0) != 0x2050) 4119 unsupported = 1; 4120 break; 4121 case B43_PHYTYPE_G: 4122 if (radio_ver != 0x2050) 4123 unsupported = 1; 4124 break; 4125 case B43_PHYTYPE_N: 4126 if (radio_ver != 0x2055 && radio_ver != 0x2056) 4127 unsupported = 1; 4128 break; 4129 case B43_PHYTYPE_LP: 4130 if (radio_ver != 0x2062 && radio_ver != 0x2063) 4131 unsupported = 1; 4132 break; 4133 default: 4134 B43_WARN_ON(1); 4135 } 4136 if (unsupported) { 4137 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 4138 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 4139 radio_manuf, radio_ver, radio_rev); 4140 return -EOPNOTSUPP; 4141 } 4142 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 4143 radio_manuf, radio_ver, radio_rev); 4144 4145 phy->radio_manuf = radio_manuf; 4146 phy->radio_ver = radio_ver; 4147 phy->radio_rev = radio_rev; 4148 4149 phy->analog = analog_type; 4150 phy->type = phy_type; 4151 phy->rev = phy_rev; 4152 4153 return 0; 4154} 4155 4156static void setup_struct_phy_for_init(struct b43_wldev *dev, 4157 struct b43_phy *phy) 4158{ 4159 phy->hardware_power_control = !!modparam_hwpctl; 4160 phy->next_txpwr_check_time = jiffies; 4161 /* PHY TX errors counter. */ 4162 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 4163 4164#if B43_DEBUG 4165 phy->phy_locked = 0; 4166 phy->radio_locked = 0; 4167#endif 4168} 4169 4170static void setup_struct_wldev_for_init(struct b43_wldev *dev) 4171{ 4172 dev->dfq_valid = 0; 4173 4174 /* Assume the radio is enabled. If it's not enabled, the state will 4175 * immediately get fixed on the first periodic work run. */ 4176 dev->radio_hw_enable = 1; 4177 4178 /* Stats */ 4179 memset(&dev->stats, 0, sizeof(dev->stats)); 4180 4181 setup_struct_phy_for_init(dev, &dev->phy); 4182 4183 /* IRQ related flags */ 4184 dev->irq_reason = 0; 4185 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 4186 dev->irq_mask = B43_IRQ_MASKTEMPLATE; 4187 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 4188 dev->irq_mask &= ~B43_IRQ_PHY_TXERR; 4189 4190 dev->mac_suspended = 1; 4191 4192 /* Noise calculation context */ 4193 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 4194} 4195 4196static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 4197{ 4198 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 4199 u64 hf; 4200 4201 if (!modparam_btcoex) 4202 return; 4203 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 4204 return; 4205 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 4206 return; 4207 4208 hf = b43_hf_read(dev); 4209 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 4210 hf |= B43_HF_BTCOEXALT; 4211 else 4212 hf |= B43_HF_BTCOEX; 4213 b43_hf_write(dev, hf); 4214} 4215 4216static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 4217{ 4218 if (!modparam_btcoex) 4219 return; 4220 //TODO 4221} 4222 4223static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 4224{ 4225 struct ssb_bus *bus = dev->dev->bus; 4226 u32 tmp; 4227 4228 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || 4229 (bus->chip_id == 0x4312)) { 4230 tmp = ssb_read32(dev->dev, SSB_IMCFGLO); 4231 tmp &= ~SSB_IMCFGLO_REQTO; 4232 tmp &= ~SSB_IMCFGLO_SERTO; 4233 tmp |= 0x3; 4234 ssb_write32(dev->dev, SSB_IMCFGLO, tmp); 4235 ssb_commit_settings(bus); 4236 } 4237} 4238 4239static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) 4240{ 4241 u16 pu_delay; 4242 4243 /* The time value is in microseconds. */ 4244 if (dev->phy.type == B43_PHYTYPE_A) 4245 pu_delay = 3700; 4246 else 4247 pu_delay = 1050; 4248 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) 4249 pu_delay = 500; 4250 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) 4251 pu_delay = max(pu_delay, (u16)2400); 4252 4253 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); 4254} 4255 4256/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ 4257static void b43_set_pretbtt(struct b43_wldev *dev) 4258{ 4259 u16 pretbtt; 4260 4261 /* The time value is in microseconds. */ 4262 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) { 4263 pretbtt = 2; 4264 } else { 4265 if (dev->phy.type == B43_PHYTYPE_A) 4266 pretbtt = 120; 4267 else 4268 pretbtt = 250; 4269 } 4270 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); 4271 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); 4272} 4273 4274/* Shutdown a wireless core */ 4275/* Locking: wl->mutex */ 4276static void b43_wireless_core_exit(struct b43_wldev *dev) 4277{ 4278 u32 macctl; 4279 4280 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED); 4281 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED) 4282 return; 4283 4284 /* Unregister HW RNG driver */ 4285 b43_rng_exit(dev->wl); 4286 4287 b43_set_status(dev, B43_STAT_UNINIT); 4288 4289 /* Stop the microcode PSM. */ 4290 macctl = b43_read32(dev, B43_MMIO_MACCTL); 4291 macctl &= ~B43_MACCTL_PSM_RUN; 4292 macctl |= B43_MACCTL_PSM_JMP0; 4293 b43_write32(dev, B43_MMIO_MACCTL, macctl); 4294 4295 b43_dma_free(dev); 4296 b43_pio_free(dev); 4297 b43_chip_exit(dev); 4298 dev->phy.ops->switch_analog(dev, 0); 4299 if (dev->wl->current_beacon) { 4300 dev_kfree_skb_any(dev->wl->current_beacon); 4301 dev->wl->current_beacon = NULL; 4302 } 4303 4304 ssb_device_disable(dev->dev, 0); 4305 ssb_bus_may_powerdown(dev->dev->bus); 4306} 4307 4308/* Initialize a wireless core */ 4309static int b43_wireless_core_init(struct b43_wldev *dev) 4310{ 4311 struct ssb_bus *bus = dev->dev->bus; 4312 struct ssb_sprom *sprom = &bus->sprom; 4313 struct b43_phy *phy = &dev->phy; 4314 int err; 4315 u64 hf; 4316 u32 tmp; 4317 4318 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4319 4320 err = ssb_bus_powerup(bus, 0); 4321 if (err) 4322 goto out; 4323 if (!ssb_device_is_enabled(dev->dev)) { 4324 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 4325 b43_wireless_core_reset(dev, tmp); 4326 } 4327 4328 /* Reset all data structures. */ 4329 setup_struct_wldev_for_init(dev); 4330 phy->ops->prepare_structs(dev); 4331 4332 /* Enable IRQ routing to this device. */ 4333 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 4334 4335 b43_imcfglo_timeouts_workaround(dev); 4336 b43_bluetooth_coext_disable(dev); 4337 if (phy->ops->prepare_hardware) { 4338 err = phy->ops->prepare_hardware(dev); 4339 if (err) 4340 goto err_busdown; 4341 } 4342 err = b43_chip_init(dev); 4343 if (err) 4344 goto err_busdown; 4345 b43_shm_write16(dev, B43_SHM_SHARED, 4346 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 4347 hf = b43_hf_read(dev); 4348 if (phy->type == B43_PHYTYPE_G) { 4349 hf |= B43_HF_SYMW; 4350 if (phy->rev == 1) 4351 hf |= B43_HF_GDCW; 4352 if (sprom->boardflags_lo & B43_BFL_PACTRL) 4353 hf |= B43_HF_OFDMPABOOST; 4354 } 4355 if (phy->radio_ver == 0x2050) { 4356 if (phy->radio_rev == 6) 4357 hf |= B43_HF_4318TSSI; 4358 if (phy->radio_rev < 6) 4359 hf |= B43_HF_VCORECALC; 4360 } 4361 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) 4362 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ 4363#ifdef CONFIG_SSB_DRIVER_PCICORE 4364 if ((bus->bustype == SSB_BUSTYPE_PCI) && 4365 (bus->pcicore.dev->id.revision <= 10)) 4366 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ 4367#endif 4368 hf &= ~B43_HF_SKCFPUP; 4369 b43_hf_write(dev, hf); 4370 4371 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 4372 B43_DEFAULT_LONG_RETRY_LIMIT); 4373 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 4374 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 4375 4376 /* Disable sending probe responses from firmware. 4377 * Setting the MaxTime to one usec will always trigger 4378 * a timeout, so we never send any probe resp. 4379 * A timeout of zero is infinite. */ 4380 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 4381 4382 b43_rate_memory_init(dev); 4383 b43_set_phytxctl_defaults(dev); 4384 4385 /* Minimum Contention Window */ 4386 if (phy->type == B43_PHYTYPE_B) 4387 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 4388 else 4389 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 4390 /* Maximum Contention Window */ 4391 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 4392 4393 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || 4394 (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) || 4395 dev->use_pio) { 4396 dev->__using_pio_transfers = 1; 4397 err = b43_pio_init(dev); 4398 } else { 4399 dev->__using_pio_transfers = 0; 4400 err = b43_dma_init(dev); 4401 } 4402 if (err) 4403 goto err_chip_exit; 4404 b43_qos_init(dev); 4405 b43_set_synth_pu_delay(dev, 1); 4406 b43_bluetooth_coext_enable(dev); 4407 4408 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); 4409 b43_upload_card_macaddress(dev); 4410 b43_security_init(dev); 4411 4412 ieee80211_wake_queues(dev->wl->hw); 4413 4414 b43_set_status(dev, B43_STAT_INITIALIZED); 4415 4416 /* Register HW RNG driver */ 4417 b43_rng_init(dev->wl); 4418 4419out: 4420 return err; 4421 4422err_chip_exit: 4423 b43_chip_exit(dev); 4424err_busdown: 4425 ssb_bus_may_powerdown(bus); 4426 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4427 return err; 4428} 4429 4430static int b43_op_add_interface(struct ieee80211_hw *hw, 4431 struct ieee80211_vif *vif) 4432{ 4433 struct b43_wl *wl = hw_to_b43_wl(hw); 4434 struct b43_wldev *dev; 4435 int err = -EOPNOTSUPP; 4436 4437 /* TODO: allow WDS/AP devices to coexist */ 4438 4439 if (vif->type != NL80211_IFTYPE_AP && 4440 vif->type != NL80211_IFTYPE_MESH_POINT && 4441 vif->type != NL80211_IFTYPE_STATION && 4442 vif->type != NL80211_IFTYPE_WDS && 4443 vif->type != NL80211_IFTYPE_ADHOC) 4444 return -EOPNOTSUPP; 4445 4446 mutex_lock(&wl->mutex); 4447 if (wl->operating) 4448 goto out_mutex_unlock; 4449 4450 b43dbg(wl, "Adding Interface type %d\n", vif->type); 4451 4452 dev = wl->current_dev; 4453 wl->operating = 1; 4454 wl->vif = vif; 4455 wl->if_type = vif->type; 4456 memcpy(wl->mac_addr, vif->addr, ETH_ALEN); 4457 4458 b43_adjust_opmode(dev); 4459 b43_set_pretbtt(dev); 4460 b43_set_synth_pu_delay(dev, 0); 4461 b43_upload_card_macaddress(dev); 4462 4463 err = 0; 4464 out_mutex_unlock: 4465 mutex_unlock(&wl->mutex); 4466 4467 return err; 4468} 4469 4470static void b43_op_remove_interface(struct ieee80211_hw *hw, 4471 struct ieee80211_vif *vif) 4472{ 4473 struct b43_wl *wl = hw_to_b43_wl(hw); 4474 struct b43_wldev *dev = wl->current_dev; 4475 4476 b43dbg(wl, "Removing Interface type %d\n", vif->type); 4477 4478 mutex_lock(&wl->mutex); 4479 4480 B43_WARN_ON(!wl->operating); 4481 B43_WARN_ON(wl->vif != vif); 4482 wl->vif = NULL; 4483 4484 wl->operating = 0; 4485 4486 b43_adjust_opmode(dev); 4487 memset(wl->mac_addr, 0, ETH_ALEN); 4488 b43_upload_card_macaddress(dev); 4489 4490 mutex_unlock(&wl->mutex); 4491} 4492 4493static int b43_op_start(struct ieee80211_hw *hw) 4494{ 4495 struct b43_wl *wl = hw_to_b43_wl(hw); 4496 struct b43_wldev *dev = wl->current_dev; 4497 int did_init = 0; 4498 int err = 0; 4499 4500 /* Kill all old instance specific information to make sure 4501 * the card won't use it in the short timeframe between start 4502 * and mac80211 reconfiguring it. */ 4503 memset(wl->bssid, 0, ETH_ALEN); 4504 memset(wl->mac_addr, 0, ETH_ALEN); 4505 wl->filter_flags = 0; 4506 wl->radiotap_enabled = 0; 4507 b43_qos_clear(wl); 4508 wl->beacon0_uploaded = 0; 4509 wl->beacon1_uploaded = 0; 4510 wl->beacon_templates_virgin = 1; 4511 wl->radio_enabled = 1; 4512 4513 mutex_lock(&wl->mutex); 4514 4515 if (b43_status(dev) < B43_STAT_INITIALIZED) { 4516 err = b43_wireless_core_init(dev); 4517 if (err) 4518 goto out_mutex_unlock; 4519 did_init = 1; 4520 } 4521 4522 if (b43_status(dev) < B43_STAT_STARTED) { 4523 err = b43_wireless_core_start(dev); 4524 if (err) { 4525 if (did_init) 4526 b43_wireless_core_exit(dev); 4527 goto out_mutex_unlock; 4528 } 4529 } 4530 4531 /* XXX: only do if device doesn't support rfkill irq */ 4532 wiphy_rfkill_start_polling(hw->wiphy); 4533 4534 out_mutex_unlock: 4535 mutex_unlock(&wl->mutex); 4536 4537 return err; 4538} 4539 4540static void b43_op_stop(struct ieee80211_hw *hw) 4541{ 4542 struct b43_wl *wl = hw_to_b43_wl(hw); 4543 struct b43_wldev *dev = wl->current_dev; 4544 4545 cancel_work_sync(&(wl->beacon_update_trigger)); 4546 4547 mutex_lock(&wl->mutex); 4548 if (b43_status(dev) >= B43_STAT_STARTED) { 4549 dev = b43_wireless_core_stop(dev); 4550 if (!dev) 4551 goto out_unlock; 4552 } 4553 b43_wireless_core_exit(dev); 4554 wl->radio_enabled = 0; 4555 4556out_unlock: 4557 mutex_unlock(&wl->mutex); 4558 4559 cancel_work_sync(&(wl->txpower_adjust_work)); 4560} 4561 4562static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, 4563 struct ieee80211_sta *sta, bool set) 4564{ 4565 struct b43_wl *wl = hw_to_b43_wl(hw); 4566 4567 /* FIXME: add locking */ 4568 b43_update_templates(wl); 4569 4570 return 0; 4571} 4572 4573static void b43_op_sta_notify(struct ieee80211_hw *hw, 4574 struct ieee80211_vif *vif, 4575 enum sta_notify_cmd notify_cmd, 4576 struct ieee80211_sta *sta) 4577{ 4578 struct b43_wl *wl = hw_to_b43_wl(hw); 4579 4580 B43_WARN_ON(!vif || wl->vif != vif); 4581} 4582 4583static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw) 4584{ 4585 struct b43_wl *wl = hw_to_b43_wl(hw); 4586 struct b43_wldev *dev; 4587 4588 mutex_lock(&wl->mutex); 4589 dev = wl->current_dev; 4590 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4591 /* Disable CFP update during scan on other channels. */ 4592 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP); 4593 } 4594 mutex_unlock(&wl->mutex); 4595} 4596 4597static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw) 4598{ 4599 struct b43_wl *wl = hw_to_b43_wl(hw); 4600 struct b43_wldev *dev; 4601 4602 mutex_lock(&wl->mutex); 4603 dev = wl->current_dev; 4604 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 4605 /* Re-enable CFP update. */ 4606 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP); 4607 } 4608 mutex_unlock(&wl->mutex); 4609} 4610 4611static int b43_op_get_survey(struct ieee80211_hw *hw, int idx, 4612 struct survey_info *survey) 4613{ 4614 struct b43_wl *wl = hw_to_b43_wl(hw); 4615 struct b43_wldev *dev = wl->current_dev; 4616 struct ieee80211_conf *conf = &hw->conf; 4617 4618 if (idx != 0) 4619 return -ENOENT; 4620 4621 survey->channel = conf->channel; 4622 survey->filled = SURVEY_INFO_NOISE_DBM; 4623 survey->noise = dev->stats.link_noise; 4624 4625 return 0; 4626} 4627 4628static const struct ieee80211_ops b43_hw_ops = { 4629 .tx = b43_op_tx, 4630 .conf_tx = b43_op_conf_tx, 4631 .add_interface = b43_op_add_interface, 4632 .remove_interface = b43_op_remove_interface, 4633 .config = b43_op_config, 4634 .bss_info_changed = b43_op_bss_info_changed, 4635 .configure_filter = b43_op_configure_filter, 4636 .set_key = b43_op_set_key, 4637 .update_tkip_key = b43_op_update_tkip_key, 4638 .get_stats = b43_op_get_stats, 4639 .get_tsf = b43_op_get_tsf, 4640 .set_tsf = b43_op_set_tsf, 4641 .start = b43_op_start, 4642 .stop = b43_op_stop, 4643 .set_tim = b43_op_beacon_set_tim, 4644 .sta_notify = b43_op_sta_notify, 4645 .sw_scan_start = b43_op_sw_scan_start_notifier, 4646 .sw_scan_complete = b43_op_sw_scan_complete_notifier, 4647 .get_survey = b43_op_get_survey, 4648 .rfkill_poll = b43_rfkill_poll, 4649}; 4650 4651/* Hard-reset the chip. Do not call this directly. 4652 * Use b43_controller_restart() 4653 */ 4654static void b43_chip_reset(struct work_struct *work) 4655{ 4656 struct b43_wldev *dev = 4657 container_of(work, struct b43_wldev, restart_work); 4658 struct b43_wl *wl = dev->wl; 4659 int err = 0; 4660 int prev_status; 4661 4662 mutex_lock(&wl->mutex); 4663 4664 prev_status = b43_status(dev); 4665 /* Bring the device down... */ 4666 if (prev_status >= B43_STAT_STARTED) { 4667 dev = b43_wireless_core_stop(dev); 4668 if (!dev) { 4669 err = -ENODEV; 4670 goto out; 4671 } 4672 } 4673 if (prev_status >= B43_STAT_INITIALIZED) 4674 b43_wireless_core_exit(dev); 4675 4676 /* ...and up again. */ 4677 if (prev_status >= B43_STAT_INITIALIZED) { 4678 err = b43_wireless_core_init(dev); 4679 if (err) 4680 goto out; 4681 } 4682 if (prev_status >= B43_STAT_STARTED) { 4683 err = b43_wireless_core_start(dev); 4684 if (err) { 4685 b43_wireless_core_exit(dev); 4686 goto out; 4687 } 4688 } 4689out: 4690 if (err) 4691 wl->current_dev = NULL; /* Failed to init the dev. */ 4692 mutex_unlock(&wl->mutex); 4693 if (err) 4694 b43err(wl, "Controller restart FAILED\n"); 4695 else 4696 b43info(wl, "Controller restarted\n"); 4697} 4698 4699static int b43_setup_bands(struct b43_wldev *dev, 4700 bool have_2ghz_phy, bool have_5ghz_phy) 4701{ 4702 struct ieee80211_hw *hw = dev->wl->hw; 4703 4704 if (have_2ghz_phy) 4705 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz; 4706 if (dev->phy.type == B43_PHYTYPE_N) { 4707 if (have_5ghz_phy) 4708 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy; 4709 } else { 4710 if (have_5ghz_phy) 4711 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy; 4712 } 4713 4714 dev->phy.supports_2ghz = have_2ghz_phy; 4715 dev->phy.supports_5ghz = have_5ghz_phy; 4716 4717 return 0; 4718} 4719 4720static void b43_wireless_core_detach(struct b43_wldev *dev) 4721{ 4722 /* We release firmware that late to not be required to re-request 4723 * is all the time when we reinit the core. */ 4724 b43_release_firmware(dev); 4725 b43_phy_free(dev); 4726} 4727 4728static int b43_wireless_core_attach(struct b43_wldev *dev) 4729{ 4730 struct b43_wl *wl = dev->wl; 4731 struct ssb_bus *bus = dev->dev->bus; 4732 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL; 4733 int err; 4734 bool have_2ghz_phy = 0, have_5ghz_phy = 0; 4735 u32 tmp; 4736 4737 /* Do NOT do any device initialization here. 4738 * Do it in wireless_core_init() instead. 4739 * This function is for gathering basic information about the HW, only. 4740 * Also some structs may be set up here. But most likely you want to have 4741 * that in core_init(), too. 4742 */ 4743 4744 err = ssb_bus_powerup(bus, 0); 4745 if (err) { 4746 b43err(wl, "Bus powerup failed\n"); 4747 goto out; 4748 } 4749 /* Get the PHY type. */ 4750 if (dev->dev->id.revision >= 5) { 4751 u32 tmshigh; 4752 4753 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 4754 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY); 4755 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY); 4756 } else 4757 B43_WARN_ON(1); 4758 4759 dev->phy.gmode = have_2ghz_phy; 4760 dev->phy.radio_on = 1; 4761 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 4762 b43_wireless_core_reset(dev, tmp); 4763 4764 err = b43_phy_versioning(dev); 4765 if (err) 4766 goto err_powerdown; 4767 /* Check if this device supports multiband. */ 4768 if (!pdev || 4769 (pdev->device != 0x4312 && 4770 pdev->device != 0x4319 && pdev->device != 0x4324)) { 4771 /* No multiband support. */ 4772 have_2ghz_phy = 0; 4773 have_5ghz_phy = 0; 4774 switch (dev->phy.type) { 4775 case B43_PHYTYPE_A: 4776 have_5ghz_phy = 1; 4777 break; 4778 case B43_PHYTYPE_LP: //FIXME not always! 4779#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference 4780 have_5ghz_phy = 1; 4781#endif 4782 case B43_PHYTYPE_G: 4783 case B43_PHYTYPE_N: 4784 have_2ghz_phy = 1; 4785 break; 4786 default: 4787 B43_WARN_ON(1); 4788 } 4789 } 4790 if (dev->phy.type == B43_PHYTYPE_A) { 4791 /* FIXME */ 4792 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 4793 err = -EOPNOTSUPP; 4794 goto err_powerdown; 4795 } 4796 if (1 /* disable A-PHY */) { 4797 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */ 4798 if (dev->phy.type != B43_PHYTYPE_N && 4799 dev->phy.type != B43_PHYTYPE_LP) { 4800 have_2ghz_phy = 1; 4801 have_5ghz_phy = 0; 4802 } 4803 } 4804 4805 err = b43_phy_allocate(dev); 4806 if (err) 4807 goto err_powerdown; 4808 4809 dev->phy.gmode = have_2ghz_phy; 4810 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 4811 b43_wireless_core_reset(dev, tmp); 4812 4813 err = b43_validate_chipaccess(dev); 4814 if (err) 4815 goto err_phy_free; 4816 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); 4817 if (err) 4818 goto err_phy_free; 4819 4820 /* Now set some default "current_dev" */ 4821 if (!wl->current_dev) 4822 wl->current_dev = dev; 4823 INIT_WORK(&dev->restart_work, b43_chip_reset); 4824 4825 dev->phy.ops->switch_analog(dev, 0); 4826 ssb_device_disable(dev->dev, 0); 4827 ssb_bus_may_powerdown(bus); 4828 4829out: 4830 return err; 4831 4832err_phy_free: 4833 b43_phy_free(dev); 4834err_powerdown: 4835 ssb_bus_may_powerdown(bus); 4836 return err; 4837} 4838 4839static void b43_one_core_detach(struct ssb_device *dev) 4840{ 4841 struct b43_wldev *wldev; 4842 struct b43_wl *wl; 4843 4844 /* Do not cancel ieee80211-workqueue based work here. 4845 * See comment in b43_remove(). */ 4846 4847 wldev = ssb_get_drvdata(dev); 4848 wl = wldev->wl; 4849 b43_debugfs_remove_device(wldev); 4850 b43_wireless_core_detach(wldev); 4851 list_del(&wldev->list); 4852 wl->nr_devs--; 4853 ssb_set_drvdata(dev, NULL); 4854 kfree(wldev); 4855} 4856 4857static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 4858{ 4859 struct b43_wldev *wldev; 4860 int err = -ENOMEM; 4861 4862 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 4863 if (!wldev) 4864 goto out; 4865 4866 wldev->use_pio = b43_modparam_pio; 4867 wldev->dev = dev; 4868 wldev->wl = wl; 4869 b43_set_status(wldev, B43_STAT_UNINIT); 4870 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 4871 INIT_LIST_HEAD(&wldev->list); 4872 4873 err = b43_wireless_core_attach(wldev); 4874 if (err) 4875 goto err_kfree_wldev; 4876 4877 list_add(&wldev->list, &wl->devlist); 4878 wl->nr_devs++; 4879 ssb_set_drvdata(dev, wldev); 4880 b43_debugfs_add_device(wldev); 4881 4882 out: 4883 return err; 4884 4885 err_kfree_wldev: 4886 kfree(wldev); 4887 return err; 4888} 4889 4890#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ 4891 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ 4892 (pdev->device == _device) && \ 4893 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ 4894 (pdev->subsystem_device == _subdevice) ) 4895 4896static void b43_sprom_fixup(struct ssb_bus *bus) 4897{ 4898 struct pci_dev *pdev; 4899 4900 /* boardflags workarounds */ 4901 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 4902 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 4903 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 4904 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 4905 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 4906 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 4907 if (bus->bustype == SSB_BUSTYPE_PCI) { 4908 pdev = bus->host_pci; 4909 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || 4910 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || 4911 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || 4912 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || 4913 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || 4914 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || 4915 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) 4916 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; 4917 } 4918} 4919 4920static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 4921{ 4922 struct ieee80211_hw *hw = wl->hw; 4923 4924 ssb_set_devtypedata(dev, NULL); 4925 ieee80211_free_hw(hw); 4926} 4927 4928static int b43_wireless_init(struct ssb_device *dev) 4929{ 4930 struct ssb_sprom *sprom = &dev->bus->sprom; 4931 struct ieee80211_hw *hw; 4932 struct b43_wl *wl; 4933 int err = -ENOMEM; 4934 4935 b43_sprom_fixup(dev->bus); 4936 4937 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 4938 if (!hw) { 4939 b43err(NULL, "Could not allocate ieee80211 device\n"); 4940 goto out; 4941 } 4942 wl = hw_to_b43_wl(hw); 4943 4944 /* fill hw info */ 4945 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 4946 IEEE80211_HW_SIGNAL_DBM; 4947 4948 hw->wiphy->interface_modes = 4949 BIT(NL80211_IFTYPE_AP) | 4950 BIT(NL80211_IFTYPE_MESH_POINT) | 4951 BIT(NL80211_IFTYPE_STATION) | 4952 BIT(NL80211_IFTYPE_WDS) | 4953 BIT(NL80211_IFTYPE_ADHOC); 4954 4955 hw->queues = modparam_qos ? 4 : 1; 4956 wl->mac80211_initially_registered_queues = hw->queues; 4957 hw->max_rates = 2; 4958 SET_IEEE80211_DEV(hw, dev->dev); 4959 if (is_valid_ether_addr(sprom->et1mac)) 4960 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 4961 else 4962 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 4963 4964 /* Initialize struct b43_wl */ 4965 wl->hw = hw; 4966 mutex_init(&wl->mutex); 4967 spin_lock_init(&wl->hardirq_lock); 4968 INIT_LIST_HEAD(&wl->devlist); 4969 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); 4970 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work); 4971 INIT_WORK(&wl->tx_work, b43_tx_work); 4972 skb_queue_head_init(&wl->tx_queue); 4973 4974 ssb_set_devtypedata(dev, wl); 4975 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n", 4976 dev->bus->chip_id, dev->id.revision); 4977 err = 0; 4978out: 4979 return err; 4980} 4981 4982static int b43_ssb_probe(struct ssb_device *dev, const struct ssb_device_id *id) 4983{ 4984 struct b43_wl *wl; 4985 int err; 4986 int first = 0; 4987 4988 wl = ssb_get_devtypedata(dev); 4989 if (!wl) { 4990 /* Probing the first core. Must setup common struct b43_wl */ 4991 first = 1; 4992 err = b43_wireless_init(dev); 4993 if (err) 4994 goto out; 4995 wl = ssb_get_devtypedata(dev); 4996 B43_WARN_ON(!wl); 4997 } 4998 err = b43_one_core_attach(dev, wl); 4999 if (err) 5000 goto err_wireless_exit; 5001 5002 if (first) { 5003 err = ieee80211_register_hw(wl->hw); 5004 if (err) 5005 goto err_one_core_detach; 5006 b43_leds_register(wl->current_dev); 5007 } 5008 5009 out: 5010 return err; 5011 5012 err_one_core_detach: 5013 b43_one_core_detach(dev); 5014 err_wireless_exit: 5015 if (first) 5016 b43_wireless_exit(dev, wl); 5017 return err; 5018} 5019 5020static void b43_ssb_remove(struct ssb_device *dev) 5021{ 5022 struct b43_wl *wl = ssb_get_devtypedata(dev); 5023 struct b43_wldev *wldev = ssb_get_drvdata(dev); 5024 5025 /* We must cancel any work here before unregistering from ieee80211, 5026 * as the ieee80211 unreg will destroy the workqueue. */ 5027 cancel_work_sync(&wldev->restart_work); 5028 5029 B43_WARN_ON(!wl); 5030 if (wl->current_dev == wldev) { 5031 /* Restore the queues count before unregistering, because firmware detect 5032 * might have modified it. Restoring is important, so the networking 5033 * stack can properly free resources. */ 5034 wl->hw->queues = wl->mac80211_initially_registered_queues; 5035 b43_leds_stop(wldev); 5036 ieee80211_unregister_hw(wl->hw); 5037 } 5038 5039 b43_one_core_detach(dev); 5040 5041 if (list_empty(&wl->devlist)) { 5042 b43_leds_unregister(wl); 5043 /* Last core on the chip unregistered. 5044 * We can destroy common struct b43_wl. 5045 */ 5046 b43_wireless_exit(dev, wl); 5047 } 5048} 5049 5050/* Perform a hardware reset. This can be called from any context. */ 5051void b43_controller_restart(struct b43_wldev *dev, const char *reason) 5052{ 5053 /* Must avoid requeueing, if we are in shutdown. */ 5054 if (b43_status(dev) < B43_STAT_INITIALIZED) 5055 return; 5056 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 5057 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 5058} 5059 5060static struct ssb_driver b43_ssb_driver = { 5061 .name = KBUILD_MODNAME, 5062 .id_table = b43_ssb_tbl, 5063 .probe = b43_ssb_probe, 5064 .remove = b43_ssb_remove, 5065}; 5066 5067static void b43_print_driverinfo(void) 5068{ 5069 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", 5070 *feat_leds = "", *feat_sdio = ""; 5071 5072#ifdef CONFIG_B43_PCI_AUTOSELECT 5073 feat_pci = "P"; 5074#endif 5075#ifdef CONFIG_B43_PCMCIA 5076 feat_pcmcia = "M"; 5077#endif 5078#ifdef CONFIG_B43_PHY_N 5079 feat_nphy = "N"; 5080#endif 5081#ifdef CONFIG_B43_LEDS 5082 feat_leds = "L"; 5083#endif 5084#ifdef CONFIG_B43_SDIO 5085 feat_sdio = "S"; 5086#endif 5087 printk(KERN_INFO "Broadcom 43xx driver loaded " 5088 "[ Features: %s%s%s%s%s, Firmware-ID: " 5089 B43_SUPPORTED_FIRMWARE_ID " ]\n", 5090 feat_pci, feat_pcmcia, feat_nphy, 5091 feat_leds, feat_sdio); 5092} 5093 5094static int __init b43_init(void) 5095{ 5096 int err; 5097 5098 b43_debugfs_init(); 5099 err = b43_pcmcia_init(); 5100 if (err) 5101 goto err_dfs_exit; 5102 err = b43_sdio_init(); 5103 if (err) 5104 goto err_pcmcia_exit; 5105 err = ssb_driver_register(&b43_ssb_driver); 5106 if (err) 5107 goto err_sdio_exit; 5108 b43_print_driverinfo(); 5109 5110 return err; 5111 5112err_sdio_exit: 5113 b43_sdio_exit(); 5114err_pcmcia_exit: 5115 b43_pcmcia_exit(); 5116err_dfs_exit: 5117 b43_debugfs_exit(); 5118 return err; 5119} 5120 5121static void __exit b43_exit(void) 5122{ 5123 ssb_driver_unregister(&b43_ssb_driver); 5124 b43_sdio_exit(); 5125 b43_pcmcia_exit(); 5126 b43_debugfs_exit(); 5127} 5128 5129module_init(b43_init) 5130module_exit(b43_exit) 5131