main.c revision e66fee6aa04b27b6b6f812af0e4123eded5bf8ac
1/* 2 3 Broadcom B43 wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 11 Some parts of the code in this file are derived from the ipw2200 12 driver Copyright(c) 2003 - 2004 Intel Corporation. 13 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; either version 2 of the License, or 17 (at your option) any later version. 18 19 This program is distributed in the hope that it will be useful, 20 but WITHOUT ANY WARRANTY; without even the implied warranty of 21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 GNU General Public License for more details. 23 24 You should have received a copy of the GNU General Public License 25 along with this program; see the file COPYING. If not, write to 26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 27 Boston, MA 02110-1301, USA. 28 29*/ 30 31#include <linux/delay.h> 32#include <linux/init.h> 33#include <linux/moduleparam.h> 34#include <linux/if_arp.h> 35#include <linux/etherdevice.h> 36#include <linux/version.h> 37#include <linux/firmware.h> 38#include <linux/wireless.h> 39#include <linux/workqueue.h> 40#include <linux/skbuff.h> 41#include <linux/dma-mapping.h> 42#include <asm/unaligned.h> 43 44#include "b43.h" 45#include "main.h" 46#include "debugfs.h" 47#include "phy.h" 48#include "dma.h" 49#include "sysfs.h" 50#include "xmit.h" 51#include "lo.h" 52#include "pcmcia.h" 53 54MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 55MODULE_AUTHOR("Martin Langer"); 56MODULE_AUTHOR("Stefano Brivio"); 57MODULE_AUTHOR("Michael Buesch"); 58MODULE_LICENSE("GPL"); 59 60 61static int modparam_bad_frames_preempt; 62module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 63MODULE_PARM_DESC(bad_frames_preempt, 64 "enable(1) / disable(0) Bad Frames Preemption"); 65 66static char modparam_fwpostfix[16]; 67module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 68MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 69 70static int modparam_hwpctl; 71module_param_named(hwpctl, modparam_hwpctl, int, 0444); 72MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 73 74static int modparam_nohwcrypt; 75module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 76MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 77 78static const struct ssb_device_id b43_ssb_tbl[] = { 79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 86 SSB_DEVTABLE_END 87}; 88 89MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 90 91/* Channel and ratetables are shared for all devices. 92 * They can't be const, because ieee80211 puts some precalculated 93 * data in there. This data is the same for all devices, so we don't 94 * get concurrency issues */ 95#define RATETAB_ENT(_rateid, _flags) \ 96 { \ 97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \ 98 .val = (_rateid), \ 99 .val2 = (_rateid), \ 100 .flags = (_flags), \ 101 } 102static struct ieee80211_rate __b43_ratetable[] = { 103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK), 104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2), 105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2), 106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2), 107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM), 108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM), 109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM), 110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM), 111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM), 112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM), 113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM), 114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM), 115}; 116 117#define b43_a_ratetable (__b43_ratetable + 4) 118#define b43_a_ratetable_size 8 119#define b43_b_ratetable (__b43_ratetable + 0) 120#define b43_b_ratetable_size 4 121#define b43_g_ratetable (__b43_ratetable + 0) 122#define b43_g_ratetable_size 12 123 124#define CHANTAB_ENT(_chanid, _freq) \ 125 { \ 126 .chan = (_chanid), \ 127 .freq = (_freq), \ 128 .val = (_chanid), \ 129 .flag = IEEE80211_CHAN_W_SCAN | \ 130 IEEE80211_CHAN_W_ACTIVE_SCAN | \ 131 IEEE80211_CHAN_W_IBSS, \ 132 .power_level = 0xFF, \ 133 .antenna_max = 0xFF, \ 134 } 135static struct ieee80211_channel b43_2ghz_chantable[] = { 136 CHANTAB_ENT(1, 2412), 137 CHANTAB_ENT(2, 2417), 138 CHANTAB_ENT(3, 2422), 139 CHANTAB_ENT(4, 2427), 140 CHANTAB_ENT(5, 2432), 141 CHANTAB_ENT(6, 2437), 142 CHANTAB_ENT(7, 2442), 143 CHANTAB_ENT(8, 2447), 144 CHANTAB_ENT(9, 2452), 145 CHANTAB_ENT(10, 2457), 146 CHANTAB_ENT(11, 2462), 147 CHANTAB_ENT(12, 2467), 148 CHANTAB_ENT(13, 2472), 149 CHANTAB_ENT(14, 2484), 150}; 151#define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable) 152 153#if 0 154static struct ieee80211_channel b43_5ghz_chantable[] = { 155 CHANTAB_ENT(36, 5180), 156 CHANTAB_ENT(40, 5200), 157 CHANTAB_ENT(44, 5220), 158 CHANTAB_ENT(48, 5240), 159 CHANTAB_ENT(52, 5260), 160 CHANTAB_ENT(56, 5280), 161 CHANTAB_ENT(60, 5300), 162 CHANTAB_ENT(64, 5320), 163 CHANTAB_ENT(149, 5745), 164 CHANTAB_ENT(153, 5765), 165 CHANTAB_ENT(157, 5785), 166 CHANTAB_ENT(161, 5805), 167 CHANTAB_ENT(165, 5825), 168}; 169#define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable) 170#endif 171 172static void b43_wireless_core_exit(struct b43_wldev *dev); 173static int b43_wireless_core_init(struct b43_wldev *dev); 174static void b43_wireless_core_stop(struct b43_wldev *dev); 175static int b43_wireless_core_start(struct b43_wldev *dev); 176 177static int b43_ratelimit(struct b43_wl *wl) 178{ 179 if (!wl || !wl->current_dev) 180 return 1; 181 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 182 return 1; 183 /* We are up and running. 184 * Ratelimit the messages to avoid DoS over the net. */ 185 return net_ratelimit(); 186} 187 188void b43info(struct b43_wl *wl, const char *fmt, ...) 189{ 190 va_list args; 191 192 if (!b43_ratelimit(wl)) 193 return; 194 va_start(args, fmt); 195 printk(KERN_INFO "b43-%s: ", 196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 197 vprintk(fmt, args); 198 va_end(args); 199} 200 201void b43err(struct b43_wl *wl, const char *fmt, ...) 202{ 203 va_list args; 204 205 if (!b43_ratelimit(wl)) 206 return; 207 va_start(args, fmt); 208 printk(KERN_ERR "b43-%s ERROR: ", 209 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 210 vprintk(fmt, args); 211 va_end(args); 212} 213 214void b43warn(struct b43_wl *wl, const char *fmt, ...) 215{ 216 va_list args; 217 218 if (!b43_ratelimit(wl)) 219 return; 220 va_start(args, fmt); 221 printk(KERN_WARNING "b43-%s warning: ", 222 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 223 vprintk(fmt, args); 224 va_end(args); 225} 226 227#if B43_DEBUG 228void b43dbg(struct b43_wl *wl, const char *fmt, ...) 229{ 230 va_list args; 231 232 va_start(args, fmt); 233 printk(KERN_DEBUG "b43-%s debug: ", 234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); 235 vprintk(fmt, args); 236 va_end(args); 237} 238#endif /* DEBUG */ 239 240static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 241{ 242 u32 macctl; 243 244 B43_WARN_ON(offset % 4 != 0); 245 246 macctl = b43_read32(dev, B43_MMIO_MACCTL); 247 if (macctl & B43_MACCTL_BE) 248 val = swab32(val); 249 250 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 251 mmiowb(); 252 b43_write32(dev, B43_MMIO_RAM_DATA, val); 253} 254 255static inline 256 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset) 257{ 258 u32 control; 259 260 /* "offset" is the WORD offset. */ 261 262 control = routing; 263 control <<= 16; 264 control |= offset; 265 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 266} 267 268u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 269{ 270 u32 ret; 271 272 if (routing == B43_SHM_SHARED) { 273 B43_WARN_ON(offset & 0x0001); 274 if (offset & 0x0003) { 275 /* Unaligned access */ 276 b43_shm_control_word(dev, routing, offset >> 2); 277 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 278 ret <<= 16; 279 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 280 ret |= b43_read16(dev, B43_MMIO_SHM_DATA); 281 282 return ret; 283 } 284 offset >>= 2; 285 } 286 b43_shm_control_word(dev, routing, offset); 287 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 288 289 return ret; 290} 291 292u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset) 293{ 294 u16 ret; 295 296 if (routing == B43_SHM_SHARED) { 297 B43_WARN_ON(offset & 0x0001); 298 if (offset & 0x0003) { 299 /* Unaligned access */ 300 b43_shm_control_word(dev, routing, offset >> 2); 301 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 302 303 return ret; 304 } 305 offset >>= 2; 306 } 307 b43_shm_control_word(dev, routing, offset); 308 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 309 310 return ret; 311} 312 313void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 314{ 315 if (routing == B43_SHM_SHARED) { 316 B43_WARN_ON(offset & 0x0001); 317 if (offset & 0x0003) { 318 /* Unaligned access */ 319 b43_shm_control_word(dev, routing, offset >> 2); 320 mmiowb(); 321 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 322 (value >> 16) & 0xffff); 323 mmiowb(); 324 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 325 mmiowb(); 326 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff); 327 return; 328 } 329 offset >>= 2; 330 } 331 b43_shm_control_word(dev, routing, offset); 332 mmiowb(); 333 b43_write32(dev, B43_MMIO_SHM_DATA, value); 334} 335 336void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 337{ 338 if (routing == B43_SHM_SHARED) { 339 B43_WARN_ON(offset & 0x0001); 340 if (offset & 0x0003) { 341 /* Unaligned access */ 342 b43_shm_control_word(dev, routing, offset >> 2); 343 mmiowb(); 344 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 345 return; 346 } 347 offset >>= 2; 348 } 349 b43_shm_control_word(dev, routing, offset); 350 mmiowb(); 351 b43_write16(dev, B43_MMIO_SHM_DATA, value); 352} 353 354/* Read HostFlags */ 355u32 b43_hf_read(struct b43_wldev * dev) 356{ 357 u32 ret; 358 359 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); 360 ret <<= 16; 361 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); 362 363 return ret; 364} 365 366/* Write HostFlags */ 367void b43_hf_write(struct b43_wldev *dev, u32 value) 368{ 369 b43_shm_write16(dev, B43_SHM_SHARED, 370 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF)); 371 b43_shm_write16(dev, B43_SHM_SHARED, 372 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16)); 373} 374 375void b43_tsf_read(struct b43_wldev *dev, u64 * tsf) 376{ 377 /* We need to be careful. As we read the TSF from multiple 378 * registers, we should take care of register overflows. 379 * In theory, the whole tsf read process should be atomic. 380 * We try to be atomic here, by restaring the read process, 381 * if any of the high registers changed (overflew). 382 */ 383 if (dev->dev->id.revision >= 3) { 384 u32 low, high, high2; 385 386 do { 387 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 388 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 389 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 390 } while (unlikely(high != high2)); 391 392 *tsf = high; 393 *tsf <<= 32; 394 *tsf |= low; 395 } else { 396 u64 tmp; 397 u16 v0, v1, v2, v3; 398 u16 test1, test2, test3; 399 400 do { 401 v3 = b43_read16(dev, B43_MMIO_TSF_3); 402 v2 = b43_read16(dev, B43_MMIO_TSF_2); 403 v1 = b43_read16(dev, B43_MMIO_TSF_1); 404 v0 = b43_read16(dev, B43_MMIO_TSF_0); 405 406 test3 = b43_read16(dev, B43_MMIO_TSF_3); 407 test2 = b43_read16(dev, B43_MMIO_TSF_2); 408 test1 = b43_read16(dev, B43_MMIO_TSF_1); 409 } while (v3 != test3 || v2 != test2 || v1 != test1); 410 411 *tsf = v3; 412 *tsf <<= 48; 413 tmp = v2; 414 tmp <<= 32; 415 *tsf |= tmp; 416 tmp = v1; 417 tmp <<= 16; 418 *tsf |= tmp; 419 *tsf |= v0; 420 } 421} 422 423static void b43_time_lock(struct b43_wldev *dev) 424{ 425 u32 macctl; 426 427 macctl = b43_read32(dev, B43_MMIO_MACCTL); 428 macctl |= B43_MACCTL_TBTTHOLD; 429 b43_write32(dev, B43_MMIO_MACCTL, macctl); 430 /* Commit the write */ 431 b43_read32(dev, B43_MMIO_MACCTL); 432} 433 434static void b43_time_unlock(struct b43_wldev *dev) 435{ 436 u32 macctl; 437 438 macctl = b43_read32(dev, B43_MMIO_MACCTL); 439 macctl &= ~B43_MACCTL_TBTTHOLD; 440 b43_write32(dev, B43_MMIO_MACCTL, macctl); 441 /* Commit the write */ 442 b43_read32(dev, B43_MMIO_MACCTL); 443} 444 445static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 446{ 447 /* Be careful with the in-progress timer. 448 * First zero out the low register, so we have a full 449 * register-overflow duration to complete the operation. 450 */ 451 if (dev->dev->id.revision >= 3) { 452 u32 lo = (tsf & 0x00000000FFFFFFFFULL); 453 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32; 454 455 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0); 456 mmiowb(); 457 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi); 458 mmiowb(); 459 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo); 460 } else { 461 u16 v0 = (tsf & 0x000000000000FFFFULL); 462 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16; 463 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32; 464 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; 465 466 b43_write16(dev, B43_MMIO_TSF_0, 0); 467 mmiowb(); 468 b43_write16(dev, B43_MMIO_TSF_3, v3); 469 mmiowb(); 470 b43_write16(dev, B43_MMIO_TSF_2, v2); 471 mmiowb(); 472 b43_write16(dev, B43_MMIO_TSF_1, v1); 473 mmiowb(); 474 b43_write16(dev, B43_MMIO_TSF_0, v0); 475 } 476} 477 478void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 479{ 480 b43_time_lock(dev); 481 b43_tsf_write_locked(dev, tsf); 482 b43_time_unlock(dev); 483} 484 485static 486void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac) 487{ 488 static const u8 zero_addr[ETH_ALEN] = { 0 }; 489 u16 data; 490 491 if (!mac) 492 mac = zero_addr; 493 494 offset |= 0x0020; 495 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 496 497 data = mac[0]; 498 data |= mac[1] << 8; 499 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 500 data = mac[2]; 501 data |= mac[3] << 8; 502 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 503 data = mac[4]; 504 data |= mac[5] << 8; 505 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 506} 507 508static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 509{ 510 const u8 *mac; 511 const u8 *bssid; 512 u8 mac_bssid[ETH_ALEN * 2]; 513 int i; 514 u32 tmp; 515 516 bssid = dev->wl->bssid; 517 mac = dev->wl->mac_addr; 518 519 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 520 521 memcpy(mac_bssid, mac, ETH_ALEN); 522 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 523 524 /* Write our MAC address and BSSID to template ram */ 525 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 526 tmp = (u32) (mac_bssid[i + 0]); 527 tmp |= (u32) (mac_bssid[i + 1]) << 8; 528 tmp |= (u32) (mac_bssid[i + 2]) << 16; 529 tmp |= (u32) (mac_bssid[i + 3]) << 24; 530 b43_ram_write(dev, 0x20 + i, tmp); 531 } 532} 533 534static void b43_upload_card_macaddress(struct b43_wldev *dev) 535{ 536 b43_write_mac_bssid_templates(dev); 537 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 538} 539 540static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 541{ 542 /* slot_time is in usec. */ 543 if (dev->phy.type != B43_PHYTYPE_G) 544 return; 545 b43_write16(dev, 0x684, 510 + slot_time); 546 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 547} 548 549static void b43_short_slot_timing_enable(struct b43_wldev *dev) 550{ 551 b43_set_slot_time(dev, 9); 552 dev->short_slot = 1; 553} 554 555static void b43_short_slot_timing_disable(struct b43_wldev *dev) 556{ 557 b43_set_slot_time(dev, 20); 558 dev->short_slot = 0; 559} 560 561/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable. 562 * Returns the _previously_ enabled IRQ mask. 563 */ 564static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask) 565{ 566 u32 old_mask; 567 568 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 569 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask); 570 571 return old_mask; 572} 573 574/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable. 575 * Returns the _previously_ enabled IRQ mask. 576 */ 577static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask) 578{ 579 u32 old_mask; 580 581 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 582 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask); 583 584 return old_mask; 585} 586 587/* Synchronize IRQ top- and bottom-half. 588 * IRQs must be masked before calling this. 589 * This must not be called with the irq_lock held. 590 */ 591static void b43_synchronize_irq(struct b43_wldev *dev) 592{ 593 synchronize_irq(dev->dev->irq); 594 tasklet_kill(&dev->isr_tasklet); 595} 596 597/* DummyTransmission function, as documented on 598 * http://bcm-specs.sipsolutions.net/DummyTransmission 599 */ 600void b43_dummy_transmission(struct b43_wldev *dev) 601{ 602 struct b43_phy *phy = &dev->phy; 603 unsigned int i, max_loop; 604 u16 value; 605 u32 buffer[5] = { 606 0x00000000, 607 0x00D40000, 608 0x00000000, 609 0x01000000, 610 0x00000000, 611 }; 612 613 switch (phy->type) { 614 case B43_PHYTYPE_A: 615 max_loop = 0x1E; 616 buffer[0] = 0x000201CC; 617 break; 618 case B43_PHYTYPE_B: 619 case B43_PHYTYPE_G: 620 max_loop = 0xFA; 621 buffer[0] = 0x000B846E; 622 break; 623 default: 624 B43_WARN_ON(1); 625 return; 626 } 627 628 for (i = 0; i < 5; i++) 629 b43_ram_write(dev, i * 4, buffer[i]); 630 631 /* Commit writes */ 632 b43_read32(dev, B43_MMIO_MACCTL); 633 634 b43_write16(dev, 0x0568, 0x0000); 635 b43_write16(dev, 0x07C0, 0x0000); 636 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0); 637 b43_write16(dev, 0x050C, value); 638 b43_write16(dev, 0x0508, 0x0000); 639 b43_write16(dev, 0x050A, 0x0000); 640 b43_write16(dev, 0x054C, 0x0000); 641 b43_write16(dev, 0x056A, 0x0014); 642 b43_write16(dev, 0x0568, 0x0826); 643 b43_write16(dev, 0x0500, 0x0000); 644 b43_write16(dev, 0x0502, 0x0030); 645 646 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 647 b43_radio_write16(dev, 0x0051, 0x0017); 648 for (i = 0x00; i < max_loop; i++) { 649 value = b43_read16(dev, 0x050E); 650 if (value & 0x0080) 651 break; 652 udelay(10); 653 } 654 for (i = 0x00; i < 0x0A; i++) { 655 value = b43_read16(dev, 0x050E); 656 if (value & 0x0400) 657 break; 658 udelay(10); 659 } 660 for (i = 0x00; i < 0x0A; i++) { 661 value = b43_read16(dev, 0x0690); 662 if (!(value & 0x0100)) 663 break; 664 udelay(10); 665 } 666 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 667 b43_radio_write16(dev, 0x0051, 0x0037); 668} 669 670static void key_write(struct b43_wldev *dev, 671 u8 index, u8 algorithm, const u8 * key) 672{ 673 unsigned int i; 674 u32 offset; 675 u16 value; 676 u16 kidx; 677 678 /* Key index/algo block */ 679 kidx = b43_kidx_to_fw(dev, index); 680 value = ((kidx << 4) | algorithm); 681 b43_shm_write16(dev, B43_SHM_SHARED, 682 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 683 684 /* Write the key to the Key Table Pointer offset */ 685 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 686 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 687 value = key[i]; 688 value |= (u16) (key[i + 1]) << 8; 689 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 690 } 691} 692 693static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr) 694{ 695 u32 addrtmp[2] = { 0, 0, }; 696 u8 per_sta_keys_start = 8; 697 698 if (b43_new_kidx_api(dev)) 699 per_sta_keys_start = 4; 700 701 B43_WARN_ON(index < per_sta_keys_start); 702 /* We have two default TX keys and possibly two default RX keys. 703 * Physical mac 0 is mapped to physical key 4 or 8, depending 704 * on the firmware version. 705 * So we must adjust the index here. 706 */ 707 index -= per_sta_keys_start; 708 709 if (addr) { 710 addrtmp[0] = addr[0]; 711 addrtmp[0] |= ((u32) (addr[1]) << 8); 712 addrtmp[0] |= ((u32) (addr[2]) << 16); 713 addrtmp[0] |= ((u32) (addr[3]) << 24); 714 addrtmp[1] = addr[4]; 715 addrtmp[1] |= ((u32) (addr[5]) << 8); 716 } 717 718 if (dev->dev->id.revision >= 5) { 719 /* Receive match transmitter address mechanism */ 720 b43_shm_write32(dev, B43_SHM_RCMTA, 721 (index * 2) + 0, addrtmp[0]); 722 b43_shm_write16(dev, B43_SHM_RCMTA, 723 (index * 2) + 1, addrtmp[1]); 724 } else { 725 /* RXE (Receive Engine) and 726 * PSM (Programmable State Machine) mechanism 727 */ 728 if (index < 8) { 729 /* TODO write to RCM 16, 19, 22 and 25 */ 730 } else { 731 b43_shm_write32(dev, B43_SHM_SHARED, 732 B43_SHM_SH_PSM + (index * 6) + 0, 733 addrtmp[0]); 734 b43_shm_write16(dev, B43_SHM_SHARED, 735 B43_SHM_SH_PSM + (index * 6) + 4, 736 addrtmp[1]); 737 } 738 } 739} 740 741static void do_key_write(struct b43_wldev *dev, 742 u8 index, u8 algorithm, 743 const u8 * key, size_t key_len, const u8 * mac_addr) 744{ 745 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 746 u8 per_sta_keys_start = 8; 747 748 if (b43_new_kidx_api(dev)) 749 per_sta_keys_start = 4; 750 751 B43_WARN_ON(index >= dev->max_nr_keys); 752 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 753 754 if (index >= per_sta_keys_start) 755 keymac_write(dev, index, NULL); /* First zero out mac. */ 756 if (key) 757 memcpy(buf, key, key_len); 758 key_write(dev, index, algorithm, buf); 759 if (index >= per_sta_keys_start) 760 keymac_write(dev, index, mac_addr); 761 762 dev->key[index].algorithm = algorithm; 763} 764 765static int b43_key_write(struct b43_wldev *dev, 766 int index, u8 algorithm, 767 const u8 * key, size_t key_len, 768 const u8 * mac_addr, 769 struct ieee80211_key_conf *keyconf) 770{ 771 int i; 772 int sta_keys_start; 773 774 if (key_len > B43_SEC_KEYSIZE) 775 return -EINVAL; 776 for (i = 0; i < dev->max_nr_keys; i++) { 777 /* Check that we don't already have this key. */ 778 B43_WARN_ON(dev->key[i].keyconf == keyconf); 779 } 780 if (index < 0) { 781 /* Either pairwise key or address is 00:00:00:00:00:00 782 * for transmit-only keys. Search the index. */ 783 if (b43_new_kidx_api(dev)) 784 sta_keys_start = 4; 785 else 786 sta_keys_start = 8; 787 for (i = sta_keys_start; i < dev->max_nr_keys; i++) { 788 if (!dev->key[i].keyconf) { 789 /* found empty */ 790 index = i; 791 break; 792 } 793 } 794 if (index < 0) { 795 b43err(dev->wl, "Out of hardware key memory\n"); 796 return -ENOSPC; 797 } 798 } else 799 B43_WARN_ON(index > 3); 800 801 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 802 if ((index <= 3) && !b43_new_kidx_api(dev)) { 803 /* Default RX key */ 804 B43_WARN_ON(mac_addr); 805 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 806 } 807 keyconf->hw_key_idx = index; 808 dev->key[index].keyconf = keyconf; 809 810 return 0; 811} 812 813static int b43_key_clear(struct b43_wldev *dev, int index) 814{ 815 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys))) 816 return -EINVAL; 817 do_key_write(dev, index, B43_SEC_ALGO_NONE, 818 NULL, B43_SEC_KEYSIZE, NULL); 819 if ((index <= 3) && !b43_new_kidx_api(dev)) { 820 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 821 NULL, B43_SEC_KEYSIZE, NULL); 822 } 823 dev->key[index].keyconf = NULL; 824 825 return 0; 826} 827 828static void b43_clear_keys(struct b43_wldev *dev) 829{ 830 int i; 831 832 for (i = 0; i < dev->max_nr_keys; i++) 833 b43_key_clear(dev, i); 834} 835 836void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 837{ 838 u32 macctl; 839 u16 ucstat; 840 bool hwps; 841 bool awake; 842 int i; 843 844 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 845 (ps_flags & B43_PS_DISABLED)); 846 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 847 848 if (ps_flags & B43_PS_ENABLED) { 849 hwps = 1; 850 } else if (ps_flags & B43_PS_DISABLED) { 851 hwps = 0; 852 } else { 853 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 854 // and thus is not an AP and we are associated, set bit 25 855 } 856 if (ps_flags & B43_PS_AWAKE) { 857 awake = 1; 858 } else if (ps_flags & B43_PS_ASLEEP) { 859 awake = 0; 860 } else { 861 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 862 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 863 // successful, set bit26 864 } 865 866/* FIXME: For now we force awake-on and hwps-off */ 867 hwps = 0; 868 awake = 1; 869 870 macctl = b43_read32(dev, B43_MMIO_MACCTL); 871 if (hwps) 872 macctl |= B43_MACCTL_HWPS; 873 else 874 macctl &= ~B43_MACCTL_HWPS; 875 if (awake) 876 macctl |= B43_MACCTL_AWAKE; 877 else 878 macctl &= ~B43_MACCTL_AWAKE; 879 b43_write32(dev, B43_MMIO_MACCTL, macctl); 880 /* Commit write */ 881 b43_read32(dev, B43_MMIO_MACCTL); 882 if (awake && dev->dev->id.revision >= 5) { 883 /* Wait for the microcode to wake up. */ 884 for (i = 0; i < 100; i++) { 885 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 886 B43_SHM_SH_UCODESTAT); 887 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 888 break; 889 udelay(10); 890 } 891 } 892} 893 894/* Turn the Analog ON/OFF */ 895static void b43_switch_analog(struct b43_wldev *dev, int on) 896{ 897 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); 898} 899 900void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 901{ 902 u32 tmslow; 903 u32 macctl; 904 905 flags |= B43_TMSLOW_PHYCLKEN; 906 flags |= B43_TMSLOW_PHYRESET; 907 ssb_device_enable(dev->dev, flags); 908 msleep(2); /* Wait for the PLL to turn on. */ 909 910 /* Now take the PHY out of Reset again */ 911 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 912 tmslow |= SSB_TMSLOW_FGC; 913 tmslow &= ~B43_TMSLOW_PHYRESET; 914 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 915 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 916 msleep(1); 917 tmslow &= ~SSB_TMSLOW_FGC; 918 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 919 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ 920 msleep(1); 921 922 /* Turn Analog ON */ 923 b43_switch_analog(dev, 1); 924 925 macctl = b43_read32(dev, B43_MMIO_MACCTL); 926 macctl &= ~B43_MACCTL_GMODE; 927 if (flags & B43_TMSLOW_GMODE) 928 macctl |= B43_MACCTL_GMODE; 929 macctl |= B43_MACCTL_IHR_ENABLED; 930 b43_write32(dev, B43_MMIO_MACCTL, macctl); 931} 932 933static void handle_irq_transmit_status(struct b43_wldev *dev) 934{ 935 u32 v0, v1; 936 u16 tmp; 937 struct b43_txstatus stat; 938 939 while (1) { 940 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 941 if (!(v0 & 0x00000001)) 942 break; 943 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 944 945 stat.cookie = (v0 >> 16); 946 stat.seq = (v1 & 0x0000FFFF); 947 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 948 tmp = (v0 & 0x0000FFFF); 949 stat.frame_count = ((tmp & 0xF000) >> 12); 950 stat.rts_count = ((tmp & 0x0F00) >> 8); 951 stat.supp_reason = ((tmp & 0x001C) >> 2); 952 stat.pm_indicated = !!(tmp & 0x0080); 953 stat.intermediate = !!(tmp & 0x0040); 954 stat.for_ampdu = !!(tmp & 0x0020); 955 stat.acked = !!(tmp & 0x0002); 956 957 b43_handle_txstatus(dev, &stat); 958 } 959} 960 961static void drain_txstatus_queue(struct b43_wldev *dev) 962{ 963 u32 dummy; 964 965 if (dev->dev->id.revision < 5) 966 return; 967 /* Read all entries from the microcode TXstatus FIFO 968 * and throw them away. 969 */ 970 while (1) { 971 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 972 if (!(dummy & 0x00000001)) 973 break; 974 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 975 } 976} 977 978static u32 b43_jssi_read(struct b43_wldev *dev) 979{ 980 u32 val = 0; 981 982 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 983 val <<= 16; 984 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 985 986 return val; 987} 988 989static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 990{ 991 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 992 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 993} 994 995static void b43_generate_noise_sample(struct b43_wldev *dev) 996{ 997 b43_jssi_write(dev, 0x7F7F7F7F); 998 b43_write32(dev, B43_MMIO_MACCMD, 999 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1000 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel); 1001} 1002 1003static void b43_calculate_link_quality(struct b43_wldev *dev) 1004{ 1005 /* Top half of Link Quality calculation. */ 1006 1007 if (dev->noisecalc.calculation_running) 1008 return; 1009 dev->noisecalc.channel_at_start = dev->phy.channel; 1010 dev->noisecalc.calculation_running = 1; 1011 dev->noisecalc.nr_samples = 0; 1012 1013 b43_generate_noise_sample(dev); 1014} 1015 1016static void handle_irq_noise(struct b43_wldev *dev) 1017{ 1018 struct b43_phy *phy = &dev->phy; 1019 u16 tmp; 1020 u8 noise[4]; 1021 u8 i, j; 1022 s32 average; 1023 1024 /* Bottom half of Link Quality calculation. */ 1025 1026 B43_WARN_ON(!dev->noisecalc.calculation_running); 1027 if (dev->noisecalc.channel_at_start != phy->channel) 1028 goto drop_calculation; 1029 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1030 if (noise[0] == 0x7F || noise[1] == 0x7F || 1031 noise[2] == 0x7F || noise[3] == 0x7F) 1032 goto generate_new; 1033 1034 /* Get the noise samples. */ 1035 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1036 i = dev->noisecalc.nr_samples; 1037 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1038 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1039 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1040 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1041 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1042 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1043 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1044 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1045 dev->noisecalc.nr_samples++; 1046 if (dev->noisecalc.nr_samples == 8) { 1047 /* Calculate the Link Quality by the noise samples. */ 1048 average = 0; 1049 for (i = 0; i < 8; i++) { 1050 for (j = 0; j < 4; j++) 1051 average += dev->noisecalc.samples[i][j]; 1052 } 1053 average /= (8 * 4); 1054 average *= 125; 1055 average += 64; 1056 average /= 128; 1057 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1058 tmp = (tmp / 128) & 0x1F; 1059 if (tmp >= 8) 1060 average += 2; 1061 else 1062 average -= 25; 1063 if (tmp == 8) 1064 average -= 72; 1065 else 1066 average -= 48; 1067 1068 dev->stats.link_noise = average; 1069 drop_calculation: 1070 dev->noisecalc.calculation_running = 0; 1071 return; 1072 } 1073 generate_new: 1074 b43_generate_noise_sample(dev); 1075} 1076 1077static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1078{ 1079 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) { 1080 ///TODO: PS TBTT 1081 } else { 1082 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1083 b43_power_saving_ctl_bits(dev, 0); 1084 } 1085 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) 1086 dev->dfq_valid = 1; 1087} 1088 1089static void handle_irq_atim_end(struct b43_wldev *dev) 1090{ 1091 if (dev->dfq_valid) { 1092 b43_write32(dev, B43_MMIO_MACCMD, 1093 b43_read32(dev, B43_MMIO_MACCMD) 1094 | B43_MACCMD_DFQ_VALID); 1095 dev->dfq_valid = 0; 1096 } 1097} 1098 1099static void handle_irq_pmq(struct b43_wldev *dev) 1100{ 1101 u32 tmp; 1102 1103 //TODO: AP mode. 1104 1105 while (1) { 1106 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1107 if (!(tmp & 0x00000008)) 1108 break; 1109 } 1110 /* 16bit write is odd, but correct. */ 1111 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1112} 1113 1114static void b43_write_template_common(struct b43_wldev *dev, 1115 const u8 * data, u16 size, 1116 u16 ram_offset, 1117 u16 shm_size_offset, u8 rate) 1118{ 1119 u32 i, tmp; 1120 struct b43_plcp_hdr4 plcp; 1121 1122 plcp.data = 0; 1123 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1124 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1125 ram_offset += sizeof(u32); 1126 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1127 * So leave the first two bytes of the next write blank. 1128 */ 1129 tmp = (u32) (data[0]) << 16; 1130 tmp |= (u32) (data[1]) << 24; 1131 b43_ram_write(dev, ram_offset, tmp); 1132 ram_offset += sizeof(u32); 1133 for (i = 2; i < size; i += sizeof(u32)) { 1134 tmp = (u32) (data[i + 0]); 1135 if (i + 1 < size) 1136 tmp |= (u32) (data[i + 1]) << 8; 1137 if (i + 2 < size) 1138 tmp |= (u32) (data[i + 2]) << 16; 1139 if (i + 3 < size) 1140 tmp |= (u32) (data[i + 3]) << 24; 1141 b43_ram_write(dev, ram_offset + i - 2, tmp); 1142 } 1143 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1144 size + sizeof(struct b43_plcp_hdr6)); 1145} 1146 1147static void b43_write_beacon_template(struct b43_wldev *dev, 1148 u16 ram_offset, 1149 u16 shm_size_offset, u8 rate) 1150{ 1151 int i, len; 1152 const struct ieee80211_mgmt *bcn; 1153 const u8 *ie; 1154 bool tim_found = 0; 1155 1156 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); 1157 len = min((size_t) dev->wl->current_beacon->len, 1158 0x200 - sizeof(struct b43_plcp_hdr6)); 1159 1160 b43_write_template_common(dev, (const u8 *)bcn, 1161 len, ram_offset, shm_size_offset, rate); 1162 1163 /* Find the position of the TIM and the DTIM_period value 1164 * and write them to SHM. */ 1165 ie = bcn->u.beacon.variable; 1166 for (i = 0; i < len - 2; ) { 1167 uint8_t ie_id, ie_len; 1168 1169 ie_id = ie[i]; 1170 ie_len = ie[i + 1]; 1171 if (ie_id == 5) { 1172 u16 tim_position; 1173 u16 dtim_period; 1174 /* This is the TIM Information Element */ 1175 1176 /* Check whether the ie_len is in the beacon data range. */ 1177 if (len < ie_len + 2 + i) 1178 break; 1179 /* A valid TIM is at least 4 bytes long. */ 1180 if (ie_len < 4) 1181 break; 1182 tim_found = 1; 1183 1184 tim_position = sizeof(struct b43_plcp_hdr6); 1185 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1186 tim_position += i; 1187 1188 dtim_period = ie[i + 3]; 1189 1190 b43_shm_write16(dev, B43_SHM_SHARED, 1191 B43_SHM_SH_TIMBPOS, tim_position); 1192 b43_shm_write16(dev, B43_SHM_SHARED, 1193 B43_SHM_SH_DTIMPER, dtim_period); 1194 break; 1195 } 1196 i += ie_len + 2; 1197 } 1198 if (!tim_found) { 1199 b43warn(dev->wl, "Did not find a valid TIM IE in " 1200 "the beacon template packet. AP or IBSS operation " 1201 "may be broken.\n"); 1202 } 1203} 1204 1205static void b43_write_probe_resp_plcp(struct b43_wldev *dev, 1206 u16 shm_offset, u16 size, u8 rate) 1207{ 1208 struct b43_plcp_hdr4 plcp; 1209 u32 tmp; 1210 __le16 dur; 1211 1212 plcp.data = 0; 1213 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1214 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1215 dev->wl->vif, size, 1216 B43_RATE_TO_BASE100KBPS(rate)); 1217 /* Write PLCP in two parts and timing for packet transfer */ 1218 tmp = le32_to_cpu(plcp.data); 1219 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF); 1220 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16); 1221 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur)); 1222} 1223 1224/* Instead of using custom probe response template, this function 1225 * just patches custom beacon template by: 1226 * 1) Changing packet type 1227 * 2) Patching duration field 1228 * 3) Stripping TIM 1229 */ 1230static const u8 * b43_generate_probe_resp(struct b43_wldev *dev, 1231 u16 *dest_size, u8 rate) 1232{ 1233 const u8 *src_data; 1234 u8 *dest_data; 1235 u16 src_size, elem_size, src_pos, dest_pos; 1236 __le16 dur; 1237 struct ieee80211_hdr *hdr; 1238 size_t ie_start; 1239 1240 src_size = dev->wl->current_beacon->len; 1241 src_data = (const u8 *)dev->wl->current_beacon->data; 1242 1243 /* Get the start offset of the variable IEs in the packet. */ 1244 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable); 1245 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable)); 1246 1247 if (B43_WARN_ON(src_size < ie_start)) 1248 return NULL; 1249 1250 dest_data = kmalloc(src_size, GFP_ATOMIC); 1251 if (unlikely(!dest_data)) 1252 return NULL; 1253 1254 /* Copy the static data and all Information Elements, except the TIM. */ 1255 memcpy(dest_data, src_data, ie_start); 1256 src_pos = ie_start; 1257 dest_pos = ie_start; 1258 for ( ; src_pos < src_size - 2; src_pos += elem_size) { 1259 elem_size = src_data[src_pos + 1] + 2; 1260 if (src_data[src_pos] == 5) { 1261 /* This is the TIM. */ 1262 continue; 1263 } 1264 memcpy(dest_data + dest_pos, src_data + src_pos, 1265 elem_size); 1266 dest_pos += elem_size; 1267 } 1268 *dest_size = dest_pos; 1269 hdr = (struct ieee80211_hdr *)dest_data; 1270 1271 /* Set the frame control. */ 1272 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | 1273 IEEE80211_STYPE_PROBE_RESP); 1274 dur = ieee80211_generic_frame_duration(dev->wl->hw, 1275 dev->wl->vif, *dest_size, 1276 B43_RATE_TO_BASE100KBPS(rate)); 1277 hdr->duration_id = dur; 1278 1279 return dest_data; 1280} 1281 1282static void b43_write_probe_resp_template(struct b43_wldev *dev, 1283 u16 ram_offset, 1284 u16 shm_size_offset, u8 rate) 1285{ 1286 const u8 *probe_resp_data; 1287 u16 size; 1288 1289 size = dev->wl->current_beacon->len; 1290 probe_resp_data = b43_generate_probe_resp(dev, &size, rate); 1291 if (unlikely(!probe_resp_data)) 1292 return; 1293 1294 /* Looks like PLCP headers plus packet timings are stored for 1295 * all possible basic rates 1296 */ 1297 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB); 1298 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB); 1299 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB); 1300 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB); 1301 1302 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6)); 1303 b43_write_template_common(dev, probe_resp_data, 1304 size, ram_offset, shm_size_offset, rate); 1305 kfree(probe_resp_data); 1306} 1307 1308/* Asynchronously update the packet templates in template RAM. */ 1309static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon) 1310{ 1311 unsigned long flags; 1312 1313 /* This is the top half of the ansynchronous beacon update. 1314 * The bottom half is the beacon IRQ. 1315 * Beacon update must be asynchronous to avoid sending an 1316 * invalid beacon. This can happen for example, if the firmware 1317 * transmits a beacon while we are updating it. */ 1318 1319 spin_lock_irqsave(&wl->irq_lock, flags); 1320 1321 if (wl->current_beacon) 1322 dev_kfree_skb_any(wl->current_beacon); 1323 wl->current_beacon = beacon; 1324 wl->beacon0_uploaded = 0; 1325 wl->beacon1_uploaded = 0; 1326 1327 spin_unlock_irqrestore(&wl->irq_lock, flags); 1328} 1329 1330static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len) 1331{ 1332 u32 tmp; 1333 u16 i, len; 1334 1335 len = min((u16) ssid_len, (u16) 0x100); 1336 for (i = 0; i < len; i += sizeof(u32)) { 1337 tmp = (u32) (ssid[i + 0]); 1338 if (i + 1 < len) 1339 tmp |= (u32) (ssid[i + 1]) << 8; 1340 if (i + 2 < len) 1341 tmp |= (u32) (ssid[i + 2]) << 16; 1342 if (i + 3 < len) 1343 tmp |= (u32) (ssid[i + 3]) << 24; 1344 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp); 1345 } 1346 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len); 1347} 1348 1349static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1350{ 1351 b43_time_lock(dev); 1352 if (dev->dev->id.revision >= 3) { 1353 b43_write32(dev, 0x188, (beacon_int << 16)); 1354 } else { 1355 b43_write16(dev, 0x606, (beacon_int >> 6)); 1356 b43_write16(dev, 0x610, beacon_int); 1357 } 1358 b43_time_unlock(dev); 1359} 1360 1361static void handle_irq_beacon(struct b43_wldev *dev) 1362{ 1363 struct b43_wl *wl = dev->wl; 1364 u32 cmd; 1365 1366 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 1367 return; 1368 1369 /* This is the bottom half of the asynchronous beacon update. */ 1370 1371 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1372 if (!(cmd & B43_MACCMD_BEACON0_VALID)) { 1373 if (!wl->beacon0_uploaded) { 1374 b43_write_beacon_template(dev, 0x68, 0x18, 1375 B43_CCK_RATE_1MB); 1376 b43_write_probe_resp_template(dev, 0x268, 0x4A, 1377 B43_CCK_RATE_11MB); 1378 wl->beacon0_uploaded = 1; 1379 } 1380 cmd |= B43_MACCMD_BEACON0_VALID; 1381 } 1382 if (!(cmd & B43_MACCMD_BEACON1_VALID)) { 1383 if (!wl->beacon1_uploaded) { 1384 b43_write_beacon_template(dev, 0x468, 0x1A, 1385 B43_CCK_RATE_1MB); 1386 wl->beacon1_uploaded = 1; 1387 } 1388 cmd |= B43_MACCMD_BEACON1_VALID; 1389 } 1390 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1391} 1392 1393static void handle_irq_ucode_debug(struct b43_wldev *dev) 1394{ 1395 //TODO 1396} 1397 1398/* Interrupt handler bottom-half */ 1399static void b43_interrupt_tasklet(struct b43_wldev *dev) 1400{ 1401 u32 reason; 1402 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1403 u32 merged_dma_reason = 0; 1404 int i; 1405 unsigned long flags; 1406 1407 spin_lock_irqsave(&dev->wl->irq_lock, flags); 1408 1409 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED); 1410 1411 reason = dev->irq_reason; 1412 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1413 dma_reason[i] = dev->dma_reason[i]; 1414 merged_dma_reason |= dma_reason[i]; 1415 } 1416 1417 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1418 b43err(dev->wl, "MAC transmission error\n"); 1419 1420 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1421 b43err(dev->wl, "PHY transmission error\n"); 1422 rmb(); 1423 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1424 atomic_set(&dev->phy.txerr_cnt, 1425 B43_PHY_TX_BADNESS_LIMIT); 1426 b43err(dev->wl, "Too many PHY TX errors, " 1427 "restarting the controller\n"); 1428 b43_controller_restart(dev, "PHY TX errors"); 1429 } 1430 } 1431 1432 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | 1433 B43_DMAIRQ_NONFATALMASK))) { 1434 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { 1435 b43err(dev->wl, "Fatal DMA error: " 1436 "0x%08X, 0x%08X, 0x%08X, " 1437 "0x%08X, 0x%08X, 0x%08X\n", 1438 dma_reason[0], dma_reason[1], 1439 dma_reason[2], dma_reason[3], 1440 dma_reason[4], dma_reason[5]); 1441 b43_controller_restart(dev, "DMA error"); 1442 mmiowb(); 1443 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1444 return; 1445 } 1446 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { 1447 b43err(dev->wl, "DMA error: " 1448 "0x%08X, 0x%08X, 0x%08X, " 1449 "0x%08X, 0x%08X, 0x%08X\n", 1450 dma_reason[0], dma_reason[1], 1451 dma_reason[2], dma_reason[3], 1452 dma_reason[4], dma_reason[5]); 1453 } 1454 } 1455 1456 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 1457 handle_irq_ucode_debug(dev); 1458 if (reason & B43_IRQ_TBTT_INDI) 1459 handle_irq_tbtt_indication(dev); 1460 if (reason & B43_IRQ_ATIM_END) 1461 handle_irq_atim_end(dev); 1462 if (reason & B43_IRQ_BEACON) 1463 handle_irq_beacon(dev); 1464 if (reason & B43_IRQ_PMQ) 1465 handle_irq_pmq(dev); 1466 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) 1467 ;/* TODO */ 1468 if (reason & B43_IRQ_NOISESAMPLE_OK) 1469 handle_irq_noise(dev); 1470 1471 /* Check the DMA reason registers for received data. */ 1472 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) 1473 b43_dma_rx(dev->dma.rx_ring0); 1474 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) 1475 b43_dma_rx(dev->dma.rx_ring3); 1476 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 1477 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 1478 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 1479 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 1480 1481 if (reason & B43_IRQ_TX_OK) 1482 handle_irq_transmit_status(dev); 1483 1484 b43_interrupt_enable(dev, dev->irq_savedstate); 1485 mmiowb(); 1486 spin_unlock_irqrestore(&dev->wl->irq_lock, flags); 1487} 1488 1489static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason) 1490{ 1491 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 1492 1493 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 1494 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 1495 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 1496 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 1497 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 1498 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 1499} 1500 1501/* Interrupt handler top-half */ 1502static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 1503{ 1504 irqreturn_t ret = IRQ_NONE; 1505 struct b43_wldev *dev = dev_id; 1506 u32 reason; 1507 1508 if (!dev) 1509 return IRQ_NONE; 1510 1511 spin_lock(&dev->wl->irq_lock); 1512 1513 if (b43_status(dev) < B43_STAT_STARTED) 1514 goto out; 1515 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1516 if (reason == 0xffffffff) /* shared IRQ */ 1517 goto out; 1518 ret = IRQ_HANDLED; 1519 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 1520 if (!reason) 1521 goto out; 1522 1523 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1524 & 0x0001DC00; 1525 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 1526 & 0x0000DC00; 1527 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 1528 & 0x0000DC00; 1529 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 1530 & 0x0001DC00; 1531 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 1532 & 0x0000DC00; 1533 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 1534 & 0x0000DC00; 1535 1536 b43_interrupt_ack(dev, reason); 1537 /* disable all IRQs. They are enabled again in the bottom half. */ 1538 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 1539 /* save the reason code and call our bottom half. */ 1540 dev->irq_reason = reason; 1541 tasklet_schedule(&dev->isr_tasklet); 1542 out: 1543 mmiowb(); 1544 spin_unlock(&dev->wl->irq_lock); 1545 1546 return ret; 1547} 1548 1549static void b43_release_firmware(struct b43_wldev *dev) 1550{ 1551 release_firmware(dev->fw.ucode); 1552 dev->fw.ucode = NULL; 1553 release_firmware(dev->fw.pcm); 1554 dev->fw.pcm = NULL; 1555 release_firmware(dev->fw.initvals); 1556 dev->fw.initvals = NULL; 1557 release_firmware(dev->fw.initvals_band); 1558 dev->fw.initvals_band = NULL; 1559} 1560 1561static void b43_print_fw_helptext(struct b43_wl *wl) 1562{ 1563 b43err(wl, "You must go to " 1564 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware " 1565 "and download the correct firmware (version 4).\n"); 1566} 1567 1568static int do_request_fw(struct b43_wldev *dev, 1569 const char *name, 1570 const struct firmware **fw) 1571{ 1572 char path[sizeof(modparam_fwpostfix) + 32]; 1573 struct b43_fw_header *hdr; 1574 u32 size; 1575 int err; 1576 1577 if (!name) 1578 return 0; 1579 1580 snprintf(path, ARRAY_SIZE(path), 1581 "b43%s/%s.fw", 1582 modparam_fwpostfix, name); 1583 err = request_firmware(fw, path, dev->dev->dev); 1584 if (err) { 1585 b43err(dev->wl, "Firmware file \"%s\" not found " 1586 "or load failed.\n", path); 1587 return err; 1588 } 1589 if ((*fw)->size < sizeof(struct b43_fw_header)) 1590 goto err_format; 1591 hdr = (struct b43_fw_header *)((*fw)->data); 1592 switch (hdr->type) { 1593 case B43_FW_TYPE_UCODE: 1594 case B43_FW_TYPE_PCM: 1595 size = be32_to_cpu(hdr->size); 1596 if (size != (*fw)->size - sizeof(struct b43_fw_header)) 1597 goto err_format; 1598 /* fallthrough */ 1599 case B43_FW_TYPE_IV: 1600 if (hdr->ver != 1) 1601 goto err_format; 1602 break; 1603 default: 1604 goto err_format; 1605 } 1606 1607 return err; 1608 1609err_format: 1610 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path); 1611 return -EPROTO; 1612} 1613 1614static int b43_request_firmware(struct b43_wldev *dev) 1615{ 1616 struct b43_firmware *fw = &dev->fw; 1617 const u8 rev = dev->dev->id.revision; 1618 const char *filename; 1619 u32 tmshigh; 1620 int err; 1621 1622 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 1623 if (!fw->ucode) { 1624 if ((rev >= 5) && (rev <= 10)) 1625 filename = "ucode5"; 1626 else if ((rev >= 11) && (rev <= 12)) 1627 filename = "ucode11"; 1628 else if (rev >= 13) 1629 filename = "ucode13"; 1630 else 1631 goto err_no_ucode; 1632 err = do_request_fw(dev, filename, &fw->ucode); 1633 if (err) 1634 goto err_load; 1635 } 1636 if (!fw->pcm) { 1637 if ((rev >= 5) && (rev <= 10)) 1638 filename = "pcm5"; 1639 else if (rev >= 11) 1640 filename = NULL; 1641 else 1642 goto err_no_pcm; 1643 err = do_request_fw(dev, filename, &fw->pcm); 1644 if (err) 1645 goto err_load; 1646 } 1647 if (!fw->initvals) { 1648 switch (dev->phy.type) { 1649 case B43_PHYTYPE_A: 1650 if ((rev >= 5) && (rev <= 10)) { 1651 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 1652 filename = "a0g1initvals5"; 1653 else 1654 filename = "a0g0initvals5"; 1655 } else 1656 goto err_no_initvals; 1657 break; 1658 case B43_PHYTYPE_G: 1659 if ((rev >= 5) && (rev <= 10)) 1660 filename = "b0g0initvals5"; 1661 else if (rev >= 13) 1662 filename = "lp0initvals13"; 1663 else 1664 goto err_no_initvals; 1665 break; 1666 default: 1667 goto err_no_initvals; 1668 } 1669 err = do_request_fw(dev, filename, &fw->initvals); 1670 if (err) 1671 goto err_load; 1672 } 1673 if (!fw->initvals_band) { 1674 switch (dev->phy.type) { 1675 case B43_PHYTYPE_A: 1676 if ((rev >= 5) && (rev <= 10)) { 1677 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 1678 filename = "a0g1bsinitvals5"; 1679 else 1680 filename = "a0g0bsinitvals5"; 1681 } else if (rev >= 11) 1682 filename = NULL; 1683 else 1684 goto err_no_initvals; 1685 break; 1686 case B43_PHYTYPE_G: 1687 if ((rev >= 5) && (rev <= 10)) 1688 filename = "b0g0bsinitvals5"; 1689 else if (rev >= 11) 1690 filename = NULL; 1691 else 1692 goto err_no_initvals; 1693 break; 1694 default: 1695 goto err_no_initvals; 1696 } 1697 err = do_request_fw(dev, filename, &fw->initvals_band); 1698 if (err) 1699 goto err_load; 1700 } 1701 1702 return 0; 1703 1704err_load: 1705 b43_print_fw_helptext(dev->wl); 1706 goto error; 1707 1708err_no_ucode: 1709 err = -ENODEV; 1710 b43err(dev->wl, "No microcode available for core rev %u\n", rev); 1711 goto error; 1712 1713err_no_pcm: 1714 err = -ENODEV; 1715 b43err(dev->wl, "No PCM available for core rev %u\n", rev); 1716 goto error; 1717 1718err_no_initvals: 1719 err = -ENODEV; 1720 b43err(dev->wl, "No Initial Values firmware file for PHY %u, " 1721 "core rev %u\n", dev->phy.type, rev); 1722 goto error; 1723 1724error: 1725 b43_release_firmware(dev); 1726 return err; 1727} 1728 1729static int b43_upload_microcode(struct b43_wldev *dev) 1730{ 1731 const size_t hdr_len = sizeof(struct b43_fw_header); 1732 const __be32 *data; 1733 unsigned int i, len; 1734 u16 fwrev, fwpatch, fwdate, fwtime; 1735 u32 tmp; 1736 int err = 0; 1737 1738 /* Upload Microcode. */ 1739 data = (__be32 *) (dev->fw.ucode->data + hdr_len); 1740 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32); 1741 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 1742 for (i = 0; i < len; i++) { 1743 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1744 udelay(10); 1745 } 1746 1747 if (dev->fw.pcm) { 1748 /* Upload PCM data. */ 1749 data = (__be32 *) (dev->fw.pcm->data + hdr_len); 1750 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32); 1751 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 1752 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 1753 /* No need for autoinc bit in SHM_HW */ 1754 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 1755 for (i = 0; i < len; i++) { 1756 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 1757 udelay(10); 1758 } 1759 } 1760 1761 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 1762 b43_write32(dev, B43_MMIO_MACCTL, 1763 B43_MACCTL_PSM_RUN | 1764 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA); 1765 1766 /* Wait for the microcode to load and respond */ 1767 i = 0; 1768 while (1) { 1769 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1770 if (tmp == B43_IRQ_MAC_SUSPENDED) 1771 break; 1772 i++; 1773 if (i >= 50) { 1774 b43err(dev->wl, "Microcode not responding\n"); 1775 b43_print_fw_helptext(dev->wl); 1776 err = -ENODEV; 1777 goto out; 1778 } 1779 udelay(10); 1780 } 1781 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 1782 1783 /* Get and check the revisions. */ 1784 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 1785 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 1786 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 1787 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 1788 1789 if (fwrev <= 0x128) { 1790 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 1791 "binary drivers older than version 4.x is unsupported. " 1792 "You must upgrade your firmware files.\n"); 1793 b43_print_fw_helptext(dev->wl); 1794 b43_write32(dev, B43_MMIO_MACCTL, 0); 1795 err = -EOPNOTSUPP; 1796 goto out; 1797 } 1798 b43dbg(dev->wl, "Loading firmware version %u.%u " 1799 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 1800 fwrev, fwpatch, 1801 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 1802 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 1803 1804 dev->fw.rev = fwrev; 1805 dev->fw.patch = fwpatch; 1806 1807 out: 1808 return err; 1809} 1810 1811static int b43_write_initvals(struct b43_wldev *dev, 1812 const struct b43_iv *ivals, 1813 size_t count, 1814 size_t array_size) 1815{ 1816 const struct b43_iv *iv; 1817 u16 offset; 1818 size_t i; 1819 bool bit32; 1820 1821 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 1822 iv = ivals; 1823 for (i = 0; i < count; i++) { 1824 if (array_size < sizeof(iv->offset_size)) 1825 goto err_format; 1826 array_size -= sizeof(iv->offset_size); 1827 offset = be16_to_cpu(iv->offset_size); 1828 bit32 = !!(offset & B43_IV_32BIT); 1829 offset &= B43_IV_OFFSET_MASK; 1830 if (offset >= 0x1000) 1831 goto err_format; 1832 if (bit32) { 1833 u32 value; 1834 1835 if (array_size < sizeof(iv->data.d32)) 1836 goto err_format; 1837 array_size -= sizeof(iv->data.d32); 1838 1839 value = be32_to_cpu(get_unaligned(&iv->data.d32)); 1840 b43_write32(dev, offset, value); 1841 1842 iv = (const struct b43_iv *)((const uint8_t *)iv + 1843 sizeof(__be16) + 1844 sizeof(__be32)); 1845 } else { 1846 u16 value; 1847 1848 if (array_size < sizeof(iv->data.d16)) 1849 goto err_format; 1850 array_size -= sizeof(iv->data.d16); 1851 1852 value = be16_to_cpu(iv->data.d16); 1853 b43_write16(dev, offset, value); 1854 1855 iv = (const struct b43_iv *)((const uint8_t *)iv + 1856 sizeof(__be16) + 1857 sizeof(__be16)); 1858 } 1859 } 1860 if (array_size) 1861 goto err_format; 1862 1863 return 0; 1864 1865err_format: 1866 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 1867 b43_print_fw_helptext(dev->wl); 1868 1869 return -EPROTO; 1870} 1871 1872static int b43_upload_initvals(struct b43_wldev *dev) 1873{ 1874 const size_t hdr_len = sizeof(struct b43_fw_header); 1875 const struct b43_fw_header *hdr; 1876 struct b43_firmware *fw = &dev->fw; 1877 const struct b43_iv *ivals; 1878 size_t count; 1879 int err; 1880 1881 hdr = (const struct b43_fw_header *)(fw->initvals->data); 1882 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len); 1883 count = be32_to_cpu(hdr->size); 1884 err = b43_write_initvals(dev, ivals, count, 1885 fw->initvals->size - hdr_len); 1886 if (err) 1887 goto out; 1888 if (fw->initvals_band) { 1889 hdr = (const struct b43_fw_header *)(fw->initvals_band->data); 1890 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len); 1891 count = be32_to_cpu(hdr->size); 1892 err = b43_write_initvals(dev, ivals, count, 1893 fw->initvals_band->size - hdr_len); 1894 if (err) 1895 goto out; 1896 } 1897out: 1898 1899 return err; 1900} 1901 1902/* Initialize the GPIOs 1903 * http://bcm-specs.sipsolutions.net/GPIO 1904 */ 1905static int b43_gpio_init(struct b43_wldev *dev) 1906{ 1907 struct ssb_bus *bus = dev->dev->bus; 1908 struct ssb_device *gpiodev, *pcidev = NULL; 1909 u32 mask, set; 1910 1911 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 1912 & ~B43_MACCTL_GPOUTSMSK); 1913 1914 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) 1915 | 0x000F); 1916 1917 mask = 0x0000001F; 1918 set = 0x0000000F; 1919 if (dev->dev->bus->chip_id == 0x4301) { 1920 mask |= 0x0060; 1921 set |= 0x0060; 1922 } 1923 if (0 /* FIXME: conditional unknown */ ) { 1924 b43_write16(dev, B43_MMIO_GPIO_MASK, 1925 b43_read16(dev, B43_MMIO_GPIO_MASK) 1926 | 0x0100); 1927 mask |= 0x0180; 1928 set |= 0x0180; 1929 } 1930 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) { 1931 b43_write16(dev, B43_MMIO_GPIO_MASK, 1932 b43_read16(dev, B43_MMIO_GPIO_MASK) 1933 | 0x0200); 1934 mask |= 0x0200; 1935 set |= 0x0200; 1936 } 1937 if (dev->dev->id.revision >= 2) 1938 mask |= 0x0010; /* FIXME: This is redundant. */ 1939 1940#ifdef CONFIG_SSB_DRIVER_PCICORE 1941 pcidev = bus->pcicore.dev; 1942#endif 1943 gpiodev = bus->chipco.dev ? : pcidev; 1944 if (!gpiodev) 1945 return 0; 1946 ssb_write32(gpiodev, B43_GPIO_CONTROL, 1947 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 1948 & mask) | set); 1949 1950 return 0; 1951} 1952 1953/* Turn off all GPIO stuff. Call this on module unload, for example. */ 1954static void b43_gpio_cleanup(struct b43_wldev *dev) 1955{ 1956 struct ssb_bus *bus = dev->dev->bus; 1957 struct ssb_device *gpiodev, *pcidev = NULL; 1958 1959#ifdef CONFIG_SSB_DRIVER_PCICORE 1960 pcidev = bus->pcicore.dev; 1961#endif 1962 gpiodev = bus->chipco.dev ? : pcidev; 1963 if (!gpiodev) 1964 return; 1965 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 1966} 1967 1968/* http://bcm-specs.sipsolutions.net/EnableMac */ 1969void b43_mac_enable(struct b43_wldev *dev) 1970{ 1971 dev->mac_suspended--; 1972 B43_WARN_ON(dev->mac_suspended < 0); 1973 B43_WARN_ON(irqs_disabled()); 1974 if (dev->mac_suspended == 0) { 1975 b43_write32(dev, B43_MMIO_MACCTL, 1976 b43_read32(dev, B43_MMIO_MACCTL) 1977 | B43_MACCTL_ENABLED); 1978 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 1979 B43_IRQ_MAC_SUSPENDED); 1980 /* Commit writes */ 1981 b43_read32(dev, B43_MMIO_MACCTL); 1982 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 1983 b43_power_saving_ctl_bits(dev, 0); 1984 1985 /* Re-enable IRQs. */ 1986 spin_lock_irq(&dev->wl->irq_lock); 1987 b43_interrupt_enable(dev, dev->irq_savedstate); 1988 spin_unlock_irq(&dev->wl->irq_lock); 1989 } 1990} 1991 1992/* http://bcm-specs.sipsolutions.net/SuspendMAC */ 1993void b43_mac_suspend(struct b43_wldev *dev) 1994{ 1995 int i; 1996 u32 tmp; 1997 1998 might_sleep(); 1999 B43_WARN_ON(irqs_disabled()); 2000 B43_WARN_ON(dev->mac_suspended < 0); 2001 2002 if (dev->mac_suspended == 0) { 2003 /* Mask IRQs before suspending MAC. Otherwise 2004 * the MAC stays busy and won't suspend. */ 2005 spin_lock_irq(&dev->wl->irq_lock); 2006 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL); 2007 spin_unlock_irq(&dev->wl->irq_lock); 2008 b43_synchronize_irq(dev); 2009 dev->irq_savedstate = tmp; 2010 2011 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2012 b43_write32(dev, B43_MMIO_MACCTL, 2013 b43_read32(dev, B43_MMIO_MACCTL) 2014 & ~B43_MACCTL_ENABLED); 2015 /* force pci to flush the write */ 2016 b43_read32(dev, B43_MMIO_MACCTL); 2017 for (i = 40; i; i--) { 2018 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2019 if (tmp & B43_IRQ_MAC_SUSPENDED) 2020 goto out; 2021 msleep(1); 2022 } 2023 b43err(dev->wl, "MAC suspend failed\n"); 2024 } 2025out: 2026 dev->mac_suspended++; 2027} 2028 2029static void b43_adjust_opmode(struct b43_wldev *dev) 2030{ 2031 struct b43_wl *wl = dev->wl; 2032 u32 ctl; 2033 u16 cfp_pretbtt; 2034 2035 ctl = b43_read32(dev, B43_MMIO_MACCTL); 2036 /* Reset status to STA infrastructure mode. */ 2037 ctl &= ~B43_MACCTL_AP; 2038 ctl &= ~B43_MACCTL_KEEP_CTL; 2039 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 2040 ctl &= ~B43_MACCTL_KEEP_BAD; 2041 ctl &= ~B43_MACCTL_PROMISC; 2042 ctl &= ~B43_MACCTL_BEACPROMISC; 2043 ctl |= B43_MACCTL_INFRA; 2044 2045 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2046 ctl |= B43_MACCTL_AP; 2047 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) 2048 ctl &= ~B43_MACCTL_INFRA; 2049 2050 if (wl->filter_flags & FIF_CONTROL) 2051 ctl |= B43_MACCTL_KEEP_CTL; 2052 if (wl->filter_flags & FIF_FCSFAIL) 2053 ctl |= B43_MACCTL_KEEP_BAD; 2054 if (wl->filter_flags & FIF_PLCPFAIL) 2055 ctl |= B43_MACCTL_KEEP_BADPLCP; 2056 if (wl->filter_flags & FIF_PROMISC_IN_BSS) 2057 ctl |= B43_MACCTL_PROMISC; 2058 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 2059 ctl |= B43_MACCTL_BEACPROMISC; 2060 2061 /* Workaround: On old hardware the HW-MAC-address-filter 2062 * doesn't work properly, so always run promisc in filter 2063 * it in software. */ 2064 if (dev->dev->id.revision <= 4) 2065 ctl |= B43_MACCTL_PROMISC; 2066 2067 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2068 2069 cfp_pretbtt = 2; 2070 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2071 if (dev->dev->bus->chip_id == 0x4306 && 2072 dev->dev->bus->chip_rev == 3) 2073 cfp_pretbtt = 100; 2074 else 2075 cfp_pretbtt = 50; 2076 } 2077 b43_write16(dev, 0x612, cfp_pretbtt); 2078} 2079 2080static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 2081{ 2082 u16 offset; 2083 2084 if (is_ofdm) { 2085 offset = 0x480; 2086 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 2087 } else { 2088 offset = 0x4C0; 2089 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 2090 } 2091 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 2092 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 2093} 2094 2095static void b43_rate_memory_init(struct b43_wldev *dev) 2096{ 2097 switch (dev->phy.type) { 2098 case B43_PHYTYPE_A: 2099 case B43_PHYTYPE_G: 2100 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 2101 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 2102 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 2103 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 2104 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 2105 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 2106 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 2107 if (dev->phy.type == B43_PHYTYPE_A) 2108 break; 2109 /* fallthrough */ 2110 case B43_PHYTYPE_B: 2111 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 2112 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 2113 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 2114 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 2115 break; 2116 default: 2117 B43_WARN_ON(1); 2118 } 2119} 2120 2121/* Set the TX-Antenna for management frames sent by firmware. */ 2122static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 2123{ 2124 u16 ant = 0; 2125 u16 tmp; 2126 2127 switch (antenna) { 2128 case B43_ANTENNA0: 2129 ant |= B43_TX4_PHY_ANT0; 2130 break; 2131 case B43_ANTENNA1: 2132 ant |= B43_TX4_PHY_ANT1; 2133 break; 2134 case B43_ANTENNA_AUTO: 2135 ant |= B43_TX4_PHY_ANTLAST; 2136 break; 2137 default: 2138 B43_WARN_ON(1); 2139 } 2140 2141 /* FIXME We also need to set the other flags of the PHY control field somewhere. */ 2142 2143 /* For Beacons */ 2144 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 2145 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2146 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp); 2147 /* For ACK/CTS */ 2148 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 2149 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2150 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 2151 /* For Probe Resposes */ 2152 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 2153 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant; 2154 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 2155} 2156 2157/* This is the opposite of b43_chip_init() */ 2158static void b43_chip_exit(struct b43_wldev *dev) 2159{ 2160 b43_radio_turn_off(dev, 1); 2161 b43_gpio_cleanup(dev); 2162 /* firmware is released later */ 2163} 2164 2165/* Initialize the chip 2166 * http://bcm-specs.sipsolutions.net/ChipInit 2167 */ 2168static int b43_chip_init(struct b43_wldev *dev) 2169{ 2170 struct b43_phy *phy = &dev->phy; 2171 int err, tmp; 2172 u32 value32; 2173 u16 value16; 2174 2175 b43_write32(dev, B43_MMIO_MACCTL, 2176 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED); 2177 2178 err = b43_request_firmware(dev); 2179 if (err) 2180 goto out; 2181 err = b43_upload_microcode(dev); 2182 if (err) 2183 goto out; /* firmware is released later */ 2184 2185 err = b43_gpio_init(dev); 2186 if (err) 2187 goto out; /* firmware is released later */ 2188 2189 err = b43_upload_initvals(dev); 2190 if (err) 2191 goto err_gpio_clean; 2192 b43_radio_turn_on(dev); 2193 2194 b43_write16(dev, 0x03E6, 0x0000); 2195 err = b43_phy_init(dev); 2196 if (err) 2197 goto err_radio_off; 2198 2199 /* Select initial Interference Mitigation. */ 2200 tmp = phy->interfmode; 2201 phy->interfmode = B43_INTERFMODE_NONE; 2202 b43_radio_set_interference_mitigation(dev, tmp); 2203 2204 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2205 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2206 2207 if (phy->type == B43_PHYTYPE_B) { 2208 value16 = b43_read16(dev, 0x005E); 2209 value16 |= 0x0004; 2210 b43_write16(dev, 0x005E, value16); 2211 } 2212 b43_write32(dev, 0x0100, 0x01000000); 2213 if (dev->dev->id.revision < 5) 2214 b43_write32(dev, 0x010C, 0x01000000); 2215 2216 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2217 & ~B43_MACCTL_INFRA); 2218 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 2219 | B43_MACCTL_INFRA); 2220 2221 /* Probe Response Timeout value */ 2222 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 2223 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 2224 2225 /* Initially set the wireless operation mode. */ 2226 b43_adjust_opmode(dev); 2227 2228 if (dev->dev->id.revision < 3) { 2229 b43_write16(dev, 0x060E, 0x0000); 2230 b43_write16(dev, 0x0610, 0x8000); 2231 b43_write16(dev, 0x0604, 0x0000); 2232 b43_write16(dev, 0x0606, 0x0200); 2233 } else { 2234 b43_write32(dev, 0x0188, 0x80000000); 2235 b43_write32(dev, 0x018C, 0x02000000); 2236 } 2237 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 2238 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); 2239 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 2240 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 2241 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 2242 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 2243 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 2244 2245 value32 = ssb_read32(dev->dev, SSB_TMSLOW); 2246 value32 |= 0x00100000; 2247 ssb_write32(dev->dev, SSB_TMSLOW, value32); 2248 2249 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 2250 dev->dev->bus->chipco.fast_pwrup_delay); 2251 2252 err = 0; 2253 b43dbg(dev->wl, "Chip initialized\n"); 2254out: 2255 return err; 2256 2257err_radio_off: 2258 b43_radio_turn_off(dev, 1); 2259err_gpio_clean: 2260 b43_gpio_cleanup(dev); 2261 return err; 2262} 2263 2264static void b43_periodic_every120sec(struct b43_wldev *dev) 2265{ 2266 struct b43_phy *phy = &dev->phy; 2267 2268 if (phy->type != B43_PHYTYPE_G || phy->rev < 2) 2269 return; 2270 2271 b43_mac_suspend(dev); 2272 b43_lo_g_measure(dev); 2273 b43_mac_enable(dev); 2274 if (b43_has_hardware_pctl(phy)) 2275 b43_lo_g_ctl_mark_all_unused(dev); 2276} 2277 2278static void b43_periodic_every60sec(struct b43_wldev *dev) 2279{ 2280 struct b43_phy *phy = &dev->phy; 2281 2282 if (!b43_has_hardware_pctl(phy)) 2283 b43_lo_g_ctl_mark_all_unused(dev); 2284 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) { 2285 b43_mac_suspend(dev); 2286 b43_calc_nrssi_slope(dev); 2287 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { 2288 u8 old_chan = phy->channel; 2289 2290 /* VCO Calibration */ 2291 if (old_chan >= 8) 2292 b43_radio_selectchannel(dev, 1, 0); 2293 else 2294 b43_radio_selectchannel(dev, 13, 0); 2295 b43_radio_selectchannel(dev, old_chan, 0); 2296 } 2297 b43_mac_enable(dev); 2298 } 2299} 2300 2301static void b43_periodic_every30sec(struct b43_wldev *dev) 2302{ 2303 /* Update device statistics. */ 2304 b43_calculate_link_quality(dev); 2305} 2306 2307static void b43_periodic_every15sec(struct b43_wldev *dev) 2308{ 2309 struct b43_phy *phy = &dev->phy; 2310 2311 if (phy->type == B43_PHYTYPE_G) { 2312 //TODO: update_aci_moving_average 2313 if (phy->aci_enable && phy->aci_wlan_automatic) { 2314 b43_mac_suspend(dev); 2315 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) { 2316 if (0 /*TODO: bunch of conditions */ ) { 2317 b43_radio_set_interference_mitigation 2318 (dev, B43_INTERFMODE_MANUALWLAN); 2319 } 2320 } else if (1 /*TODO*/) { 2321 /* 2322 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) { 2323 b43_radio_set_interference_mitigation(dev, 2324 B43_INTERFMODE_NONE); 2325 } 2326 */ 2327 } 2328 b43_mac_enable(dev); 2329 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN && 2330 phy->rev == 1) { 2331 //TODO: implement rev1 workaround 2332 } 2333 } 2334 b43_phy_xmitpower(dev); //FIXME: unless scanning? 2335 //TODO for APHY (temperature?) 2336 2337 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 2338 wmb(); 2339} 2340 2341static void do_periodic_work(struct b43_wldev *dev) 2342{ 2343 unsigned int state; 2344 2345 state = dev->periodic_state; 2346 if (state % 8 == 0) 2347 b43_periodic_every120sec(dev); 2348 if (state % 4 == 0) 2349 b43_periodic_every60sec(dev); 2350 if (state % 2 == 0) 2351 b43_periodic_every30sec(dev); 2352 b43_periodic_every15sec(dev); 2353} 2354 2355/* Periodic work locking policy: 2356 * The whole periodic work handler is protected by 2357 * wl->mutex. If another lock is needed somewhere in the 2358 * pwork callchain, it's aquired in-place, where it's needed. 2359 */ 2360static void b43_periodic_work_handler(struct work_struct *work) 2361{ 2362 struct b43_wldev *dev = container_of(work, struct b43_wldev, 2363 periodic_work.work); 2364 struct b43_wl *wl = dev->wl; 2365 unsigned long delay; 2366 2367 mutex_lock(&wl->mutex); 2368 2369 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 2370 goto out; 2371 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 2372 goto out_requeue; 2373 2374 do_periodic_work(dev); 2375 2376 dev->periodic_state++; 2377out_requeue: 2378 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 2379 delay = msecs_to_jiffies(50); 2380 else 2381 delay = round_jiffies_relative(HZ * 15); 2382 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay); 2383out: 2384 mutex_unlock(&wl->mutex); 2385} 2386 2387static void b43_periodic_tasks_setup(struct b43_wldev *dev) 2388{ 2389 struct delayed_work *work = &dev->periodic_work; 2390 2391 dev->periodic_state = 0; 2392 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 2393 queue_delayed_work(dev->wl->hw->workqueue, work, 0); 2394} 2395 2396/* Check if communication with the device works correctly. */ 2397static int b43_validate_chipaccess(struct b43_wldev *dev) 2398{ 2399 u32 v, backup; 2400 2401 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0); 2402 2403 /* Check for read/write and endianness problems. */ 2404 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 2405 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 2406 goto error; 2407 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 2408 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 2409 goto error; 2410 2411 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup); 2412 2413 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) { 2414 /* The 32bit register shadows the two 16bit registers 2415 * with update sideeffects. Validate this. */ 2416 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 2417 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 2418 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 2419 goto error; 2420 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 2421 goto error; 2422 } 2423 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 2424 2425 v = b43_read32(dev, B43_MMIO_MACCTL); 2426 v |= B43_MACCTL_GMODE; 2427 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 2428 goto error; 2429 2430 return 0; 2431error: 2432 b43err(dev->wl, "Failed to validate the chipaccess\n"); 2433 return -ENODEV; 2434} 2435 2436static void b43_security_init(struct b43_wldev *dev) 2437{ 2438 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20; 2439 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key)); 2440 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 2441 /* KTP is a word address, but we address SHM bytewise. 2442 * So multiply by two. 2443 */ 2444 dev->ktp *= 2; 2445 if (dev->dev->id.revision >= 5) { 2446 /* Number of RCMTA address slots */ 2447 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8); 2448 } 2449 b43_clear_keys(dev); 2450} 2451 2452static int b43_rng_read(struct hwrng *rng, u32 * data) 2453{ 2454 struct b43_wl *wl = (struct b43_wl *)rng->priv; 2455 unsigned long flags; 2456 2457 /* Don't take wl->mutex here, as it could deadlock with 2458 * hwrng internal locking. It's not needed to take 2459 * wl->mutex here, anyway. */ 2460 2461 spin_lock_irqsave(&wl->irq_lock, flags); 2462 *data = b43_read16(wl->current_dev, B43_MMIO_RNG); 2463 spin_unlock_irqrestore(&wl->irq_lock, flags); 2464 2465 return (sizeof(u16)); 2466} 2467 2468static void b43_rng_exit(struct b43_wl *wl) 2469{ 2470 if (wl->rng_initialized) 2471 hwrng_unregister(&wl->rng); 2472} 2473 2474static int b43_rng_init(struct b43_wl *wl) 2475{ 2476 int err; 2477 2478 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 2479 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 2480 wl->rng.name = wl->rng_name; 2481 wl->rng.data_read = b43_rng_read; 2482 wl->rng.priv = (unsigned long)wl; 2483 wl->rng_initialized = 1; 2484 err = hwrng_register(&wl->rng); 2485 if (err) { 2486 wl->rng_initialized = 0; 2487 b43err(wl, "Failed to register the random " 2488 "number generator (%d)\n", err); 2489 } 2490 2491 return err; 2492} 2493 2494static int b43_op_tx(struct ieee80211_hw *hw, 2495 struct sk_buff *skb, 2496 struct ieee80211_tx_control *ctl) 2497{ 2498 struct b43_wl *wl = hw_to_b43_wl(hw); 2499 struct b43_wldev *dev = wl->current_dev; 2500 int err = -ENODEV; 2501 2502 if (unlikely(!dev)) 2503 goto out; 2504 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2505 goto out; 2506 /* DMA-TX is done without a global lock. */ 2507 err = b43_dma_tx(dev, skb, ctl); 2508out: 2509 if (unlikely(err)) 2510 return NETDEV_TX_BUSY; 2511 return NETDEV_TX_OK; 2512} 2513 2514static int b43_op_conf_tx(struct ieee80211_hw *hw, 2515 int queue, 2516 const struct ieee80211_tx_queue_params *params) 2517{ 2518 return 0; 2519} 2520 2521static int b43_op_get_tx_stats(struct ieee80211_hw *hw, 2522 struct ieee80211_tx_queue_stats *stats) 2523{ 2524 struct b43_wl *wl = hw_to_b43_wl(hw); 2525 struct b43_wldev *dev = wl->current_dev; 2526 unsigned long flags; 2527 int err = -ENODEV; 2528 2529 if (!dev) 2530 goto out; 2531 spin_lock_irqsave(&wl->irq_lock, flags); 2532 if (likely(b43_status(dev) >= B43_STAT_STARTED)) { 2533 b43_dma_get_tx_stats(dev, stats); 2534 err = 0; 2535 } 2536 spin_unlock_irqrestore(&wl->irq_lock, flags); 2537out: 2538 return err; 2539} 2540 2541static int b43_op_get_stats(struct ieee80211_hw *hw, 2542 struct ieee80211_low_level_stats *stats) 2543{ 2544 struct b43_wl *wl = hw_to_b43_wl(hw); 2545 unsigned long flags; 2546 2547 spin_lock_irqsave(&wl->irq_lock, flags); 2548 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 2549 spin_unlock_irqrestore(&wl->irq_lock, flags); 2550 2551 return 0; 2552} 2553 2554static const char *phymode_to_string(unsigned int phymode) 2555{ 2556 switch (phymode) { 2557 case B43_PHYMODE_A: 2558 return "A"; 2559 case B43_PHYMODE_B: 2560 return "B"; 2561 case B43_PHYMODE_G: 2562 return "G"; 2563 default: 2564 B43_WARN_ON(1); 2565 } 2566 return ""; 2567} 2568 2569static int find_wldev_for_phymode(struct b43_wl *wl, 2570 unsigned int phymode, 2571 struct b43_wldev **dev, bool * gmode) 2572{ 2573 struct b43_wldev *d; 2574 2575 list_for_each_entry(d, &wl->devlist, list) { 2576 if (d->phy.possible_phymodes & phymode) { 2577 /* Ok, this device supports the PHY-mode. 2578 * Now figure out how the gmode bit has to be 2579 * set to support it. */ 2580 if (phymode == B43_PHYMODE_A) 2581 *gmode = 0; 2582 else 2583 *gmode = 1; 2584 *dev = d; 2585 2586 return 0; 2587 } 2588 } 2589 2590 return -ESRCH; 2591} 2592 2593static void b43_put_phy_into_reset(struct b43_wldev *dev) 2594{ 2595 struct ssb_device *sdev = dev->dev; 2596 u32 tmslow; 2597 2598 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2599 tmslow &= ~B43_TMSLOW_GMODE; 2600 tmslow |= B43_TMSLOW_PHYRESET; 2601 tmslow |= SSB_TMSLOW_FGC; 2602 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2603 msleep(1); 2604 2605 tmslow = ssb_read32(sdev, SSB_TMSLOW); 2606 tmslow &= ~SSB_TMSLOW_FGC; 2607 tmslow |= B43_TMSLOW_PHYRESET; 2608 ssb_write32(sdev, SSB_TMSLOW, tmslow); 2609 msleep(1); 2610} 2611 2612/* Expects wl->mutex locked */ 2613static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode) 2614{ 2615 struct b43_wldev *up_dev; 2616 struct b43_wldev *down_dev; 2617 int err; 2618 bool gmode = 0; 2619 int prev_status; 2620 2621 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode); 2622 if (err) { 2623 b43err(wl, "Could not find a device for %s-PHY mode\n", 2624 phymode_to_string(new_mode)); 2625 return err; 2626 } 2627 if ((up_dev == wl->current_dev) && 2628 (!!wl->current_dev->phy.gmode == !!gmode)) { 2629 /* This device is already running. */ 2630 return 0; 2631 } 2632 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n", 2633 phymode_to_string(new_mode)); 2634 down_dev = wl->current_dev; 2635 2636 prev_status = b43_status(down_dev); 2637 /* Shutdown the currently running core. */ 2638 if (prev_status >= B43_STAT_STARTED) 2639 b43_wireless_core_stop(down_dev); 2640 if (prev_status >= B43_STAT_INITIALIZED) 2641 b43_wireless_core_exit(down_dev); 2642 2643 if (down_dev != up_dev) { 2644 /* We switch to a different core, so we put PHY into 2645 * RESET on the old core. */ 2646 b43_put_phy_into_reset(down_dev); 2647 } 2648 2649 /* Now start the new core. */ 2650 up_dev->phy.gmode = gmode; 2651 if (prev_status >= B43_STAT_INITIALIZED) { 2652 err = b43_wireless_core_init(up_dev); 2653 if (err) { 2654 b43err(wl, "Fatal: Could not initialize device for " 2655 "newly selected %s-PHY mode\n", 2656 phymode_to_string(new_mode)); 2657 goto init_failure; 2658 } 2659 } 2660 if (prev_status >= B43_STAT_STARTED) { 2661 err = b43_wireless_core_start(up_dev); 2662 if (err) { 2663 b43err(wl, "Fatal: Coult not start device for " 2664 "newly selected %s-PHY mode\n", 2665 phymode_to_string(new_mode)); 2666 b43_wireless_core_exit(up_dev); 2667 goto init_failure; 2668 } 2669 } 2670 B43_WARN_ON(b43_status(up_dev) != prev_status); 2671 2672 wl->current_dev = up_dev; 2673 2674 return 0; 2675 init_failure: 2676 /* Whoops, failed to init the new core. No core is operating now. */ 2677 wl->current_dev = NULL; 2678 return err; 2679} 2680 2681/* Check if the use of the antenna that ieee80211 told us to 2682 * use is possible. This will fall back to DEFAULT. 2683 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 2684u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 2685 u8 antenna_nr) 2686{ 2687 u8 antenna_mask; 2688 2689 if (antenna_nr == 0) { 2690 /* Zero means "use default antenna". That's always OK. */ 2691 return 0; 2692 } 2693 2694 /* Get the mask of available antennas. */ 2695 if (dev->phy.gmode) 2696 antenna_mask = dev->dev->bus->sprom.ant_available_bg; 2697 else 2698 antenna_mask = dev->dev->bus->sprom.ant_available_a; 2699 2700 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 2701 /* This antenna is not available. Fall back to default. */ 2702 return 0; 2703 } 2704 2705 return antenna_nr; 2706} 2707 2708static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna) 2709{ 2710 antenna = b43_ieee80211_antenna_sanitize(dev, antenna); 2711 switch (antenna) { 2712 case 0: /* default/diversity */ 2713 return B43_ANTENNA_DEFAULT; 2714 case 1: /* Antenna 0 */ 2715 return B43_ANTENNA0; 2716 case 2: /* Antenna 1 */ 2717 return B43_ANTENNA1; 2718 default: 2719 return B43_ANTENNA_DEFAULT; 2720 } 2721} 2722 2723static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) 2724{ 2725 struct b43_wl *wl = hw_to_b43_wl(hw); 2726 struct b43_wldev *dev; 2727 struct b43_phy *phy; 2728 unsigned long flags; 2729 unsigned int new_phymode = 0xFFFF; 2730 int antenna; 2731 int err = 0; 2732 u32 savedirqs; 2733 2734 mutex_lock(&wl->mutex); 2735 2736 /* Switch the PHY mode (if necessary). */ 2737 switch (conf->phymode) { 2738 case MODE_IEEE80211A: 2739 new_phymode = B43_PHYMODE_A; 2740 break; 2741 case MODE_IEEE80211B: 2742 new_phymode = B43_PHYMODE_B; 2743 break; 2744 case MODE_IEEE80211G: 2745 new_phymode = B43_PHYMODE_G; 2746 break; 2747 default: 2748 B43_WARN_ON(1); 2749 } 2750 err = b43_switch_phymode(wl, new_phymode); 2751 if (err) 2752 goto out_unlock_mutex; 2753 dev = wl->current_dev; 2754 phy = &dev->phy; 2755 2756 /* Disable IRQs while reconfiguring the device. 2757 * This makes it possible to drop the spinlock throughout 2758 * the reconfiguration process. */ 2759 spin_lock_irqsave(&wl->irq_lock, flags); 2760 if (b43_status(dev) < B43_STAT_STARTED) { 2761 spin_unlock_irqrestore(&wl->irq_lock, flags); 2762 goto out_unlock_mutex; 2763 } 2764 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL); 2765 spin_unlock_irqrestore(&wl->irq_lock, flags); 2766 b43_synchronize_irq(dev); 2767 2768 /* Switch to the requested channel. 2769 * The firmware takes care of races with the TX handler. */ 2770 if (conf->channel_val != phy->channel) 2771 b43_radio_selectchannel(dev, conf->channel_val, 0); 2772 2773 /* Enable/Disable ShortSlot timing. */ 2774 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != 2775 dev->short_slot) { 2776 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2777 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) 2778 b43_short_slot_timing_enable(dev); 2779 else 2780 b43_short_slot_timing_disable(dev); 2781 } 2782 2783 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP); 2784 2785 /* Adjust the desired TX power level. */ 2786 if (conf->power_level != 0) { 2787 if (conf->power_level != phy->power_level) { 2788 phy->power_level = conf->power_level; 2789 b43_phy_xmitpower(dev); 2790 } 2791 } 2792 2793 /* Antennas for RX and management frame TX. */ 2794 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx); 2795 b43_mgmtframe_txantenna(dev, antenna); 2796 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx); 2797 b43_set_rx_antenna(dev, antenna); 2798 2799 /* Update templates for AP mode. */ 2800 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) 2801 b43_set_beacon_int(dev, conf->beacon_int); 2802 2803 if (!!conf->radio_enabled != phy->radio_on) { 2804 if (conf->radio_enabled) { 2805 b43_radio_turn_on(dev); 2806 b43info(dev->wl, "Radio turned on by software\n"); 2807 if (!dev->radio_hw_enable) { 2808 b43info(dev->wl, "The hardware RF-kill button " 2809 "still turns the radio physically off. " 2810 "Press the button to turn it on.\n"); 2811 } 2812 } else { 2813 b43_radio_turn_off(dev, 0); 2814 b43info(dev->wl, "Radio turned off by software\n"); 2815 } 2816 } 2817 2818 spin_lock_irqsave(&wl->irq_lock, flags); 2819 b43_interrupt_enable(dev, savedirqs); 2820 mmiowb(); 2821 spin_unlock_irqrestore(&wl->irq_lock, flags); 2822 out_unlock_mutex: 2823 mutex_unlock(&wl->mutex); 2824 2825 return err; 2826} 2827 2828static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 2829 const u8 *local_addr, const u8 *addr, 2830 struct ieee80211_key_conf *key) 2831{ 2832 struct b43_wl *wl = hw_to_b43_wl(hw); 2833 struct b43_wldev *dev; 2834 unsigned long flags; 2835 u8 algorithm; 2836 u8 index; 2837 int err; 2838 DECLARE_MAC_BUF(mac); 2839 2840 if (modparam_nohwcrypt) 2841 return -ENOSPC; /* User disabled HW-crypto */ 2842 2843 mutex_lock(&wl->mutex); 2844 spin_lock_irqsave(&wl->irq_lock, flags); 2845 2846 dev = wl->current_dev; 2847 err = -ENODEV; 2848 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 2849 goto out_unlock; 2850 2851 err = -EINVAL; 2852 switch (key->alg) { 2853 case ALG_WEP: 2854 if (key->keylen == 5) 2855 algorithm = B43_SEC_ALGO_WEP40; 2856 else 2857 algorithm = B43_SEC_ALGO_WEP104; 2858 break; 2859 case ALG_TKIP: 2860 algorithm = B43_SEC_ALGO_TKIP; 2861 break; 2862 case ALG_CCMP: 2863 algorithm = B43_SEC_ALGO_AES; 2864 break; 2865 default: 2866 B43_WARN_ON(1); 2867 goto out_unlock; 2868 } 2869 index = (u8) (key->keyidx); 2870 if (index > 3) 2871 goto out_unlock; 2872 2873 switch (cmd) { 2874 case SET_KEY: 2875 if (algorithm == B43_SEC_ALGO_TKIP) { 2876 /* FIXME: No TKIP hardware encryption for now. */ 2877 err = -EOPNOTSUPP; 2878 goto out_unlock; 2879 } 2880 2881 if (is_broadcast_ether_addr(addr)) { 2882 /* addr is FF:FF:FF:FF:FF:FF for default keys */ 2883 err = b43_key_write(dev, index, algorithm, 2884 key->key, key->keylen, NULL, key); 2885 } else { 2886 /* 2887 * either pairwise key or address is 00:00:00:00:00:00 2888 * for transmit-only keys 2889 */ 2890 err = b43_key_write(dev, -1, algorithm, 2891 key->key, key->keylen, addr, key); 2892 } 2893 if (err) 2894 goto out_unlock; 2895 2896 if (algorithm == B43_SEC_ALGO_WEP40 || 2897 algorithm == B43_SEC_ALGO_WEP104) { 2898 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 2899 } else { 2900 b43_hf_write(dev, 2901 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 2902 } 2903 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 2904 break; 2905 case DISABLE_KEY: { 2906 err = b43_key_clear(dev, key->hw_key_idx); 2907 if (err) 2908 goto out_unlock; 2909 break; 2910 } 2911 default: 2912 B43_WARN_ON(1); 2913 } 2914out_unlock: 2915 spin_unlock_irqrestore(&wl->irq_lock, flags); 2916 mutex_unlock(&wl->mutex); 2917 if (!err) { 2918 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 2919 "mac: %s\n", 2920 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 2921 print_mac(mac, addr)); 2922 } 2923 return err; 2924} 2925 2926static void b43_op_configure_filter(struct ieee80211_hw *hw, 2927 unsigned int changed, unsigned int *fflags, 2928 int mc_count, struct dev_addr_list *mc_list) 2929{ 2930 struct b43_wl *wl = hw_to_b43_wl(hw); 2931 struct b43_wldev *dev = wl->current_dev; 2932 unsigned long flags; 2933 2934 if (!dev) { 2935 *fflags = 0; 2936 return; 2937 } 2938 2939 spin_lock_irqsave(&wl->irq_lock, flags); 2940 *fflags &= FIF_PROMISC_IN_BSS | 2941 FIF_ALLMULTI | 2942 FIF_FCSFAIL | 2943 FIF_PLCPFAIL | 2944 FIF_CONTROL | 2945 FIF_OTHER_BSS | 2946 FIF_BCN_PRBRESP_PROMISC; 2947 2948 changed &= FIF_PROMISC_IN_BSS | 2949 FIF_ALLMULTI | 2950 FIF_FCSFAIL | 2951 FIF_PLCPFAIL | 2952 FIF_CONTROL | 2953 FIF_OTHER_BSS | 2954 FIF_BCN_PRBRESP_PROMISC; 2955 2956 wl->filter_flags = *fflags; 2957 2958 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 2959 b43_adjust_opmode(dev); 2960 spin_unlock_irqrestore(&wl->irq_lock, flags); 2961} 2962 2963static int b43_op_config_interface(struct ieee80211_hw *hw, 2964 struct ieee80211_vif *vif, 2965 struct ieee80211_if_conf *conf) 2966{ 2967 struct b43_wl *wl = hw_to_b43_wl(hw); 2968 struct b43_wldev *dev = wl->current_dev; 2969 unsigned long flags; 2970 2971 if (!dev) 2972 return -ENODEV; 2973 mutex_lock(&wl->mutex); 2974 spin_lock_irqsave(&wl->irq_lock, flags); 2975 B43_WARN_ON(wl->vif != vif); 2976 if (conf->bssid) 2977 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 2978 else 2979 memset(wl->bssid, 0, ETH_ALEN); 2980 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 2981 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) { 2982 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); 2983 b43_set_ssid(dev, conf->ssid, conf->ssid_len); 2984 if (conf->beacon) 2985 b43_update_templates(wl, conf->beacon); 2986 } 2987 b43_write_mac_bssid_templates(dev); 2988 } 2989 spin_unlock_irqrestore(&wl->irq_lock, flags); 2990 mutex_unlock(&wl->mutex); 2991 2992 return 0; 2993} 2994 2995/* Locking: wl->mutex */ 2996static void b43_wireless_core_stop(struct b43_wldev *dev) 2997{ 2998 struct b43_wl *wl = dev->wl; 2999 unsigned long flags; 3000 3001 if (b43_status(dev) < B43_STAT_STARTED) 3002 return; 3003 3004 /* Disable and sync interrupts. We must do this before than 3005 * setting the status to INITIALIZED, as the interrupt handler 3006 * won't care about IRQs then. */ 3007 spin_lock_irqsave(&wl->irq_lock, flags); 3008 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); 3009 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */ 3010 spin_unlock_irqrestore(&wl->irq_lock, flags); 3011 b43_synchronize_irq(dev); 3012 3013 b43_set_status(dev, B43_STAT_INITIALIZED); 3014 3015 mutex_unlock(&wl->mutex); 3016 /* Must unlock as it would otherwise deadlock. No races here. 3017 * Cancel the possibly running self-rearming periodic work. */ 3018 cancel_delayed_work_sync(&dev->periodic_work); 3019 mutex_lock(&wl->mutex); 3020 3021 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy. 3022 3023 b43_mac_suspend(dev); 3024 free_irq(dev->dev->irq, dev); 3025 b43dbg(wl, "Wireless interface stopped\n"); 3026} 3027 3028/* Locking: wl->mutex */ 3029static int b43_wireless_core_start(struct b43_wldev *dev) 3030{ 3031 int err; 3032 3033 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 3034 3035 drain_txstatus_queue(dev); 3036 err = request_irq(dev->dev->irq, b43_interrupt_handler, 3037 IRQF_SHARED, KBUILD_MODNAME, dev); 3038 if (err) { 3039 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); 3040 goto out; 3041 } 3042 3043 /* We are ready to run. */ 3044 b43_set_status(dev, B43_STAT_STARTED); 3045 3046 /* Start data flow (TX/RX). */ 3047 b43_mac_enable(dev); 3048 b43_interrupt_enable(dev, dev->irq_savedstate); 3049 ieee80211_start_queues(dev->wl->hw); 3050 3051 /* Start maintainance work */ 3052 b43_periodic_tasks_setup(dev); 3053 3054 b43dbg(dev->wl, "Wireless interface started\n"); 3055 out: 3056 return err; 3057} 3058 3059/* Get PHY and RADIO versioning numbers */ 3060static int b43_phy_versioning(struct b43_wldev *dev) 3061{ 3062 struct b43_phy *phy = &dev->phy; 3063 u32 tmp; 3064 u8 analog_type; 3065 u8 phy_type; 3066 u8 phy_rev; 3067 u16 radio_manuf; 3068 u16 radio_ver; 3069 u16 radio_rev; 3070 int unsupported = 0; 3071 3072 /* Get PHY versioning */ 3073 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 3074 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 3075 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 3076 phy_rev = (tmp & B43_PHYVER_VERSION); 3077 switch (phy_type) { 3078 case B43_PHYTYPE_A: 3079 if (phy_rev >= 4) 3080 unsupported = 1; 3081 break; 3082 case B43_PHYTYPE_B: 3083 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 3084 && phy_rev != 7) 3085 unsupported = 1; 3086 break; 3087 case B43_PHYTYPE_G: 3088 if (phy_rev > 9) 3089 unsupported = 1; 3090 break; 3091#ifdef CONFIG_B43_NPHY 3092 case B43_PHYTYPE_N: 3093 if (phy_rev > 1) 3094 unsupported = 1; 3095 break; 3096#endif 3097 default: 3098 unsupported = 1; 3099 }; 3100 if (unsupported) { 3101 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 3102 "(Analog %u, Type %u, Revision %u)\n", 3103 analog_type, phy_type, phy_rev); 3104 return -EOPNOTSUPP; 3105 } 3106 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", 3107 analog_type, phy_type, phy_rev); 3108 3109 /* Get RADIO versioning */ 3110 if (dev->dev->bus->chip_id == 0x4317) { 3111 if (dev->dev->bus->chip_rev == 0) 3112 tmp = 0x3205017F; 3113 else if (dev->dev->bus->chip_rev == 1) 3114 tmp = 0x4205017F; 3115 else 3116 tmp = 0x5205017F; 3117 } else { 3118 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3119 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH); 3120 tmp <<= 16; 3121 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 3122 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3123 } 3124 radio_manuf = (tmp & 0x00000FFF); 3125 radio_ver = (tmp & 0x0FFFF000) >> 12; 3126 radio_rev = (tmp & 0xF0000000) >> 28; 3127 if (radio_manuf != 0x17F /* Broadcom */) 3128 unsupported = 1; 3129 switch (phy_type) { 3130 case B43_PHYTYPE_A: 3131 if (radio_ver != 0x2060) 3132 unsupported = 1; 3133 if (radio_rev != 1) 3134 unsupported = 1; 3135 if (radio_manuf != 0x17F) 3136 unsupported = 1; 3137 break; 3138 case B43_PHYTYPE_B: 3139 if ((radio_ver & 0xFFF0) != 0x2050) 3140 unsupported = 1; 3141 break; 3142 case B43_PHYTYPE_G: 3143 if (radio_ver != 0x2050) 3144 unsupported = 1; 3145 break; 3146 case B43_PHYTYPE_N: 3147 if (radio_ver != 5) 3148 unsupported = 1; 3149 break; 3150 default: 3151 B43_WARN_ON(1); 3152 } 3153 if (unsupported) { 3154 b43err(dev->wl, "FOUND UNSUPPORTED RADIO " 3155 "(Manuf 0x%X, Version 0x%X, Revision %u)\n", 3156 radio_manuf, radio_ver, radio_rev); 3157 return -EOPNOTSUPP; 3158 } 3159 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", 3160 radio_manuf, radio_ver, radio_rev); 3161 3162 phy->radio_manuf = radio_manuf; 3163 phy->radio_ver = radio_ver; 3164 phy->radio_rev = radio_rev; 3165 3166 phy->analog = analog_type; 3167 phy->type = phy_type; 3168 phy->rev = phy_rev; 3169 3170 return 0; 3171} 3172 3173static void setup_struct_phy_for_init(struct b43_wldev *dev, 3174 struct b43_phy *phy) 3175{ 3176 struct b43_txpower_lo_control *lo; 3177 int i; 3178 3179 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); 3180 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); 3181 3182 phy->aci_enable = 0; 3183 phy->aci_wlan_automatic = 0; 3184 phy->aci_hw_rssi = 0; 3185 3186 phy->radio_off_context.valid = 0; 3187 3188 lo = phy->lo_control; 3189 if (lo) { 3190 memset(lo, 0, sizeof(*(phy->lo_control))); 3191 lo->rebuild = 1; 3192 lo->tx_bias = 0xFF; 3193 } 3194 phy->max_lb_gain = 0; 3195 phy->trsw_rx_gain = 0; 3196 phy->txpwr_offset = 0; 3197 3198 /* NRSSI */ 3199 phy->nrssislope = 0; 3200 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) 3201 phy->nrssi[i] = -1000; 3202 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) 3203 phy->nrssi_lt[i] = i; 3204 3205 phy->lofcal = 0xFFFF; 3206 phy->initval = 0xFFFF; 3207 3208 phy->interfmode = B43_INTERFMODE_NONE; 3209 phy->channel = 0xFF; 3210 3211 phy->hardware_power_control = !!modparam_hwpctl; 3212 3213 /* PHY TX errors counter. */ 3214 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3215 3216 /* OFDM-table address caching. */ 3217 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN; 3218} 3219 3220static void setup_struct_wldev_for_init(struct b43_wldev *dev) 3221{ 3222 dev->dfq_valid = 0; 3223 3224 /* Assume the radio is enabled. If it's not enabled, the state will 3225 * immediately get fixed on the first periodic work run. */ 3226 dev->radio_hw_enable = 1; 3227 3228 /* Stats */ 3229 memset(&dev->stats, 0, sizeof(dev->stats)); 3230 3231 setup_struct_phy_for_init(dev, &dev->phy); 3232 3233 /* IRQ related flags */ 3234 dev->irq_reason = 0; 3235 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 3236 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE; 3237 3238 dev->mac_suspended = 1; 3239 3240 /* Noise calculation context */ 3241 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 3242} 3243 3244static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 3245{ 3246 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 3247 u32 hf; 3248 3249 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 3250 return; 3251 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 3252 return; 3253 3254 hf = b43_hf_read(dev); 3255 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 3256 hf |= B43_HF_BTCOEXALT; 3257 else 3258 hf |= B43_HF_BTCOEX; 3259 b43_hf_write(dev, hf); 3260 //TODO 3261} 3262 3263static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 3264{ //TODO 3265} 3266 3267static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 3268{ 3269#ifdef CONFIG_SSB_DRIVER_PCICORE 3270 struct ssb_bus *bus = dev->dev->bus; 3271 u32 tmp; 3272 3273 if (bus->pcicore.dev && 3274 bus->pcicore.dev->id.coreid == SSB_DEV_PCI && 3275 bus->pcicore.dev->id.revision <= 5) { 3276 /* IMCFGLO timeouts workaround. */ 3277 tmp = ssb_read32(dev->dev, SSB_IMCFGLO); 3278 tmp &= ~SSB_IMCFGLO_REQTO; 3279 tmp &= ~SSB_IMCFGLO_SERTO; 3280 switch (bus->bustype) { 3281 case SSB_BUSTYPE_PCI: 3282 case SSB_BUSTYPE_PCMCIA: 3283 tmp |= 0x32; 3284 break; 3285 case SSB_BUSTYPE_SSB: 3286 tmp |= 0x53; 3287 break; 3288 } 3289 ssb_write32(dev->dev, SSB_IMCFGLO, tmp); 3290 } 3291#endif /* CONFIG_SSB_DRIVER_PCICORE */ 3292} 3293 3294/* Write the short and long frame retry limit values. */ 3295static void b43_set_retry_limits(struct b43_wldev *dev, 3296 unsigned int short_retry, 3297 unsigned int long_retry) 3298{ 3299 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3300 * the chip-internal counter. */ 3301 short_retry = min(short_retry, (unsigned int)0xF); 3302 long_retry = min(long_retry, (unsigned int)0xF); 3303 3304 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3305 short_retry); 3306 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3307 long_retry); 3308} 3309 3310/* Shutdown a wireless core */ 3311/* Locking: wl->mutex */ 3312static void b43_wireless_core_exit(struct b43_wldev *dev) 3313{ 3314 struct b43_phy *phy = &dev->phy; 3315 3316 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED); 3317 if (b43_status(dev) != B43_STAT_INITIALIZED) 3318 return; 3319 b43_set_status(dev, B43_STAT_UNINIT); 3320 3321 b43_leds_exit(dev); 3322 b43_rng_exit(dev->wl); 3323 b43_dma_free(dev); 3324 b43_chip_exit(dev); 3325 b43_radio_turn_off(dev, 1); 3326 b43_switch_analog(dev, 0); 3327 if (phy->dyn_tssi_tbl) 3328 kfree(phy->tssi2dbm); 3329 kfree(phy->lo_control); 3330 phy->lo_control = NULL; 3331 if (dev->wl->current_beacon) { 3332 dev_kfree_skb_any(dev->wl->current_beacon); 3333 dev->wl->current_beacon = NULL; 3334 } 3335 3336 ssb_device_disable(dev->dev, 0); 3337 ssb_bus_may_powerdown(dev->dev->bus); 3338} 3339 3340/* Initialize a wireless core */ 3341static int b43_wireless_core_init(struct b43_wldev *dev) 3342{ 3343 struct b43_wl *wl = dev->wl; 3344 struct ssb_bus *bus = dev->dev->bus; 3345 struct ssb_sprom *sprom = &bus->sprom; 3346 struct b43_phy *phy = &dev->phy; 3347 int err; 3348 u32 hf, tmp; 3349 3350 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3351 3352 err = ssb_bus_powerup(bus, 0); 3353 if (err) 3354 goto out; 3355 if (!ssb_device_is_enabled(dev->dev)) { 3356 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 3357 b43_wireless_core_reset(dev, tmp); 3358 } 3359 3360 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) { 3361 phy->lo_control = 3362 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL); 3363 if (!phy->lo_control) { 3364 err = -ENOMEM; 3365 goto err_busdown; 3366 } 3367 } 3368 setup_struct_wldev_for_init(dev); 3369 3370 err = b43_phy_init_tssi2dbm_table(dev); 3371 if (err) 3372 goto err_kfree_lo_control; 3373 3374 /* Enable IRQ routing to this device. */ 3375 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 3376 3377 b43_imcfglo_timeouts_workaround(dev); 3378 b43_bluetooth_coext_disable(dev); 3379 b43_phy_early_init(dev); 3380 err = b43_chip_init(dev); 3381 if (err) 3382 goto err_kfree_tssitbl; 3383 b43_shm_write16(dev, B43_SHM_SHARED, 3384 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 3385 hf = b43_hf_read(dev); 3386 if (phy->type == B43_PHYTYPE_G) { 3387 hf |= B43_HF_SYMW; 3388 if (phy->rev == 1) 3389 hf |= B43_HF_GDCW; 3390 if (sprom->boardflags_lo & B43_BFL_PACTRL) 3391 hf |= B43_HF_OFDMPABOOST; 3392 } else if (phy->type == B43_PHYTYPE_B) { 3393 hf |= B43_HF_SYMW; 3394 if (phy->rev >= 2 && phy->radio_ver == 0x2050) 3395 hf &= ~B43_HF_GDCW; 3396 } 3397 b43_hf_write(dev, hf); 3398 3399 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 3400 B43_DEFAULT_LONG_RETRY_LIMIT); 3401 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 3402 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 3403 3404 /* Disable sending probe responses from firmware. 3405 * Setting the MaxTime to one usec will always trigger 3406 * a timeout, so we never send any probe resp. 3407 * A timeout of zero is infinite. */ 3408 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 3409 3410 b43_rate_memory_init(dev); 3411 3412 /* Minimum Contention Window */ 3413 if (phy->type == B43_PHYTYPE_B) { 3414 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 3415 } else { 3416 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 3417 } 3418 /* Maximum Contention Window */ 3419 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 3420 3421 err = b43_dma_init(dev); 3422 if (err) 3423 goto err_chip_exit; 3424 b43_qos_init(dev); 3425 3426//FIXME 3427#if 1 3428 b43_write16(dev, 0x0612, 0x0050); 3429 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050); 3430 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4); 3431#endif 3432 3433 b43_bluetooth_coext_enable(dev); 3434 3435 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */ 3436 memset(wl->bssid, 0, ETH_ALEN); 3437 memset(wl->mac_addr, 0, ETH_ALEN); 3438 b43_upload_card_macaddress(dev); 3439 b43_security_init(dev); 3440 b43_rng_init(wl); 3441 3442 b43_set_status(dev, B43_STAT_INITIALIZED); 3443 3444 b43_leds_init(dev); 3445out: 3446 return err; 3447 3448 err_chip_exit: 3449 b43_chip_exit(dev); 3450 err_kfree_tssitbl: 3451 if (phy->dyn_tssi_tbl) 3452 kfree(phy->tssi2dbm); 3453 err_kfree_lo_control: 3454 kfree(phy->lo_control); 3455 phy->lo_control = NULL; 3456 err_busdown: 3457 ssb_bus_may_powerdown(bus); 3458 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 3459 return err; 3460} 3461 3462static int b43_op_add_interface(struct ieee80211_hw *hw, 3463 struct ieee80211_if_init_conf *conf) 3464{ 3465 struct b43_wl *wl = hw_to_b43_wl(hw); 3466 struct b43_wldev *dev; 3467 unsigned long flags; 3468 int err = -EOPNOTSUPP; 3469 3470 /* TODO: allow WDS/AP devices to coexist */ 3471 3472 if (conf->type != IEEE80211_IF_TYPE_AP && 3473 conf->type != IEEE80211_IF_TYPE_STA && 3474 conf->type != IEEE80211_IF_TYPE_WDS && 3475 conf->type != IEEE80211_IF_TYPE_IBSS) 3476 return -EOPNOTSUPP; 3477 3478 mutex_lock(&wl->mutex); 3479 if (wl->operating) 3480 goto out_mutex_unlock; 3481 3482 b43dbg(wl, "Adding Interface type %d\n", conf->type); 3483 3484 dev = wl->current_dev; 3485 wl->operating = 1; 3486 wl->vif = conf->vif; 3487 wl->if_type = conf->type; 3488 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN); 3489 3490 spin_lock_irqsave(&wl->irq_lock, flags); 3491 b43_adjust_opmode(dev); 3492 b43_upload_card_macaddress(dev); 3493 spin_unlock_irqrestore(&wl->irq_lock, flags); 3494 3495 err = 0; 3496 out_mutex_unlock: 3497 mutex_unlock(&wl->mutex); 3498 3499 return err; 3500} 3501 3502static void b43_op_remove_interface(struct ieee80211_hw *hw, 3503 struct ieee80211_if_init_conf *conf) 3504{ 3505 struct b43_wl *wl = hw_to_b43_wl(hw); 3506 struct b43_wldev *dev = wl->current_dev; 3507 unsigned long flags; 3508 3509 b43dbg(wl, "Removing Interface type %d\n", conf->type); 3510 3511 mutex_lock(&wl->mutex); 3512 3513 B43_WARN_ON(!wl->operating); 3514 B43_WARN_ON(wl->vif != conf->vif); 3515 wl->vif = NULL; 3516 3517 wl->operating = 0; 3518 3519 spin_lock_irqsave(&wl->irq_lock, flags); 3520 b43_adjust_opmode(dev); 3521 memset(wl->mac_addr, 0, ETH_ALEN); 3522 b43_upload_card_macaddress(dev); 3523 spin_unlock_irqrestore(&wl->irq_lock, flags); 3524 3525 mutex_unlock(&wl->mutex); 3526} 3527 3528static int b43_op_start(struct ieee80211_hw *hw) 3529{ 3530 struct b43_wl *wl = hw_to_b43_wl(hw); 3531 struct b43_wldev *dev = wl->current_dev; 3532 int did_init = 0; 3533 int err = 0; 3534 3535 /* First register RFkill. 3536 * LEDs that are registered later depend on it. */ 3537 b43_rfkill_init(dev); 3538 3539 mutex_lock(&wl->mutex); 3540 3541 if (b43_status(dev) < B43_STAT_INITIALIZED) { 3542 err = b43_wireless_core_init(dev); 3543 if (err) 3544 goto out_mutex_unlock; 3545 did_init = 1; 3546 } 3547 3548 if (b43_status(dev) < B43_STAT_STARTED) { 3549 err = b43_wireless_core_start(dev); 3550 if (err) { 3551 if (did_init) 3552 b43_wireless_core_exit(dev); 3553 goto out_mutex_unlock; 3554 } 3555 } 3556 3557 out_mutex_unlock: 3558 mutex_unlock(&wl->mutex); 3559 3560 return err; 3561} 3562 3563static void b43_op_stop(struct ieee80211_hw *hw) 3564{ 3565 struct b43_wl *wl = hw_to_b43_wl(hw); 3566 struct b43_wldev *dev = wl->current_dev; 3567 3568 b43_rfkill_exit(dev); 3569 3570 mutex_lock(&wl->mutex); 3571 if (b43_status(dev) >= B43_STAT_STARTED) 3572 b43_wireless_core_stop(dev); 3573 b43_wireless_core_exit(dev); 3574 mutex_unlock(&wl->mutex); 3575} 3576 3577static int b43_op_set_retry_limit(struct ieee80211_hw *hw, 3578 u32 short_retry_limit, u32 long_retry_limit) 3579{ 3580 struct b43_wl *wl = hw_to_b43_wl(hw); 3581 struct b43_wldev *dev; 3582 int err = 0; 3583 3584 mutex_lock(&wl->mutex); 3585 dev = wl->current_dev; 3586 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) { 3587 err = -ENODEV; 3588 goto out_unlock; 3589 } 3590 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit); 3591out_unlock: 3592 mutex_unlock(&wl->mutex); 3593 3594 return err; 3595} 3596 3597static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set) 3598{ 3599 struct b43_wl *wl = hw_to_b43_wl(hw); 3600 struct sk_buff *beacon; 3601 3602 /* We could modify the existing beacon and set the aid bit in 3603 * the TIM field, but that would probably require resizing and 3604 * moving of data within the beacon template. 3605 * Simply request a new beacon and let mac80211 do the hard work. */ 3606 beacon = ieee80211_beacon_get(hw, wl->vif, NULL); 3607 if (unlikely(!beacon)) 3608 return -ENOMEM; 3609 b43_update_templates(wl, beacon); 3610 3611 return 0; 3612} 3613 3614static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw, 3615 struct sk_buff *beacon, 3616 struct ieee80211_tx_control *ctl) 3617{ 3618 struct b43_wl *wl = hw_to_b43_wl(hw); 3619 3620 b43_update_templates(wl, beacon); 3621 3622 return 0; 3623} 3624 3625static const struct ieee80211_ops b43_hw_ops = { 3626 .tx = b43_op_tx, 3627 .conf_tx = b43_op_conf_tx, 3628 .add_interface = b43_op_add_interface, 3629 .remove_interface = b43_op_remove_interface, 3630 .config = b43_op_config, 3631 .config_interface = b43_op_config_interface, 3632 .configure_filter = b43_op_configure_filter, 3633 .set_key = b43_op_set_key, 3634 .get_stats = b43_op_get_stats, 3635 .get_tx_stats = b43_op_get_tx_stats, 3636 .start = b43_op_start, 3637 .stop = b43_op_stop, 3638 .set_retry_limit = b43_op_set_retry_limit, 3639 .set_tim = b43_op_beacon_set_tim, 3640 .beacon_update = b43_op_ibss_beacon_update, 3641}; 3642 3643/* Hard-reset the chip. Do not call this directly. 3644 * Use b43_controller_restart() 3645 */ 3646static void b43_chip_reset(struct work_struct *work) 3647{ 3648 struct b43_wldev *dev = 3649 container_of(work, struct b43_wldev, restart_work); 3650 struct b43_wl *wl = dev->wl; 3651 int err = 0; 3652 int prev_status; 3653 3654 mutex_lock(&wl->mutex); 3655 3656 prev_status = b43_status(dev); 3657 /* Bring the device down... */ 3658 if (prev_status >= B43_STAT_STARTED) 3659 b43_wireless_core_stop(dev); 3660 if (prev_status >= B43_STAT_INITIALIZED) 3661 b43_wireless_core_exit(dev); 3662 3663 /* ...and up again. */ 3664 if (prev_status >= B43_STAT_INITIALIZED) { 3665 err = b43_wireless_core_init(dev); 3666 if (err) 3667 goto out; 3668 } 3669 if (prev_status >= B43_STAT_STARTED) { 3670 err = b43_wireless_core_start(dev); 3671 if (err) { 3672 b43_wireless_core_exit(dev); 3673 goto out; 3674 } 3675 } 3676 out: 3677 mutex_unlock(&wl->mutex); 3678 if (err) 3679 b43err(wl, "Controller restart FAILED\n"); 3680 else 3681 b43info(wl, "Controller restarted\n"); 3682} 3683 3684static int b43_setup_modes(struct b43_wldev *dev, 3685 bool have_2ghz_phy, bool have_5ghz_phy) 3686{ 3687 struct ieee80211_hw *hw = dev->wl->hw; 3688 struct ieee80211_hw_mode *mode; 3689 struct b43_phy *phy = &dev->phy; 3690 int err; 3691 3692 /* XXX: This function will go away soon, when mac80211 3693 * band stuff is rewritten. So this is just a hack. 3694 * For now we always claim GPHY mode, as there is no 3695 * support for NPHY and APHY in the device, yet. 3696 * This assumption is OK, as any B, N or A PHY will already 3697 * have died a horrible sanity check death earlier. */ 3698 3699 mode = &phy->hwmodes[0]; 3700 mode->mode = MODE_IEEE80211G; 3701 mode->num_channels = b43_2ghz_chantable_size; 3702 mode->channels = b43_2ghz_chantable; 3703 mode->num_rates = b43_g_ratetable_size; 3704 mode->rates = b43_g_ratetable; 3705 err = ieee80211_register_hwmode(hw, mode); 3706 if (err) 3707 return err; 3708 phy->possible_phymodes |= B43_PHYMODE_G; 3709 3710 return 0; 3711} 3712 3713static void b43_wireless_core_detach(struct b43_wldev *dev) 3714{ 3715 /* We release firmware that late to not be required to re-request 3716 * is all the time when we reinit the core. */ 3717 b43_release_firmware(dev); 3718} 3719 3720static int b43_wireless_core_attach(struct b43_wldev *dev) 3721{ 3722 struct b43_wl *wl = dev->wl; 3723 struct ssb_bus *bus = dev->dev->bus; 3724 struct pci_dev *pdev = bus->host_pci; 3725 int err; 3726 bool have_2ghz_phy = 0, have_5ghz_phy = 0; 3727 u32 tmp; 3728 3729 /* Do NOT do any device initialization here. 3730 * Do it in wireless_core_init() instead. 3731 * This function is for gathering basic information about the HW, only. 3732 * Also some structs may be set up here. But most likely you want to have 3733 * that in core_init(), too. 3734 */ 3735 3736 err = ssb_bus_powerup(bus, 0); 3737 if (err) { 3738 b43err(wl, "Bus powerup failed\n"); 3739 goto out; 3740 } 3741 /* Get the PHY type. */ 3742 if (dev->dev->id.revision >= 5) { 3743 u32 tmshigh; 3744 3745 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 3746 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY); 3747 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY); 3748 } else 3749 B43_WARN_ON(1); 3750 3751 dev->phy.gmode = have_2ghz_phy; 3752 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3753 b43_wireless_core_reset(dev, tmp); 3754 3755 err = b43_phy_versioning(dev); 3756 if (err) 3757 goto err_powerdown; 3758 /* Check if this device supports multiband. */ 3759 if (!pdev || 3760 (pdev->device != 0x4312 && 3761 pdev->device != 0x4319 && pdev->device != 0x4324)) { 3762 /* No multiband support. */ 3763 have_2ghz_phy = 0; 3764 have_5ghz_phy = 0; 3765 switch (dev->phy.type) { 3766 case B43_PHYTYPE_A: 3767 have_5ghz_phy = 1; 3768 break; 3769 case B43_PHYTYPE_G: 3770 case B43_PHYTYPE_N: 3771 have_2ghz_phy = 1; 3772 break; 3773 default: 3774 B43_WARN_ON(1); 3775 } 3776 } 3777 if (dev->phy.type == B43_PHYTYPE_A) { 3778 /* FIXME */ 3779 b43err(wl, "IEEE 802.11a devices are unsupported\n"); 3780 err = -EOPNOTSUPP; 3781 goto err_powerdown; 3782 } 3783 dev->phy.gmode = have_2ghz_phy; 3784 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 3785 b43_wireless_core_reset(dev, tmp); 3786 3787 err = b43_validate_chipaccess(dev); 3788 if (err) 3789 goto err_powerdown; 3790 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy); 3791 if (err) 3792 goto err_powerdown; 3793 3794 /* Now set some default "current_dev" */ 3795 if (!wl->current_dev) 3796 wl->current_dev = dev; 3797 INIT_WORK(&dev->restart_work, b43_chip_reset); 3798 3799 b43_radio_turn_off(dev, 1); 3800 b43_switch_analog(dev, 0); 3801 ssb_device_disable(dev->dev, 0); 3802 ssb_bus_may_powerdown(bus); 3803 3804out: 3805 return err; 3806 3807err_powerdown: 3808 ssb_bus_may_powerdown(bus); 3809 return err; 3810} 3811 3812static void b43_one_core_detach(struct ssb_device *dev) 3813{ 3814 struct b43_wldev *wldev; 3815 struct b43_wl *wl; 3816 3817 wldev = ssb_get_drvdata(dev); 3818 wl = wldev->wl; 3819 cancel_work_sync(&wldev->restart_work); 3820 b43_debugfs_remove_device(wldev); 3821 b43_wireless_core_detach(wldev); 3822 list_del(&wldev->list); 3823 wl->nr_devs--; 3824 ssb_set_drvdata(dev, NULL); 3825 kfree(wldev); 3826} 3827 3828static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 3829{ 3830 struct b43_wldev *wldev; 3831 struct pci_dev *pdev; 3832 int err = -ENOMEM; 3833 3834 if (!list_empty(&wl->devlist)) { 3835 /* We are not the first core on this chip. */ 3836 pdev = dev->bus->host_pci; 3837 /* Only special chips support more than one wireless 3838 * core, although some of the other chips have more than 3839 * one wireless core as well. Check for this and 3840 * bail out early. 3841 */ 3842 if (!pdev || 3843 ((pdev->device != 0x4321) && 3844 (pdev->device != 0x4313) && (pdev->device != 0x431A))) { 3845 b43dbg(wl, "Ignoring unconnected 802.11 core\n"); 3846 return -ENODEV; 3847 } 3848 } 3849 3850 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); 3851 if (!wldev) 3852 goto out; 3853 3854 wldev->dev = dev; 3855 wldev->wl = wl; 3856 b43_set_status(wldev, B43_STAT_UNINIT); 3857 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 3858 tasklet_init(&wldev->isr_tasklet, 3859 (void (*)(unsigned long))b43_interrupt_tasklet, 3860 (unsigned long)wldev); 3861 INIT_LIST_HEAD(&wldev->list); 3862 3863 err = b43_wireless_core_attach(wldev); 3864 if (err) 3865 goto err_kfree_wldev; 3866 3867 list_add(&wldev->list, &wl->devlist); 3868 wl->nr_devs++; 3869 ssb_set_drvdata(dev, wldev); 3870 b43_debugfs_add_device(wldev); 3871 3872 out: 3873 return err; 3874 3875 err_kfree_wldev: 3876 kfree(wldev); 3877 return err; 3878} 3879 3880static void b43_sprom_fixup(struct ssb_bus *bus) 3881{ 3882 /* boardflags workarounds */ 3883 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 3884 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) 3885 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 3886 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3887 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) 3888 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 3889} 3890 3891static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 3892{ 3893 struct ieee80211_hw *hw = wl->hw; 3894 3895 ssb_set_devtypedata(dev, NULL); 3896 ieee80211_free_hw(hw); 3897} 3898 3899static int b43_wireless_init(struct ssb_device *dev) 3900{ 3901 struct ssb_sprom *sprom = &dev->bus->sprom; 3902 struct ieee80211_hw *hw; 3903 struct b43_wl *wl; 3904 int err = -ENOMEM; 3905 3906 b43_sprom_fixup(dev->bus); 3907 3908 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 3909 if (!hw) { 3910 b43err(NULL, "Could not allocate ieee80211 device\n"); 3911 goto out; 3912 } 3913 3914 /* fill hw info */ 3915 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | 3916 IEEE80211_HW_RX_INCLUDES_FCS; 3917 hw->max_signal = 100; 3918 hw->max_rssi = -110; 3919 hw->max_noise = -110; 3920 hw->queues = 1; /* FIXME: hardware has more queues */ 3921 SET_IEEE80211_DEV(hw, dev->dev); 3922 if (is_valid_ether_addr(sprom->et1mac)) 3923 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 3924 else 3925 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 3926 3927 /* Get and initialize struct b43_wl */ 3928 wl = hw_to_b43_wl(hw); 3929 memset(wl, 0, sizeof(*wl)); 3930 wl->hw = hw; 3931 spin_lock_init(&wl->irq_lock); 3932 spin_lock_init(&wl->leds_lock); 3933 mutex_init(&wl->mutex); 3934 INIT_LIST_HEAD(&wl->devlist); 3935 3936 ssb_set_devtypedata(dev, wl); 3937 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id); 3938 err = 0; 3939 out: 3940 return err; 3941} 3942 3943static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id) 3944{ 3945 struct b43_wl *wl; 3946 int err; 3947 int first = 0; 3948 3949 wl = ssb_get_devtypedata(dev); 3950 if (!wl) { 3951 /* Probing the first core. Must setup common struct b43_wl */ 3952 first = 1; 3953 err = b43_wireless_init(dev); 3954 if (err) 3955 goto out; 3956 wl = ssb_get_devtypedata(dev); 3957 B43_WARN_ON(!wl); 3958 } 3959 err = b43_one_core_attach(dev, wl); 3960 if (err) 3961 goto err_wireless_exit; 3962 3963 if (first) { 3964 err = ieee80211_register_hw(wl->hw); 3965 if (err) 3966 goto err_one_core_detach; 3967 } 3968 3969 out: 3970 return err; 3971 3972 err_one_core_detach: 3973 b43_one_core_detach(dev); 3974 err_wireless_exit: 3975 if (first) 3976 b43_wireless_exit(dev, wl); 3977 return err; 3978} 3979 3980static void b43_remove(struct ssb_device *dev) 3981{ 3982 struct b43_wl *wl = ssb_get_devtypedata(dev); 3983 struct b43_wldev *wldev = ssb_get_drvdata(dev); 3984 3985 B43_WARN_ON(!wl); 3986 if (wl->current_dev == wldev) 3987 ieee80211_unregister_hw(wl->hw); 3988 3989 b43_one_core_detach(dev); 3990 3991 if (list_empty(&wl->devlist)) { 3992 /* Last core on the chip unregistered. 3993 * We can destroy common struct b43_wl. 3994 */ 3995 b43_wireless_exit(dev, wl); 3996 } 3997} 3998 3999/* Perform a hardware reset. This can be called from any context. */ 4000void b43_controller_restart(struct b43_wldev *dev, const char *reason) 4001{ 4002 /* Must avoid requeueing, if we are in shutdown. */ 4003 if (b43_status(dev) < B43_STAT_INITIALIZED) 4004 return; 4005 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 4006 queue_work(dev->wl->hw->workqueue, &dev->restart_work); 4007} 4008 4009#ifdef CONFIG_PM 4010 4011static int b43_suspend(struct ssb_device *dev, pm_message_t state) 4012{ 4013 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4014 struct b43_wl *wl = wldev->wl; 4015 4016 b43dbg(wl, "Suspending...\n"); 4017 4018 mutex_lock(&wl->mutex); 4019 wldev->suspend_init_status = b43_status(wldev); 4020 if (wldev->suspend_init_status >= B43_STAT_STARTED) 4021 b43_wireless_core_stop(wldev); 4022 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) 4023 b43_wireless_core_exit(wldev); 4024 mutex_unlock(&wl->mutex); 4025 4026 b43dbg(wl, "Device suspended.\n"); 4027 4028 return 0; 4029} 4030 4031static int b43_resume(struct ssb_device *dev) 4032{ 4033 struct b43_wldev *wldev = ssb_get_drvdata(dev); 4034 struct b43_wl *wl = wldev->wl; 4035 int err = 0; 4036 4037 b43dbg(wl, "Resuming...\n"); 4038 4039 mutex_lock(&wl->mutex); 4040 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) { 4041 err = b43_wireless_core_init(wldev); 4042 if (err) { 4043 b43err(wl, "Resume failed at core init\n"); 4044 goto out; 4045 } 4046 } 4047 if (wldev->suspend_init_status >= B43_STAT_STARTED) { 4048 err = b43_wireless_core_start(wldev); 4049 if (err) { 4050 b43_wireless_core_exit(wldev); 4051 b43err(wl, "Resume failed at core start\n"); 4052 goto out; 4053 } 4054 } 4055 mutex_unlock(&wl->mutex); 4056 4057 b43dbg(wl, "Device resumed.\n"); 4058 out: 4059 return err; 4060} 4061 4062#else /* CONFIG_PM */ 4063# define b43_suspend NULL 4064# define b43_resume NULL 4065#endif /* CONFIG_PM */ 4066 4067static struct ssb_driver b43_ssb_driver = { 4068 .name = KBUILD_MODNAME, 4069 .id_table = b43_ssb_tbl, 4070 .probe = b43_probe, 4071 .remove = b43_remove, 4072 .suspend = b43_suspend, 4073 .resume = b43_resume, 4074}; 4075 4076static int __init b43_init(void) 4077{ 4078 int err; 4079 4080 b43_debugfs_init(); 4081 err = b43_pcmcia_init(); 4082 if (err) 4083 goto err_dfs_exit; 4084 err = ssb_driver_register(&b43_ssb_driver); 4085 if (err) 4086 goto err_pcmcia_exit; 4087 4088 return err; 4089 4090err_pcmcia_exit: 4091 b43_pcmcia_exit(); 4092err_dfs_exit: 4093 b43_debugfs_exit(); 4094 return err; 4095} 4096 4097static void __exit b43_exit(void) 4098{ 4099 ssb_driver_unregister(&b43_ssb_driver); 4100 b43_pcmcia_exit(); 4101 b43_debugfs_exit(); 4102} 4103 4104module_init(b43_init) 4105module_exit(b43_exit) 4106