phy_n.c revision 087de74ae512fe31894c1556d5f8d5a126322de7
1/* 2 3 Broadcom B43 wireless driver 4 IEEE 802.11n PHY support 5 6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING. If not, write to 20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 21 Boston, MA 02110-1301, USA. 22 23*/ 24 25#include <linux/delay.h> 26#include <linux/slab.h> 27#include <linux/types.h> 28 29#include "b43.h" 30#include "phy_n.h" 31#include "tables_nphy.h" 32#include "main.h" 33 34struct nphy_txgains { 35 u16 txgm[2]; 36 u16 pga[2]; 37 u16 pad[2]; 38 u16 ipa[2]; 39}; 40 41struct nphy_iqcal_params { 42 u16 txgm; 43 u16 pga; 44 u16 pad; 45 u16 ipa; 46 u16 cal_gain; 47 u16 ncorr[5]; 48}; 49 50struct nphy_iq_est { 51 s32 iq0_prod; 52 u32 i0_pwr; 53 u32 q0_pwr; 54 s32 iq1_prod; 55 u32 i1_pwr; 56 u32 q1_pwr; 57}; 58 59enum b43_nphy_rf_sequence { 60 B43_RFSEQ_RX2TX, 61 B43_RFSEQ_TX2RX, 62 B43_RFSEQ_RESET2RX, 63 B43_RFSEQ_UPDATE_GAINH, 64 B43_RFSEQ_UPDATE_GAINL, 65 B43_RFSEQ_UPDATE_GAINU, 66}; 67 68static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, 69 u8 *events, u8 *delays, u8 length); 70static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 71 enum b43_nphy_rf_sequence seq); 72static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 73 u16 value, u8 core, bool off); 74static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, 75 u16 value, u8 core); 76 77static inline bool b43_channel_type_is_40mhz( 78 enum nl80211_channel_type channel_type) 79{ 80 return (channel_type == NL80211_CHAN_HT40MINUS || 81 channel_type == NL80211_CHAN_HT40PLUS); 82} 83 84static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec) 85{ 86 return !chanspec->channel && !chanspec->sideband && 87 !chanspec->b_width && !chanspec->b_freq; 88} 89 90static inline bool b43_eq_chanspecs(struct b43_chanspec *chanspec1, 91 struct b43_chanspec *chanspec2) 92{ 93 return (chanspec1->channel == chanspec2->channel && 94 chanspec1->sideband == chanspec2->sideband && 95 chanspec1->b_width == chanspec2->b_width && 96 chanspec1->b_freq == chanspec2->b_freq); 97} 98 99void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) 100{//TODO 101} 102 103static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev) 104{//TODO 105} 106 107static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, 108 bool ignore_tssi) 109{//TODO 110 return B43_TXPWR_RES_DONE; 111} 112 113static void b43_chantab_radio_upload(struct b43_wldev *dev, 114 const struct b43_nphy_channeltab_entry_rev2 *e) 115{ 116 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); 117 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); 118 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); 119 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); 120 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 121 122 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); 123 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); 124 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); 125 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); 126 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 127 128 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); 129 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); 130 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); 131 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); 132 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 133 134 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); 135 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); 136 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); 137 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); 138 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 139 140 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); 141 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); 142 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); 143 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); 144 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 145 146 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); 147 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); 148} 149 150static void b43_chantab_phy_upload(struct b43_wldev *dev, 151 const struct b43_phy_n_sfo_cfg *e) 152{ 153 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); 154 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); 155 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); 156 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); 157 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); 158 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); 159} 160 161static void b43_nphy_tx_power_fix(struct b43_wldev *dev) 162{ 163 //TODO 164} 165 166 167/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ 168static void b43_radio_2055_setup(struct b43_wldev *dev, 169 const struct b43_nphy_channeltab_entry_rev2 *e) 170{ 171 B43_WARN_ON(dev->phy.rev >= 3); 172 173 b43_chantab_radio_upload(dev, e); 174 udelay(50); 175 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); 176 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); 177 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 178 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); 179 udelay(300); 180} 181 182static void b43_radio_init2055_pre(struct b43_wldev *dev) 183{ 184 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 185 ~B43_NPHY_RFCTL_CMD_PORFORCE); 186 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 187 B43_NPHY_RFCTL_CMD_CHIP0PU | 188 B43_NPHY_RFCTL_CMD_OEPORFORCE); 189 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 190 B43_NPHY_RFCTL_CMD_PORFORCE); 191} 192 193static void b43_radio_init2055_post(struct b43_wldev *dev) 194{ 195 struct b43_phy_n *nphy = dev->phy.n; 196 struct ssb_sprom *sprom = &(dev->dev->bus->sprom); 197 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo); 198 int i; 199 u16 val; 200 bool workaround = false; 201 202 if (sprom->revision < 4) 203 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM || 204 binfo->type != 0x46D || 205 binfo->rev < 0x41); 206 else 207 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0); 208 209 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); 210 if (workaround) { 211 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); 212 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); 213 } 214 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); 215 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); 216 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); 217 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); 218 b43_radio_set(dev, B2055_CAL_MISC, 0x1); 219 msleep(1); 220 b43_radio_set(dev, B2055_CAL_MISC, 0x40); 221 for (i = 0; i < 200; i++) { 222 val = b43_radio_read(dev, B2055_CAL_COUT2); 223 if (val & 0x80) { 224 i = 0; 225 break; 226 } 227 udelay(10); 228 } 229 if (i) 230 b43err(dev->wl, "radio post init timeout\n"); 231 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); 232 b43_switch_channel(dev, dev->phy.channel); 233 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); 234 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); 235 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); 236 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); 237 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); 238 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); 239 if (!nphy->gain_boost) { 240 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); 241 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); 242 } else { 243 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); 244 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); 245 } 246 udelay(2); 247} 248 249/* 250 * Initialize a Broadcom 2055 N-radio 251 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init 252 */ 253static void b43_radio_init2055(struct b43_wldev *dev) 254{ 255 b43_radio_init2055_pre(dev); 256 if (b43_status(dev) < B43_STAT_INITIALIZED) 257 b2055_upload_inittab(dev, 0, 1); 258 else 259 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0); 260 b43_radio_init2055_post(dev); 261} 262 263/* 264 * Initialize a Broadcom 2056 N-radio 265 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init 266 */ 267static void b43_radio_init2056(struct b43_wldev *dev) 268{ 269 /* TODO */ 270} 271 272 273/* 274 * Upload the N-PHY tables. 275 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables 276 */ 277static void b43_nphy_tables_init(struct b43_wldev *dev) 278{ 279 if (dev->phy.rev < 3) 280 b43_nphy_rev0_1_2_tables_init(dev); 281 else 282 b43_nphy_rev3plus_tables_init(dev); 283} 284 285/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ 286static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) 287{ 288 struct b43_phy_n *nphy = dev->phy.n; 289 enum ieee80211_band band; 290 u16 tmp; 291 292 if (!enable) { 293 nphy->rfctrl_intc1_save = b43_phy_read(dev, 294 B43_NPHY_RFCTL_INTC1); 295 nphy->rfctrl_intc2_save = b43_phy_read(dev, 296 B43_NPHY_RFCTL_INTC2); 297 band = b43_current_band(dev->wl); 298 if (dev->phy.rev >= 3) { 299 if (band == IEEE80211_BAND_5GHZ) 300 tmp = 0x600; 301 else 302 tmp = 0x480; 303 } else { 304 if (band == IEEE80211_BAND_5GHZ) 305 tmp = 0x180; 306 else 307 tmp = 0x120; 308 } 309 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 310 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 311 } else { 312 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 313 nphy->rfctrl_intc1_save); 314 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 315 nphy->rfctrl_intc2_save); 316 } 317} 318 319/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ 320static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) 321{ 322 struct b43_phy_n *nphy = dev->phy.n; 323 u16 tmp; 324 enum ieee80211_band band = b43_current_band(dev->wl); 325 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) || 326 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ); 327 328 if (dev->phy.rev >= 3) { 329 if (ipa) { 330 tmp = 4; 331 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, 332 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); 333 } 334 335 tmp = 1; 336 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, 337 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); 338 } 339} 340 341/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ 342static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force) 343{ 344 u32 tmslow; 345 346 if (dev->phy.type != B43_PHYTYPE_N) 347 return; 348 349 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 350 if (force) 351 tmslow |= SSB_TMSLOW_FGC; 352 else 353 tmslow &= ~SSB_TMSLOW_FGC; 354 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 355} 356 357/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ 358static void b43_nphy_reset_cca(struct b43_wldev *dev) 359{ 360 u16 bbcfg; 361 362 b43_nphy_bmac_clock_fgc(dev, 1); 363 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); 364 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); 365 udelay(1); 366 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); 367 b43_nphy_bmac_clock_fgc(dev, 0); 368 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 369} 370 371/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ 372static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) 373{ 374 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); 375 376 mimocfg |= B43_NPHY_MIMOCFG_AUTO; 377 if (preamble == 1) 378 mimocfg |= B43_NPHY_MIMOCFG_GFMIX; 379 else 380 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; 381 382 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); 383} 384 385/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ 386static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) 387{ 388 struct b43_phy_n *nphy = dev->phy.n; 389 390 bool override = false; 391 u16 chain = 0x33; 392 393 if (nphy->txrx_chain == 0) { 394 chain = 0x11; 395 override = true; 396 } else if (nphy->txrx_chain == 1) { 397 chain = 0x22; 398 override = true; 399 } 400 401 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 402 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), 403 chain); 404 405 if (override) 406 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 407 B43_NPHY_RFSEQMODE_CAOVER); 408 else 409 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 410 ~B43_NPHY_RFSEQMODE_CAOVER); 411} 412 413/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ 414static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, 415 u16 samps, u8 time, bool wait) 416{ 417 int i; 418 u16 tmp; 419 420 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); 421 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); 422 if (wait) 423 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); 424 else 425 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); 426 427 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); 428 429 for (i = 1000; i; i--) { 430 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); 431 if (!(tmp & B43_NPHY_IQEST_CMD_START)) { 432 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | 433 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); 434 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | 435 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); 436 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | 437 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); 438 439 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | 440 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); 441 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | 442 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); 443 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | 444 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); 445 return; 446 } 447 udelay(10); 448 } 449 memset(est, 0, sizeof(*est)); 450} 451 452/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ 453static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, 454 struct b43_phy_n_iq_comp *pcomp) 455{ 456 if (write) { 457 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); 458 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); 459 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); 460 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); 461 } else { 462 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); 463 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); 464 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); 465 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); 466 } 467} 468 469/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ 470static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) 471{ 472 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 473 474 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); 475 if (core == 0) { 476 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); 477 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 478 } else { 479 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 480 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 481 } 482 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); 483 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); 484 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); 485 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); 486 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); 487 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); 488 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 489 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 490} 491 492/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ 493static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) 494{ 495 u8 rxval, txval; 496 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 497 498 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 499 if (core == 0) { 500 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 501 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 502 } else { 503 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 504 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 505 } 506 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 507 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 508 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); 509 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); 510 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); 511 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); 512 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 513 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 514 515 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 516 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 517 518 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 519 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 520 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 521 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 522 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); 523 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 524 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); 525 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, 526 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); 527 528 if (core == 0) { 529 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); 530 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); 531 } else { 532 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); 533 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); 534 } 535 536 b43_nphy_rf_control_intc_override(dev, 2, 0, 3); 537 b43_nphy_rf_control_override(dev, 8, 0, 3, false); 538 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 539 540 if (core == 0) { 541 rxval = 1; 542 txval = 8; 543 } else { 544 rxval = 4; 545 txval = 2; 546 } 547 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1)); 548 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core)); 549} 550 551/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ 552static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) 553{ 554 int i; 555 s32 iq; 556 u32 ii; 557 u32 qq; 558 int iq_nbits, qq_nbits; 559 int arsh, brsh; 560 u16 tmp, a, b; 561 562 struct nphy_iq_est est; 563 struct b43_phy_n_iq_comp old; 564 struct b43_phy_n_iq_comp new = { }; 565 bool error = false; 566 567 if (mask == 0) 568 return; 569 570 b43_nphy_rx_iq_coeffs(dev, false, &old); 571 b43_nphy_rx_iq_coeffs(dev, true, &new); 572 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); 573 new = old; 574 575 for (i = 0; i < 2; i++) { 576 if (i == 0 && (mask & 1)) { 577 iq = est.iq0_prod; 578 ii = est.i0_pwr; 579 qq = est.q0_pwr; 580 } else if (i == 1 && (mask & 2)) { 581 iq = est.iq1_prod; 582 ii = est.i1_pwr; 583 qq = est.q1_pwr; 584 } else { 585 B43_WARN_ON(1); 586 continue; 587 } 588 589 if (ii + qq < 2) { 590 error = true; 591 break; 592 } 593 594 iq_nbits = fls(abs(iq)); 595 qq_nbits = fls(qq); 596 597 arsh = iq_nbits - 20; 598 if (arsh >= 0) { 599 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); 600 tmp = ii >> arsh; 601 } else { 602 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); 603 tmp = ii << -arsh; 604 } 605 if (tmp == 0) { 606 error = true; 607 break; 608 } 609 a /= tmp; 610 611 brsh = qq_nbits - 11; 612 if (brsh >= 0) { 613 b = (qq << (31 - qq_nbits)); 614 tmp = ii >> brsh; 615 } else { 616 b = (qq << (31 - qq_nbits)); 617 tmp = ii << -brsh; 618 } 619 if (tmp == 0) { 620 error = true; 621 break; 622 } 623 b = int_sqrt(b / tmp - a * a) - (1 << 10); 624 625 if (i == 0 && (mask & 0x1)) { 626 if (dev->phy.rev >= 3) { 627 new.a0 = a & 0x3FF; 628 new.b0 = b & 0x3FF; 629 } else { 630 new.a0 = b & 0x3FF; 631 new.b0 = a & 0x3FF; 632 } 633 } else if (i == 1 && (mask & 0x2)) { 634 if (dev->phy.rev >= 3) { 635 new.a1 = a & 0x3FF; 636 new.b1 = b & 0x3FF; 637 } else { 638 new.a1 = b & 0x3FF; 639 new.b1 = a & 0x3FF; 640 } 641 } 642 } 643 644 if (error) 645 new = old; 646 647 b43_nphy_rx_iq_coeffs(dev, true, &new); 648} 649 650/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ 651static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) 652{ 653 u16 array[4]; 654 int i; 655 656 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50); 657 for (i = 0; i < 4; i++) 658 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); 659 660 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); 661 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); 662 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); 663 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); 664} 665 666/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 667static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st) 668{ 669 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); 670 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); 671} 672 673/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 674static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) 675{ 676 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); 677 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); 678} 679 680/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ 681static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) 682{ 683 if (dev->phy.rev >= 3) { 684 if (!init) 685 return; 686 if (0 /* FIXME */) { 687 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); 688 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); 689 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); 690 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); 691 } 692 } else { 693 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); 694 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); 695 696 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00, 697 0xFC00); 698 b43_write32(dev, B43_MMIO_MACCTL, 699 b43_read32(dev, B43_MMIO_MACCTL) & 700 ~B43_MACCTL_GPOUTSMSK); 701 b43_write16(dev, B43_MMIO_GPIO_MASK, 702 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00); 703 b43_write16(dev, B43_MMIO_GPIO_CONTROL, 704 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00); 705 706 if (init) { 707 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 708 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 709 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 710 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 711 } 712 } 713} 714 715/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ 716static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) 717{ 718 u16 tmp; 719 720 if (dev->dev->id.revision == 16) 721 b43_mac_suspend(dev); 722 723 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); 724 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | 725 B43_NPHY_CLASSCTL_WAITEDEN); 726 tmp &= ~mask; 727 tmp |= (val & mask); 728 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); 729 730 if (dev->dev->id.revision == 16) 731 b43_mac_enable(dev); 732 733 return tmp; 734} 735 736/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ 737static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) 738{ 739 struct b43_phy *phy = &dev->phy; 740 struct b43_phy_n *nphy = phy->n; 741 742 if (enable) { 743 u16 clip[] = { 0xFFFF, 0xFFFF }; 744 if (nphy->deaf_count++ == 0) { 745 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); 746 b43_nphy_classifier(dev, 0x7, 0); 747 b43_nphy_read_clip_detection(dev, nphy->clip_state); 748 b43_nphy_write_clip_detection(dev, clip); 749 } 750 b43_nphy_reset_cca(dev); 751 } else { 752 if (--nphy->deaf_count == 0) { 753 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); 754 b43_nphy_write_clip_detection(dev, nphy->clip_state); 755 } 756 } 757} 758 759/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ 760static void b43_nphy_stop_playback(struct b43_wldev *dev) 761{ 762 struct b43_phy_n *nphy = dev->phy.n; 763 u16 tmp; 764 765 if (nphy->hang_avoid) 766 b43_nphy_stay_in_carrier_search(dev, 1); 767 768 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); 769 if (tmp & 0x1) 770 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); 771 else if (tmp & 0x2) 772 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 773 774 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); 775 776 if (nphy->bb_mult_save & 0x80000000) { 777 tmp = nphy->bb_mult_save & 0xFFFF; 778 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 779 nphy->bb_mult_save = 0; 780 } 781 782 if (nphy->hang_avoid) 783 b43_nphy_stay_in_carrier_search(dev, 0); 784} 785 786/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ 787static void b43_nphy_spur_workaround(struct b43_wldev *dev) 788{ 789 struct b43_phy_n *nphy = dev->phy.n; 790 791 u8 channel = nphy->radio_chanspec.channel; 792 int tone[2] = { 57, 58 }; 793 u32 noise[2] = { 0x3FF, 0x3FF }; 794 795 B43_WARN_ON(dev->phy.rev < 3); 796 797 if (nphy->hang_avoid) 798 b43_nphy_stay_in_carrier_search(dev, 1); 799 800 if (nphy->gband_spurwar_en) { 801 /* TODO: N PHY Adjust Analog Pfbw (7) */ 802 if (channel == 11 && dev->phy.is_40mhz) 803 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ 804 else 805 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 806 /* TODO: N PHY Adjust CRS Min Power (0x1E) */ 807 } 808 809 if (nphy->aband_spurwar_en) { 810 if (channel == 54) { 811 tone[0] = 0x20; 812 noise[0] = 0x25F; 813 } else if (channel == 38 || channel == 102 || channel == 118) { 814 if (0 /* FIXME */) { 815 tone[0] = 0x20; 816 noise[0] = 0x21F; 817 } else { 818 tone[0] = 0; 819 noise[0] = 0; 820 } 821 } else if (channel == 134) { 822 tone[0] = 0x20; 823 noise[0] = 0x21F; 824 } else if (channel == 151) { 825 tone[0] = 0x10; 826 noise[0] = 0x23F; 827 } else if (channel == 153 || channel == 161) { 828 tone[0] = 0x30; 829 noise[0] = 0x23F; 830 } else { 831 tone[0] = 0; 832 noise[0] = 0; 833 } 834 835 if (!tone[0] && !noise[0]) 836 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ 837 else 838 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 839 } 840 841 if (nphy->hang_avoid) 842 b43_nphy_stay_in_carrier_search(dev, 0); 843} 844 845/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ 846static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) 847{ 848 struct b43_phy_n *nphy = dev->phy.n; 849 850 u8 i; 851 s16 tmp; 852 u16 data[4]; 853 s16 gain[2]; 854 u16 minmax[2]; 855 u16 lna_gain[4] = { -2, 10, 19, 25 }; 856 857 if (nphy->hang_avoid) 858 b43_nphy_stay_in_carrier_search(dev, 1); 859 860 if (nphy->gain_boost) { 861 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 862 gain[0] = 6; 863 gain[1] = 6; 864 } else { 865 tmp = 40370 - 315 * nphy->radio_chanspec.channel; 866 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); 867 tmp = 23242 - 224 * nphy->radio_chanspec.channel; 868 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); 869 } 870 } else { 871 gain[0] = 0; 872 gain[1] = 0; 873 } 874 875 for (i = 0; i < 2; i++) { 876 if (nphy->elna_gain_config) { 877 data[0] = 19 + gain[i]; 878 data[1] = 25 + gain[i]; 879 data[2] = 25 + gain[i]; 880 data[3] = 25 + gain[i]; 881 } else { 882 data[0] = lna_gain[0] + gain[i]; 883 data[1] = lna_gain[1] + gain[i]; 884 data[2] = lna_gain[2] + gain[i]; 885 data[3] = lna_gain[3] + gain[i]; 886 } 887 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data); 888 889 minmax[i] = 23 + gain[i]; 890 } 891 892 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, 893 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT); 894 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, 895 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT); 896 897 if (nphy->hang_avoid) 898 b43_nphy_stay_in_carrier_search(dev, 0); 899} 900 901/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ 902static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) 903{ 904 struct b43_phy_n *nphy = dev->phy.n; 905 u8 i, j; 906 u8 code; 907 908 /* TODO: for PHY >= 3 909 s8 *lna1_gain, *lna2_gain; 910 u8 *gain_db, *gain_bits; 911 u16 *rfseq_init; 912 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; 913 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; 914 */ 915 916 u8 rfseq_events[3] = { 6, 8, 7 }; 917 u8 rfseq_delays[3] = { 10, 30, 1 }; 918 919 if (dev->phy.rev >= 3) { 920 /* TODO */ 921 } else { 922 /* Set Clip 2 detect */ 923 b43_phy_set(dev, B43_NPHY_C1_CGAINI, 924 B43_NPHY_C1_CGAINI_CL2DETECT); 925 b43_phy_set(dev, B43_NPHY_C2_CGAINI, 926 B43_NPHY_C2_CGAINI_CL2DETECT); 927 928 /* Set narrowband clip threshold */ 929 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); 930 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); 931 932 if (!dev->phy.is_40mhz) { 933 /* Set dwell lengths */ 934 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); 935 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); 936 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); 937 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); 938 } 939 940 /* Set wideband clip 2 threshold */ 941 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 942 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 943 21); 944 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, 945 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 946 21); 947 948 if (!dev->phy.is_40mhz) { 949 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, 950 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); 951 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, 952 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); 953 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, 954 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); 955 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, 956 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); 957 } 958 959 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); 960 961 if (nphy->gain_boost) { 962 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && 963 dev->phy.is_40mhz) 964 code = 4; 965 else 966 code = 5; 967 } else { 968 code = dev->phy.is_40mhz ? 6 : 7; 969 } 970 971 /* Set HPVGA2 index */ 972 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, 973 ~B43_NPHY_C1_INITGAIN_HPVGA2, 974 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); 975 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, 976 ~B43_NPHY_C2_INITGAIN_HPVGA2, 977 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); 978 979 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 980 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 981 (code << 8 | 0x7C)); 982 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 983 (code << 8 | 0x7C)); 984 985 b43_nphy_adjust_lna_gain_table(dev); 986 987 if (nphy->elna_gain_config) { 988 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); 989 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 990 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 991 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 992 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 993 994 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); 995 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 996 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 997 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 998 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 999 1000 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 1001 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1002 (code << 8 | 0x74)); 1003 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1004 (code << 8 | 0x74)); 1005 } 1006 1007 if (dev->phy.rev == 2) { 1008 for (i = 0; i < 4; i++) { 1009 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1010 (0x0400 * i) + 0x0020); 1011 for (j = 0; j < 21; j++) 1012 b43_phy_write(dev, 1013 B43_NPHY_TABLE_DATALO, 3 * j); 1014 } 1015 1016 b43_nphy_set_rf_sequence(dev, 5, 1017 rfseq_events, rfseq_delays, 3); 1018 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, 1019 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, 1020 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); 1021 1022 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 1023 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 1024 0xFF80, 4); 1025 } 1026 } 1027} 1028 1029/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ 1030static void b43_nphy_workarounds(struct b43_wldev *dev) 1031{ 1032 struct ssb_bus *bus = dev->dev->bus; 1033 struct b43_phy *phy = &dev->phy; 1034 struct b43_phy_n *nphy = phy->n; 1035 1036 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; 1037 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; 1038 1039 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; 1040 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; 1041 1042 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 1043 b43_nphy_classifier(dev, 1, 0); 1044 else 1045 b43_nphy_classifier(dev, 1, 1); 1046 1047 if (nphy->hang_avoid) 1048 b43_nphy_stay_in_carrier_search(dev, 1); 1049 1050 b43_phy_set(dev, B43_NPHY_IQFLIP, 1051 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); 1052 1053 if (dev->phy.rev >= 3) { 1054 /* TODO */ 1055 } else { 1056 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && 1057 nphy->band5g_pwrgain) { 1058 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); 1059 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); 1060 } else { 1061 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); 1062 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); 1063 } 1064 1065 /* TODO: convert to b43_ntab_write? */ 1066 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000); 1067 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); 1068 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010); 1069 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); 1070 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002); 1071 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); 1072 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012); 1073 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); 1074 1075 if (dev->phy.rev < 2) { 1076 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008); 1077 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); 1078 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018); 1079 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); 1080 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007); 1081 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); 1082 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017); 1083 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); 1084 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006); 1085 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); 1086 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016); 1087 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); 1088 } 1089 1090 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 1091 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 1092 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 1093 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 1094 1095 if (bus->sprom.boardflags2_lo & 0x100 && 1096 bus->boardinfo.type == 0x8B) { 1097 delays1[0] = 0x1; 1098 delays1[5] = 0x14; 1099 } 1100 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); 1101 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); 1102 1103 b43_nphy_gain_ctrl_workarounds(dev); 1104 1105 if (dev->phy.rev < 2) { 1106 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) 1107 b43_hf_write(dev, b43_hf_read(dev) | 1108 B43_HF_MLADVW); 1109 } else if (dev->phy.rev == 2) { 1110 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); 1111 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); 1112 } 1113 1114 if (dev->phy.rev < 2) 1115 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, 1116 ~B43_NPHY_SCRAM_SIGCTL_SCM); 1117 1118 /* Set phase track alpha and beta */ 1119 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); 1120 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); 1121 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); 1122 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); 1123 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); 1124 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); 1125 1126 b43_phy_mask(dev, B43_NPHY_PIL_DW1, 1127 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); 1128 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); 1129 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); 1130 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); 1131 1132 if (dev->phy.rev == 2) 1133 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 1134 B43_NPHY_FINERX2_CGC_DECGC); 1135 } 1136 1137 if (nphy->hang_avoid) 1138 b43_nphy_stay_in_carrier_search(dev, 0); 1139} 1140 1141/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ 1142static int b43_nphy_load_samples(struct b43_wldev *dev, 1143 struct b43_c32 *samples, u16 len) { 1144 struct b43_phy_n *nphy = dev->phy.n; 1145 u16 i; 1146 u32 *data; 1147 1148 data = kzalloc(len * sizeof(u32), GFP_KERNEL); 1149 if (!data) { 1150 b43err(dev->wl, "allocation for samples loading failed\n"); 1151 return -ENOMEM; 1152 } 1153 if (nphy->hang_avoid) 1154 b43_nphy_stay_in_carrier_search(dev, 1); 1155 1156 for (i = 0; i < len; i++) { 1157 data[i] = (samples[i].i & 0x3FF << 10); 1158 data[i] |= samples[i].q & 0x3FF; 1159 } 1160 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); 1161 1162 kfree(data); 1163 if (nphy->hang_avoid) 1164 b43_nphy_stay_in_carrier_search(dev, 0); 1165 return 0; 1166} 1167 1168/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ 1169static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, 1170 bool test) 1171{ 1172 int i; 1173 u16 bw, len, rot, angle; 1174 struct b43_c32 *samples; 1175 1176 1177 bw = (dev->phy.is_40mhz) ? 40 : 20; 1178 len = bw << 3; 1179 1180 if (test) { 1181 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) 1182 bw = 82; 1183 else 1184 bw = 80; 1185 1186 if (dev->phy.is_40mhz) 1187 bw <<= 1; 1188 1189 len = bw << 1; 1190 } 1191 1192 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL); 1193 if (!samples) { 1194 b43err(dev->wl, "allocation for samples generation failed\n"); 1195 return 0; 1196 } 1197 rot = (((freq * 36) / bw) << 16) / 100; 1198 angle = 0; 1199 1200 for (i = 0; i < len; i++) { 1201 samples[i] = b43_cordic(angle); 1202 angle += rot; 1203 samples[i].q = CORDIC_CONVERT(samples[i].q * max); 1204 samples[i].i = CORDIC_CONVERT(samples[i].i * max); 1205 } 1206 1207 i = b43_nphy_load_samples(dev, samples, len); 1208 kfree(samples); 1209 return (i < 0) ? 0 : len; 1210} 1211 1212/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ 1213static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, 1214 u16 wait, bool iqmode, bool dac_test) 1215{ 1216 struct b43_phy_n *nphy = dev->phy.n; 1217 int i; 1218 u16 seq_mode; 1219 u32 tmp; 1220 1221 if (nphy->hang_avoid) 1222 b43_nphy_stay_in_carrier_search(dev, true); 1223 1224 if ((nphy->bb_mult_save & 0x80000000) == 0) { 1225 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); 1226 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; 1227 } 1228 1229 if (!dev->phy.is_40mhz) 1230 tmp = 0x6464; 1231 else 1232 tmp = 0x4747; 1233 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 1234 1235 if (nphy->hang_avoid) 1236 b43_nphy_stay_in_carrier_search(dev, false); 1237 1238 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); 1239 1240 if (loops != 0xFFFF) 1241 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); 1242 else 1243 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); 1244 1245 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); 1246 1247 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 1248 1249 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); 1250 if (iqmode) { 1251 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 1252 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); 1253 } else { 1254 if (dac_test) 1255 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5); 1256 else 1257 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1); 1258 } 1259 for (i = 0; i < 100; i++) { 1260 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) { 1261 i = 0; 1262 break; 1263 } 1264 udelay(10); 1265 } 1266 if (i) 1267 b43err(dev->wl, "run samples timeout\n"); 1268 1269 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 1270} 1271 1272/* 1273 * Transmits a known value for LO calibration 1274 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone 1275 */ 1276static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, 1277 bool iqmode, bool dac_test) 1278{ 1279 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); 1280 if (samp == 0) 1281 return -1; 1282 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test); 1283 return 0; 1284} 1285 1286/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ 1287static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) 1288{ 1289 struct b43_phy_n *nphy = dev->phy.n; 1290 int i, j; 1291 u32 tmp; 1292 u32 cur_real, cur_imag, real_part, imag_part; 1293 1294 u16 buffer[7]; 1295 1296 if (nphy->hang_avoid) 1297 b43_nphy_stay_in_carrier_search(dev, true); 1298 1299 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 1300 1301 for (i = 0; i < 2; i++) { 1302 tmp = ((buffer[i * 2] & 0x3FF) << 10) | 1303 (buffer[i * 2 + 1] & 0x3FF); 1304 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1305 (((i + 26) << 10) | 320)); 1306 for (j = 0; j < 128; j++) { 1307 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 1308 ((tmp >> 16) & 0xFFFF)); 1309 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1310 (tmp & 0xFFFF)); 1311 } 1312 } 1313 1314 for (i = 0; i < 2; i++) { 1315 tmp = buffer[5 + i]; 1316 real_part = (tmp >> 8) & 0xFF; 1317 imag_part = (tmp & 0xFF); 1318 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1319 (((i + 26) << 10) | 448)); 1320 1321 if (dev->phy.rev >= 3) { 1322 cur_real = real_part; 1323 cur_imag = imag_part; 1324 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); 1325 } 1326 1327 for (j = 0; j < 128; j++) { 1328 if (dev->phy.rev < 3) { 1329 cur_real = (real_part * loscale[j] + 128) >> 8; 1330 cur_imag = (imag_part * loscale[j] + 128) >> 8; 1331 tmp = ((cur_real & 0xFF) << 8) | 1332 (cur_imag & 0xFF); 1333 } 1334 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 1335 ((tmp >> 16) & 0xFFFF)); 1336 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1337 (tmp & 0xFFFF)); 1338 } 1339 } 1340 1341 if (dev->phy.rev >= 3) { 1342 b43_shm_write16(dev, B43_SHM_SHARED, 1343 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); 1344 b43_shm_write16(dev, B43_SHM_SHARED, 1345 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); 1346 } 1347 1348 if (nphy->hang_avoid) 1349 b43_nphy_stay_in_carrier_search(dev, false); 1350} 1351 1352/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ 1353static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, 1354 u8 *events, u8 *delays, u8 length) 1355{ 1356 struct b43_phy_n *nphy = dev->phy.n; 1357 u8 i; 1358 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; 1359 u16 offset1 = cmd << 4; 1360 u16 offset2 = offset1 + 0x80; 1361 1362 if (nphy->hang_avoid) 1363 b43_nphy_stay_in_carrier_search(dev, true); 1364 1365 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); 1366 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); 1367 1368 for (i = length; i < 16; i++) { 1369 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); 1370 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); 1371 } 1372 1373 if (nphy->hang_avoid) 1374 b43_nphy_stay_in_carrier_search(dev, false); 1375} 1376 1377/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ 1378static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 1379 enum b43_nphy_rf_sequence seq) 1380{ 1381 static const u16 trigger[] = { 1382 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, 1383 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, 1384 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, 1385 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, 1386 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, 1387 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, 1388 }; 1389 int i; 1390 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 1391 1392 B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); 1393 1394 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 1395 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); 1396 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); 1397 for (i = 0; i < 200; i++) { 1398 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) 1399 goto ok; 1400 msleep(1); 1401 } 1402 b43err(dev->wl, "RF sequence status timeout\n"); 1403ok: 1404 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 1405} 1406 1407/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ 1408static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 1409 u16 value, u8 core, bool off) 1410{ 1411 int i; 1412 u8 index = fls(field); 1413 u8 addr, en_addr, val_addr; 1414 /* we expect only one bit set */ 1415 B43_WARN_ON(field & (~(1 << (index - 1)))); 1416 1417 if (dev->phy.rev >= 3) { 1418 const struct nphy_rf_control_override_rev3 *rf_ctrl; 1419 for (i = 0; i < 2; i++) { 1420 if (index == 0 || index == 16) { 1421 b43err(dev->wl, 1422 "Unsupported RF Ctrl Override call\n"); 1423 return; 1424 } 1425 1426 rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; 1427 en_addr = B43_PHY_N((i == 0) ? 1428 rf_ctrl->en_addr0 : rf_ctrl->en_addr1); 1429 val_addr = B43_PHY_N((i == 0) ? 1430 rf_ctrl->val_addr0 : rf_ctrl->val_addr1); 1431 1432 if (off) { 1433 b43_phy_mask(dev, en_addr, ~(field)); 1434 b43_phy_mask(dev, val_addr, 1435 ~(rf_ctrl->val_mask)); 1436 } else { 1437 if (core == 0 || ((1 << core) & i) != 0) { 1438 b43_phy_set(dev, en_addr, field); 1439 b43_phy_maskset(dev, val_addr, 1440 ~(rf_ctrl->val_mask), 1441 (value << rf_ctrl->val_shift)); 1442 } 1443 } 1444 } 1445 } else { 1446 const struct nphy_rf_control_override_rev2 *rf_ctrl; 1447 if (off) { 1448 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); 1449 value = 0; 1450 } else { 1451 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); 1452 } 1453 1454 for (i = 0; i < 2; i++) { 1455 if (index <= 1 || index == 16) { 1456 b43err(dev->wl, 1457 "Unsupported RF Ctrl Override call\n"); 1458 return; 1459 } 1460 1461 if (index == 2 || index == 10 || 1462 (index >= 13 && index <= 15)) { 1463 core = 1; 1464 } 1465 1466 rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; 1467 addr = B43_PHY_N((i == 0) ? 1468 rf_ctrl->addr0 : rf_ctrl->addr1); 1469 1470 if ((core & (1 << i)) != 0) 1471 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), 1472 (value << rf_ctrl->shift)); 1473 1474 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); 1475 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1476 B43_NPHY_RFCTL_CMD_START); 1477 udelay(1); 1478 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); 1479 } 1480 } 1481} 1482 1483/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ 1484static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, 1485 u16 value, u8 core) 1486{ 1487 u8 i, j; 1488 u16 reg, tmp, val; 1489 1490 B43_WARN_ON(dev->phy.rev < 3); 1491 B43_WARN_ON(field > 4); 1492 1493 for (i = 0; i < 2; i++) { 1494 if ((core == 1 && i == 1) || (core == 2 && !i)) 1495 continue; 1496 1497 reg = (i == 0) ? 1498 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 1499 b43_phy_mask(dev, reg, 0xFBFF); 1500 1501 switch (field) { 1502 case 0: 1503 b43_phy_write(dev, reg, 0); 1504 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 1505 break; 1506 case 1: 1507 if (!i) { 1508 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, 1509 0xFC3F, (value << 6)); 1510 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, 1511 0xFFFE, 1); 1512 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1513 B43_NPHY_RFCTL_CMD_START); 1514 for (j = 0; j < 100; j++) { 1515 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) { 1516 j = 0; 1517 break; 1518 } 1519 udelay(10); 1520 } 1521 if (j) 1522 b43err(dev->wl, 1523 "intc override timeout\n"); 1524 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, 1525 0xFFFE); 1526 } else { 1527 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, 1528 0xFC3F, (value << 6)); 1529 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 1530 0xFFFE, 1); 1531 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1532 B43_NPHY_RFCTL_CMD_RXTX); 1533 for (j = 0; j < 100; j++) { 1534 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) { 1535 j = 0; 1536 break; 1537 } 1538 udelay(10); 1539 } 1540 if (j) 1541 b43err(dev->wl, 1542 "intc override timeout\n"); 1543 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 1544 0xFFFE); 1545 } 1546 break; 1547 case 2: 1548 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1549 tmp = 0x0020; 1550 val = value << 5; 1551 } else { 1552 tmp = 0x0010; 1553 val = value << 4; 1554 } 1555 b43_phy_maskset(dev, reg, ~tmp, val); 1556 break; 1557 case 3: 1558 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1559 tmp = 0x0001; 1560 val = value; 1561 } else { 1562 tmp = 0x0004; 1563 val = value << 2; 1564 } 1565 b43_phy_maskset(dev, reg, ~tmp, val); 1566 break; 1567 case 4: 1568 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1569 tmp = 0x0002; 1570 val = value << 1; 1571 } else { 1572 tmp = 0x0008; 1573 val = value << 3; 1574 } 1575 b43_phy_maskset(dev, reg, ~tmp, val); 1576 break; 1577 } 1578 } 1579} 1580 1581static void b43_nphy_bphy_init(struct b43_wldev *dev) 1582{ 1583 unsigned int i; 1584 u16 val; 1585 1586 val = 0x1E1F; 1587 for (i = 0; i < 14; i++) { 1588 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); 1589 val -= 0x202; 1590 } 1591 val = 0x3E3F; 1592 for (i = 0; i < 16; i++) { 1593 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val); 1594 val -= 0x202; 1595 } 1596 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); 1597} 1598 1599/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ 1600static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, 1601 s8 offset, u8 core, u8 rail, u8 type) 1602{ 1603 u16 tmp; 1604 bool core1or5 = (core == 1) || (core == 5); 1605 bool core2or5 = (core == 2) || (core == 5); 1606 1607 offset = clamp_val(offset, -32, 31); 1608 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); 1609 1610 if (core1or5 && (rail == 0) && (type == 2)) 1611 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); 1612 if (core1or5 && (rail == 1) && (type == 2)) 1613 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); 1614 if (core2or5 && (rail == 0) && (type == 2)) 1615 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); 1616 if (core2or5 && (rail == 1) && (type == 2)) 1617 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); 1618 if (core1or5 && (rail == 0) && (type == 0)) 1619 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); 1620 if (core1or5 && (rail == 1) && (type == 0)) 1621 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); 1622 if (core2or5 && (rail == 0) && (type == 0)) 1623 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); 1624 if (core2or5 && (rail == 1) && (type == 0)) 1625 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); 1626 if (core1or5 && (rail == 0) && (type == 1)) 1627 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); 1628 if (core1or5 && (rail == 1) && (type == 1)) 1629 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); 1630 if (core2or5 && (rail == 0) && (type == 1)) 1631 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); 1632 if (core2or5 && (rail == 1) && (type == 1)) 1633 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); 1634 if (core1or5 && (rail == 0) && (type == 6)) 1635 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); 1636 if (core1or5 && (rail == 1) && (type == 6)) 1637 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); 1638 if (core2or5 && (rail == 0) && (type == 6)) 1639 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); 1640 if (core2or5 && (rail == 1) && (type == 6)) 1641 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); 1642 if (core1or5 && (rail == 0) && (type == 3)) 1643 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); 1644 if (core1or5 && (rail == 1) && (type == 3)) 1645 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); 1646 if (core2or5 && (rail == 0) && (type == 3)) 1647 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); 1648 if (core2or5 && (rail == 1) && (type == 3)) 1649 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); 1650 if (core1or5 && (type == 4)) 1651 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); 1652 if (core2or5 && (type == 4)) 1653 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); 1654 if (core1or5 && (type == 5)) 1655 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); 1656 if (core2or5 && (type == 5)) 1657 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); 1658} 1659 1660static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1661{ 1662 u16 val; 1663 1664 if (type < 3) 1665 val = 0; 1666 else if (type == 6) 1667 val = 1; 1668 else if (type == 3) 1669 val = 2; 1670 else 1671 val = 3; 1672 1673 val = (val << 12) | (val << 14); 1674 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); 1675 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); 1676 1677 if (type < 3) { 1678 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, 1679 (type + 1) << 4); 1680 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, 1681 (type + 1) << 4); 1682 } 1683 1684 /* TODO use some definitions */ 1685 if (code == 0) { 1686 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0); 1687 if (type < 3) { 1688 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0); 1689 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0); 1690 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0); 1691 udelay(20); 1692 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0); 1693 } 1694 } else { 1695 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 1696 0x3000); 1697 if (type < 3) { 1698 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 1699 0xFEC7, 0x0180); 1700 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 1701 0xEFDC, (code << 1 | 0x1021)); 1702 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1); 1703 udelay(20); 1704 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0); 1705 } 1706 } 1707} 1708 1709static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1710{ 1711 struct b43_phy_n *nphy = dev->phy.n; 1712 u8 i; 1713 u16 reg, val; 1714 1715 if (code == 0) { 1716 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); 1717 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); 1718 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); 1719 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); 1720 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); 1721 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); 1722 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); 1723 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); 1724 } else { 1725 for (i = 0; i < 2; i++) { 1726 if ((code == 1 && i == 1) || (code == 2 && !i)) 1727 continue; 1728 1729 reg = (i == 0) ? 1730 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; 1731 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); 1732 1733 if (type < 3) { 1734 reg = (i == 0) ? 1735 B43_NPHY_AFECTL_C1 : 1736 B43_NPHY_AFECTL_C2; 1737 b43_phy_maskset(dev, reg, 0xFCFF, 0); 1738 1739 reg = (i == 0) ? 1740 B43_NPHY_RFCTL_LUT_TRSW_UP1 : 1741 B43_NPHY_RFCTL_LUT_TRSW_UP2; 1742 b43_phy_maskset(dev, reg, 0xFFC3, 0); 1743 1744 if (type == 0) 1745 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; 1746 else if (type == 1) 1747 val = 16; 1748 else 1749 val = 32; 1750 b43_phy_set(dev, reg, val); 1751 1752 reg = (i == 0) ? 1753 B43_NPHY_TXF_40CO_B1S0 : 1754 B43_NPHY_TXF_40CO_B32S1; 1755 b43_phy_set(dev, reg, 0x0020); 1756 } else { 1757 if (type == 6) 1758 val = 0x0100; 1759 else if (type == 3) 1760 val = 0x0200; 1761 else 1762 val = 0x0300; 1763 1764 reg = (i == 0) ? 1765 B43_NPHY_AFECTL_C1 : 1766 B43_NPHY_AFECTL_C2; 1767 1768 b43_phy_maskset(dev, reg, 0xFCFF, val); 1769 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); 1770 1771 if (type != 3 && type != 6) { 1772 enum ieee80211_band band = 1773 b43_current_band(dev->wl); 1774 1775 if ((nphy->ipa2g_on && 1776 band == IEEE80211_BAND_2GHZ) || 1777 (nphy->ipa5g_on && 1778 band == IEEE80211_BAND_5GHZ)) 1779 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; 1780 else 1781 val = 0x11; 1782 reg = (i == 0) ? 0x2000 : 0x3000; 1783 reg |= B2055_PADDRV; 1784 b43_radio_write16(dev, reg, val); 1785 1786 reg = (i == 0) ? 1787 B43_NPHY_AFECTL_OVER1 : 1788 B43_NPHY_AFECTL_OVER; 1789 b43_phy_set(dev, reg, 0x0200); 1790 } 1791 } 1792 } 1793 } 1794} 1795 1796/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ 1797static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1798{ 1799 if (dev->phy.rev >= 3) 1800 b43_nphy_rev3_rssi_select(dev, code, type); 1801 else 1802 b43_nphy_rev2_rssi_select(dev, code, type); 1803} 1804 1805/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ 1806static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) 1807{ 1808 int i; 1809 for (i = 0; i < 2; i++) { 1810 if (type == 2) { 1811 if (i == 0) { 1812 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, 1813 0xFC, buf[0]); 1814 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1815 0xFC, buf[1]); 1816 } else { 1817 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, 1818 0xFC, buf[2 * i]); 1819 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1820 0xFC, buf[2 * i + 1]); 1821 } 1822 } else { 1823 if (i == 0) 1824 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1825 0xF3, buf[0] << 2); 1826 else 1827 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1828 0xF3, buf[2 * i + 1] << 2); 1829 } 1830 } 1831} 1832 1833/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ 1834static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, 1835 u8 nsamp) 1836{ 1837 int i; 1838 int out; 1839 u16 save_regs_phy[9]; 1840 u16 s[2]; 1841 1842 if (dev->phy.rev >= 3) { 1843 save_regs_phy[0] = b43_phy_read(dev, 1844 B43_NPHY_RFCTL_LUT_TRSW_UP1); 1845 save_regs_phy[1] = b43_phy_read(dev, 1846 B43_NPHY_RFCTL_LUT_TRSW_UP2); 1847 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 1848 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 1849 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 1850 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 1851 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); 1852 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); 1853 } 1854 1855 b43_nphy_rssi_select(dev, 5, type); 1856 1857 if (dev->phy.rev < 2) { 1858 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); 1859 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); 1860 } 1861 1862 for (i = 0; i < 4; i++) 1863 buf[i] = 0; 1864 1865 for (i = 0; i < nsamp; i++) { 1866 if (dev->phy.rev < 2) { 1867 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); 1868 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); 1869 } else { 1870 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); 1871 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); 1872 } 1873 1874 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; 1875 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; 1876 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; 1877 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; 1878 } 1879 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | 1880 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); 1881 1882 if (dev->phy.rev < 2) 1883 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); 1884 1885 if (dev->phy.rev >= 3) { 1886 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 1887 save_regs_phy[0]); 1888 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 1889 save_regs_phy[1]); 1890 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]); 1891 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]); 1892 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); 1893 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); 1894 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); 1895 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); 1896 } 1897 1898 return out; 1899} 1900 1901/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ 1902static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) 1903{ 1904 int i, j; 1905 u8 state[4]; 1906 u8 code, val; 1907 u16 class, override; 1908 u8 regs_save_radio[2]; 1909 u16 regs_save_phy[2]; 1910 s8 offset[4]; 1911 1912 u16 clip_state[2]; 1913 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; 1914 s32 results_min[4] = { }; 1915 u8 vcm_final[4] = { }; 1916 s32 results[4][4] = { }; 1917 s32 miniq[4][2] = { }; 1918 1919 if (type == 2) { 1920 code = 0; 1921 val = 6; 1922 } else if (type < 2) { 1923 code = 25; 1924 val = 4; 1925 } else { 1926 B43_WARN_ON(1); 1927 return; 1928 } 1929 1930 class = b43_nphy_classifier(dev, 0, 0); 1931 b43_nphy_classifier(dev, 7, 4); 1932 b43_nphy_read_clip_detection(dev, clip_state); 1933 b43_nphy_write_clip_detection(dev, clip_off); 1934 1935 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 1936 override = 0x140; 1937 else 1938 override = 0x110; 1939 1940 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 1941 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); 1942 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); 1943 b43_radio_write16(dev, B2055_C1_PD_RXTX, val); 1944 1945 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 1946 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); 1947 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); 1948 b43_radio_write16(dev, B2055_C2_PD_RXTX, val); 1949 1950 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; 1951 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; 1952 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); 1953 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); 1954 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; 1955 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; 1956 1957 b43_nphy_rssi_select(dev, 5, type); 1958 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); 1959 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); 1960 1961 for (i = 0; i < 4; i++) { 1962 u8 tmp[4]; 1963 for (j = 0; j < 4; j++) 1964 tmp[j] = i; 1965 if (type != 1) 1966 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); 1967 b43_nphy_poll_rssi(dev, type, results[i], 8); 1968 if (type < 2) 1969 for (j = 0; j < 2; j++) 1970 miniq[i][j] = min(results[i][2 * j], 1971 results[i][2 * j + 1]); 1972 } 1973 1974 for (i = 0; i < 4; i++) { 1975 s32 mind = 40; 1976 u8 minvcm = 0; 1977 s32 minpoll = 249; 1978 s32 curr; 1979 for (j = 0; j < 4; j++) { 1980 if (type == 2) 1981 curr = abs(results[j][i]); 1982 else 1983 curr = abs(miniq[j][i / 2] - code * 8); 1984 1985 if (curr < mind) { 1986 mind = curr; 1987 minvcm = j; 1988 } 1989 1990 if (results[j][i] < minpoll) 1991 minpoll = results[j][i]; 1992 } 1993 results_min[i] = minpoll; 1994 vcm_final[i] = minvcm; 1995 } 1996 1997 if (type != 1) 1998 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); 1999 2000 for (i = 0; i < 4; i++) { 2001 offset[i] = (code * 8) - results[vcm_final[i]][i]; 2002 2003 if (offset[i] < 0) 2004 offset[i] = -((abs(offset[i]) + 4) / 8); 2005 else 2006 offset[i] = (offset[i] + 4) / 8; 2007 2008 if (results_min[i] == 248) 2009 offset[i] = code - 32; 2010 2011 if (i % 2 == 0) 2012 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0, 2013 type); 2014 else 2015 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1, 2016 type); 2017 } 2018 2019 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); 2020 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]); 2021 2022 switch (state[2]) { 2023 case 1: 2024 b43_nphy_rssi_select(dev, 1, 2); 2025 break; 2026 case 4: 2027 b43_nphy_rssi_select(dev, 1, 0); 2028 break; 2029 case 2: 2030 b43_nphy_rssi_select(dev, 1, 1); 2031 break; 2032 default: 2033 b43_nphy_rssi_select(dev, 1, 1); 2034 break; 2035 } 2036 2037 switch (state[3]) { 2038 case 1: 2039 b43_nphy_rssi_select(dev, 2, 2); 2040 break; 2041 case 4: 2042 b43_nphy_rssi_select(dev, 2, 0); 2043 break; 2044 default: 2045 b43_nphy_rssi_select(dev, 2, 1); 2046 break; 2047 } 2048 2049 b43_nphy_rssi_select(dev, 0, type); 2050 2051 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); 2052 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); 2053 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); 2054 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); 2055 2056 b43_nphy_classifier(dev, 7, class); 2057 b43_nphy_write_clip_detection(dev, clip_state); 2058} 2059 2060/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ 2061static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) 2062{ 2063 /* TODO */ 2064} 2065 2066/* 2067 * RSSI Calibration 2068 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal 2069 */ 2070static void b43_nphy_rssi_cal(struct b43_wldev *dev) 2071{ 2072 if (dev->phy.rev >= 3) { 2073 b43_nphy_rev3_rssi_cal(dev); 2074 } else { 2075 b43_nphy_rev2_rssi_cal(dev, 2); 2076 b43_nphy_rev2_rssi_cal(dev, 0); 2077 b43_nphy_rev2_rssi_cal(dev, 1); 2078 } 2079} 2080 2081/* 2082 * Restore RSSI Calibration 2083 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal 2084 */ 2085static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) 2086{ 2087 struct b43_phy_n *nphy = dev->phy.n; 2088 2089 u16 *rssical_radio_regs = NULL; 2090 u16 *rssical_phy_regs = NULL; 2091 2092 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2093 if (b43_empty_chanspec(&nphy->rssical_chanspec_2G)) 2094 return; 2095 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; 2096 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; 2097 } else { 2098 if (b43_empty_chanspec(&nphy->rssical_chanspec_5G)) 2099 return; 2100 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 2101 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 2102 } 2103 2104 /* TODO use some definitions */ 2105 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); 2106 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); 2107 2108 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); 2109 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); 2110 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); 2111 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); 2112 2113 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); 2114 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); 2115 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); 2116 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); 2117 2118 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); 2119 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); 2120 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); 2121 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); 2122} 2123 2124/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ 2125static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) 2126{ 2127 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2128 if (dev->phy.rev >= 6) { 2129 /* TODO If the chip is 47162 2130 return txpwrctrl_tx_gain_ipa_rev5 */ 2131 return txpwrctrl_tx_gain_ipa_rev6; 2132 } else if (dev->phy.rev >= 5) { 2133 return txpwrctrl_tx_gain_ipa_rev5; 2134 } else { 2135 return txpwrctrl_tx_gain_ipa; 2136 } 2137 } else { 2138 return txpwrctrl_tx_gain_ipa_5g; 2139 } 2140} 2141 2142/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ 2143static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) 2144{ 2145 struct b43_phy_n *nphy = dev->phy.n; 2146 u16 *save = nphy->tx_rx_cal_radio_saveregs; 2147 u16 tmp; 2148 u8 offset, i; 2149 2150 if (dev->phy.rev >= 3) { 2151 for (i = 0; i < 2; i++) { 2152 tmp = (i == 0) ? 0x2000 : 0x3000; 2153 offset = i * 11; 2154 2155 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); 2156 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); 2157 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); 2158 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); 2159 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); 2160 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); 2161 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); 2162 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); 2163 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); 2164 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); 2165 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); 2166 2167 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2168 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); 2169 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 2170 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 2171 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 2172 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 2173 if (nphy->ipa5g_on) { 2174 b43_radio_write16(dev, tmp | B2055_PADDRV, 4); 2175 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); 2176 } else { 2177 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 2178 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); 2179 } 2180 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 2181 } else { 2182 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); 2183 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 2184 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 2185 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 2186 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 2187 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); 2188 if (nphy->ipa2g_on) { 2189 b43_radio_write16(dev, tmp | B2055_PADDRV, 6); 2190 b43_radio_write16(dev, tmp | B2055_XOCTL2, 2191 (dev->phy.rev < 5) ? 0x11 : 0x01); 2192 } else { 2193 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 2194 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 2195 } 2196 } 2197 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); 2198 b43_radio_write16(dev, tmp | B2055_XOMISC, 0); 2199 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); 2200 } 2201 } else { 2202 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); 2203 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); 2204 2205 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); 2206 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); 2207 2208 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); 2209 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); 2210 2211 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); 2212 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); 2213 2214 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); 2215 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); 2216 2217 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & 2218 B43_NPHY_BANDCTL_5GHZ)) { 2219 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); 2220 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); 2221 } else { 2222 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); 2223 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); 2224 } 2225 2226 if (dev->phy.rev < 2) { 2227 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); 2228 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); 2229 } else { 2230 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); 2231 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); 2232 } 2233 } 2234} 2235 2236/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ 2237static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, 2238 struct nphy_txgains target, 2239 struct nphy_iqcal_params *params) 2240{ 2241 int i, j, indx; 2242 u16 gain; 2243 2244 if (dev->phy.rev >= 3) { 2245 params->txgm = target.txgm[core]; 2246 params->pga = target.pga[core]; 2247 params->pad = target.pad[core]; 2248 params->ipa = target.ipa[core]; 2249 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | 2250 (params->pad << 4) | (params->ipa); 2251 for (j = 0; j < 5; j++) 2252 params->ncorr[j] = 0x79; 2253 } else { 2254 gain = (target.pad[core]) | (target.pga[core] << 4) | 2255 (target.txgm[core] << 8); 2256 2257 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 2258 1 : 0; 2259 for (i = 0; i < 9; i++) 2260 if (tbl_iqcal_gainparams[indx][i][0] == gain) 2261 break; 2262 i = min(i, 8); 2263 2264 params->txgm = tbl_iqcal_gainparams[indx][i][1]; 2265 params->pga = tbl_iqcal_gainparams[indx][i][2]; 2266 params->pad = tbl_iqcal_gainparams[indx][i][3]; 2267 params->cal_gain = (params->txgm << 7) | (params->pga << 4) | 2268 (params->pad << 2); 2269 for (j = 0; j < 4; j++) 2270 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; 2271 } 2272} 2273 2274/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ 2275static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) 2276{ 2277 struct b43_phy_n *nphy = dev->phy.n; 2278 int i; 2279 u16 scale, entry; 2280 2281 u16 tmp = nphy->txcal_bbmult; 2282 if (core == 0) 2283 tmp >>= 8; 2284 tmp &= 0xff; 2285 2286 for (i = 0; i < 18; i++) { 2287 scale = (ladder_lo[i].percent * tmp) / 100; 2288 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; 2289 b43_ntab_write(dev, B43_NTAB16(15, i), entry); 2290 2291 scale = (ladder_iq[i].percent * tmp) / 100; 2292 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; 2293 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); 2294 } 2295} 2296 2297/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ 2298static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) 2299{ 2300 int i; 2301 for (i = 0; i < 15; i++) 2302 b43_phy_write(dev, B43_PHY_N(0x2C5 + i), 2303 tbl_tx_filter_coef_rev4[2][i]); 2304} 2305 2306/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ 2307static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) 2308{ 2309 int i, j; 2310 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ 2311 u16 offset[] = { 0x186, 0x195, 0x2C5 }; 2312 2313 for (i = 0; i < 3; i++) 2314 for (j = 0; j < 15; j++) 2315 b43_phy_write(dev, B43_PHY_N(offset[i] + j), 2316 tbl_tx_filter_coef_rev4[i][j]); 2317 2318 if (dev->phy.is_40mhz) { 2319 for (j = 0; j < 15; j++) 2320 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2321 tbl_tx_filter_coef_rev4[3][j]); 2322 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2323 for (j = 0; j < 15; j++) 2324 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2325 tbl_tx_filter_coef_rev4[5][j]); 2326 } 2327 2328 if (dev->phy.channel == 14) 2329 for (j = 0; j < 15; j++) 2330 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2331 tbl_tx_filter_coef_rev4[6][j]); 2332} 2333 2334/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ 2335static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) 2336{ 2337 struct b43_phy_n *nphy = dev->phy.n; 2338 2339 u16 curr_gain[2]; 2340 struct nphy_txgains target; 2341 const u32 *table = NULL; 2342 2343 if (nphy->txpwrctrl == 0) { 2344 int i; 2345 2346 if (nphy->hang_avoid) 2347 b43_nphy_stay_in_carrier_search(dev, true); 2348 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); 2349 if (nphy->hang_avoid) 2350 b43_nphy_stay_in_carrier_search(dev, false); 2351 2352 for (i = 0; i < 2; ++i) { 2353 if (dev->phy.rev >= 3) { 2354 target.ipa[i] = curr_gain[i] & 0x000F; 2355 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; 2356 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; 2357 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; 2358 } else { 2359 target.ipa[i] = curr_gain[i] & 0x0003; 2360 target.pad[i] = (curr_gain[i] & 0x000C) >> 2; 2361 target.pga[i] = (curr_gain[i] & 0x0070) >> 4; 2362 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; 2363 } 2364 } 2365 } else { 2366 int i; 2367 u16 index[2]; 2368 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & 2369 B43_NPHY_TXPCTL_STAT_BIDX) >> 2370 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 2371 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & 2372 B43_NPHY_TXPCTL_STAT_BIDX) >> 2373 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 2374 2375 for (i = 0; i < 2; ++i) { 2376 if (dev->phy.rev >= 3) { 2377 enum ieee80211_band band = 2378 b43_current_band(dev->wl); 2379 2380 if ((nphy->ipa2g_on && 2381 band == IEEE80211_BAND_2GHZ) || 2382 (nphy->ipa5g_on && 2383 band == IEEE80211_BAND_5GHZ)) { 2384 table = b43_nphy_get_ipa_gain_table(dev); 2385 } else { 2386 if (band == IEEE80211_BAND_5GHZ) { 2387 if (dev->phy.rev == 3) 2388 table = b43_ntab_tx_gain_rev3_5ghz; 2389 else if (dev->phy.rev == 4) 2390 table = b43_ntab_tx_gain_rev4_5ghz; 2391 else 2392 table = b43_ntab_tx_gain_rev5plus_5ghz; 2393 } else { 2394 table = b43_ntab_tx_gain_rev3plus_2ghz; 2395 } 2396 } 2397 2398 target.ipa[i] = (table[index[i]] >> 16) & 0xF; 2399 target.pad[i] = (table[index[i]] >> 20) & 0xF; 2400 target.pga[i] = (table[index[i]] >> 24) & 0xF; 2401 target.txgm[i] = (table[index[i]] >> 28) & 0xF; 2402 } else { 2403 table = b43_ntab_tx_gain_rev0_1_2; 2404 2405 target.ipa[i] = (table[index[i]] >> 16) & 0x3; 2406 target.pad[i] = (table[index[i]] >> 18) & 0x3; 2407 target.pga[i] = (table[index[i]] >> 20) & 0x7; 2408 target.txgm[i] = (table[index[i]] >> 23) & 0x7; 2409 } 2410 } 2411 } 2412 2413 return target; 2414} 2415 2416/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ 2417static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) 2418{ 2419 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 2420 2421 if (dev->phy.rev >= 3) { 2422 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); 2423 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 2424 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 2425 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); 2426 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); 2427 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); 2428 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); 2429 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); 2430 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); 2431 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 2432 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 2433 b43_nphy_reset_cca(dev); 2434 } else { 2435 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); 2436 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); 2437 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 2438 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); 2439 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); 2440 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); 2441 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); 2442 } 2443} 2444 2445/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ 2446static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) 2447{ 2448 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 2449 u16 tmp; 2450 2451 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 2452 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 2453 if (dev->phy.rev >= 3) { 2454 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); 2455 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); 2456 2457 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 2458 regs[2] = tmp; 2459 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); 2460 2461 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2462 regs[3] = tmp; 2463 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); 2464 2465 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); 2466 b43_phy_mask(dev, B43_NPHY_BBCFG, 2467 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); 2468 2469 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); 2470 regs[5] = tmp; 2471 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); 2472 2473 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); 2474 regs[6] = tmp; 2475 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); 2476 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2477 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2478 2479 b43_nphy_rf_control_intc_override(dev, 2, 1, 3); 2480 b43_nphy_rf_control_intc_override(dev, 1, 2, 1); 2481 b43_nphy_rf_control_intc_override(dev, 1, 8, 2); 2482 2483 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 2484 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 2485 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 2486 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 2487 } else { 2488 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); 2489 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); 2490 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2491 regs[2] = tmp; 2492 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); 2493 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); 2494 regs[3] = tmp; 2495 tmp |= 0x2000; 2496 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); 2497 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); 2498 regs[4] = tmp; 2499 tmp |= 0x2000; 2500 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); 2501 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2502 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2503 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 2504 tmp = 0x0180; 2505 else 2506 tmp = 0x0120; 2507 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 2508 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 2509 } 2510} 2511 2512/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ 2513static void b43_nphy_save_cal(struct b43_wldev *dev) 2514{ 2515 struct b43_phy_n *nphy = dev->phy.n; 2516 2517 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 2518 u16 *txcal_radio_regs = NULL; 2519 struct b43_chanspec *iqcal_chanspec; 2520 u16 *table = NULL; 2521 2522 if (nphy->hang_avoid) 2523 b43_nphy_stay_in_carrier_search(dev, 1); 2524 2525 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2526 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 2527 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 2528 iqcal_chanspec = &nphy->iqcal_chanspec_2G; 2529 table = nphy->cal_cache.txcal_coeffs_2G; 2530 } else { 2531 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 2532 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 2533 iqcal_chanspec = &nphy->iqcal_chanspec_5G; 2534 table = nphy->cal_cache.txcal_coeffs_5G; 2535 } 2536 2537 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); 2538 /* TODO use some definitions */ 2539 if (dev->phy.rev >= 3) { 2540 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); 2541 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); 2542 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); 2543 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); 2544 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); 2545 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); 2546 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); 2547 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); 2548 } else { 2549 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); 2550 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); 2551 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); 2552 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); 2553 } 2554 *iqcal_chanspec = nphy->radio_chanspec; 2555 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table); 2556 2557 if (nphy->hang_avoid) 2558 b43_nphy_stay_in_carrier_search(dev, 0); 2559} 2560 2561/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ 2562static void b43_nphy_restore_cal(struct b43_wldev *dev) 2563{ 2564 struct b43_phy_n *nphy = dev->phy.n; 2565 2566 u16 coef[4]; 2567 u16 *loft = NULL; 2568 u16 *table = NULL; 2569 2570 int i; 2571 u16 *txcal_radio_regs = NULL; 2572 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 2573 2574 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2575 if (b43_empty_chanspec(&nphy->iqcal_chanspec_2G)) 2576 return; 2577 table = nphy->cal_cache.txcal_coeffs_2G; 2578 loft = &nphy->cal_cache.txcal_coeffs_2G[5]; 2579 } else { 2580 if (b43_empty_chanspec(&nphy->iqcal_chanspec_5G)) 2581 return; 2582 table = nphy->cal_cache.txcal_coeffs_5G; 2583 loft = &nphy->cal_cache.txcal_coeffs_5G[5]; 2584 } 2585 2586 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); 2587 2588 for (i = 0; i < 4; i++) { 2589 if (dev->phy.rev >= 3) 2590 table[i] = coef[i]; 2591 else 2592 coef[i] = 0; 2593 } 2594 2595 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); 2596 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); 2597 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); 2598 2599 if (dev->phy.rev < 2) 2600 b43_nphy_tx_iq_workaround(dev); 2601 2602 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2603 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 2604 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 2605 } else { 2606 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 2607 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 2608 } 2609 2610 /* TODO use some definitions */ 2611 if (dev->phy.rev >= 3) { 2612 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); 2613 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); 2614 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); 2615 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); 2616 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); 2617 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); 2618 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); 2619 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); 2620 } else { 2621 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); 2622 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); 2623 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); 2624 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); 2625 } 2626 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); 2627} 2628 2629/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ 2630static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, 2631 struct nphy_txgains target, 2632 bool full, bool mphase) 2633{ 2634 struct b43_phy_n *nphy = dev->phy.n; 2635 int i; 2636 int error = 0; 2637 int freq; 2638 bool avoid = false; 2639 u8 length; 2640 u16 tmp, core, type, count, max, numb, last, cmd; 2641 const u16 *table; 2642 bool phy6or5x; 2643 2644 u16 buffer[11]; 2645 u16 diq_start = 0; 2646 u16 save[2]; 2647 u16 gain[2]; 2648 struct nphy_iqcal_params params[2]; 2649 bool updated[2] = { }; 2650 2651 b43_nphy_stay_in_carrier_search(dev, true); 2652 2653 if (dev->phy.rev >= 4) { 2654 avoid = nphy->hang_avoid; 2655 nphy->hang_avoid = 0; 2656 } 2657 2658 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 2659 2660 for (i = 0; i < 2; i++) { 2661 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); 2662 gain[i] = params[i].cal_gain; 2663 } 2664 2665 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); 2666 2667 b43_nphy_tx_cal_radio_setup(dev); 2668 b43_nphy_tx_cal_phy_setup(dev); 2669 2670 phy6or5x = dev->phy.rev >= 6 || 2671 (dev->phy.rev == 5 && nphy->ipa2g_on && 2672 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); 2673 if (phy6or5x) { 2674 if (dev->phy.is_40mhz) { 2675 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 2676 tbl_tx_iqlo_cal_loft_ladder_40); 2677 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 2678 tbl_tx_iqlo_cal_iqimb_ladder_40); 2679 } else { 2680 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 2681 tbl_tx_iqlo_cal_loft_ladder_20); 2682 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 2683 tbl_tx_iqlo_cal_iqimb_ladder_20); 2684 } 2685 } 2686 2687 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); 2688 2689 if (!dev->phy.is_40mhz) 2690 freq = 2500; 2691 else 2692 freq = 5000; 2693 2694 if (nphy->mphase_cal_phase_id > 2) 2695 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8, 2696 0xFFFF, 0, true, false); 2697 else 2698 error = b43_nphy_tx_tone(dev, freq, 250, true, false); 2699 2700 if (error == 0) { 2701 if (nphy->mphase_cal_phase_id > 2) { 2702 table = nphy->mphase_txcal_bestcoeffs; 2703 length = 11; 2704 if (dev->phy.rev < 3) 2705 length -= 2; 2706 } else { 2707 if (!full && nphy->txiqlocal_coeffsvalid) { 2708 table = nphy->txiqlocal_bestc; 2709 length = 11; 2710 if (dev->phy.rev < 3) 2711 length -= 2; 2712 } else { 2713 full = true; 2714 if (dev->phy.rev >= 3) { 2715 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; 2716 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; 2717 } else { 2718 table = tbl_tx_iqlo_cal_startcoefs; 2719 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; 2720 } 2721 } 2722 } 2723 2724 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); 2725 2726 if (full) { 2727 if (dev->phy.rev >= 3) 2728 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; 2729 else 2730 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; 2731 } else { 2732 if (dev->phy.rev >= 3) 2733 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; 2734 else 2735 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; 2736 } 2737 2738 if (mphase) { 2739 count = nphy->mphase_txcal_cmdidx; 2740 numb = min(max, 2741 (u16)(count + nphy->mphase_txcal_numcmds)); 2742 } else { 2743 count = 0; 2744 numb = max; 2745 } 2746 2747 for (; count < numb; count++) { 2748 if (full) { 2749 if (dev->phy.rev >= 3) 2750 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; 2751 else 2752 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; 2753 } else { 2754 if (dev->phy.rev >= 3) 2755 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; 2756 else 2757 cmd = tbl_tx_iqlo_cal_cmds_recal[count]; 2758 } 2759 2760 core = (cmd & 0x3000) >> 12; 2761 type = (cmd & 0x0F00) >> 8; 2762 2763 if (phy6or5x && updated[core] == 0) { 2764 b43_nphy_update_tx_cal_ladder(dev, core); 2765 updated[core] = 1; 2766 } 2767 2768 tmp = (params[core].ncorr[type] << 8) | 0x66; 2769 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); 2770 2771 if (type == 1 || type == 3 || type == 4) { 2772 buffer[0] = b43_ntab_read(dev, 2773 B43_NTAB16(15, 69 + core)); 2774 diq_start = buffer[0]; 2775 buffer[0] = 0; 2776 b43_ntab_write(dev, B43_NTAB16(15, 69 + core), 2777 0); 2778 } 2779 2780 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); 2781 for (i = 0; i < 2000; i++) { 2782 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); 2783 if (tmp & 0xC000) 2784 break; 2785 udelay(10); 2786 } 2787 2788 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 2789 buffer); 2790 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, 2791 buffer); 2792 2793 if (type == 1 || type == 3 || type == 4) 2794 buffer[0] = diq_start; 2795 } 2796 2797 if (mphase) 2798 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; 2799 2800 last = (dev->phy.rev < 3) ? 6 : 7; 2801 2802 if (!mphase || nphy->mphase_cal_phase_id == last) { 2803 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); 2804 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); 2805 if (dev->phy.rev < 3) { 2806 buffer[0] = 0; 2807 buffer[1] = 0; 2808 buffer[2] = 0; 2809 buffer[3] = 0; 2810 } 2811 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 2812 buffer); 2813 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, 2814 buffer); 2815 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 2816 buffer); 2817 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 2818 buffer); 2819 length = 11; 2820 if (dev->phy.rev < 3) 2821 length -= 2; 2822 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 2823 nphy->txiqlocal_bestc); 2824 nphy->txiqlocal_coeffsvalid = true; 2825 nphy->txiqlocal_chanspec = nphy->radio_chanspec; 2826 } else { 2827 length = 11; 2828 if (dev->phy.rev < 3) 2829 length -= 2; 2830 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 2831 nphy->mphase_txcal_bestcoeffs); 2832 } 2833 2834 b43_nphy_stop_playback(dev); 2835 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); 2836 } 2837 2838 b43_nphy_tx_cal_phy_cleanup(dev); 2839 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 2840 2841 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) 2842 b43_nphy_tx_iq_workaround(dev); 2843 2844 if (dev->phy.rev >= 4) 2845 nphy->hang_avoid = avoid; 2846 2847 b43_nphy_stay_in_carrier_search(dev, false); 2848 2849 return error; 2850} 2851 2852/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ 2853static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) 2854{ 2855 struct b43_phy_n *nphy = dev->phy.n; 2856 u8 i; 2857 u16 buffer[7]; 2858 bool equal = true; 2859 2860 if (!nphy->txiqlocal_coeffsvalid || 2861 b43_eq_chanspecs(&nphy->txiqlocal_chanspec, &nphy->radio_chanspec)) 2862 return; 2863 2864 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 2865 for (i = 0; i < 4; i++) { 2866 if (buffer[i] != nphy->txiqlocal_bestc[i]) { 2867 equal = false; 2868 break; 2869 } 2870 } 2871 2872 if (!equal) { 2873 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, 2874 nphy->txiqlocal_bestc); 2875 for (i = 0; i < 4; i++) 2876 buffer[i] = 0; 2877 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 2878 buffer); 2879 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 2880 &nphy->txiqlocal_bestc[5]); 2881 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 2882 &nphy->txiqlocal_bestc[5]); 2883 } 2884} 2885 2886/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ 2887static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, 2888 struct nphy_txgains target, u8 type, bool debug) 2889{ 2890 struct b43_phy_n *nphy = dev->phy.n; 2891 int i, j, index; 2892 u8 rfctl[2]; 2893 u8 afectl_core; 2894 u16 tmp[6]; 2895 u16 cur_hpf1, cur_hpf2, cur_lna; 2896 u32 real, imag; 2897 enum ieee80211_band band; 2898 2899 u8 use; 2900 u16 cur_hpf; 2901 u16 lna[3] = { 3, 3, 1 }; 2902 u16 hpf1[3] = { 7, 2, 0 }; 2903 u16 hpf2[3] = { 2, 0, 0 }; 2904 u32 power[3] = { }; 2905 u16 gain_save[2]; 2906 u16 cal_gain[2]; 2907 struct nphy_iqcal_params cal_params[2]; 2908 struct nphy_iq_est est; 2909 int ret = 0; 2910 bool playtone = true; 2911 int desired = 13; 2912 2913 b43_nphy_stay_in_carrier_search(dev, 1); 2914 2915 if (dev->phy.rev < 2) 2916 b43_nphy_reapply_tx_cal_coeffs(dev); 2917 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 2918 for (i = 0; i < 2; i++) { 2919 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); 2920 cal_gain[i] = cal_params[i].cal_gain; 2921 } 2922 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); 2923 2924 for (i = 0; i < 2; i++) { 2925 if (i == 0) { 2926 rfctl[0] = B43_NPHY_RFCTL_INTC1; 2927 rfctl[1] = B43_NPHY_RFCTL_INTC2; 2928 afectl_core = B43_NPHY_AFECTL_C1; 2929 } else { 2930 rfctl[0] = B43_NPHY_RFCTL_INTC2; 2931 rfctl[1] = B43_NPHY_RFCTL_INTC1; 2932 afectl_core = B43_NPHY_AFECTL_C2; 2933 } 2934 2935 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 2936 tmp[2] = b43_phy_read(dev, afectl_core); 2937 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2938 tmp[4] = b43_phy_read(dev, rfctl[0]); 2939 tmp[5] = b43_phy_read(dev, rfctl[1]); 2940 2941 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 2942 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 2943 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 2944 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 2945 (1 - i)); 2946 b43_phy_set(dev, afectl_core, 0x0006); 2947 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); 2948 2949 band = b43_current_band(dev->wl); 2950 2951 if (nphy->rxcalparams & 0xFF000000) { 2952 if (band == IEEE80211_BAND_5GHZ) 2953 b43_phy_write(dev, rfctl[0], 0x140); 2954 else 2955 b43_phy_write(dev, rfctl[0], 0x110); 2956 } else { 2957 if (band == IEEE80211_BAND_5GHZ) 2958 b43_phy_write(dev, rfctl[0], 0x180); 2959 else 2960 b43_phy_write(dev, rfctl[0], 0x120); 2961 } 2962 2963 if (band == IEEE80211_BAND_5GHZ) 2964 b43_phy_write(dev, rfctl[1], 0x148); 2965 else 2966 b43_phy_write(dev, rfctl[1], 0x114); 2967 2968 if (nphy->rxcalparams & 0x10000) { 2969 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, 2970 (i + 1)); 2971 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, 2972 (2 - i)); 2973 } 2974 2975 for (j = 0; i < 4; j++) { 2976 if (j < 3) { 2977 cur_lna = lna[j]; 2978 cur_hpf1 = hpf1[j]; 2979 cur_hpf2 = hpf2[j]; 2980 } else { 2981 if (power[1] > 10000) { 2982 use = 1; 2983 cur_hpf = cur_hpf1; 2984 index = 2; 2985 } else { 2986 if (power[0] > 10000) { 2987 use = 1; 2988 cur_hpf = cur_hpf1; 2989 index = 1; 2990 } else { 2991 index = 0; 2992 use = 2; 2993 cur_hpf = cur_hpf2; 2994 } 2995 } 2996 cur_lna = lna[index]; 2997 cur_hpf1 = hpf1[index]; 2998 cur_hpf2 = hpf2[index]; 2999 cur_hpf += desired - hweight32(power[index]); 3000 cur_hpf = clamp_val(cur_hpf, 0, 10); 3001 if (use == 1) 3002 cur_hpf1 = cur_hpf; 3003 else 3004 cur_hpf2 = cur_hpf; 3005 } 3006 3007 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | 3008 (cur_lna << 2)); 3009 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, 3010 false); 3011 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3012 b43_nphy_stop_playback(dev); 3013 3014 if (playtone) { 3015 ret = b43_nphy_tx_tone(dev, 4000, 3016 (nphy->rxcalparams & 0xFFFF), 3017 false, false); 3018 playtone = false; 3019 } else { 3020 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, 3021 false, false); 3022 } 3023 3024 if (ret == 0) { 3025 if (j < 3) { 3026 b43_nphy_rx_iq_est(dev, &est, 1024, 32, 3027 false); 3028 if (i == 0) { 3029 real = est.i0_pwr; 3030 imag = est.q0_pwr; 3031 } else { 3032 real = est.i1_pwr; 3033 imag = est.q1_pwr; 3034 } 3035 power[i] = ((real + imag) / 1024) + 1; 3036 } else { 3037 b43_nphy_calc_rx_iq_comp(dev, 1 << i); 3038 } 3039 b43_nphy_stop_playback(dev); 3040 } 3041 3042 if (ret != 0) 3043 break; 3044 } 3045 3046 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); 3047 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); 3048 b43_phy_write(dev, rfctl[1], tmp[5]); 3049 b43_phy_write(dev, rfctl[0], tmp[4]); 3050 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); 3051 b43_phy_write(dev, afectl_core, tmp[2]); 3052 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); 3053 3054 if (ret != 0) 3055 break; 3056 } 3057 3058 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); 3059 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3060 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 3061 3062 b43_nphy_stay_in_carrier_search(dev, 0); 3063 3064 return ret; 3065} 3066 3067static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, 3068 struct nphy_txgains target, u8 type, bool debug) 3069{ 3070 return -1; 3071} 3072 3073/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ 3074static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, 3075 struct nphy_txgains target, u8 type, bool debug) 3076{ 3077 if (dev->phy.rev >= 3) 3078 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); 3079 else 3080 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); 3081} 3082 3083/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 3084static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on) 3085{ 3086 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 3087 if (on) 3088 tmslow |= SSB_TMSLOW_PHYCLK; 3089 else 3090 tmslow &= ~SSB_TMSLOW_PHYCLK; 3091 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 3092} 3093 3094/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */ 3095static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) 3096{ 3097 struct b43_phy *phy = &dev->phy; 3098 struct b43_phy_n *nphy = phy->n; 3099 u16 buf[16]; 3100 3101 nphy->phyrxchain = mask; 3102 3103 if (0 /* FIXME clk */) 3104 return; 3105 3106 b43_mac_suspend(dev); 3107 3108 if (nphy->hang_avoid) 3109 b43_nphy_stay_in_carrier_search(dev, true); 3110 3111 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 3112 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT); 3113 3114 if ((mask & 0x3) != 0x3) { 3115 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); 3116 if (dev->phy.rev >= 3) { 3117 /* TODO */ 3118 } 3119 } else { 3120 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); 3121 if (dev->phy.rev >= 3) { 3122 /* TODO */ 3123 } 3124 } 3125 3126 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3127 3128 if (nphy->hang_avoid) 3129 b43_nphy_stay_in_carrier_search(dev, false); 3130 3131 b43_mac_enable(dev); 3132} 3133 3134/* 3135 * Init N-PHY 3136 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N 3137 */ 3138int b43_phy_initn(struct b43_wldev *dev) 3139{ 3140 struct ssb_bus *bus = dev->dev->bus; 3141 struct b43_phy *phy = &dev->phy; 3142 struct b43_phy_n *nphy = phy->n; 3143 u8 tx_pwr_state; 3144 struct nphy_txgains target; 3145 u16 tmp; 3146 enum ieee80211_band tmp2; 3147 bool do_rssi_cal; 3148 3149 u16 clip[2]; 3150 bool do_cal = false; 3151 3152 if ((dev->phy.rev >= 3) && 3153 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) && 3154 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { 3155 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40); 3156 } 3157 nphy->deaf_count = 0; 3158 b43_nphy_tables_init(dev); 3159 nphy->crsminpwr_adjusted = false; 3160 nphy->noisevars_adjusted = false; 3161 3162 /* Clear all overrides */ 3163 if (dev->phy.rev >= 3) { 3164 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); 3165 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 3166 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); 3167 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); 3168 } else { 3169 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 3170 } 3171 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); 3172 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); 3173 if (dev->phy.rev < 6) { 3174 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); 3175 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); 3176 } 3177 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 3178 ~(B43_NPHY_RFSEQMODE_CAOVER | 3179 B43_NPHY_RFSEQMODE_TROVER)); 3180 if (dev->phy.rev >= 3) 3181 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); 3182 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); 3183 3184 if (dev->phy.rev <= 2) { 3185 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; 3186 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 3187 ~B43_NPHY_BPHY_CTL3_SCALE, 3188 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); 3189 } 3190 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); 3191 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); 3192 3193 if (bus->sprom.boardflags2_lo & 0x100 || 3194 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3195 bus->boardinfo.type == 0x8B)) 3196 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); 3197 else 3198 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); 3199 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); 3200 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); 3201 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); 3202 3203 b43_nphy_update_mimo_config(dev, nphy->preamble_override); 3204 b43_nphy_update_txrx_chain(dev); 3205 3206 if (phy->rev < 2) { 3207 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); 3208 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); 3209 } 3210 3211 tmp2 = b43_current_band(dev->wl); 3212 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) || 3213 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) { 3214 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); 3215 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, 3216 nphy->papd_epsilon_offset[0] << 7); 3217 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); 3218 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, 3219 nphy->papd_epsilon_offset[1] << 7); 3220 b43_nphy_int_pa_set_tx_dig_filters(dev); 3221 } else if (phy->rev >= 5) { 3222 b43_nphy_ext_pa_set_tx_dig_filters(dev); 3223 } 3224 3225 b43_nphy_workarounds(dev); 3226 3227 /* Reset CCA, in init code it differs a little from standard way */ 3228 b43_nphy_bmac_clock_fgc(dev, 1); 3229 tmp = b43_phy_read(dev, B43_NPHY_BBCFG); 3230 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); 3231 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); 3232 b43_nphy_bmac_clock_fgc(dev, 0); 3233 3234 b43_nphy_mac_phy_clock_set(dev, true); 3235 3236 b43_nphy_pa_override(dev, false); 3237 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 3238 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3239 b43_nphy_pa_override(dev, true); 3240 3241 b43_nphy_classifier(dev, 0, 0); 3242 b43_nphy_read_clip_detection(dev, clip); 3243 tx_pwr_state = nphy->txpwrctrl; 3244 /* TODO N PHY TX power control with argument 0 3245 (turning off power control) */ 3246 /* TODO Fix the TX Power Settings */ 3247 /* TODO N PHY TX Power Control Idle TSSI */ 3248 /* TODO N PHY TX Power Control Setup */ 3249 3250 if (phy->rev >= 3) { 3251 /* TODO */ 3252 } else { 3253 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, 3254 b43_ntab_tx_gain_rev0_1_2); 3255 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, 3256 b43_ntab_tx_gain_rev0_1_2); 3257 } 3258 3259 if (nphy->phyrxchain != 3) 3260 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); 3261 if (nphy->mphase_cal_phase_id > 0) 3262 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ 3263 3264 do_rssi_cal = false; 3265 if (phy->rev >= 3) { 3266 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3267 do_rssi_cal = 3268 b43_empty_chanspec(&nphy->rssical_chanspec_2G); 3269 else 3270 do_rssi_cal = 3271 b43_empty_chanspec(&nphy->rssical_chanspec_5G); 3272 3273 if (do_rssi_cal) 3274 b43_nphy_rssi_cal(dev); 3275 else 3276 b43_nphy_restore_rssi_cal(dev); 3277 } else { 3278 b43_nphy_rssi_cal(dev); 3279 } 3280 3281 if (!((nphy->measure_hold & 0x6) != 0)) { 3282 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3283 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_2G); 3284 else 3285 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_5G); 3286 3287 if (nphy->mute) 3288 do_cal = false; 3289 3290 if (do_cal) { 3291 target = b43_nphy_get_tx_gains(dev); 3292 3293 if (nphy->antsel_type == 2) 3294 b43_nphy_superswitch_init(dev, true); 3295 if (nphy->perical != 2) { 3296 b43_nphy_rssi_cal(dev); 3297 if (phy->rev >= 3) { 3298 nphy->cal_orig_pwr_idx[0] = 3299 nphy->txpwrindex[0].index_internal; 3300 nphy->cal_orig_pwr_idx[1] = 3301 nphy->txpwrindex[1].index_internal; 3302 /* TODO N PHY Pre Calibrate TX Gain */ 3303 target = b43_nphy_get_tx_gains(dev); 3304 } 3305 } 3306 } 3307 } 3308 3309 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) { 3310 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) 3311 b43_nphy_save_cal(dev); 3312 else if (nphy->mphase_cal_phase_id == 0) 3313 ;/* N PHY Periodic Calibration with argument 3 */ 3314 } else { 3315 b43_nphy_restore_cal(dev); 3316 } 3317 3318 b43_nphy_tx_pwr_ctrl_coef_setup(dev); 3319 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */ 3320 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); 3321 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); 3322 if (phy->rev >= 3 && phy->rev <= 6) 3323 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014); 3324 b43_nphy_tx_lp_fbw(dev); 3325 if (phy->rev >= 3) 3326 b43_nphy_spur_workaround(dev); 3327 3328 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n"); 3329 return 0; 3330} 3331 3332/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ 3333static void b43_nphy_channel_setup(struct b43_wldev *dev, 3334 const struct b43_phy_n_sfo_cfg *e, 3335 struct ieee80211_channel *new_channel) 3336{ 3337 struct b43_phy *phy = &dev->phy; 3338 struct b43_phy_n *nphy = dev->phy.n; 3339 3340 u16 old_band_5ghz; 3341 u32 tmp32; 3342 3343 old_band_5ghz = 3344 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ; 3345 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) { 3346 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR); 3347 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4); 3348 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000); 3349 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32); 3350 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); 3351 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) { 3352 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); 3353 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR); 3354 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4); 3355 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF); 3356 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32); 3357 } 3358 3359 b43_chantab_phy_upload(dev, e); 3360 3361 if (new_channel->hw_value == 14) { 3362 b43_nphy_classifier(dev, 2, 0); 3363 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); 3364 } else { 3365 b43_nphy_classifier(dev, 2, 2); 3366 if (new_channel->band == IEEE80211_BAND_2GHZ) 3367 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); 3368 } 3369 3370 if (nphy->txpwrctrl) 3371 b43_nphy_tx_power_fix(dev); 3372 3373 if (dev->phy.rev < 3) 3374 b43_nphy_adjust_lna_gain_table(dev); 3375 3376 b43_nphy_tx_lp_fbw(dev); 3377 3378 if (dev->phy.rev >= 3 && 0) { 3379 /* TODO */ 3380 } 3381 3382 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); 3383 3384 if (phy->rev >= 3) 3385 b43_nphy_spur_workaround(dev); 3386} 3387 3388/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ 3389static int b43_nphy_set_channel(struct b43_wldev *dev, 3390 struct ieee80211_channel *channel, 3391 enum nl80211_channel_type channel_type) 3392{ 3393 struct b43_phy *phy = &dev->phy; 3394 struct b43_phy_n *nphy = dev->phy.n; 3395 3396 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2; 3397 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3; 3398 3399 u8 tmp; 3400 3401 if (dev->phy.rev >= 3) { 3402 /* TODO */ 3403 tabent_r3 = NULL; 3404 if (!tabent_r3) 3405 return -ESRCH; 3406 } else { 3407 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, 3408 channel->hw_value); 3409 if (!tabent_r2) 3410 return -ESRCH; 3411 } 3412 3413 nphy->radio_chanspec.channel = channel->hw_value; 3414 3415 if (b43_channel_type_is_40mhz(phy->channel_type) != 3416 b43_channel_type_is_40mhz(channel_type)) 3417 ; /* TODO: BMAC BW Set (channel_type) */ 3418 3419 if (channel_type == NL80211_CHAN_HT40PLUS) 3420 b43_phy_set(dev, B43_NPHY_RXCTL, 3421 B43_NPHY_RXCTL_BSELU20); 3422 else if (channel_type == NL80211_CHAN_HT40MINUS) 3423 b43_phy_mask(dev, B43_NPHY_RXCTL, 3424 ~B43_NPHY_RXCTL_BSELU20); 3425 3426 if (dev->phy.rev >= 3) { 3427 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0; 3428 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); 3429 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */ 3430 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel); 3431 } else { 3432 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050; 3433 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); 3434 b43_radio_2055_setup(dev, tabent_r2); 3435 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel); 3436 } 3437 3438 return 0; 3439} 3440 3441static int b43_nphy_op_allocate(struct b43_wldev *dev) 3442{ 3443 struct b43_phy_n *nphy; 3444 3445 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); 3446 if (!nphy) 3447 return -ENOMEM; 3448 dev->phy.n = nphy; 3449 3450 return 0; 3451} 3452 3453static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) 3454{ 3455 struct b43_phy *phy = &dev->phy; 3456 struct b43_phy_n *nphy = phy->n; 3457 3458 memset(nphy, 0, sizeof(*nphy)); 3459 3460 //TODO init struct b43_phy_n 3461} 3462 3463static void b43_nphy_op_free(struct b43_wldev *dev) 3464{ 3465 struct b43_phy *phy = &dev->phy; 3466 struct b43_phy_n *nphy = phy->n; 3467 3468 kfree(nphy); 3469 phy->n = NULL; 3470} 3471 3472static int b43_nphy_op_init(struct b43_wldev *dev) 3473{ 3474 return b43_phy_initn(dev); 3475} 3476 3477static inline void check_phyreg(struct b43_wldev *dev, u16 offset) 3478{ 3479#if B43_DEBUG 3480 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { 3481 /* OFDM registers are onnly available on A/G-PHYs */ 3482 b43err(dev->wl, "Invalid OFDM PHY access at " 3483 "0x%04X on N-PHY\n", offset); 3484 dump_stack(); 3485 } 3486 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { 3487 /* Ext-G registers are only available on G-PHYs */ 3488 b43err(dev->wl, "Invalid EXT-G PHY access at " 3489 "0x%04X on N-PHY\n", offset); 3490 dump_stack(); 3491 } 3492#endif /* B43_DEBUG */ 3493} 3494 3495static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg) 3496{ 3497 check_phyreg(dev, reg); 3498 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); 3499 return b43_read16(dev, B43_MMIO_PHY_DATA); 3500} 3501 3502static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) 3503{ 3504 check_phyreg(dev, reg); 3505 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); 3506 b43_write16(dev, B43_MMIO_PHY_DATA, value); 3507} 3508 3509static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) 3510{ 3511 /* Register 1 is a 32-bit register. */ 3512 B43_WARN_ON(reg == 1); 3513 /* N-PHY needs 0x100 for read access */ 3514 reg |= 0x100; 3515 3516 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); 3517 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3518} 3519 3520static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) 3521{ 3522 /* Register 1 is a 32-bit register. */ 3523 B43_WARN_ON(reg == 1); 3524 3525 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); 3526 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); 3527} 3528 3529/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ 3530static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, 3531 bool blocked) 3532{ 3533 struct b43_phy_n *nphy = dev->phy.n; 3534 3535 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) 3536 b43err(dev->wl, "MAC not suspended\n"); 3537 3538 if (blocked) { 3539 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 3540 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 3541 if (dev->phy.rev >= 3) { 3542 b43_radio_mask(dev, 0x09, ~0x2); 3543 3544 b43_radio_write(dev, 0x204D, 0); 3545 b43_radio_write(dev, 0x2053, 0); 3546 b43_radio_write(dev, 0x2058, 0); 3547 b43_radio_write(dev, 0x205E, 0); 3548 b43_radio_mask(dev, 0x2062, ~0xF0); 3549 b43_radio_write(dev, 0x2064, 0); 3550 3551 b43_radio_write(dev, 0x304D, 0); 3552 b43_radio_write(dev, 0x3053, 0); 3553 b43_radio_write(dev, 0x3058, 0); 3554 b43_radio_write(dev, 0x305E, 0); 3555 b43_radio_mask(dev, 0x3062, ~0xF0); 3556 b43_radio_write(dev, 0x3064, 0); 3557 } 3558 } else { 3559 if (dev->phy.rev >= 3) { 3560 b43_radio_init2056(dev); 3561 b43_switch_channel(dev, dev->phy.channel); 3562 } else { 3563 b43_radio_init2055(dev); 3564 } 3565 } 3566} 3567 3568static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) 3569{ 3570 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 3571 on ? 0 : 0x7FFF); 3572} 3573 3574static int b43_nphy_op_switch_channel(struct b43_wldev *dev, 3575 unsigned int new_channel) 3576{ 3577 struct ieee80211_channel *channel = dev->wl->hw->conf.channel; 3578 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type; 3579 3580 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 3581 if ((new_channel < 1) || (new_channel > 14)) 3582 return -EINVAL; 3583 } else { 3584 if (new_channel > 200) 3585 return -EINVAL; 3586 } 3587 3588 return b43_nphy_set_channel(dev, channel, channel_type); 3589} 3590 3591static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) 3592{ 3593 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3594 return 1; 3595 return 36; 3596} 3597 3598const struct b43_phy_operations b43_phyops_n = { 3599 .allocate = b43_nphy_op_allocate, 3600 .free = b43_nphy_op_free, 3601 .prepare_structs = b43_nphy_op_prepare_structs, 3602 .init = b43_nphy_op_init, 3603 .phy_read = b43_nphy_op_read, 3604 .phy_write = b43_nphy_op_write, 3605 .radio_read = b43_nphy_op_radio_read, 3606 .radio_write = b43_nphy_op_radio_write, 3607 .software_rfkill = b43_nphy_op_software_rfkill, 3608 .switch_analog = b43_nphy_op_switch_analog, 3609 .switch_channel = b43_nphy_op_switch_channel, 3610 .get_default_chan = b43_nphy_op_get_default_chan, 3611 .recalc_txpower = b43_nphy_op_recalc_txpower, 3612 .adjust_txpower = b43_nphy_op_adjust_txpower, 3613}; 3614