phy_n.c revision 78159788e1d0909ffa6beb714dcca7f3aa4574a2
1/* 2 3 Broadcom B43 wireless driver 4 IEEE 802.11n PHY support 5 6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING. If not, write to 20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 21 Boston, MA 02110-1301, USA. 22 23*/ 24 25#include <linux/delay.h> 26#include <linux/slab.h> 27#include <linux/types.h> 28 29#include "b43.h" 30#include "phy_n.h" 31#include "tables_nphy.h" 32#include "main.h" 33 34struct nphy_txgains { 35 u16 txgm[2]; 36 u16 pga[2]; 37 u16 pad[2]; 38 u16 ipa[2]; 39}; 40 41struct nphy_iqcal_params { 42 u16 txgm; 43 u16 pga; 44 u16 pad; 45 u16 ipa; 46 u16 cal_gain; 47 u16 ncorr[5]; 48}; 49 50struct nphy_iq_est { 51 s32 iq0_prod; 52 u32 i0_pwr; 53 u32 q0_pwr; 54 s32 iq1_prod; 55 u32 i1_pwr; 56 u32 q1_pwr; 57}; 58 59enum b43_nphy_rf_sequence { 60 B43_RFSEQ_RX2TX, 61 B43_RFSEQ_TX2RX, 62 B43_RFSEQ_RESET2RX, 63 B43_RFSEQ_UPDATE_GAINH, 64 B43_RFSEQ_UPDATE_GAINL, 65 B43_RFSEQ_UPDATE_GAINU, 66}; 67 68static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, 69 u8 *events, u8 *delays, u8 length); 70static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 71 enum b43_nphy_rf_sequence seq); 72static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 73 u16 value, u8 core, bool off); 74static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, 75 u16 value, u8 core); 76 77static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec) 78{ 79 return !chanspec->channel && !chanspec->sideband && 80 !chanspec->b_width && !chanspec->b_freq; 81} 82 83static inline bool b43_eq_chanspecs(struct b43_chanspec *chanspec1, 84 struct b43_chanspec *chanspec2) 85{ 86 return (chanspec1->channel == chanspec2->channel && 87 chanspec1->sideband == chanspec2->sideband && 88 chanspec1->b_width == chanspec2->b_width && 89 chanspec1->b_freq == chanspec2->b_freq); 90} 91 92void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) 93{//TODO 94} 95 96static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev) 97{//TODO 98} 99 100static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, 101 bool ignore_tssi) 102{//TODO 103 return B43_TXPWR_RES_DONE; 104} 105 106static void b43_chantab_radio_upload(struct b43_wldev *dev, 107 const struct b43_nphy_channeltab_entry_rev2 *e) 108{ 109 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); 110 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); 111 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); 112 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); 113 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 114 115 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); 116 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); 117 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); 118 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); 119 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 120 121 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); 122 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); 123 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); 124 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); 125 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 126 127 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); 128 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); 129 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); 130 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); 131 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 132 133 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); 134 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); 135 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); 136 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); 137 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 138 139 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); 140 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); 141} 142 143static void b43_chantab_phy_upload(struct b43_wldev *dev, 144 const struct b43_phy_n_sfo_cfg *e) 145{ 146 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); 147 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); 148 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); 149 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); 150 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); 151 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); 152} 153 154static void b43_nphy_tx_power_fix(struct b43_wldev *dev) 155{ 156 //TODO 157} 158 159 160/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ 161static void b43_radio_2055_setup(struct b43_wldev *dev, 162 const struct b43_nphy_channeltab_entry_rev2 *e) 163{ 164 B43_WARN_ON(dev->phy.rev >= 3); 165 166 b43_chantab_radio_upload(dev, e); 167 udelay(50); 168 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); 169 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); 170 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 171 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); 172 udelay(300); 173} 174 175static void b43_radio_init2055_pre(struct b43_wldev *dev) 176{ 177 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 178 ~B43_NPHY_RFCTL_CMD_PORFORCE); 179 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 180 B43_NPHY_RFCTL_CMD_CHIP0PU | 181 B43_NPHY_RFCTL_CMD_OEPORFORCE); 182 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 183 B43_NPHY_RFCTL_CMD_PORFORCE); 184} 185 186static void b43_radio_init2055_post(struct b43_wldev *dev) 187{ 188 struct b43_phy_n *nphy = dev->phy.n; 189 struct ssb_sprom *sprom = &(dev->dev->bus->sprom); 190 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo); 191 int i; 192 u16 val; 193 bool workaround = false; 194 195 if (sprom->revision < 4) 196 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM || 197 binfo->type != 0x46D || 198 binfo->rev < 0x41); 199 else 200 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0); 201 202 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); 203 if (workaround) { 204 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); 205 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); 206 } 207 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); 208 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); 209 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); 210 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); 211 b43_radio_set(dev, B2055_CAL_MISC, 0x1); 212 msleep(1); 213 b43_radio_set(dev, B2055_CAL_MISC, 0x40); 214 for (i = 0; i < 200; i++) { 215 val = b43_radio_read(dev, B2055_CAL_COUT2); 216 if (val & 0x80) { 217 i = 0; 218 break; 219 } 220 udelay(10); 221 } 222 if (i) 223 b43err(dev->wl, "radio post init timeout\n"); 224 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); 225 b43_switch_channel(dev, dev->phy.channel); 226 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); 227 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); 228 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); 229 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); 230 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); 231 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); 232 if (!nphy->gain_boost) { 233 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); 234 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); 235 } else { 236 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); 237 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); 238 } 239 udelay(2); 240} 241 242/* 243 * Initialize a Broadcom 2055 N-radio 244 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init 245 */ 246static void b43_radio_init2055(struct b43_wldev *dev) 247{ 248 b43_radio_init2055_pre(dev); 249 if (b43_status(dev) < B43_STAT_INITIALIZED) 250 b2055_upload_inittab(dev, 0, 1); 251 else 252 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0); 253 b43_radio_init2055_post(dev); 254} 255 256/* 257 * Initialize a Broadcom 2056 N-radio 258 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init 259 */ 260static void b43_radio_init2056(struct b43_wldev *dev) 261{ 262 /* TODO */ 263} 264 265 266/* 267 * Upload the N-PHY tables. 268 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables 269 */ 270static void b43_nphy_tables_init(struct b43_wldev *dev) 271{ 272 if (dev->phy.rev < 3) 273 b43_nphy_rev0_1_2_tables_init(dev); 274 else 275 b43_nphy_rev3plus_tables_init(dev); 276} 277 278/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ 279static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) 280{ 281 struct b43_phy_n *nphy = dev->phy.n; 282 enum ieee80211_band band; 283 u16 tmp; 284 285 if (!enable) { 286 nphy->rfctrl_intc1_save = b43_phy_read(dev, 287 B43_NPHY_RFCTL_INTC1); 288 nphy->rfctrl_intc2_save = b43_phy_read(dev, 289 B43_NPHY_RFCTL_INTC2); 290 band = b43_current_band(dev->wl); 291 if (dev->phy.rev >= 3) { 292 if (band == IEEE80211_BAND_5GHZ) 293 tmp = 0x600; 294 else 295 tmp = 0x480; 296 } else { 297 if (band == IEEE80211_BAND_5GHZ) 298 tmp = 0x180; 299 else 300 tmp = 0x120; 301 } 302 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 303 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 304 } else { 305 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 306 nphy->rfctrl_intc1_save); 307 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 308 nphy->rfctrl_intc2_save); 309 } 310} 311 312/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ 313static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) 314{ 315 struct b43_phy_n *nphy = dev->phy.n; 316 u16 tmp; 317 enum ieee80211_band band = b43_current_band(dev->wl); 318 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) || 319 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ); 320 321 if (dev->phy.rev >= 3) { 322 if (ipa) { 323 tmp = 4; 324 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, 325 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); 326 } 327 328 tmp = 1; 329 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, 330 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); 331 } 332} 333 334/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ 335static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force) 336{ 337 u32 tmslow; 338 339 if (dev->phy.type != B43_PHYTYPE_N) 340 return; 341 342 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 343 if (force) 344 tmslow |= SSB_TMSLOW_FGC; 345 else 346 tmslow &= ~SSB_TMSLOW_FGC; 347 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 348} 349 350/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ 351static void b43_nphy_reset_cca(struct b43_wldev *dev) 352{ 353 u16 bbcfg; 354 355 b43_nphy_bmac_clock_fgc(dev, 1); 356 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); 357 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); 358 udelay(1); 359 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); 360 b43_nphy_bmac_clock_fgc(dev, 0); 361 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 362} 363 364/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ 365static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) 366{ 367 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); 368 369 mimocfg |= B43_NPHY_MIMOCFG_AUTO; 370 if (preamble == 1) 371 mimocfg |= B43_NPHY_MIMOCFG_GFMIX; 372 else 373 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; 374 375 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); 376} 377 378/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ 379static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) 380{ 381 struct b43_phy_n *nphy = dev->phy.n; 382 383 bool override = false; 384 u16 chain = 0x33; 385 386 if (nphy->txrx_chain == 0) { 387 chain = 0x11; 388 override = true; 389 } else if (nphy->txrx_chain == 1) { 390 chain = 0x22; 391 override = true; 392 } 393 394 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 395 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), 396 chain); 397 398 if (override) 399 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 400 B43_NPHY_RFSEQMODE_CAOVER); 401 else 402 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 403 ~B43_NPHY_RFSEQMODE_CAOVER); 404} 405 406/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ 407static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, 408 u16 samps, u8 time, bool wait) 409{ 410 int i; 411 u16 tmp; 412 413 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); 414 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); 415 if (wait) 416 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); 417 else 418 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); 419 420 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); 421 422 for (i = 1000; i; i--) { 423 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); 424 if (!(tmp & B43_NPHY_IQEST_CMD_START)) { 425 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | 426 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); 427 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | 428 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); 429 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | 430 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); 431 432 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | 433 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); 434 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | 435 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); 436 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | 437 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); 438 return; 439 } 440 udelay(10); 441 } 442 memset(est, 0, sizeof(*est)); 443} 444 445/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ 446static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, 447 struct b43_phy_n_iq_comp *pcomp) 448{ 449 if (write) { 450 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); 451 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); 452 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); 453 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); 454 } else { 455 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); 456 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); 457 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); 458 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); 459 } 460} 461 462/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ 463static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) 464{ 465 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 466 467 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); 468 if (core == 0) { 469 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); 470 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 471 } else { 472 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 473 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 474 } 475 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); 476 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); 477 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); 478 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); 479 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); 480 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); 481 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 482 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 483} 484 485/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ 486static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) 487{ 488 u8 rxval, txval; 489 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 490 491 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 492 if (core == 0) { 493 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 494 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 495 } else { 496 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 497 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 498 } 499 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 500 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 501 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); 502 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); 503 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); 504 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); 505 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 506 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 507 508 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 509 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 510 511 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 512 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 513 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 514 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 515 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); 516 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 517 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); 518 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, 519 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); 520 521 if (core == 0) { 522 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); 523 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); 524 } else { 525 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); 526 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); 527 } 528 529 b43_nphy_rf_control_intc_override(dev, 2, 0, 3); 530 b43_nphy_rf_control_override(dev, 8, 0, 3, false); 531 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 532 533 if (core == 0) { 534 rxval = 1; 535 txval = 8; 536 } else { 537 rxval = 4; 538 txval = 2; 539 } 540 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1)); 541 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core)); 542} 543 544/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ 545static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) 546{ 547 int i; 548 s32 iq; 549 u32 ii; 550 u32 qq; 551 int iq_nbits, qq_nbits; 552 int arsh, brsh; 553 u16 tmp, a, b; 554 555 struct nphy_iq_est est; 556 struct b43_phy_n_iq_comp old; 557 struct b43_phy_n_iq_comp new = { }; 558 bool error = false; 559 560 if (mask == 0) 561 return; 562 563 b43_nphy_rx_iq_coeffs(dev, false, &old); 564 b43_nphy_rx_iq_coeffs(dev, true, &new); 565 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); 566 new = old; 567 568 for (i = 0; i < 2; i++) { 569 if (i == 0 && (mask & 1)) { 570 iq = est.iq0_prod; 571 ii = est.i0_pwr; 572 qq = est.q0_pwr; 573 } else if (i == 1 && (mask & 2)) { 574 iq = est.iq1_prod; 575 ii = est.i1_pwr; 576 qq = est.q1_pwr; 577 } else { 578 B43_WARN_ON(1); 579 continue; 580 } 581 582 if (ii + qq < 2) { 583 error = true; 584 break; 585 } 586 587 iq_nbits = fls(abs(iq)); 588 qq_nbits = fls(qq); 589 590 arsh = iq_nbits - 20; 591 if (arsh >= 0) { 592 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); 593 tmp = ii >> arsh; 594 } else { 595 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); 596 tmp = ii << -arsh; 597 } 598 if (tmp == 0) { 599 error = true; 600 break; 601 } 602 a /= tmp; 603 604 brsh = qq_nbits - 11; 605 if (brsh >= 0) { 606 b = (qq << (31 - qq_nbits)); 607 tmp = ii >> brsh; 608 } else { 609 b = (qq << (31 - qq_nbits)); 610 tmp = ii << -brsh; 611 } 612 if (tmp == 0) { 613 error = true; 614 break; 615 } 616 b = int_sqrt(b / tmp - a * a) - (1 << 10); 617 618 if (i == 0 && (mask & 0x1)) { 619 if (dev->phy.rev >= 3) { 620 new.a0 = a & 0x3FF; 621 new.b0 = b & 0x3FF; 622 } else { 623 new.a0 = b & 0x3FF; 624 new.b0 = a & 0x3FF; 625 } 626 } else if (i == 1 && (mask & 0x2)) { 627 if (dev->phy.rev >= 3) { 628 new.a1 = a & 0x3FF; 629 new.b1 = b & 0x3FF; 630 } else { 631 new.a1 = b & 0x3FF; 632 new.b1 = a & 0x3FF; 633 } 634 } 635 } 636 637 if (error) 638 new = old; 639 640 b43_nphy_rx_iq_coeffs(dev, true, &new); 641} 642 643/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ 644static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) 645{ 646 u16 array[4]; 647 int i; 648 649 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50); 650 for (i = 0; i < 4; i++) 651 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); 652 653 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); 654 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); 655 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); 656 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); 657} 658 659/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 660static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st) 661{ 662 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); 663 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); 664} 665 666/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 667static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) 668{ 669 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); 670 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); 671} 672 673/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ 674static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) 675{ 676 if (dev->phy.rev >= 3) { 677 if (!init) 678 return; 679 if (0 /* FIXME */) { 680 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); 681 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); 682 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); 683 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); 684 } 685 } else { 686 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); 687 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); 688 689 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00, 690 0xFC00); 691 b43_write32(dev, B43_MMIO_MACCTL, 692 b43_read32(dev, B43_MMIO_MACCTL) & 693 ~B43_MACCTL_GPOUTSMSK); 694 b43_write16(dev, B43_MMIO_GPIO_MASK, 695 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00); 696 b43_write16(dev, B43_MMIO_GPIO_CONTROL, 697 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00); 698 699 if (init) { 700 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 701 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 702 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 703 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 704 } 705 } 706} 707 708/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ 709static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) 710{ 711 u16 tmp; 712 713 if (dev->dev->id.revision == 16) 714 b43_mac_suspend(dev); 715 716 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); 717 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | 718 B43_NPHY_CLASSCTL_WAITEDEN); 719 tmp &= ~mask; 720 tmp |= (val & mask); 721 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); 722 723 if (dev->dev->id.revision == 16) 724 b43_mac_enable(dev); 725 726 return tmp; 727} 728 729/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ 730static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) 731{ 732 struct b43_phy *phy = &dev->phy; 733 struct b43_phy_n *nphy = phy->n; 734 735 if (enable) { 736 u16 clip[] = { 0xFFFF, 0xFFFF }; 737 if (nphy->deaf_count++ == 0) { 738 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); 739 b43_nphy_classifier(dev, 0x7, 0); 740 b43_nphy_read_clip_detection(dev, nphy->clip_state); 741 b43_nphy_write_clip_detection(dev, clip); 742 } 743 b43_nphy_reset_cca(dev); 744 } else { 745 if (--nphy->deaf_count == 0) { 746 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); 747 b43_nphy_write_clip_detection(dev, nphy->clip_state); 748 } 749 } 750} 751 752/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ 753static void b43_nphy_stop_playback(struct b43_wldev *dev) 754{ 755 struct b43_phy_n *nphy = dev->phy.n; 756 u16 tmp; 757 758 if (nphy->hang_avoid) 759 b43_nphy_stay_in_carrier_search(dev, 1); 760 761 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); 762 if (tmp & 0x1) 763 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); 764 else if (tmp & 0x2) 765 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 766 767 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); 768 769 if (nphy->bb_mult_save & 0x80000000) { 770 tmp = nphy->bb_mult_save & 0xFFFF; 771 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 772 nphy->bb_mult_save = 0; 773 } 774 775 if (nphy->hang_avoid) 776 b43_nphy_stay_in_carrier_search(dev, 0); 777} 778 779/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ 780static void b43_nphy_spur_workaround(struct b43_wldev *dev) 781{ 782 struct b43_phy_n *nphy = dev->phy.n; 783 784 u8 channel = nphy->radio_chanspec.channel; 785 int tone[2] = { 57, 58 }; 786 u32 noise[2] = { 0x3FF, 0x3FF }; 787 788 B43_WARN_ON(dev->phy.rev < 3); 789 790 if (nphy->hang_avoid) 791 b43_nphy_stay_in_carrier_search(dev, 1); 792 793 if (nphy->gband_spurwar_en) { 794 /* TODO: N PHY Adjust Analog Pfbw (7) */ 795 if (channel == 11 && dev->phy.is_40mhz) 796 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ 797 else 798 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 799 /* TODO: N PHY Adjust CRS Min Power (0x1E) */ 800 } 801 802 if (nphy->aband_spurwar_en) { 803 if (channel == 54) { 804 tone[0] = 0x20; 805 noise[0] = 0x25F; 806 } else if (channel == 38 || channel == 102 || channel == 118) { 807 if (0 /* FIXME */) { 808 tone[0] = 0x20; 809 noise[0] = 0x21F; 810 } else { 811 tone[0] = 0; 812 noise[0] = 0; 813 } 814 } else if (channel == 134) { 815 tone[0] = 0x20; 816 noise[0] = 0x21F; 817 } else if (channel == 151) { 818 tone[0] = 0x10; 819 noise[0] = 0x23F; 820 } else if (channel == 153 || channel == 161) { 821 tone[0] = 0x30; 822 noise[0] = 0x23F; 823 } else { 824 tone[0] = 0; 825 noise[0] = 0; 826 } 827 828 if (!tone[0] && !noise[0]) 829 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ 830 else 831 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 832 } 833 834 if (nphy->hang_avoid) 835 b43_nphy_stay_in_carrier_search(dev, 0); 836} 837 838/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ 839static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) 840{ 841 struct b43_phy_n *nphy = dev->phy.n; 842 843 u8 i; 844 s16 tmp; 845 u16 data[4]; 846 s16 gain[2]; 847 u16 minmax[2]; 848 u16 lna_gain[4] = { -2, 10, 19, 25 }; 849 850 if (nphy->hang_avoid) 851 b43_nphy_stay_in_carrier_search(dev, 1); 852 853 if (nphy->gain_boost) { 854 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 855 gain[0] = 6; 856 gain[1] = 6; 857 } else { 858 tmp = 40370 - 315 * nphy->radio_chanspec.channel; 859 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); 860 tmp = 23242 - 224 * nphy->radio_chanspec.channel; 861 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); 862 } 863 } else { 864 gain[0] = 0; 865 gain[1] = 0; 866 } 867 868 for (i = 0; i < 2; i++) { 869 if (nphy->elna_gain_config) { 870 data[0] = 19 + gain[i]; 871 data[1] = 25 + gain[i]; 872 data[2] = 25 + gain[i]; 873 data[3] = 25 + gain[i]; 874 } else { 875 data[0] = lna_gain[0] + gain[i]; 876 data[1] = lna_gain[1] + gain[i]; 877 data[2] = lna_gain[2] + gain[i]; 878 data[3] = lna_gain[3] + gain[i]; 879 } 880 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data); 881 882 minmax[i] = 23 + gain[i]; 883 } 884 885 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, 886 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT); 887 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, 888 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT); 889 890 if (nphy->hang_avoid) 891 b43_nphy_stay_in_carrier_search(dev, 0); 892} 893 894/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ 895static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) 896{ 897 struct b43_phy_n *nphy = dev->phy.n; 898 u8 i, j; 899 u8 code; 900 901 /* TODO: for PHY >= 3 902 s8 *lna1_gain, *lna2_gain; 903 u8 *gain_db, *gain_bits; 904 u16 *rfseq_init; 905 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; 906 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; 907 */ 908 909 u8 rfseq_events[3] = { 6, 8, 7 }; 910 u8 rfseq_delays[3] = { 10, 30, 1 }; 911 912 if (dev->phy.rev >= 3) { 913 /* TODO */ 914 } else { 915 /* Set Clip 2 detect */ 916 b43_phy_set(dev, B43_NPHY_C1_CGAINI, 917 B43_NPHY_C1_CGAINI_CL2DETECT); 918 b43_phy_set(dev, B43_NPHY_C2_CGAINI, 919 B43_NPHY_C2_CGAINI_CL2DETECT); 920 921 /* Set narrowband clip threshold */ 922 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); 923 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); 924 925 if (!dev->phy.is_40mhz) { 926 /* Set dwell lengths */ 927 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); 928 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); 929 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); 930 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); 931 } 932 933 /* Set wideband clip 2 threshold */ 934 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 935 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 936 21); 937 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, 938 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 939 21); 940 941 if (!dev->phy.is_40mhz) { 942 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, 943 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); 944 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, 945 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); 946 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, 947 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); 948 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, 949 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); 950 } 951 952 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); 953 954 if (nphy->gain_boost) { 955 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && 956 dev->phy.is_40mhz) 957 code = 4; 958 else 959 code = 5; 960 } else { 961 code = dev->phy.is_40mhz ? 6 : 7; 962 } 963 964 /* Set HPVGA2 index */ 965 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, 966 ~B43_NPHY_C1_INITGAIN_HPVGA2, 967 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); 968 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, 969 ~B43_NPHY_C2_INITGAIN_HPVGA2, 970 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); 971 972 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 973 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 974 (code << 8 | 0x7C)); 975 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 976 (code << 8 | 0x7C)); 977 978 b43_nphy_adjust_lna_gain_table(dev); 979 980 if (nphy->elna_gain_config) { 981 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); 982 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 983 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 984 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 985 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 986 987 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); 988 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 989 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 990 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 991 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 992 993 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 994 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 995 (code << 8 | 0x74)); 996 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 997 (code << 8 | 0x74)); 998 } 999 1000 if (dev->phy.rev == 2) { 1001 for (i = 0; i < 4; i++) { 1002 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1003 (0x0400 * i) + 0x0020); 1004 for (j = 0; j < 21; j++) 1005 b43_phy_write(dev, 1006 B43_NPHY_TABLE_DATALO, 3 * j); 1007 } 1008 1009 b43_nphy_set_rf_sequence(dev, 5, 1010 rfseq_events, rfseq_delays, 3); 1011 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, 1012 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, 1013 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); 1014 1015 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 1016 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 1017 0xFF80, 4); 1018 } 1019 } 1020} 1021 1022/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ 1023static void b43_nphy_workarounds(struct b43_wldev *dev) 1024{ 1025 struct ssb_bus *bus = dev->dev->bus; 1026 struct b43_phy *phy = &dev->phy; 1027 struct b43_phy_n *nphy = phy->n; 1028 1029 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; 1030 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; 1031 1032 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; 1033 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; 1034 1035 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 1036 b43_nphy_classifier(dev, 1, 0); 1037 else 1038 b43_nphy_classifier(dev, 1, 1); 1039 1040 if (nphy->hang_avoid) 1041 b43_nphy_stay_in_carrier_search(dev, 1); 1042 1043 b43_phy_set(dev, B43_NPHY_IQFLIP, 1044 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); 1045 1046 if (dev->phy.rev >= 3) { 1047 /* TODO */ 1048 } else { 1049 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && 1050 nphy->band5g_pwrgain) { 1051 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); 1052 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); 1053 } else { 1054 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); 1055 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); 1056 } 1057 1058 /* TODO: convert to b43_ntab_write? */ 1059 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000); 1060 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); 1061 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010); 1062 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); 1063 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002); 1064 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); 1065 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012); 1066 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); 1067 1068 if (dev->phy.rev < 2) { 1069 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008); 1070 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); 1071 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018); 1072 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); 1073 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007); 1074 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); 1075 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017); 1076 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); 1077 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006); 1078 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); 1079 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016); 1080 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); 1081 } 1082 1083 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 1084 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 1085 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 1086 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 1087 1088 if (bus->sprom.boardflags2_lo & 0x100 && 1089 bus->boardinfo.type == 0x8B) { 1090 delays1[0] = 0x1; 1091 delays1[5] = 0x14; 1092 } 1093 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); 1094 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); 1095 1096 b43_nphy_gain_ctrl_workarounds(dev); 1097 1098 if (dev->phy.rev < 2) { 1099 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) 1100 b43_hf_write(dev, b43_hf_read(dev) | 1101 B43_HF_MLADVW); 1102 } else if (dev->phy.rev == 2) { 1103 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); 1104 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); 1105 } 1106 1107 if (dev->phy.rev < 2) 1108 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, 1109 ~B43_NPHY_SCRAM_SIGCTL_SCM); 1110 1111 /* Set phase track alpha and beta */ 1112 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); 1113 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); 1114 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); 1115 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); 1116 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); 1117 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); 1118 1119 b43_phy_mask(dev, B43_NPHY_PIL_DW1, 1120 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); 1121 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); 1122 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); 1123 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); 1124 1125 if (dev->phy.rev == 2) 1126 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 1127 B43_NPHY_FINERX2_CGC_DECGC); 1128 } 1129 1130 if (nphy->hang_avoid) 1131 b43_nphy_stay_in_carrier_search(dev, 0); 1132} 1133 1134/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ 1135static int b43_nphy_load_samples(struct b43_wldev *dev, 1136 struct b43_c32 *samples, u16 len) { 1137 struct b43_phy_n *nphy = dev->phy.n; 1138 u16 i; 1139 u32 *data; 1140 1141 data = kzalloc(len * sizeof(u32), GFP_KERNEL); 1142 if (!data) { 1143 b43err(dev->wl, "allocation for samples loading failed\n"); 1144 return -ENOMEM; 1145 } 1146 if (nphy->hang_avoid) 1147 b43_nphy_stay_in_carrier_search(dev, 1); 1148 1149 for (i = 0; i < len; i++) { 1150 data[i] = (samples[i].i & 0x3FF << 10); 1151 data[i] |= samples[i].q & 0x3FF; 1152 } 1153 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); 1154 1155 kfree(data); 1156 if (nphy->hang_avoid) 1157 b43_nphy_stay_in_carrier_search(dev, 0); 1158 return 0; 1159} 1160 1161/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ 1162static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, 1163 bool test) 1164{ 1165 int i; 1166 u16 bw, len, rot, angle; 1167 struct b43_c32 *samples; 1168 1169 1170 bw = (dev->phy.is_40mhz) ? 40 : 20; 1171 len = bw << 3; 1172 1173 if (test) { 1174 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) 1175 bw = 82; 1176 else 1177 bw = 80; 1178 1179 if (dev->phy.is_40mhz) 1180 bw <<= 1; 1181 1182 len = bw << 1; 1183 } 1184 1185 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL); 1186 if (!samples) { 1187 b43err(dev->wl, "allocation for samples generation failed\n"); 1188 return 0; 1189 } 1190 rot = (((freq * 36) / bw) << 16) / 100; 1191 angle = 0; 1192 1193 for (i = 0; i < len; i++) { 1194 samples[i] = b43_cordic(angle); 1195 angle += rot; 1196 samples[i].q = CORDIC_CONVERT(samples[i].q * max); 1197 samples[i].i = CORDIC_CONVERT(samples[i].i * max); 1198 } 1199 1200 i = b43_nphy_load_samples(dev, samples, len); 1201 kfree(samples); 1202 return (i < 0) ? 0 : len; 1203} 1204 1205/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ 1206static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, 1207 u16 wait, bool iqmode, bool dac_test) 1208{ 1209 struct b43_phy_n *nphy = dev->phy.n; 1210 int i; 1211 u16 seq_mode; 1212 u32 tmp; 1213 1214 if (nphy->hang_avoid) 1215 b43_nphy_stay_in_carrier_search(dev, true); 1216 1217 if ((nphy->bb_mult_save & 0x80000000) == 0) { 1218 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); 1219 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; 1220 } 1221 1222 if (!dev->phy.is_40mhz) 1223 tmp = 0x6464; 1224 else 1225 tmp = 0x4747; 1226 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 1227 1228 if (nphy->hang_avoid) 1229 b43_nphy_stay_in_carrier_search(dev, false); 1230 1231 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); 1232 1233 if (loops != 0xFFFF) 1234 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); 1235 else 1236 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); 1237 1238 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); 1239 1240 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 1241 1242 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); 1243 if (iqmode) { 1244 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 1245 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); 1246 } else { 1247 if (dac_test) 1248 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5); 1249 else 1250 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1); 1251 } 1252 for (i = 0; i < 100; i++) { 1253 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) { 1254 i = 0; 1255 break; 1256 } 1257 udelay(10); 1258 } 1259 if (i) 1260 b43err(dev->wl, "run samples timeout\n"); 1261 1262 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 1263} 1264 1265/* 1266 * Transmits a known value for LO calibration 1267 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone 1268 */ 1269static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, 1270 bool iqmode, bool dac_test) 1271{ 1272 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); 1273 if (samp == 0) 1274 return -1; 1275 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test); 1276 return 0; 1277} 1278 1279/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ 1280static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) 1281{ 1282 struct b43_phy_n *nphy = dev->phy.n; 1283 int i, j; 1284 u32 tmp; 1285 u32 cur_real, cur_imag, real_part, imag_part; 1286 1287 u16 buffer[7]; 1288 1289 if (nphy->hang_avoid) 1290 b43_nphy_stay_in_carrier_search(dev, true); 1291 1292 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 1293 1294 for (i = 0; i < 2; i++) { 1295 tmp = ((buffer[i * 2] & 0x3FF) << 10) | 1296 (buffer[i * 2 + 1] & 0x3FF); 1297 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1298 (((i + 26) << 10) | 320)); 1299 for (j = 0; j < 128; j++) { 1300 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 1301 ((tmp >> 16) & 0xFFFF)); 1302 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1303 (tmp & 0xFFFF)); 1304 } 1305 } 1306 1307 for (i = 0; i < 2; i++) { 1308 tmp = buffer[5 + i]; 1309 real_part = (tmp >> 8) & 0xFF; 1310 imag_part = (tmp & 0xFF); 1311 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1312 (((i + 26) << 10) | 448)); 1313 1314 if (dev->phy.rev >= 3) { 1315 cur_real = real_part; 1316 cur_imag = imag_part; 1317 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); 1318 } 1319 1320 for (j = 0; j < 128; j++) { 1321 if (dev->phy.rev < 3) { 1322 cur_real = (real_part * loscale[j] + 128) >> 8; 1323 cur_imag = (imag_part * loscale[j] + 128) >> 8; 1324 tmp = ((cur_real & 0xFF) << 8) | 1325 (cur_imag & 0xFF); 1326 } 1327 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 1328 ((tmp >> 16) & 0xFFFF)); 1329 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1330 (tmp & 0xFFFF)); 1331 } 1332 } 1333 1334 if (dev->phy.rev >= 3) { 1335 b43_shm_write16(dev, B43_SHM_SHARED, 1336 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); 1337 b43_shm_write16(dev, B43_SHM_SHARED, 1338 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); 1339 } 1340 1341 if (nphy->hang_avoid) 1342 b43_nphy_stay_in_carrier_search(dev, false); 1343} 1344 1345/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ 1346static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, 1347 u8 *events, u8 *delays, u8 length) 1348{ 1349 struct b43_phy_n *nphy = dev->phy.n; 1350 u8 i; 1351 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; 1352 u16 offset1 = cmd << 4; 1353 u16 offset2 = offset1 + 0x80; 1354 1355 if (nphy->hang_avoid) 1356 b43_nphy_stay_in_carrier_search(dev, true); 1357 1358 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); 1359 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); 1360 1361 for (i = length; i < 16; i++) { 1362 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); 1363 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); 1364 } 1365 1366 if (nphy->hang_avoid) 1367 b43_nphy_stay_in_carrier_search(dev, false); 1368} 1369 1370/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ 1371static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 1372 enum b43_nphy_rf_sequence seq) 1373{ 1374 static const u16 trigger[] = { 1375 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, 1376 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, 1377 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, 1378 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, 1379 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, 1380 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, 1381 }; 1382 int i; 1383 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 1384 1385 B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); 1386 1387 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 1388 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); 1389 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); 1390 for (i = 0; i < 200; i++) { 1391 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) 1392 goto ok; 1393 msleep(1); 1394 } 1395 b43err(dev->wl, "RF sequence status timeout\n"); 1396ok: 1397 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 1398} 1399 1400/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ 1401static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 1402 u16 value, u8 core, bool off) 1403{ 1404 int i; 1405 u8 index = fls(field); 1406 u8 addr, en_addr, val_addr; 1407 /* we expect only one bit set */ 1408 B43_WARN_ON(field & (~(1 << (index - 1)))); 1409 1410 if (dev->phy.rev >= 3) { 1411 const struct nphy_rf_control_override_rev3 *rf_ctrl; 1412 for (i = 0; i < 2; i++) { 1413 if (index == 0 || index == 16) { 1414 b43err(dev->wl, 1415 "Unsupported RF Ctrl Override call\n"); 1416 return; 1417 } 1418 1419 rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; 1420 en_addr = B43_PHY_N((i == 0) ? 1421 rf_ctrl->en_addr0 : rf_ctrl->en_addr1); 1422 val_addr = B43_PHY_N((i == 0) ? 1423 rf_ctrl->val_addr0 : rf_ctrl->val_addr1); 1424 1425 if (off) { 1426 b43_phy_mask(dev, en_addr, ~(field)); 1427 b43_phy_mask(dev, val_addr, 1428 ~(rf_ctrl->val_mask)); 1429 } else { 1430 if (core == 0 || ((1 << core) & i) != 0) { 1431 b43_phy_set(dev, en_addr, field); 1432 b43_phy_maskset(dev, val_addr, 1433 ~(rf_ctrl->val_mask), 1434 (value << rf_ctrl->val_shift)); 1435 } 1436 } 1437 } 1438 } else { 1439 const struct nphy_rf_control_override_rev2 *rf_ctrl; 1440 if (off) { 1441 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); 1442 value = 0; 1443 } else { 1444 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); 1445 } 1446 1447 for (i = 0; i < 2; i++) { 1448 if (index <= 1 || index == 16) { 1449 b43err(dev->wl, 1450 "Unsupported RF Ctrl Override call\n"); 1451 return; 1452 } 1453 1454 if (index == 2 || index == 10 || 1455 (index >= 13 && index <= 15)) { 1456 core = 1; 1457 } 1458 1459 rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; 1460 addr = B43_PHY_N((i == 0) ? 1461 rf_ctrl->addr0 : rf_ctrl->addr1); 1462 1463 if ((core & (1 << i)) != 0) 1464 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), 1465 (value << rf_ctrl->shift)); 1466 1467 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); 1468 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1469 B43_NPHY_RFCTL_CMD_START); 1470 udelay(1); 1471 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); 1472 } 1473 } 1474} 1475 1476/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ 1477static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, 1478 u16 value, u8 core) 1479{ 1480 u8 i, j; 1481 u16 reg, tmp, val; 1482 1483 B43_WARN_ON(dev->phy.rev < 3); 1484 B43_WARN_ON(field > 4); 1485 1486 for (i = 0; i < 2; i++) { 1487 if ((core == 1 && i == 1) || (core == 2 && !i)) 1488 continue; 1489 1490 reg = (i == 0) ? 1491 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 1492 b43_phy_mask(dev, reg, 0xFBFF); 1493 1494 switch (field) { 1495 case 0: 1496 b43_phy_write(dev, reg, 0); 1497 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 1498 break; 1499 case 1: 1500 if (!i) { 1501 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, 1502 0xFC3F, (value << 6)); 1503 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, 1504 0xFFFE, 1); 1505 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1506 B43_NPHY_RFCTL_CMD_START); 1507 for (j = 0; j < 100; j++) { 1508 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) { 1509 j = 0; 1510 break; 1511 } 1512 udelay(10); 1513 } 1514 if (j) 1515 b43err(dev->wl, 1516 "intc override timeout\n"); 1517 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, 1518 0xFFFE); 1519 } else { 1520 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, 1521 0xFC3F, (value << 6)); 1522 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 1523 0xFFFE, 1); 1524 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1525 B43_NPHY_RFCTL_CMD_RXTX); 1526 for (j = 0; j < 100; j++) { 1527 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) { 1528 j = 0; 1529 break; 1530 } 1531 udelay(10); 1532 } 1533 if (j) 1534 b43err(dev->wl, 1535 "intc override timeout\n"); 1536 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 1537 0xFFFE); 1538 } 1539 break; 1540 case 2: 1541 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1542 tmp = 0x0020; 1543 val = value << 5; 1544 } else { 1545 tmp = 0x0010; 1546 val = value << 4; 1547 } 1548 b43_phy_maskset(dev, reg, ~tmp, val); 1549 break; 1550 case 3: 1551 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1552 tmp = 0x0001; 1553 val = value; 1554 } else { 1555 tmp = 0x0004; 1556 val = value << 2; 1557 } 1558 b43_phy_maskset(dev, reg, ~tmp, val); 1559 break; 1560 case 4: 1561 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1562 tmp = 0x0002; 1563 val = value << 1; 1564 } else { 1565 tmp = 0x0008; 1566 val = value << 3; 1567 } 1568 b43_phy_maskset(dev, reg, ~tmp, val); 1569 break; 1570 } 1571 } 1572} 1573 1574static void b43_nphy_bphy_init(struct b43_wldev *dev) 1575{ 1576 unsigned int i; 1577 u16 val; 1578 1579 val = 0x1E1F; 1580 for (i = 0; i < 14; i++) { 1581 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); 1582 val -= 0x202; 1583 } 1584 val = 0x3E3F; 1585 for (i = 0; i < 16; i++) { 1586 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val); 1587 val -= 0x202; 1588 } 1589 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); 1590} 1591 1592/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ 1593static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, 1594 s8 offset, u8 core, u8 rail, u8 type) 1595{ 1596 u16 tmp; 1597 bool core1or5 = (core == 1) || (core == 5); 1598 bool core2or5 = (core == 2) || (core == 5); 1599 1600 offset = clamp_val(offset, -32, 31); 1601 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); 1602 1603 if (core1or5 && (rail == 0) && (type == 2)) 1604 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); 1605 if (core1or5 && (rail == 1) && (type == 2)) 1606 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); 1607 if (core2or5 && (rail == 0) && (type == 2)) 1608 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); 1609 if (core2or5 && (rail == 1) && (type == 2)) 1610 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); 1611 if (core1or5 && (rail == 0) && (type == 0)) 1612 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); 1613 if (core1or5 && (rail == 1) && (type == 0)) 1614 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); 1615 if (core2or5 && (rail == 0) && (type == 0)) 1616 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); 1617 if (core2or5 && (rail == 1) && (type == 0)) 1618 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); 1619 if (core1or5 && (rail == 0) && (type == 1)) 1620 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); 1621 if (core1or5 && (rail == 1) && (type == 1)) 1622 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); 1623 if (core2or5 && (rail == 0) && (type == 1)) 1624 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); 1625 if (core2or5 && (rail == 1) && (type == 1)) 1626 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); 1627 if (core1or5 && (rail == 0) && (type == 6)) 1628 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); 1629 if (core1or5 && (rail == 1) && (type == 6)) 1630 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); 1631 if (core2or5 && (rail == 0) && (type == 6)) 1632 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); 1633 if (core2or5 && (rail == 1) && (type == 6)) 1634 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); 1635 if (core1or5 && (rail == 0) && (type == 3)) 1636 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); 1637 if (core1or5 && (rail == 1) && (type == 3)) 1638 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); 1639 if (core2or5 && (rail == 0) && (type == 3)) 1640 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); 1641 if (core2or5 && (rail == 1) && (type == 3)) 1642 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); 1643 if (core1or5 && (type == 4)) 1644 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); 1645 if (core2or5 && (type == 4)) 1646 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); 1647 if (core1or5 && (type == 5)) 1648 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); 1649 if (core2or5 && (type == 5)) 1650 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); 1651} 1652 1653static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1654{ 1655 u16 val; 1656 1657 if (type < 3) 1658 val = 0; 1659 else if (type == 6) 1660 val = 1; 1661 else if (type == 3) 1662 val = 2; 1663 else 1664 val = 3; 1665 1666 val = (val << 12) | (val << 14); 1667 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); 1668 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); 1669 1670 if (type < 3) { 1671 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, 1672 (type + 1) << 4); 1673 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, 1674 (type + 1) << 4); 1675 } 1676 1677 /* TODO use some definitions */ 1678 if (code == 0) { 1679 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0); 1680 if (type < 3) { 1681 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0); 1682 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0); 1683 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0); 1684 udelay(20); 1685 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0); 1686 } 1687 } else { 1688 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 1689 0x3000); 1690 if (type < 3) { 1691 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 1692 0xFEC7, 0x0180); 1693 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 1694 0xEFDC, (code << 1 | 0x1021)); 1695 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1); 1696 udelay(20); 1697 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0); 1698 } 1699 } 1700} 1701 1702static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1703{ 1704 struct b43_phy_n *nphy = dev->phy.n; 1705 u8 i; 1706 u16 reg, val; 1707 1708 if (code == 0) { 1709 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); 1710 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); 1711 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); 1712 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); 1713 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); 1714 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); 1715 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); 1716 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); 1717 } else { 1718 for (i = 0; i < 2; i++) { 1719 if ((code == 1 && i == 1) || (code == 2 && !i)) 1720 continue; 1721 1722 reg = (i == 0) ? 1723 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; 1724 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); 1725 1726 if (type < 3) { 1727 reg = (i == 0) ? 1728 B43_NPHY_AFECTL_C1 : 1729 B43_NPHY_AFECTL_C2; 1730 b43_phy_maskset(dev, reg, 0xFCFF, 0); 1731 1732 reg = (i == 0) ? 1733 B43_NPHY_RFCTL_LUT_TRSW_UP1 : 1734 B43_NPHY_RFCTL_LUT_TRSW_UP2; 1735 b43_phy_maskset(dev, reg, 0xFFC3, 0); 1736 1737 if (type == 0) 1738 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; 1739 else if (type == 1) 1740 val = 16; 1741 else 1742 val = 32; 1743 b43_phy_set(dev, reg, val); 1744 1745 reg = (i == 0) ? 1746 B43_NPHY_TXF_40CO_B1S0 : 1747 B43_NPHY_TXF_40CO_B32S1; 1748 b43_phy_set(dev, reg, 0x0020); 1749 } else { 1750 if (type == 6) 1751 val = 0x0100; 1752 else if (type == 3) 1753 val = 0x0200; 1754 else 1755 val = 0x0300; 1756 1757 reg = (i == 0) ? 1758 B43_NPHY_AFECTL_C1 : 1759 B43_NPHY_AFECTL_C2; 1760 1761 b43_phy_maskset(dev, reg, 0xFCFF, val); 1762 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); 1763 1764 if (type != 3 && type != 6) { 1765 enum ieee80211_band band = 1766 b43_current_band(dev->wl); 1767 1768 if ((nphy->ipa2g_on && 1769 band == IEEE80211_BAND_2GHZ) || 1770 (nphy->ipa5g_on && 1771 band == IEEE80211_BAND_5GHZ)) 1772 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; 1773 else 1774 val = 0x11; 1775 reg = (i == 0) ? 0x2000 : 0x3000; 1776 reg |= B2055_PADDRV; 1777 b43_radio_write16(dev, reg, val); 1778 1779 reg = (i == 0) ? 1780 B43_NPHY_AFECTL_OVER1 : 1781 B43_NPHY_AFECTL_OVER; 1782 b43_phy_set(dev, reg, 0x0200); 1783 } 1784 } 1785 } 1786 } 1787} 1788 1789/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ 1790static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1791{ 1792 if (dev->phy.rev >= 3) 1793 b43_nphy_rev3_rssi_select(dev, code, type); 1794 else 1795 b43_nphy_rev2_rssi_select(dev, code, type); 1796} 1797 1798/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ 1799static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) 1800{ 1801 int i; 1802 for (i = 0; i < 2; i++) { 1803 if (type == 2) { 1804 if (i == 0) { 1805 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, 1806 0xFC, buf[0]); 1807 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1808 0xFC, buf[1]); 1809 } else { 1810 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, 1811 0xFC, buf[2 * i]); 1812 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1813 0xFC, buf[2 * i + 1]); 1814 } 1815 } else { 1816 if (i == 0) 1817 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1818 0xF3, buf[0] << 2); 1819 else 1820 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1821 0xF3, buf[2 * i + 1] << 2); 1822 } 1823 } 1824} 1825 1826/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ 1827static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, 1828 u8 nsamp) 1829{ 1830 int i; 1831 int out; 1832 u16 save_regs_phy[9]; 1833 u16 s[2]; 1834 1835 if (dev->phy.rev >= 3) { 1836 save_regs_phy[0] = b43_phy_read(dev, 1837 B43_NPHY_RFCTL_LUT_TRSW_UP1); 1838 save_regs_phy[1] = b43_phy_read(dev, 1839 B43_NPHY_RFCTL_LUT_TRSW_UP2); 1840 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 1841 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 1842 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 1843 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 1844 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); 1845 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); 1846 } 1847 1848 b43_nphy_rssi_select(dev, 5, type); 1849 1850 if (dev->phy.rev < 2) { 1851 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); 1852 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); 1853 } 1854 1855 for (i = 0; i < 4; i++) 1856 buf[i] = 0; 1857 1858 for (i = 0; i < nsamp; i++) { 1859 if (dev->phy.rev < 2) { 1860 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); 1861 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); 1862 } else { 1863 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); 1864 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); 1865 } 1866 1867 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; 1868 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; 1869 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; 1870 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; 1871 } 1872 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | 1873 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); 1874 1875 if (dev->phy.rev < 2) 1876 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); 1877 1878 if (dev->phy.rev >= 3) { 1879 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 1880 save_regs_phy[0]); 1881 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 1882 save_regs_phy[1]); 1883 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]); 1884 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]); 1885 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); 1886 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); 1887 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); 1888 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); 1889 } 1890 1891 return out; 1892} 1893 1894/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ 1895static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) 1896{ 1897 int i, j; 1898 u8 state[4]; 1899 u8 code, val; 1900 u16 class, override; 1901 u8 regs_save_radio[2]; 1902 u16 regs_save_phy[2]; 1903 s8 offset[4]; 1904 1905 u16 clip_state[2]; 1906 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; 1907 s32 results_min[4] = { }; 1908 u8 vcm_final[4] = { }; 1909 s32 results[4][4] = { }; 1910 s32 miniq[4][2] = { }; 1911 1912 if (type == 2) { 1913 code = 0; 1914 val = 6; 1915 } else if (type < 2) { 1916 code = 25; 1917 val = 4; 1918 } else { 1919 B43_WARN_ON(1); 1920 return; 1921 } 1922 1923 class = b43_nphy_classifier(dev, 0, 0); 1924 b43_nphy_classifier(dev, 7, 4); 1925 b43_nphy_read_clip_detection(dev, clip_state); 1926 b43_nphy_write_clip_detection(dev, clip_off); 1927 1928 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 1929 override = 0x140; 1930 else 1931 override = 0x110; 1932 1933 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 1934 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); 1935 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); 1936 b43_radio_write16(dev, B2055_C1_PD_RXTX, val); 1937 1938 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 1939 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); 1940 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); 1941 b43_radio_write16(dev, B2055_C2_PD_RXTX, val); 1942 1943 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; 1944 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; 1945 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); 1946 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); 1947 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; 1948 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; 1949 1950 b43_nphy_rssi_select(dev, 5, type); 1951 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); 1952 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); 1953 1954 for (i = 0; i < 4; i++) { 1955 u8 tmp[4]; 1956 for (j = 0; j < 4; j++) 1957 tmp[j] = i; 1958 if (type != 1) 1959 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); 1960 b43_nphy_poll_rssi(dev, type, results[i], 8); 1961 if (type < 2) 1962 for (j = 0; j < 2; j++) 1963 miniq[i][j] = min(results[i][2 * j], 1964 results[i][2 * j + 1]); 1965 } 1966 1967 for (i = 0; i < 4; i++) { 1968 s32 mind = 40; 1969 u8 minvcm = 0; 1970 s32 minpoll = 249; 1971 s32 curr; 1972 for (j = 0; j < 4; j++) { 1973 if (type == 2) 1974 curr = abs(results[j][i]); 1975 else 1976 curr = abs(miniq[j][i / 2] - code * 8); 1977 1978 if (curr < mind) { 1979 mind = curr; 1980 minvcm = j; 1981 } 1982 1983 if (results[j][i] < minpoll) 1984 minpoll = results[j][i]; 1985 } 1986 results_min[i] = minpoll; 1987 vcm_final[i] = minvcm; 1988 } 1989 1990 if (type != 1) 1991 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); 1992 1993 for (i = 0; i < 4; i++) { 1994 offset[i] = (code * 8) - results[vcm_final[i]][i]; 1995 1996 if (offset[i] < 0) 1997 offset[i] = -((abs(offset[i]) + 4) / 8); 1998 else 1999 offset[i] = (offset[i] + 4) / 8; 2000 2001 if (results_min[i] == 248) 2002 offset[i] = code - 32; 2003 2004 if (i % 2 == 0) 2005 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0, 2006 type); 2007 else 2008 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1, 2009 type); 2010 } 2011 2012 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); 2013 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]); 2014 2015 switch (state[2]) { 2016 case 1: 2017 b43_nphy_rssi_select(dev, 1, 2); 2018 break; 2019 case 4: 2020 b43_nphy_rssi_select(dev, 1, 0); 2021 break; 2022 case 2: 2023 b43_nphy_rssi_select(dev, 1, 1); 2024 break; 2025 default: 2026 b43_nphy_rssi_select(dev, 1, 1); 2027 break; 2028 } 2029 2030 switch (state[3]) { 2031 case 1: 2032 b43_nphy_rssi_select(dev, 2, 2); 2033 break; 2034 case 4: 2035 b43_nphy_rssi_select(dev, 2, 0); 2036 break; 2037 default: 2038 b43_nphy_rssi_select(dev, 2, 1); 2039 break; 2040 } 2041 2042 b43_nphy_rssi_select(dev, 0, type); 2043 2044 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); 2045 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); 2046 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); 2047 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); 2048 2049 b43_nphy_classifier(dev, 7, class); 2050 b43_nphy_write_clip_detection(dev, clip_state); 2051} 2052 2053/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ 2054static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) 2055{ 2056 /* TODO */ 2057} 2058 2059/* 2060 * RSSI Calibration 2061 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal 2062 */ 2063static void b43_nphy_rssi_cal(struct b43_wldev *dev) 2064{ 2065 if (dev->phy.rev >= 3) { 2066 b43_nphy_rev3_rssi_cal(dev); 2067 } else { 2068 b43_nphy_rev2_rssi_cal(dev, 2); 2069 b43_nphy_rev2_rssi_cal(dev, 0); 2070 b43_nphy_rev2_rssi_cal(dev, 1); 2071 } 2072} 2073 2074/* 2075 * Restore RSSI Calibration 2076 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal 2077 */ 2078static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) 2079{ 2080 struct b43_phy_n *nphy = dev->phy.n; 2081 2082 u16 *rssical_radio_regs = NULL; 2083 u16 *rssical_phy_regs = NULL; 2084 2085 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2086 if (b43_empty_chanspec(&nphy->rssical_chanspec_2G)) 2087 return; 2088 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; 2089 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; 2090 } else { 2091 if (b43_empty_chanspec(&nphy->rssical_chanspec_5G)) 2092 return; 2093 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 2094 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 2095 } 2096 2097 /* TODO use some definitions */ 2098 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); 2099 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); 2100 2101 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); 2102 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); 2103 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); 2104 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); 2105 2106 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); 2107 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); 2108 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); 2109 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); 2110 2111 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); 2112 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); 2113 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); 2114 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); 2115} 2116 2117/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ 2118static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) 2119{ 2120 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2121 if (dev->phy.rev >= 6) { 2122 /* TODO If the chip is 47162 2123 return txpwrctrl_tx_gain_ipa_rev5 */ 2124 return txpwrctrl_tx_gain_ipa_rev6; 2125 } else if (dev->phy.rev >= 5) { 2126 return txpwrctrl_tx_gain_ipa_rev5; 2127 } else { 2128 return txpwrctrl_tx_gain_ipa; 2129 } 2130 } else { 2131 return txpwrctrl_tx_gain_ipa_5g; 2132 } 2133} 2134 2135/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ 2136static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) 2137{ 2138 struct b43_phy_n *nphy = dev->phy.n; 2139 u16 *save = nphy->tx_rx_cal_radio_saveregs; 2140 u16 tmp; 2141 u8 offset, i; 2142 2143 if (dev->phy.rev >= 3) { 2144 for (i = 0; i < 2; i++) { 2145 tmp = (i == 0) ? 0x2000 : 0x3000; 2146 offset = i * 11; 2147 2148 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); 2149 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); 2150 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); 2151 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); 2152 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); 2153 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); 2154 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); 2155 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); 2156 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); 2157 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); 2158 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); 2159 2160 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2161 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); 2162 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 2163 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 2164 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 2165 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 2166 if (nphy->ipa5g_on) { 2167 b43_radio_write16(dev, tmp | B2055_PADDRV, 4); 2168 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); 2169 } else { 2170 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 2171 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); 2172 } 2173 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 2174 } else { 2175 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); 2176 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 2177 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 2178 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 2179 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 2180 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); 2181 if (nphy->ipa2g_on) { 2182 b43_radio_write16(dev, tmp | B2055_PADDRV, 6); 2183 b43_radio_write16(dev, tmp | B2055_XOCTL2, 2184 (dev->phy.rev < 5) ? 0x11 : 0x01); 2185 } else { 2186 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 2187 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 2188 } 2189 } 2190 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); 2191 b43_radio_write16(dev, tmp | B2055_XOMISC, 0); 2192 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); 2193 } 2194 } else { 2195 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); 2196 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); 2197 2198 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); 2199 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); 2200 2201 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); 2202 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); 2203 2204 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); 2205 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); 2206 2207 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); 2208 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); 2209 2210 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & 2211 B43_NPHY_BANDCTL_5GHZ)) { 2212 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); 2213 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); 2214 } else { 2215 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); 2216 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); 2217 } 2218 2219 if (dev->phy.rev < 2) { 2220 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); 2221 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); 2222 } else { 2223 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); 2224 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); 2225 } 2226 } 2227} 2228 2229/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ 2230static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, 2231 struct nphy_txgains target, 2232 struct nphy_iqcal_params *params) 2233{ 2234 int i, j, indx; 2235 u16 gain; 2236 2237 if (dev->phy.rev >= 3) { 2238 params->txgm = target.txgm[core]; 2239 params->pga = target.pga[core]; 2240 params->pad = target.pad[core]; 2241 params->ipa = target.ipa[core]; 2242 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | 2243 (params->pad << 4) | (params->ipa); 2244 for (j = 0; j < 5; j++) 2245 params->ncorr[j] = 0x79; 2246 } else { 2247 gain = (target.pad[core]) | (target.pga[core] << 4) | 2248 (target.txgm[core] << 8); 2249 2250 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 2251 1 : 0; 2252 for (i = 0; i < 9; i++) 2253 if (tbl_iqcal_gainparams[indx][i][0] == gain) 2254 break; 2255 i = min(i, 8); 2256 2257 params->txgm = tbl_iqcal_gainparams[indx][i][1]; 2258 params->pga = tbl_iqcal_gainparams[indx][i][2]; 2259 params->pad = tbl_iqcal_gainparams[indx][i][3]; 2260 params->cal_gain = (params->txgm << 7) | (params->pga << 4) | 2261 (params->pad << 2); 2262 for (j = 0; j < 4; j++) 2263 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; 2264 } 2265} 2266 2267/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ 2268static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) 2269{ 2270 struct b43_phy_n *nphy = dev->phy.n; 2271 int i; 2272 u16 scale, entry; 2273 2274 u16 tmp = nphy->txcal_bbmult; 2275 if (core == 0) 2276 tmp >>= 8; 2277 tmp &= 0xff; 2278 2279 for (i = 0; i < 18; i++) { 2280 scale = (ladder_lo[i].percent * tmp) / 100; 2281 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; 2282 b43_ntab_write(dev, B43_NTAB16(15, i), entry); 2283 2284 scale = (ladder_iq[i].percent * tmp) / 100; 2285 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; 2286 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); 2287 } 2288} 2289 2290/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ 2291static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) 2292{ 2293 int i; 2294 for (i = 0; i < 15; i++) 2295 b43_phy_write(dev, B43_PHY_N(0x2C5 + i), 2296 tbl_tx_filter_coef_rev4[2][i]); 2297} 2298 2299/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ 2300static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) 2301{ 2302 int i, j; 2303 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ 2304 u16 offset[] = { 0x186, 0x195, 0x2C5 }; 2305 2306 for (i = 0; i < 3; i++) 2307 for (j = 0; j < 15; j++) 2308 b43_phy_write(dev, B43_PHY_N(offset[i] + j), 2309 tbl_tx_filter_coef_rev4[i][j]); 2310 2311 if (dev->phy.is_40mhz) { 2312 for (j = 0; j < 15; j++) 2313 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2314 tbl_tx_filter_coef_rev4[3][j]); 2315 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2316 for (j = 0; j < 15; j++) 2317 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2318 tbl_tx_filter_coef_rev4[5][j]); 2319 } 2320 2321 if (dev->phy.channel == 14) 2322 for (j = 0; j < 15; j++) 2323 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2324 tbl_tx_filter_coef_rev4[6][j]); 2325} 2326 2327/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ 2328static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) 2329{ 2330 struct b43_phy_n *nphy = dev->phy.n; 2331 2332 u16 curr_gain[2]; 2333 struct nphy_txgains target; 2334 const u32 *table = NULL; 2335 2336 if (nphy->txpwrctrl == 0) { 2337 int i; 2338 2339 if (nphy->hang_avoid) 2340 b43_nphy_stay_in_carrier_search(dev, true); 2341 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); 2342 if (nphy->hang_avoid) 2343 b43_nphy_stay_in_carrier_search(dev, false); 2344 2345 for (i = 0; i < 2; ++i) { 2346 if (dev->phy.rev >= 3) { 2347 target.ipa[i] = curr_gain[i] & 0x000F; 2348 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; 2349 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; 2350 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; 2351 } else { 2352 target.ipa[i] = curr_gain[i] & 0x0003; 2353 target.pad[i] = (curr_gain[i] & 0x000C) >> 2; 2354 target.pga[i] = (curr_gain[i] & 0x0070) >> 4; 2355 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; 2356 } 2357 } 2358 } else { 2359 int i; 2360 u16 index[2]; 2361 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & 2362 B43_NPHY_TXPCTL_STAT_BIDX) >> 2363 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 2364 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & 2365 B43_NPHY_TXPCTL_STAT_BIDX) >> 2366 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 2367 2368 for (i = 0; i < 2; ++i) { 2369 if (dev->phy.rev >= 3) { 2370 enum ieee80211_band band = 2371 b43_current_band(dev->wl); 2372 2373 if ((nphy->ipa2g_on && 2374 band == IEEE80211_BAND_2GHZ) || 2375 (nphy->ipa5g_on && 2376 band == IEEE80211_BAND_5GHZ)) { 2377 table = b43_nphy_get_ipa_gain_table(dev); 2378 } else { 2379 if (band == IEEE80211_BAND_5GHZ) { 2380 if (dev->phy.rev == 3) 2381 table = b43_ntab_tx_gain_rev3_5ghz; 2382 else if (dev->phy.rev == 4) 2383 table = b43_ntab_tx_gain_rev4_5ghz; 2384 else 2385 table = b43_ntab_tx_gain_rev5plus_5ghz; 2386 } else { 2387 table = b43_ntab_tx_gain_rev3plus_2ghz; 2388 } 2389 } 2390 2391 target.ipa[i] = (table[index[i]] >> 16) & 0xF; 2392 target.pad[i] = (table[index[i]] >> 20) & 0xF; 2393 target.pga[i] = (table[index[i]] >> 24) & 0xF; 2394 target.txgm[i] = (table[index[i]] >> 28) & 0xF; 2395 } else { 2396 table = b43_ntab_tx_gain_rev0_1_2; 2397 2398 target.ipa[i] = (table[index[i]] >> 16) & 0x3; 2399 target.pad[i] = (table[index[i]] >> 18) & 0x3; 2400 target.pga[i] = (table[index[i]] >> 20) & 0x7; 2401 target.txgm[i] = (table[index[i]] >> 23) & 0x7; 2402 } 2403 } 2404 } 2405 2406 return target; 2407} 2408 2409/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ 2410static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) 2411{ 2412 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 2413 2414 if (dev->phy.rev >= 3) { 2415 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); 2416 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 2417 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 2418 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); 2419 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); 2420 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); 2421 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); 2422 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); 2423 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); 2424 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 2425 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 2426 b43_nphy_reset_cca(dev); 2427 } else { 2428 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); 2429 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); 2430 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 2431 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); 2432 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); 2433 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); 2434 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); 2435 } 2436} 2437 2438/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ 2439static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) 2440{ 2441 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 2442 u16 tmp; 2443 2444 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 2445 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 2446 if (dev->phy.rev >= 3) { 2447 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); 2448 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); 2449 2450 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 2451 regs[2] = tmp; 2452 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); 2453 2454 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2455 regs[3] = tmp; 2456 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); 2457 2458 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); 2459 b43_phy_mask(dev, B43_NPHY_BBCFG, 2460 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); 2461 2462 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); 2463 regs[5] = tmp; 2464 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); 2465 2466 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); 2467 regs[6] = tmp; 2468 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); 2469 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2470 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2471 2472 b43_nphy_rf_control_intc_override(dev, 2, 1, 3); 2473 b43_nphy_rf_control_intc_override(dev, 1, 2, 1); 2474 b43_nphy_rf_control_intc_override(dev, 1, 8, 2); 2475 2476 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 2477 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 2478 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 2479 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 2480 } else { 2481 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); 2482 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); 2483 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2484 regs[2] = tmp; 2485 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); 2486 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); 2487 regs[3] = tmp; 2488 tmp |= 0x2000; 2489 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); 2490 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); 2491 regs[4] = tmp; 2492 tmp |= 0x2000; 2493 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); 2494 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2495 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2496 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 2497 tmp = 0x0180; 2498 else 2499 tmp = 0x0120; 2500 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 2501 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 2502 } 2503} 2504 2505/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ 2506static void b43_nphy_save_cal(struct b43_wldev *dev) 2507{ 2508 struct b43_phy_n *nphy = dev->phy.n; 2509 2510 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 2511 u16 *txcal_radio_regs = NULL; 2512 struct b43_chanspec *iqcal_chanspec; 2513 u16 *table = NULL; 2514 2515 if (nphy->hang_avoid) 2516 b43_nphy_stay_in_carrier_search(dev, 1); 2517 2518 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2519 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 2520 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 2521 iqcal_chanspec = &nphy->iqcal_chanspec_2G; 2522 table = nphy->cal_cache.txcal_coeffs_2G; 2523 } else { 2524 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 2525 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 2526 iqcal_chanspec = &nphy->iqcal_chanspec_5G; 2527 table = nphy->cal_cache.txcal_coeffs_5G; 2528 } 2529 2530 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); 2531 /* TODO use some definitions */ 2532 if (dev->phy.rev >= 3) { 2533 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); 2534 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); 2535 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); 2536 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); 2537 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); 2538 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); 2539 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); 2540 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); 2541 } else { 2542 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); 2543 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); 2544 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); 2545 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); 2546 } 2547 *iqcal_chanspec = nphy->radio_chanspec; 2548 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table); 2549 2550 if (nphy->hang_avoid) 2551 b43_nphy_stay_in_carrier_search(dev, 0); 2552} 2553 2554/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ 2555static void b43_nphy_restore_cal(struct b43_wldev *dev) 2556{ 2557 struct b43_phy_n *nphy = dev->phy.n; 2558 2559 u16 coef[4]; 2560 u16 *loft = NULL; 2561 u16 *table = NULL; 2562 2563 int i; 2564 u16 *txcal_radio_regs = NULL; 2565 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 2566 2567 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2568 if (b43_empty_chanspec(&nphy->iqcal_chanspec_2G)) 2569 return; 2570 table = nphy->cal_cache.txcal_coeffs_2G; 2571 loft = &nphy->cal_cache.txcal_coeffs_2G[5]; 2572 } else { 2573 if (b43_empty_chanspec(&nphy->iqcal_chanspec_5G)) 2574 return; 2575 table = nphy->cal_cache.txcal_coeffs_5G; 2576 loft = &nphy->cal_cache.txcal_coeffs_5G[5]; 2577 } 2578 2579 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); 2580 2581 for (i = 0; i < 4; i++) { 2582 if (dev->phy.rev >= 3) 2583 table[i] = coef[i]; 2584 else 2585 coef[i] = 0; 2586 } 2587 2588 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); 2589 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); 2590 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); 2591 2592 if (dev->phy.rev < 2) 2593 b43_nphy_tx_iq_workaround(dev); 2594 2595 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2596 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 2597 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 2598 } else { 2599 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 2600 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 2601 } 2602 2603 /* TODO use some definitions */ 2604 if (dev->phy.rev >= 3) { 2605 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); 2606 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); 2607 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); 2608 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); 2609 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); 2610 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); 2611 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); 2612 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); 2613 } else { 2614 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); 2615 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); 2616 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); 2617 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); 2618 } 2619 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); 2620} 2621 2622/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ 2623static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, 2624 struct nphy_txgains target, 2625 bool full, bool mphase) 2626{ 2627 struct b43_phy_n *nphy = dev->phy.n; 2628 int i; 2629 int error = 0; 2630 int freq; 2631 bool avoid = false; 2632 u8 length; 2633 u16 tmp, core, type, count, max, numb, last, cmd; 2634 const u16 *table; 2635 bool phy6or5x; 2636 2637 u16 buffer[11]; 2638 u16 diq_start = 0; 2639 u16 save[2]; 2640 u16 gain[2]; 2641 struct nphy_iqcal_params params[2]; 2642 bool updated[2] = { }; 2643 2644 b43_nphy_stay_in_carrier_search(dev, true); 2645 2646 if (dev->phy.rev >= 4) { 2647 avoid = nphy->hang_avoid; 2648 nphy->hang_avoid = 0; 2649 } 2650 2651 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 2652 2653 for (i = 0; i < 2; i++) { 2654 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); 2655 gain[i] = params[i].cal_gain; 2656 } 2657 2658 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); 2659 2660 b43_nphy_tx_cal_radio_setup(dev); 2661 b43_nphy_tx_cal_phy_setup(dev); 2662 2663 phy6or5x = dev->phy.rev >= 6 || 2664 (dev->phy.rev == 5 && nphy->ipa2g_on && 2665 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); 2666 if (phy6or5x) { 2667 if (dev->phy.is_40mhz) { 2668 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 2669 tbl_tx_iqlo_cal_loft_ladder_40); 2670 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 2671 tbl_tx_iqlo_cal_iqimb_ladder_40); 2672 } else { 2673 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 2674 tbl_tx_iqlo_cal_loft_ladder_20); 2675 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 2676 tbl_tx_iqlo_cal_iqimb_ladder_20); 2677 } 2678 } 2679 2680 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); 2681 2682 if (!dev->phy.is_40mhz) 2683 freq = 2500; 2684 else 2685 freq = 5000; 2686 2687 if (nphy->mphase_cal_phase_id > 2) 2688 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8, 2689 0xFFFF, 0, true, false); 2690 else 2691 error = b43_nphy_tx_tone(dev, freq, 250, true, false); 2692 2693 if (error == 0) { 2694 if (nphy->mphase_cal_phase_id > 2) { 2695 table = nphy->mphase_txcal_bestcoeffs; 2696 length = 11; 2697 if (dev->phy.rev < 3) 2698 length -= 2; 2699 } else { 2700 if (!full && nphy->txiqlocal_coeffsvalid) { 2701 table = nphy->txiqlocal_bestc; 2702 length = 11; 2703 if (dev->phy.rev < 3) 2704 length -= 2; 2705 } else { 2706 full = true; 2707 if (dev->phy.rev >= 3) { 2708 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; 2709 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; 2710 } else { 2711 table = tbl_tx_iqlo_cal_startcoefs; 2712 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; 2713 } 2714 } 2715 } 2716 2717 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); 2718 2719 if (full) { 2720 if (dev->phy.rev >= 3) 2721 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; 2722 else 2723 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; 2724 } else { 2725 if (dev->phy.rev >= 3) 2726 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; 2727 else 2728 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; 2729 } 2730 2731 if (mphase) { 2732 count = nphy->mphase_txcal_cmdidx; 2733 numb = min(max, 2734 (u16)(count + nphy->mphase_txcal_numcmds)); 2735 } else { 2736 count = 0; 2737 numb = max; 2738 } 2739 2740 for (; count < numb; count++) { 2741 if (full) { 2742 if (dev->phy.rev >= 3) 2743 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; 2744 else 2745 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; 2746 } else { 2747 if (dev->phy.rev >= 3) 2748 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; 2749 else 2750 cmd = tbl_tx_iqlo_cal_cmds_recal[count]; 2751 } 2752 2753 core = (cmd & 0x3000) >> 12; 2754 type = (cmd & 0x0F00) >> 8; 2755 2756 if (phy6or5x && updated[core] == 0) { 2757 b43_nphy_update_tx_cal_ladder(dev, core); 2758 updated[core] = 1; 2759 } 2760 2761 tmp = (params[core].ncorr[type] << 8) | 0x66; 2762 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); 2763 2764 if (type == 1 || type == 3 || type == 4) { 2765 buffer[0] = b43_ntab_read(dev, 2766 B43_NTAB16(15, 69 + core)); 2767 diq_start = buffer[0]; 2768 buffer[0] = 0; 2769 b43_ntab_write(dev, B43_NTAB16(15, 69 + core), 2770 0); 2771 } 2772 2773 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); 2774 for (i = 0; i < 2000; i++) { 2775 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); 2776 if (tmp & 0xC000) 2777 break; 2778 udelay(10); 2779 } 2780 2781 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 2782 buffer); 2783 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, 2784 buffer); 2785 2786 if (type == 1 || type == 3 || type == 4) 2787 buffer[0] = diq_start; 2788 } 2789 2790 if (mphase) 2791 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; 2792 2793 last = (dev->phy.rev < 3) ? 6 : 7; 2794 2795 if (!mphase || nphy->mphase_cal_phase_id == last) { 2796 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); 2797 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); 2798 if (dev->phy.rev < 3) { 2799 buffer[0] = 0; 2800 buffer[1] = 0; 2801 buffer[2] = 0; 2802 buffer[3] = 0; 2803 } 2804 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 2805 buffer); 2806 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, 2807 buffer); 2808 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 2809 buffer); 2810 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 2811 buffer); 2812 length = 11; 2813 if (dev->phy.rev < 3) 2814 length -= 2; 2815 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 2816 nphy->txiqlocal_bestc); 2817 nphy->txiqlocal_coeffsvalid = true; 2818 nphy->txiqlocal_chanspec = nphy->radio_chanspec; 2819 } else { 2820 length = 11; 2821 if (dev->phy.rev < 3) 2822 length -= 2; 2823 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 2824 nphy->mphase_txcal_bestcoeffs); 2825 } 2826 2827 b43_nphy_stop_playback(dev); 2828 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); 2829 } 2830 2831 b43_nphy_tx_cal_phy_cleanup(dev); 2832 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 2833 2834 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) 2835 b43_nphy_tx_iq_workaround(dev); 2836 2837 if (dev->phy.rev >= 4) 2838 nphy->hang_avoid = avoid; 2839 2840 b43_nphy_stay_in_carrier_search(dev, false); 2841 2842 return error; 2843} 2844 2845/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ 2846static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) 2847{ 2848 struct b43_phy_n *nphy = dev->phy.n; 2849 u8 i; 2850 u16 buffer[7]; 2851 bool equal = true; 2852 2853 if (!nphy->txiqlocal_coeffsvalid || 2854 b43_eq_chanspecs(&nphy->txiqlocal_chanspec, &nphy->radio_chanspec)) 2855 return; 2856 2857 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 2858 for (i = 0; i < 4; i++) { 2859 if (buffer[i] != nphy->txiqlocal_bestc[i]) { 2860 equal = false; 2861 break; 2862 } 2863 } 2864 2865 if (!equal) { 2866 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, 2867 nphy->txiqlocal_bestc); 2868 for (i = 0; i < 4; i++) 2869 buffer[i] = 0; 2870 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 2871 buffer); 2872 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 2873 &nphy->txiqlocal_bestc[5]); 2874 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 2875 &nphy->txiqlocal_bestc[5]); 2876 } 2877} 2878 2879/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ 2880static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, 2881 struct nphy_txgains target, u8 type, bool debug) 2882{ 2883 struct b43_phy_n *nphy = dev->phy.n; 2884 int i, j, index; 2885 u8 rfctl[2]; 2886 u8 afectl_core; 2887 u16 tmp[6]; 2888 u16 cur_hpf1, cur_hpf2, cur_lna; 2889 u32 real, imag; 2890 enum ieee80211_band band; 2891 2892 u8 use; 2893 u16 cur_hpf; 2894 u16 lna[3] = { 3, 3, 1 }; 2895 u16 hpf1[3] = { 7, 2, 0 }; 2896 u16 hpf2[3] = { 2, 0, 0 }; 2897 u32 power[3] = { }; 2898 u16 gain_save[2]; 2899 u16 cal_gain[2]; 2900 struct nphy_iqcal_params cal_params[2]; 2901 struct nphy_iq_est est; 2902 int ret = 0; 2903 bool playtone = true; 2904 int desired = 13; 2905 2906 b43_nphy_stay_in_carrier_search(dev, 1); 2907 2908 if (dev->phy.rev < 2) 2909 b43_nphy_reapply_tx_cal_coeffs(dev); 2910 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 2911 for (i = 0; i < 2; i++) { 2912 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); 2913 cal_gain[i] = cal_params[i].cal_gain; 2914 } 2915 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); 2916 2917 for (i = 0; i < 2; i++) { 2918 if (i == 0) { 2919 rfctl[0] = B43_NPHY_RFCTL_INTC1; 2920 rfctl[1] = B43_NPHY_RFCTL_INTC2; 2921 afectl_core = B43_NPHY_AFECTL_C1; 2922 } else { 2923 rfctl[0] = B43_NPHY_RFCTL_INTC2; 2924 rfctl[1] = B43_NPHY_RFCTL_INTC1; 2925 afectl_core = B43_NPHY_AFECTL_C2; 2926 } 2927 2928 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 2929 tmp[2] = b43_phy_read(dev, afectl_core); 2930 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2931 tmp[4] = b43_phy_read(dev, rfctl[0]); 2932 tmp[5] = b43_phy_read(dev, rfctl[1]); 2933 2934 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 2935 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 2936 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 2937 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 2938 (1 - i)); 2939 b43_phy_set(dev, afectl_core, 0x0006); 2940 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); 2941 2942 band = b43_current_band(dev->wl); 2943 2944 if (nphy->rxcalparams & 0xFF000000) { 2945 if (band == IEEE80211_BAND_5GHZ) 2946 b43_phy_write(dev, rfctl[0], 0x140); 2947 else 2948 b43_phy_write(dev, rfctl[0], 0x110); 2949 } else { 2950 if (band == IEEE80211_BAND_5GHZ) 2951 b43_phy_write(dev, rfctl[0], 0x180); 2952 else 2953 b43_phy_write(dev, rfctl[0], 0x120); 2954 } 2955 2956 if (band == IEEE80211_BAND_5GHZ) 2957 b43_phy_write(dev, rfctl[1], 0x148); 2958 else 2959 b43_phy_write(dev, rfctl[1], 0x114); 2960 2961 if (nphy->rxcalparams & 0x10000) { 2962 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, 2963 (i + 1)); 2964 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, 2965 (2 - i)); 2966 } 2967 2968 for (j = 0; i < 4; j++) { 2969 if (j < 3) { 2970 cur_lna = lna[j]; 2971 cur_hpf1 = hpf1[j]; 2972 cur_hpf2 = hpf2[j]; 2973 } else { 2974 if (power[1] > 10000) { 2975 use = 1; 2976 cur_hpf = cur_hpf1; 2977 index = 2; 2978 } else { 2979 if (power[0] > 10000) { 2980 use = 1; 2981 cur_hpf = cur_hpf1; 2982 index = 1; 2983 } else { 2984 index = 0; 2985 use = 2; 2986 cur_hpf = cur_hpf2; 2987 } 2988 } 2989 cur_lna = lna[index]; 2990 cur_hpf1 = hpf1[index]; 2991 cur_hpf2 = hpf2[index]; 2992 cur_hpf += desired - hweight32(power[index]); 2993 cur_hpf = clamp_val(cur_hpf, 0, 10); 2994 if (use == 1) 2995 cur_hpf1 = cur_hpf; 2996 else 2997 cur_hpf2 = cur_hpf; 2998 } 2999 3000 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | 3001 (cur_lna << 2)); 3002 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, 3003 false); 3004 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3005 b43_nphy_stop_playback(dev); 3006 3007 if (playtone) { 3008 ret = b43_nphy_tx_tone(dev, 4000, 3009 (nphy->rxcalparams & 0xFFFF), 3010 false, false); 3011 playtone = false; 3012 } else { 3013 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, 3014 false, false); 3015 } 3016 3017 if (ret == 0) { 3018 if (j < 3) { 3019 b43_nphy_rx_iq_est(dev, &est, 1024, 32, 3020 false); 3021 if (i == 0) { 3022 real = est.i0_pwr; 3023 imag = est.q0_pwr; 3024 } else { 3025 real = est.i1_pwr; 3026 imag = est.q1_pwr; 3027 } 3028 power[i] = ((real + imag) / 1024) + 1; 3029 } else { 3030 b43_nphy_calc_rx_iq_comp(dev, 1 << i); 3031 } 3032 b43_nphy_stop_playback(dev); 3033 } 3034 3035 if (ret != 0) 3036 break; 3037 } 3038 3039 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); 3040 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); 3041 b43_phy_write(dev, rfctl[1], tmp[5]); 3042 b43_phy_write(dev, rfctl[0], tmp[4]); 3043 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); 3044 b43_phy_write(dev, afectl_core, tmp[2]); 3045 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); 3046 3047 if (ret != 0) 3048 break; 3049 } 3050 3051 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); 3052 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3053 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 3054 3055 b43_nphy_stay_in_carrier_search(dev, 0); 3056 3057 return ret; 3058} 3059 3060static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, 3061 struct nphy_txgains target, u8 type, bool debug) 3062{ 3063 return -1; 3064} 3065 3066/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ 3067static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, 3068 struct nphy_txgains target, u8 type, bool debug) 3069{ 3070 if (dev->phy.rev >= 3) 3071 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); 3072 else 3073 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); 3074} 3075 3076/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 3077static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on) 3078{ 3079 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 3080 if (on) 3081 tmslow |= SSB_TMSLOW_PHYCLK; 3082 else 3083 tmslow &= ~SSB_TMSLOW_PHYCLK; 3084 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 3085} 3086 3087/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */ 3088static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) 3089{ 3090 struct b43_phy *phy = &dev->phy; 3091 struct b43_phy_n *nphy = phy->n; 3092 u16 buf[16]; 3093 3094 nphy->phyrxchain = mask; 3095 3096 if (0 /* FIXME clk */) 3097 return; 3098 3099 b43_mac_suspend(dev); 3100 3101 if (nphy->hang_avoid) 3102 b43_nphy_stay_in_carrier_search(dev, true); 3103 3104 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 3105 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT); 3106 3107 if ((mask & 0x3) != 0x3) { 3108 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); 3109 if (dev->phy.rev >= 3) { 3110 /* TODO */ 3111 } 3112 } else { 3113 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); 3114 if (dev->phy.rev >= 3) { 3115 /* TODO */ 3116 } 3117 } 3118 3119 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3120 3121 if (nphy->hang_avoid) 3122 b43_nphy_stay_in_carrier_search(dev, false); 3123 3124 b43_mac_enable(dev); 3125} 3126 3127/* 3128 * Init N-PHY 3129 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N 3130 */ 3131int b43_phy_initn(struct b43_wldev *dev) 3132{ 3133 struct ssb_bus *bus = dev->dev->bus; 3134 struct b43_phy *phy = &dev->phy; 3135 struct b43_phy_n *nphy = phy->n; 3136 u8 tx_pwr_state; 3137 struct nphy_txgains target; 3138 u16 tmp; 3139 enum ieee80211_band tmp2; 3140 bool do_rssi_cal; 3141 3142 u16 clip[2]; 3143 bool do_cal = false; 3144 3145 if ((dev->phy.rev >= 3) && 3146 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) && 3147 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { 3148 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40); 3149 } 3150 nphy->deaf_count = 0; 3151 b43_nphy_tables_init(dev); 3152 nphy->crsminpwr_adjusted = false; 3153 nphy->noisevars_adjusted = false; 3154 3155 /* Clear all overrides */ 3156 if (dev->phy.rev >= 3) { 3157 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); 3158 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 3159 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); 3160 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); 3161 } else { 3162 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 3163 } 3164 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); 3165 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); 3166 if (dev->phy.rev < 6) { 3167 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); 3168 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); 3169 } 3170 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 3171 ~(B43_NPHY_RFSEQMODE_CAOVER | 3172 B43_NPHY_RFSEQMODE_TROVER)); 3173 if (dev->phy.rev >= 3) 3174 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); 3175 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); 3176 3177 if (dev->phy.rev <= 2) { 3178 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; 3179 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 3180 ~B43_NPHY_BPHY_CTL3_SCALE, 3181 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); 3182 } 3183 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); 3184 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); 3185 3186 if (bus->sprom.boardflags2_lo & 0x100 || 3187 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3188 bus->boardinfo.type == 0x8B)) 3189 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); 3190 else 3191 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); 3192 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); 3193 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); 3194 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); 3195 3196 b43_nphy_update_mimo_config(dev, nphy->preamble_override); 3197 b43_nphy_update_txrx_chain(dev); 3198 3199 if (phy->rev < 2) { 3200 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); 3201 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); 3202 } 3203 3204 tmp2 = b43_current_band(dev->wl); 3205 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) || 3206 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) { 3207 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); 3208 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, 3209 nphy->papd_epsilon_offset[0] << 7); 3210 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); 3211 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, 3212 nphy->papd_epsilon_offset[1] << 7); 3213 b43_nphy_int_pa_set_tx_dig_filters(dev); 3214 } else if (phy->rev >= 5) { 3215 b43_nphy_ext_pa_set_tx_dig_filters(dev); 3216 } 3217 3218 b43_nphy_workarounds(dev); 3219 3220 /* Reset CCA, in init code it differs a little from standard way */ 3221 b43_nphy_bmac_clock_fgc(dev, 1); 3222 tmp = b43_phy_read(dev, B43_NPHY_BBCFG); 3223 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); 3224 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); 3225 b43_nphy_bmac_clock_fgc(dev, 0); 3226 3227 b43_nphy_mac_phy_clock_set(dev, true); 3228 3229 b43_nphy_pa_override(dev, false); 3230 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 3231 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3232 b43_nphy_pa_override(dev, true); 3233 3234 b43_nphy_classifier(dev, 0, 0); 3235 b43_nphy_read_clip_detection(dev, clip); 3236 tx_pwr_state = nphy->txpwrctrl; 3237 /* TODO N PHY TX power control with argument 0 3238 (turning off power control) */ 3239 /* TODO Fix the TX Power Settings */ 3240 /* TODO N PHY TX Power Control Idle TSSI */ 3241 /* TODO N PHY TX Power Control Setup */ 3242 3243 if (phy->rev >= 3) { 3244 /* TODO */ 3245 } else { 3246 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, 3247 b43_ntab_tx_gain_rev0_1_2); 3248 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, 3249 b43_ntab_tx_gain_rev0_1_2); 3250 } 3251 3252 if (nphy->phyrxchain != 3) 3253 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); 3254 if (nphy->mphase_cal_phase_id > 0) 3255 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ 3256 3257 do_rssi_cal = false; 3258 if (phy->rev >= 3) { 3259 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3260 do_rssi_cal = 3261 b43_empty_chanspec(&nphy->rssical_chanspec_2G); 3262 else 3263 do_rssi_cal = 3264 b43_empty_chanspec(&nphy->rssical_chanspec_5G); 3265 3266 if (do_rssi_cal) 3267 b43_nphy_rssi_cal(dev); 3268 else 3269 b43_nphy_restore_rssi_cal(dev); 3270 } else { 3271 b43_nphy_rssi_cal(dev); 3272 } 3273 3274 if (!((nphy->measure_hold & 0x6) != 0)) { 3275 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3276 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_2G); 3277 else 3278 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_5G); 3279 3280 if (nphy->mute) 3281 do_cal = false; 3282 3283 if (do_cal) { 3284 target = b43_nphy_get_tx_gains(dev); 3285 3286 if (nphy->antsel_type == 2) 3287 b43_nphy_superswitch_init(dev, true); 3288 if (nphy->perical != 2) { 3289 b43_nphy_rssi_cal(dev); 3290 if (phy->rev >= 3) { 3291 nphy->cal_orig_pwr_idx[0] = 3292 nphy->txpwrindex[0].index_internal; 3293 nphy->cal_orig_pwr_idx[1] = 3294 nphy->txpwrindex[1].index_internal; 3295 /* TODO N PHY Pre Calibrate TX Gain */ 3296 target = b43_nphy_get_tx_gains(dev); 3297 } 3298 } 3299 } 3300 } 3301 3302 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) { 3303 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) 3304 b43_nphy_save_cal(dev); 3305 else if (nphy->mphase_cal_phase_id == 0) 3306 ;/* N PHY Periodic Calibration with argument 3 */ 3307 } else { 3308 b43_nphy_restore_cal(dev); 3309 } 3310 3311 b43_nphy_tx_pwr_ctrl_coef_setup(dev); 3312 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */ 3313 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); 3314 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); 3315 if (phy->rev >= 3 && phy->rev <= 6) 3316 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014); 3317 b43_nphy_tx_lp_fbw(dev); 3318 if (phy->rev >= 3) 3319 b43_nphy_spur_workaround(dev); 3320 3321 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n"); 3322 return 0; 3323} 3324 3325/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ 3326static void b43_nphy_chanspec_setup(struct b43_wldev *dev, 3327 const struct b43_phy_n_sfo_cfg *e, 3328 struct b43_chanspec chanspec) 3329{ 3330 struct b43_phy *phy = &dev->phy; 3331 struct b43_phy_n *nphy = dev->phy.n; 3332 3333 u16 tmp; 3334 u32 tmp32; 3335 3336 tmp = b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ; 3337 if (chanspec.b_freq == 1 && tmp == 0) { 3338 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR); 3339 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4); 3340 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000); 3341 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32); 3342 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); 3343 } else if (chanspec.b_freq == 1) { 3344 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); 3345 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR); 3346 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4); 3347 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF); 3348 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32); 3349 } 3350 3351 b43_chantab_phy_upload(dev, e); 3352 3353 3354 if (nphy->radio_chanspec.channel == 14) { 3355 b43_nphy_classifier(dev, 2, 0); 3356 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); 3357 } else { 3358 b43_nphy_classifier(dev, 2, 2); 3359 if (chanspec.b_freq == 2) 3360 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); 3361 } 3362 3363 if (nphy->txpwrctrl) 3364 b43_nphy_tx_power_fix(dev); 3365 3366 if (dev->phy.rev < 3) 3367 b43_nphy_adjust_lna_gain_table(dev); 3368 3369 b43_nphy_tx_lp_fbw(dev); 3370 3371 if (dev->phy.rev >= 3 && 0) { 3372 /* TODO */ 3373 } 3374 3375 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); 3376 3377 if (phy->rev >= 3) 3378 b43_nphy_spur_workaround(dev); 3379} 3380 3381/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ 3382static int b43_nphy_set_chanspec(struct b43_wldev *dev, 3383 struct b43_chanspec chanspec) 3384{ 3385 struct b43_phy_n *nphy = dev->phy.n; 3386 3387 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2; 3388 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3; 3389 3390 u8 tmp; 3391 u8 channel = chanspec.channel; 3392 3393 if (dev->phy.rev >= 3) { 3394 /* TODO */ 3395 tabent_r3 = NULL; 3396 if (!tabent_r3) 3397 return -ESRCH; 3398 } else { 3399 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, channel); 3400 if (!tabent_r2) 3401 return -ESRCH; 3402 } 3403 3404 nphy->radio_chanspec = chanspec; 3405 3406 if (chanspec.b_width != nphy->b_width) 3407 ; /* TODO: BMAC BW Set (chanspec.b_width) */ 3408 3409 /* TODO: use defines */ 3410 if (chanspec.b_width == 3) { 3411 if (chanspec.sideband == 2) 3412 b43_phy_set(dev, B43_NPHY_RXCTL, 3413 B43_NPHY_RXCTL_BSELU20); 3414 else 3415 b43_phy_mask(dev, B43_NPHY_RXCTL, 3416 ~B43_NPHY_RXCTL_BSELU20); 3417 } 3418 3419 if (dev->phy.rev >= 3) { 3420 tmp = (chanspec.b_freq == 1) ? 4 : 0; 3421 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); 3422 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */ 3423 b43_nphy_chanspec_setup(dev, &(tabent_r3->phy_regs), chanspec); 3424 } else { 3425 tmp = (chanspec.b_freq == 1) ? 0x0020 : 0x0050; 3426 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); 3427 b43_radio_2055_setup(dev, tabent_r2); 3428 b43_nphy_chanspec_setup(dev, &(tabent_r2->phy_regs), chanspec); 3429 } 3430 3431 return 0; 3432} 3433 3434static int b43_nphy_op_allocate(struct b43_wldev *dev) 3435{ 3436 struct b43_phy_n *nphy; 3437 3438 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); 3439 if (!nphy) 3440 return -ENOMEM; 3441 dev->phy.n = nphy; 3442 3443 return 0; 3444} 3445 3446static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) 3447{ 3448 struct b43_phy *phy = &dev->phy; 3449 struct b43_phy_n *nphy = phy->n; 3450 3451 memset(nphy, 0, sizeof(*nphy)); 3452 3453 //TODO init struct b43_phy_n 3454} 3455 3456static void b43_nphy_op_free(struct b43_wldev *dev) 3457{ 3458 struct b43_phy *phy = &dev->phy; 3459 struct b43_phy_n *nphy = phy->n; 3460 3461 kfree(nphy); 3462 phy->n = NULL; 3463} 3464 3465static int b43_nphy_op_init(struct b43_wldev *dev) 3466{ 3467 return b43_phy_initn(dev); 3468} 3469 3470static inline void check_phyreg(struct b43_wldev *dev, u16 offset) 3471{ 3472#if B43_DEBUG 3473 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { 3474 /* OFDM registers are onnly available on A/G-PHYs */ 3475 b43err(dev->wl, "Invalid OFDM PHY access at " 3476 "0x%04X on N-PHY\n", offset); 3477 dump_stack(); 3478 } 3479 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { 3480 /* Ext-G registers are only available on G-PHYs */ 3481 b43err(dev->wl, "Invalid EXT-G PHY access at " 3482 "0x%04X on N-PHY\n", offset); 3483 dump_stack(); 3484 } 3485#endif /* B43_DEBUG */ 3486} 3487 3488static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg) 3489{ 3490 check_phyreg(dev, reg); 3491 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); 3492 return b43_read16(dev, B43_MMIO_PHY_DATA); 3493} 3494 3495static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) 3496{ 3497 check_phyreg(dev, reg); 3498 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); 3499 b43_write16(dev, B43_MMIO_PHY_DATA, value); 3500} 3501 3502static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) 3503{ 3504 /* Register 1 is a 32-bit register. */ 3505 B43_WARN_ON(reg == 1); 3506 /* N-PHY needs 0x100 for read access */ 3507 reg |= 0x100; 3508 3509 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); 3510 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3511} 3512 3513static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) 3514{ 3515 /* Register 1 is a 32-bit register. */ 3516 B43_WARN_ON(reg == 1); 3517 3518 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); 3519 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); 3520} 3521 3522/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ 3523static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, 3524 bool blocked) 3525{ 3526 struct b43_phy_n *nphy = dev->phy.n; 3527 3528 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) 3529 b43err(dev->wl, "MAC not suspended\n"); 3530 3531 if (blocked) { 3532 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 3533 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 3534 if (dev->phy.rev >= 3) { 3535 b43_radio_mask(dev, 0x09, ~0x2); 3536 3537 b43_radio_write(dev, 0x204D, 0); 3538 b43_radio_write(dev, 0x2053, 0); 3539 b43_radio_write(dev, 0x2058, 0); 3540 b43_radio_write(dev, 0x205E, 0); 3541 b43_radio_mask(dev, 0x2062, ~0xF0); 3542 b43_radio_write(dev, 0x2064, 0); 3543 3544 b43_radio_write(dev, 0x304D, 0); 3545 b43_radio_write(dev, 0x3053, 0); 3546 b43_radio_write(dev, 0x3058, 0); 3547 b43_radio_write(dev, 0x305E, 0); 3548 b43_radio_mask(dev, 0x3062, ~0xF0); 3549 b43_radio_write(dev, 0x3064, 0); 3550 } 3551 } else { 3552 if (dev->phy.rev >= 3) { 3553 b43_radio_init2056(dev); 3554 b43_switch_channel(dev, dev->phy.channel); 3555 } else { 3556 b43_radio_init2055(dev); 3557 } 3558 } 3559} 3560 3561static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) 3562{ 3563 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 3564 on ? 0 : 0x7FFF); 3565} 3566 3567static int b43_nphy_op_switch_channel(struct b43_wldev *dev, 3568 unsigned int new_channel) 3569{ 3570 struct b43_phy_n *nphy = dev->phy.n; 3571 struct b43_chanspec chanspec; 3572 3573 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 3574 if ((new_channel < 1) || (new_channel > 14)) 3575 return -EINVAL; 3576 } else { 3577 if (new_channel > 200) 3578 return -EINVAL; 3579 } 3580 3581 chanspec = nphy->radio_chanspec; 3582 chanspec.channel = new_channel; 3583 3584 return b43_nphy_set_chanspec(dev, chanspec); 3585} 3586 3587static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) 3588{ 3589 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3590 return 1; 3591 return 36; 3592} 3593 3594const struct b43_phy_operations b43_phyops_n = { 3595 .allocate = b43_nphy_op_allocate, 3596 .free = b43_nphy_op_free, 3597 .prepare_structs = b43_nphy_op_prepare_structs, 3598 .init = b43_nphy_op_init, 3599 .phy_read = b43_nphy_op_read, 3600 .phy_write = b43_nphy_op_write, 3601 .radio_read = b43_nphy_op_radio_read, 3602 .radio_write = b43_nphy_op_radio_write, 3603 .software_rfkill = b43_nphy_op_software_rfkill, 3604 .switch_analog = b43_nphy_op_switch_analog, 3605 .switch_channel = b43_nphy_op_switch_channel, 3606 .get_default_chan = b43_nphy_op_get_default_chan, 3607 .recalc_txpower = b43_nphy_op_recalc_txpower, 3608 .adjust_txpower = b43_nphy_op_adjust_txpower, 3609}; 3610