phy_n.c revision 82a52043c7801f83c7387deb45bf9323af04644b
1/* 2 3 Broadcom B43 wireless driver 4 IEEE 802.11n PHY support 5 6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; see the file COPYING. If not, write to 20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 21 Boston, MA 02110-1301, USA. 22 23*/ 24 25#include <linux/delay.h> 26#include <linux/slab.h> 27#include <linux/types.h> 28 29#include "b43.h" 30#include "phy_n.h" 31#include "tables_nphy.h" 32#include "radio_2055.h" 33#include "radio_2056.h" 34#include "main.h" 35 36struct nphy_txgains { 37 u16 txgm[2]; 38 u16 pga[2]; 39 u16 pad[2]; 40 u16 ipa[2]; 41}; 42 43struct nphy_iqcal_params { 44 u16 txgm; 45 u16 pga; 46 u16 pad; 47 u16 ipa; 48 u16 cal_gain; 49 u16 ncorr[5]; 50}; 51 52struct nphy_iq_est { 53 s32 iq0_prod; 54 u32 i0_pwr; 55 u32 q0_pwr; 56 s32 iq1_prod; 57 u32 i1_pwr; 58 u32 q1_pwr; 59}; 60 61enum b43_nphy_rf_sequence { 62 B43_RFSEQ_RX2TX, 63 B43_RFSEQ_TX2RX, 64 B43_RFSEQ_RESET2RX, 65 B43_RFSEQ_UPDATE_GAINH, 66 B43_RFSEQ_UPDATE_GAINL, 67 B43_RFSEQ_UPDATE_GAINU, 68}; 69 70enum b43_nphy_rssi_type { 71 B43_NPHY_RSSI_X = 0, 72 B43_NPHY_RSSI_Y, 73 B43_NPHY_RSSI_Z, 74 B43_NPHY_RSSI_PWRDET, 75 B43_NPHY_RSSI_TSSI_I, 76 B43_NPHY_RSSI_TSSI_Q, 77 B43_NPHY_RSSI_TBD, 78}; 79 80static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, 81 bool enable); 82static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, 83 u8 *events, u8 *delays, u8 length); 84static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 85 enum b43_nphy_rf_sequence seq); 86static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 87 u16 value, u8 core, bool off); 88static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, 89 u16 value, u8 core); 90 91void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) 92{//TODO 93} 94 95static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev) 96{//TODO 97} 98 99static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, 100 bool ignore_tssi) 101{//TODO 102 return B43_TXPWR_RES_DONE; 103} 104 105static void b43_chantab_radio_upload(struct b43_wldev *dev, 106 const struct b43_nphy_channeltab_entry_rev2 *e) 107{ 108 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); 109 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); 110 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); 111 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); 112 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 113 114 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); 115 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); 116 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); 117 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); 118 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 119 120 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); 121 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); 122 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); 123 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); 124 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 125 126 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); 127 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); 128 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); 129 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); 130 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 131 132 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); 133 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); 134 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); 135 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); 136 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 137 138 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); 139 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); 140} 141 142static void b43_chantab_phy_upload(struct b43_wldev *dev, 143 const struct b43_phy_n_sfo_cfg *e) 144{ 145 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); 146 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); 147 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); 148 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); 149 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); 150 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); 151} 152 153/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */ 154static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) 155{ 156 struct b43_phy_n *nphy = dev->phy.n; 157 u8 i; 158 u16 tmp; 159 160 if (nphy->hang_avoid) 161 b43_nphy_stay_in_carrier_search(dev, 1); 162 163 nphy->txpwrctrl = enable; 164 if (!enable) { 165 if (dev->phy.rev >= 3) 166 ; /* TODO */ 167 168 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); 169 for (i = 0; i < 84; i++) 170 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); 171 172 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40); 173 for (i = 0; i < 84; i++) 174 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); 175 176 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; 177 if (dev->phy.rev >= 3) 178 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN; 179 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp); 180 181 if (dev->phy.rev >= 3) { 182 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); 183 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); 184 } else { 185 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); 186 } 187 188 if (dev->phy.rev == 2) 189 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 190 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53); 191 else if (dev->phy.rev < 2) 192 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 193 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A); 194 195 if (dev->phy.rev < 2 && 0) 196 ; /* TODO */ 197 } else { 198 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n"); 199 } 200 201 if (nphy->hang_avoid) 202 b43_nphy_stay_in_carrier_search(dev, 0); 203} 204 205/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */ 206static void b43_nphy_tx_power_fix(struct b43_wldev *dev) 207{ 208 struct b43_phy_n *nphy = dev->phy.n; 209 struct ssb_sprom *sprom = &(dev->dev->bus->sprom); 210 211 u8 txpi[2], bbmult, i; 212 u16 tmp, radio_gain, dac_gain; 213 u16 freq = dev->phy.channel_freq; 214 u32 txgain; 215 /* u32 gaintbl; rev3+ */ 216 217 if (nphy->hang_avoid) 218 b43_nphy_stay_in_carrier_search(dev, 1); 219 220 if (dev->phy.rev >= 3) { 221 txpi[0] = 40; 222 txpi[1] = 40; 223 } else if (sprom->revision < 4) { 224 txpi[0] = 72; 225 txpi[1] = 72; 226 } else { 227 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 228 txpi[0] = sprom->txpid2g[0]; 229 txpi[1] = sprom->txpid2g[1]; 230 } else if (freq >= 4900 && freq < 5100) { 231 txpi[0] = sprom->txpid5gl[0]; 232 txpi[1] = sprom->txpid5gl[1]; 233 } else if (freq >= 5100 && freq < 5500) { 234 txpi[0] = sprom->txpid5g[0]; 235 txpi[1] = sprom->txpid5g[1]; 236 } else if (freq >= 5500) { 237 txpi[0] = sprom->txpid5gh[0]; 238 txpi[1] = sprom->txpid5gh[1]; 239 } else { 240 txpi[0] = 91; 241 txpi[1] = 91; 242 } 243 } 244 245 /* 246 for (i = 0; i < 2; i++) { 247 nphy->txpwrindex[i].index_internal = txpi[i]; 248 nphy->txpwrindex[i].index_internal_save = txpi[i]; 249 } 250 */ 251 252 for (i = 0; i < 2; i++) { 253 if (dev->phy.rev >= 3) { 254 /* FIXME: support 5GHz */ 255 txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]]; 256 radio_gain = (txgain >> 16) & 0x1FFFF; 257 } else { 258 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]]; 259 radio_gain = (txgain >> 16) & 0x1FFF; 260 } 261 262 dac_gain = (txgain >> 8) & 0x3F; 263 bbmult = txgain & 0xFF; 264 265 if (dev->phy.rev >= 3) { 266 if (i == 0) 267 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); 268 else 269 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); 270 } else { 271 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); 272 } 273 274 if (i == 0) 275 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain); 276 else 277 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); 278 279 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i); 280 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain); 281 282 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57); 283 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); 284 285 if (i == 0) 286 tmp = (tmp & 0x00FF) | (bbmult << 8); 287 else 288 tmp = (tmp & 0xFF00) | bbmult; 289 290 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57); 291 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp); 292 293 if (0) 294 ; /* TODO */ 295 } 296 297 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); 298 299 if (nphy->hang_avoid) 300 b43_nphy_stay_in_carrier_search(dev, 0); 301} 302 303 304/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ 305static void b43_radio_2055_setup(struct b43_wldev *dev, 306 const struct b43_nphy_channeltab_entry_rev2 *e) 307{ 308 B43_WARN_ON(dev->phy.rev >= 3); 309 310 b43_chantab_radio_upload(dev, e); 311 udelay(50); 312 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); 313 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); 314 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 315 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); 316 udelay(300); 317} 318 319static void b43_radio_init2055_pre(struct b43_wldev *dev) 320{ 321 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 322 ~B43_NPHY_RFCTL_CMD_PORFORCE); 323 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 324 B43_NPHY_RFCTL_CMD_CHIP0PU | 325 B43_NPHY_RFCTL_CMD_OEPORFORCE); 326 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 327 B43_NPHY_RFCTL_CMD_PORFORCE); 328} 329 330static void b43_radio_init2055_post(struct b43_wldev *dev) 331{ 332 struct b43_phy_n *nphy = dev->phy.n; 333 struct ssb_sprom *sprom = &(dev->dev->bus->sprom); 334 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo); 335 int i; 336 u16 val; 337 bool workaround = false; 338 339 if (sprom->revision < 4) 340 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM || 341 binfo->type != 0x46D || 342 binfo->rev < 0x41); 343 else 344 workaround = 345 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS); 346 347 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); 348 if (workaround) { 349 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); 350 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); 351 } 352 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); 353 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); 354 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); 355 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); 356 b43_radio_set(dev, B2055_CAL_MISC, 0x1); 357 msleep(1); 358 b43_radio_set(dev, B2055_CAL_MISC, 0x40); 359 for (i = 0; i < 200; i++) { 360 val = b43_radio_read(dev, B2055_CAL_COUT2); 361 if (val & 0x80) { 362 i = 0; 363 break; 364 } 365 udelay(10); 366 } 367 if (i) 368 b43err(dev->wl, "radio post init timeout\n"); 369 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); 370 b43_switch_channel(dev, dev->phy.channel); 371 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); 372 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); 373 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); 374 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); 375 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); 376 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); 377 if (!nphy->gain_boost) { 378 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); 379 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); 380 } else { 381 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); 382 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); 383 } 384 udelay(2); 385} 386 387/* 388 * Initialize a Broadcom 2055 N-radio 389 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init 390 */ 391static void b43_radio_init2055(struct b43_wldev *dev) 392{ 393 b43_radio_init2055_pre(dev); 394 if (b43_status(dev) < B43_STAT_INITIALIZED) { 395 /* Follow wl, not specs. Do not force uploading all regs */ 396 b2055_upload_inittab(dev, 0, 0); 397 } else { 398 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ; 399 b2055_upload_inittab(dev, ghz5, 0); 400 } 401 b43_radio_init2055_post(dev); 402} 403 404/* 405 * Initialize a Broadcom 2056 N-radio 406 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init 407 */ 408static void b43_radio_init2056(struct b43_wldev *dev) 409{ 410 /* TODO */ 411} 412 413 414/* 415 * Upload the N-PHY tables. 416 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables 417 */ 418static void b43_nphy_tables_init(struct b43_wldev *dev) 419{ 420 if (dev->phy.rev < 3) 421 b43_nphy_rev0_1_2_tables_init(dev); 422 else 423 b43_nphy_rev3plus_tables_init(dev); 424} 425 426/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ 427static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) 428{ 429 struct b43_phy_n *nphy = dev->phy.n; 430 enum ieee80211_band band; 431 u16 tmp; 432 433 if (!enable) { 434 nphy->rfctrl_intc1_save = b43_phy_read(dev, 435 B43_NPHY_RFCTL_INTC1); 436 nphy->rfctrl_intc2_save = b43_phy_read(dev, 437 B43_NPHY_RFCTL_INTC2); 438 band = b43_current_band(dev->wl); 439 if (dev->phy.rev >= 3) { 440 if (band == IEEE80211_BAND_5GHZ) 441 tmp = 0x600; 442 else 443 tmp = 0x480; 444 } else { 445 if (band == IEEE80211_BAND_5GHZ) 446 tmp = 0x180; 447 else 448 tmp = 0x120; 449 } 450 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 451 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 452 } else { 453 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 454 nphy->rfctrl_intc1_save); 455 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 456 nphy->rfctrl_intc2_save); 457 } 458} 459 460/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ 461static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) 462{ 463 struct b43_phy_n *nphy = dev->phy.n; 464 u16 tmp; 465 enum ieee80211_band band = b43_current_band(dev->wl); 466 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) || 467 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ); 468 469 if (dev->phy.rev >= 3) { 470 if (ipa) { 471 tmp = 4; 472 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, 473 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); 474 } 475 476 tmp = 1; 477 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, 478 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); 479 } 480} 481 482/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ 483static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force) 484{ 485 u32 tmslow; 486 487 if (dev->phy.type != B43_PHYTYPE_N) 488 return; 489 490 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 491 if (force) 492 tmslow |= SSB_TMSLOW_FGC; 493 else 494 tmslow &= ~SSB_TMSLOW_FGC; 495 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 496} 497 498/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ 499static void b43_nphy_reset_cca(struct b43_wldev *dev) 500{ 501 u16 bbcfg; 502 503 b43_nphy_bmac_clock_fgc(dev, 1); 504 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); 505 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); 506 udelay(1); 507 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); 508 b43_nphy_bmac_clock_fgc(dev, 0); 509 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 510} 511 512/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ 513static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) 514{ 515 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); 516 517 mimocfg |= B43_NPHY_MIMOCFG_AUTO; 518 if (preamble == 1) 519 mimocfg |= B43_NPHY_MIMOCFG_GFMIX; 520 else 521 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; 522 523 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); 524} 525 526/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ 527static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) 528{ 529 struct b43_phy_n *nphy = dev->phy.n; 530 531 bool override = false; 532 u16 chain = 0x33; 533 534 if (nphy->txrx_chain == 0) { 535 chain = 0x11; 536 override = true; 537 } else if (nphy->txrx_chain == 1) { 538 chain = 0x22; 539 override = true; 540 } 541 542 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 543 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), 544 chain); 545 546 if (override) 547 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 548 B43_NPHY_RFSEQMODE_CAOVER); 549 else 550 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 551 ~B43_NPHY_RFSEQMODE_CAOVER); 552} 553 554/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ 555static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, 556 u16 samps, u8 time, bool wait) 557{ 558 int i; 559 u16 tmp; 560 561 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); 562 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); 563 if (wait) 564 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); 565 else 566 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); 567 568 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); 569 570 for (i = 1000; i; i--) { 571 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); 572 if (!(tmp & B43_NPHY_IQEST_CMD_START)) { 573 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | 574 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); 575 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | 576 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); 577 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | 578 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); 579 580 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | 581 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); 582 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | 583 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); 584 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | 585 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); 586 return; 587 } 588 udelay(10); 589 } 590 memset(est, 0, sizeof(*est)); 591} 592 593/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ 594static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, 595 struct b43_phy_n_iq_comp *pcomp) 596{ 597 if (write) { 598 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); 599 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); 600 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); 601 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); 602 } else { 603 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); 604 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); 605 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); 606 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); 607 } 608} 609 610#if 0 611/* Ready but not used anywhere */ 612/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ 613static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) 614{ 615 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 616 617 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); 618 if (core == 0) { 619 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); 620 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 621 } else { 622 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 623 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 624 } 625 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); 626 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); 627 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); 628 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); 629 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); 630 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); 631 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 632 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 633} 634 635/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ 636static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) 637{ 638 u8 rxval, txval; 639 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 640 641 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 642 if (core == 0) { 643 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 644 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 645 } else { 646 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 647 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 648 } 649 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 650 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 651 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); 652 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); 653 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); 654 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); 655 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 656 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 657 658 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 659 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 660 661 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 662 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 663 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 664 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 665 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); 666 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 667 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); 668 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, 669 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); 670 671 if (core == 0) { 672 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); 673 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); 674 } else { 675 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); 676 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); 677 } 678 679 b43_nphy_rf_control_intc_override(dev, 2, 0, 3); 680 b43_nphy_rf_control_override(dev, 8, 0, 3, false); 681 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 682 683 if (core == 0) { 684 rxval = 1; 685 txval = 8; 686 } else { 687 rxval = 4; 688 txval = 2; 689 } 690 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1)); 691 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core)); 692} 693#endif 694 695/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ 696static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) 697{ 698 int i; 699 s32 iq; 700 u32 ii; 701 u32 qq; 702 int iq_nbits, qq_nbits; 703 int arsh, brsh; 704 u16 tmp, a, b; 705 706 struct nphy_iq_est est; 707 struct b43_phy_n_iq_comp old; 708 struct b43_phy_n_iq_comp new = { }; 709 bool error = false; 710 711 if (mask == 0) 712 return; 713 714 b43_nphy_rx_iq_coeffs(dev, false, &old); 715 b43_nphy_rx_iq_coeffs(dev, true, &new); 716 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); 717 new = old; 718 719 for (i = 0; i < 2; i++) { 720 if (i == 0 && (mask & 1)) { 721 iq = est.iq0_prod; 722 ii = est.i0_pwr; 723 qq = est.q0_pwr; 724 } else if (i == 1 && (mask & 2)) { 725 iq = est.iq1_prod; 726 ii = est.i1_pwr; 727 qq = est.q1_pwr; 728 } else { 729 continue; 730 } 731 732 if (ii + qq < 2) { 733 error = true; 734 break; 735 } 736 737 iq_nbits = fls(abs(iq)); 738 qq_nbits = fls(qq); 739 740 arsh = iq_nbits - 20; 741 if (arsh >= 0) { 742 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); 743 tmp = ii >> arsh; 744 } else { 745 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); 746 tmp = ii << -arsh; 747 } 748 if (tmp == 0) { 749 error = true; 750 break; 751 } 752 a /= tmp; 753 754 brsh = qq_nbits - 11; 755 if (brsh >= 0) { 756 b = (qq << (31 - qq_nbits)); 757 tmp = ii >> brsh; 758 } else { 759 b = (qq << (31 - qq_nbits)); 760 tmp = ii << -brsh; 761 } 762 if (tmp == 0) { 763 error = true; 764 break; 765 } 766 b = int_sqrt(b / tmp - a * a) - (1 << 10); 767 768 if (i == 0 && (mask & 0x1)) { 769 if (dev->phy.rev >= 3) { 770 new.a0 = a & 0x3FF; 771 new.b0 = b & 0x3FF; 772 } else { 773 new.a0 = b & 0x3FF; 774 new.b0 = a & 0x3FF; 775 } 776 } else if (i == 1 && (mask & 0x2)) { 777 if (dev->phy.rev >= 3) { 778 new.a1 = a & 0x3FF; 779 new.b1 = b & 0x3FF; 780 } else { 781 new.a1 = b & 0x3FF; 782 new.b1 = a & 0x3FF; 783 } 784 } 785 } 786 787 if (error) 788 new = old; 789 790 b43_nphy_rx_iq_coeffs(dev, true, &new); 791} 792 793/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ 794static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) 795{ 796 u16 array[4]; 797 int i; 798 799 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50); 800 for (i = 0; i < 4; i++) 801 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); 802 803 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); 804 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); 805 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); 806 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); 807} 808 809/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 810static void b43_nphy_write_clip_detection(struct b43_wldev *dev, 811 const u16 *clip_st) 812{ 813 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); 814 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); 815} 816 817/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 818static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) 819{ 820 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); 821 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); 822} 823 824/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ 825static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) 826{ 827 if (dev->phy.rev >= 3) { 828 if (!init) 829 return; 830 if (0 /* FIXME */) { 831 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); 832 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); 833 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); 834 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); 835 } 836 } else { 837 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); 838 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); 839 840 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00, 841 0xFC00); 842 b43_write32(dev, B43_MMIO_MACCTL, 843 b43_read32(dev, B43_MMIO_MACCTL) & 844 ~B43_MACCTL_GPOUTSMSK); 845 b43_write16(dev, B43_MMIO_GPIO_MASK, 846 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00); 847 b43_write16(dev, B43_MMIO_GPIO_CONTROL, 848 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00); 849 850 if (init) { 851 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 852 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 853 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 854 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 855 } 856 } 857} 858 859/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ 860static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) 861{ 862 u16 tmp; 863 864 if (dev->dev->id.revision == 16) 865 b43_mac_suspend(dev); 866 867 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); 868 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | 869 B43_NPHY_CLASSCTL_WAITEDEN); 870 tmp &= ~mask; 871 tmp |= (val & mask); 872 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); 873 874 if (dev->dev->id.revision == 16) 875 b43_mac_enable(dev); 876 877 return tmp; 878} 879 880/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ 881static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) 882{ 883 struct b43_phy *phy = &dev->phy; 884 struct b43_phy_n *nphy = phy->n; 885 886 if (enable) { 887 static const u16 clip[] = { 0xFFFF, 0xFFFF }; 888 if (nphy->deaf_count++ == 0) { 889 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); 890 b43_nphy_classifier(dev, 0x7, 0); 891 b43_nphy_read_clip_detection(dev, nphy->clip_state); 892 b43_nphy_write_clip_detection(dev, clip); 893 } 894 b43_nphy_reset_cca(dev); 895 } else { 896 if (--nphy->deaf_count == 0) { 897 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); 898 b43_nphy_write_clip_detection(dev, nphy->clip_state); 899 } 900 } 901} 902 903/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ 904static void b43_nphy_stop_playback(struct b43_wldev *dev) 905{ 906 struct b43_phy_n *nphy = dev->phy.n; 907 u16 tmp; 908 909 if (nphy->hang_avoid) 910 b43_nphy_stay_in_carrier_search(dev, 1); 911 912 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); 913 if (tmp & 0x1) 914 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); 915 else if (tmp & 0x2) 916 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 917 918 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); 919 920 if (nphy->bb_mult_save & 0x80000000) { 921 tmp = nphy->bb_mult_save & 0xFFFF; 922 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 923 nphy->bb_mult_save = 0; 924 } 925 926 if (nphy->hang_avoid) 927 b43_nphy_stay_in_carrier_search(dev, 0); 928} 929 930/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ 931static void b43_nphy_spur_workaround(struct b43_wldev *dev) 932{ 933 struct b43_phy_n *nphy = dev->phy.n; 934 935 u8 channel = dev->phy.channel; 936 int tone[2] = { 57, 58 }; 937 u32 noise[2] = { 0x3FF, 0x3FF }; 938 939 B43_WARN_ON(dev->phy.rev < 3); 940 941 if (nphy->hang_avoid) 942 b43_nphy_stay_in_carrier_search(dev, 1); 943 944 if (nphy->gband_spurwar_en) { 945 /* TODO: N PHY Adjust Analog Pfbw (7) */ 946 if (channel == 11 && dev->phy.is_40mhz) 947 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ 948 else 949 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 950 /* TODO: N PHY Adjust CRS Min Power (0x1E) */ 951 } 952 953 if (nphy->aband_spurwar_en) { 954 if (channel == 54) { 955 tone[0] = 0x20; 956 noise[0] = 0x25F; 957 } else if (channel == 38 || channel == 102 || channel == 118) { 958 if (0 /* FIXME */) { 959 tone[0] = 0x20; 960 noise[0] = 0x21F; 961 } else { 962 tone[0] = 0; 963 noise[0] = 0; 964 } 965 } else if (channel == 134) { 966 tone[0] = 0x20; 967 noise[0] = 0x21F; 968 } else if (channel == 151) { 969 tone[0] = 0x10; 970 noise[0] = 0x23F; 971 } else if (channel == 153 || channel == 161) { 972 tone[0] = 0x30; 973 noise[0] = 0x23F; 974 } else { 975 tone[0] = 0; 976 noise[0] = 0; 977 } 978 979 if (!tone[0] && !noise[0]) 980 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ 981 else 982 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 983 } 984 985 if (nphy->hang_avoid) 986 b43_nphy_stay_in_carrier_search(dev, 0); 987} 988 989/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ 990static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) 991{ 992 struct b43_phy_n *nphy = dev->phy.n; 993 994 u8 i; 995 s16 tmp; 996 u16 data[4]; 997 s16 gain[2]; 998 u16 minmax[2]; 999 static const u16 lna_gain[4] = { -2, 10, 19, 25 }; 1000 1001 if (nphy->hang_avoid) 1002 b43_nphy_stay_in_carrier_search(dev, 1); 1003 1004 if (nphy->gain_boost) { 1005 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 1006 gain[0] = 6; 1007 gain[1] = 6; 1008 } else { 1009 tmp = 40370 - 315 * dev->phy.channel; 1010 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); 1011 tmp = 23242 - 224 * dev->phy.channel; 1012 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); 1013 } 1014 } else { 1015 gain[0] = 0; 1016 gain[1] = 0; 1017 } 1018 1019 for (i = 0; i < 2; i++) { 1020 if (nphy->elna_gain_config) { 1021 data[0] = 19 + gain[i]; 1022 data[1] = 25 + gain[i]; 1023 data[2] = 25 + gain[i]; 1024 data[3] = 25 + gain[i]; 1025 } else { 1026 data[0] = lna_gain[0] + gain[i]; 1027 data[1] = lna_gain[1] + gain[i]; 1028 data[2] = lna_gain[2] + gain[i]; 1029 data[3] = lna_gain[3] + gain[i]; 1030 } 1031 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data); 1032 1033 minmax[i] = 23 + gain[i]; 1034 } 1035 1036 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, 1037 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT); 1038 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, 1039 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT); 1040 1041 if (nphy->hang_avoid) 1042 b43_nphy_stay_in_carrier_search(dev, 0); 1043} 1044 1045/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ 1046static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) 1047{ 1048 struct b43_phy_n *nphy = dev->phy.n; 1049 u8 i, j; 1050 u8 code; 1051 u16 tmp; 1052 1053 /* TODO: for PHY >= 3 1054 s8 *lna1_gain, *lna2_gain; 1055 u8 *gain_db, *gain_bits; 1056 u16 *rfseq_init; 1057 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; 1058 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; 1059 */ 1060 1061 u8 rfseq_events[3] = { 6, 8, 7 }; 1062 u8 rfseq_delays[3] = { 10, 30, 1 }; 1063 1064 if (dev->phy.rev >= 3) { 1065 /* TODO */ 1066 } else { 1067 /* Set Clip 2 detect */ 1068 b43_phy_set(dev, B43_NPHY_C1_CGAINI, 1069 B43_NPHY_C1_CGAINI_CL2DETECT); 1070 b43_phy_set(dev, B43_NPHY_C2_CGAINI, 1071 B43_NPHY_C2_CGAINI_CL2DETECT); 1072 1073 /* Set narrowband clip threshold */ 1074 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); 1075 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); 1076 1077 if (!dev->phy.is_40mhz) { 1078 /* Set dwell lengths */ 1079 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); 1080 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); 1081 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); 1082 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); 1083 } 1084 1085 /* Set wideband clip 2 threshold */ 1086 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 1087 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 1088 21); 1089 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, 1090 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 1091 21); 1092 1093 if (!dev->phy.is_40mhz) { 1094 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, 1095 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); 1096 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, 1097 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); 1098 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, 1099 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); 1100 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, 1101 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); 1102 } 1103 1104 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); 1105 1106 if (nphy->gain_boost) { 1107 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && 1108 dev->phy.is_40mhz) 1109 code = 4; 1110 else 1111 code = 5; 1112 } else { 1113 code = dev->phy.is_40mhz ? 6 : 7; 1114 } 1115 1116 /* Set HPVGA2 index */ 1117 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, 1118 ~B43_NPHY_C1_INITGAIN_HPVGA2, 1119 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); 1120 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, 1121 ~B43_NPHY_C2_INITGAIN_HPVGA2, 1122 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); 1123 1124 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 1125 /* specs say about 2 loops, but wl does 4 */ 1126 for (i = 0; i < 4; i++) 1127 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1128 (code << 8 | 0x7C)); 1129 1130 b43_nphy_adjust_lna_gain_table(dev); 1131 1132 if (nphy->elna_gain_config) { 1133 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); 1134 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 1135 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 1136 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 1137 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 1138 1139 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); 1140 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 1141 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 1142 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 1143 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 1144 1145 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 1146 /* specs say about 2 loops, but wl does 4 */ 1147 for (i = 0; i < 4; i++) 1148 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1149 (code << 8 | 0x74)); 1150 } 1151 1152 if (dev->phy.rev == 2) { 1153 for (i = 0; i < 4; i++) { 1154 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1155 (0x0400 * i) + 0x0020); 1156 for (j = 0; j < 21; j++) { 1157 tmp = j * (i < 2 ? 3 : 1); 1158 b43_phy_write(dev, 1159 B43_NPHY_TABLE_DATALO, tmp); 1160 } 1161 } 1162 1163 b43_nphy_set_rf_sequence(dev, 5, 1164 rfseq_events, rfseq_delays, 3); 1165 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, 1166 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, 1167 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); 1168 1169 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 1170 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 1171 0xFF80, 4); 1172 } 1173 } 1174} 1175 1176/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ 1177static void b43_nphy_workarounds(struct b43_wldev *dev) 1178{ 1179 struct ssb_bus *bus = dev->dev->bus; 1180 struct b43_phy *phy = &dev->phy; 1181 struct b43_phy_n *nphy = phy->n; 1182 1183 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; 1184 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; 1185 1186 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; 1187 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; 1188 1189 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 1190 b43_nphy_classifier(dev, 1, 0); 1191 else 1192 b43_nphy_classifier(dev, 1, 1); 1193 1194 if (nphy->hang_avoid) 1195 b43_nphy_stay_in_carrier_search(dev, 1); 1196 1197 b43_phy_set(dev, B43_NPHY_IQFLIP, 1198 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); 1199 1200 if (dev->phy.rev >= 3) { 1201 /* TODO */ 1202 } else { 1203 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && 1204 nphy->band5g_pwrgain) { 1205 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); 1206 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); 1207 } else { 1208 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); 1209 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); 1210 } 1211 1212 /* TODO: convert to b43_ntab_write? */ 1213 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000); 1214 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); 1215 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010); 1216 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); 1217 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002); 1218 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); 1219 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012); 1220 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); 1221 1222 if (dev->phy.rev < 2) { 1223 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008); 1224 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); 1225 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018); 1226 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); 1227 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007); 1228 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); 1229 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017); 1230 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); 1231 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006); 1232 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); 1233 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016); 1234 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); 1235 } 1236 1237 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 1238 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 1239 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 1240 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 1241 1242 if (bus->sprom.boardflags2_lo & 0x100 && 1243 bus->boardinfo.type == 0x8B) { 1244 delays1[0] = 0x1; 1245 delays1[5] = 0x14; 1246 } 1247 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); 1248 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); 1249 1250 b43_nphy_gain_ctrl_workarounds(dev); 1251 1252 if (dev->phy.rev < 2) { 1253 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) 1254 b43_hf_write(dev, b43_hf_read(dev) | 1255 B43_HF_MLADVW); 1256 } else if (dev->phy.rev == 2) { 1257 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); 1258 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); 1259 } 1260 1261 if (dev->phy.rev < 2) 1262 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, 1263 ~B43_NPHY_SCRAM_SIGCTL_SCM); 1264 1265 /* Set phase track alpha and beta */ 1266 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); 1267 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); 1268 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); 1269 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); 1270 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); 1271 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); 1272 1273 b43_phy_mask(dev, B43_NPHY_PIL_DW1, 1274 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); 1275 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); 1276 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); 1277 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); 1278 1279 if (dev->phy.rev == 2) 1280 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 1281 B43_NPHY_FINERX2_CGC_DECGC); 1282 } 1283 1284 if (nphy->hang_avoid) 1285 b43_nphy_stay_in_carrier_search(dev, 0); 1286} 1287 1288/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ 1289static int b43_nphy_load_samples(struct b43_wldev *dev, 1290 struct b43_c32 *samples, u16 len) { 1291 struct b43_phy_n *nphy = dev->phy.n; 1292 u16 i; 1293 u32 *data; 1294 1295 data = kzalloc(len * sizeof(u32), GFP_KERNEL); 1296 if (!data) { 1297 b43err(dev->wl, "allocation for samples loading failed\n"); 1298 return -ENOMEM; 1299 } 1300 if (nphy->hang_avoid) 1301 b43_nphy_stay_in_carrier_search(dev, 1); 1302 1303 for (i = 0; i < len; i++) { 1304 data[i] = (samples[i].i & 0x3FF << 10); 1305 data[i] |= samples[i].q & 0x3FF; 1306 } 1307 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); 1308 1309 kfree(data); 1310 if (nphy->hang_avoid) 1311 b43_nphy_stay_in_carrier_search(dev, 0); 1312 return 0; 1313} 1314 1315/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ 1316static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, 1317 bool test) 1318{ 1319 int i; 1320 u16 bw, len, rot, angle; 1321 struct b43_c32 *samples; 1322 1323 1324 bw = (dev->phy.is_40mhz) ? 40 : 20; 1325 len = bw << 3; 1326 1327 if (test) { 1328 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) 1329 bw = 82; 1330 else 1331 bw = 80; 1332 1333 if (dev->phy.is_40mhz) 1334 bw <<= 1; 1335 1336 len = bw << 1; 1337 } 1338 1339 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL); 1340 if (!samples) { 1341 b43err(dev->wl, "allocation for samples generation failed\n"); 1342 return 0; 1343 } 1344 rot = (((freq * 36) / bw) << 16) / 100; 1345 angle = 0; 1346 1347 for (i = 0; i < len; i++) { 1348 samples[i] = b43_cordic(angle); 1349 angle += rot; 1350 samples[i].q = CORDIC_CONVERT(samples[i].q * max); 1351 samples[i].i = CORDIC_CONVERT(samples[i].i * max); 1352 } 1353 1354 i = b43_nphy_load_samples(dev, samples, len); 1355 kfree(samples); 1356 return (i < 0) ? 0 : len; 1357} 1358 1359/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ 1360static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, 1361 u16 wait, bool iqmode, bool dac_test) 1362{ 1363 struct b43_phy_n *nphy = dev->phy.n; 1364 int i; 1365 u16 seq_mode; 1366 u32 tmp; 1367 1368 if (nphy->hang_avoid) 1369 b43_nphy_stay_in_carrier_search(dev, true); 1370 1371 if ((nphy->bb_mult_save & 0x80000000) == 0) { 1372 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); 1373 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; 1374 } 1375 1376 if (!dev->phy.is_40mhz) 1377 tmp = 0x6464; 1378 else 1379 tmp = 0x4747; 1380 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 1381 1382 if (nphy->hang_avoid) 1383 b43_nphy_stay_in_carrier_search(dev, false); 1384 1385 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); 1386 1387 if (loops != 0xFFFF) 1388 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); 1389 else 1390 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); 1391 1392 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); 1393 1394 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 1395 1396 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); 1397 if (iqmode) { 1398 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 1399 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); 1400 } else { 1401 if (dac_test) 1402 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5); 1403 else 1404 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1); 1405 } 1406 for (i = 0; i < 100; i++) { 1407 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) { 1408 i = 0; 1409 break; 1410 } 1411 udelay(10); 1412 } 1413 if (i) 1414 b43err(dev->wl, "run samples timeout\n"); 1415 1416 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 1417} 1418 1419/* 1420 * Transmits a known value for LO calibration 1421 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone 1422 */ 1423static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, 1424 bool iqmode, bool dac_test) 1425{ 1426 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); 1427 if (samp == 0) 1428 return -1; 1429 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test); 1430 return 0; 1431} 1432 1433/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ 1434static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) 1435{ 1436 struct b43_phy_n *nphy = dev->phy.n; 1437 int i, j; 1438 u32 tmp; 1439 u32 cur_real, cur_imag, real_part, imag_part; 1440 1441 u16 buffer[7]; 1442 1443 if (nphy->hang_avoid) 1444 b43_nphy_stay_in_carrier_search(dev, true); 1445 1446 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 1447 1448 for (i = 0; i < 2; i++) { 1449 tmp = ((buffer[i * 2] & 0x3FF) << 10) | 1450 (buffer[i * 2 + 1] & 0x3FF); 1451 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1452 (((i + 26) << 10) | 320)); 1453 for (j = 0; j < 128; j++) { 1454 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 1455 ((tmp >> 16) & 0xFFFF)); 1456 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1457 (tmp & 0xFFFF)); 1458 } 1459 } 1460 1461 for (i = 0; i < 2; i++) { 1462 tmp = buffer[5 + i]; 1463 real_part = (tmp >> 8) & 0xFF; 1464 imag_part = (tmp & 0xFF); 1465 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 1466 (((i + 26) << 10) | 448)); 1467 1468 if (dev->phy.rev >= 3) { 1469 cur_real = real_part; 1470 cur_imag = imag_part; 1471 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); 1472 } 1473 1474 for (j = 0; j < 128; j++) { 1475 if (dev->phy.rev < 3) { 1476 cur_real = (real_part * loscale[j] + 128) >> 8; 1477 cur_imag = (imag_part * loscale[j] + 128) >> 8; 1478 tmp = ((cur_real & 0xFF) << 8) | 1479 (cur_imag & 0xFF); 1480 } 1481 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 1482 ((tmp >> 16) & 0xFFFF)); 1483 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 1484 (tmp & 0xFFFF)); 1485 } 1486 } 1487 1488 if (dev->phy.rev >= 3) { 1489 b43_shm_write16(dev, B43_SHM_SHARED, 1490 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); 1491 b43_shm_write16(dev, B43_SHM_SHARED, 1492 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); 1493 } 1494 1495 if (nphy->hang_avoid) 1496 b43_nphy_stay_in_carrier_search(dev, false); 1497} 1498 1499/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ 1500static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, 1501 u8 *events, u8 *delays, u8 length) 1502{ 1503 struct b43_phy_n *nphy = dev->phy.n; 1504 u8 i; 1505 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; 1506 u16 offset1 = cmd << 4; 1507 u16 offset2 = offset1 + 0x80; 1508 1509 if (nphy->hang_avoid) 1510 b43_nphy_stay_in_carrier_search(dev, true); 1511 1512 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); 1513 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); 1514 1515 for (i = length; i < 16; i++) { 1516 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); 1517 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); 1518 } 1519 1520 if (nphy->hang_avoid) 1521 b43_nphy_stay_in_carrier_search(dev, false); 1522} 1523 1524/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ 1525static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 1526 enum b43_nphy_rf_sequence seq) 1527{ 1528 static const u16 trigger[] = { 1529 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, 1530 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, 1531 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, 1532 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, 1533 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, 1534 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, 1535 }; 1536 int i; 1537 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 1538 1539 B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); 1540 1541 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 1542 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); 1543 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); 1544 for (i = 0; i < 200; i++) { 1545 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) 1546 goto ok; 1547 msleep(1); 1548 } 1549 b43err(dev->wl, "RF sequence status timeout\n"); 1550ok: 1551 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 1552} 1553 1554/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ 1555static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 1556 u16 value, u8 core, bool off) 1557{ 1558 int i; 1559 u8 index = fls(field); 1560 u8 addr, en_addr, val_addr; 1561 /* we expect only one bit set */ 1562 B43_WARN_ON(field & (~(1 << (index - 1)))); 1563 1564 if (dev->phy.rev >= 3) { 1565 const struct nphy_rf_control_override_rev3 *rf_ctrl; 1566 for (i = 0; i < 2; i++) { 1567 if (index == 0 || index == 16) { 1568 b43err(dev->wl, 1569 "Unsupported RF Ctrl Override call\n"); 1570 return; 1571 } 1572 1573 rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; 1574 en_addr = B43_PHY_N((i == 0) ? 1575 rf_ctrl->en_addr0 : rf_ctrl->en_addr1); 1576 val_addr = B43_PHY_N((i == 0) ? 1577 rf_ctrl->val_addr0 : rf_ctrl->val_addr1); 1578 1579 if (off) { 1580 b43_phy_mask(dev, en_addr, ~(field)); 1581 b43_phy_mask(dev, val_addr, 1582 ~(rf_ctrl->val_mask)); 1583 } else { 1584 if (core == 0 || ((1 << core) & i) != 0) { 1585 b43_phy_set(dev, en_addr, field); 1586 b43_phy_maskset(dev, val_addr, 1587 ~(rf_ctrl->val_mask), 1588 (value << rf_ctrl->val_shift)); 1589 } 1590 } 1591 } 1592 } else { 1593 const struct nphy_rf_control_override_rev2 *rf_ctrl; 1594 if (off) { 1595 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); 1596 value = 0; 1597 } else { 1598 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); 1599 } 1600 1601 for (i = 0; i < 2; i++) { 1602 if (index <= 1 || index == 16) { 1603 b43err(dev->wl, 1604 "Unsupported RF Ctrl Override call\n"); 1605 return; 1606 } 1607 1608 if (index == 2 || index == 10 || 1609 (index >= 13 && index <= 15)) { 1610 core = 1; 1611 } 1612 1613 rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; 1614 addr = B43_PHY_N((i == 0) ? 1615 rf_ctrl->addr0 : rf_ctrl->addr1); 1616 1617 if ((core & (1 << i)) != 0) 1618 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), 1619 (value << rf_ctrl->shift)); 1620 1621 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); 1622 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1623 B43_NPHY_RFCTL_CMD_START); 1624 udelay(1); 1625 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); 1626 } 1627 } 1628} 1629 1630/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ 1631static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, 1632 u16 value, u8 core) 1633{ 1634 u8 i, j; 1635 u16 reg, tmp, val; 1636 1637 B43_WARN_ON(dev->phy.rev < 3); 1638 B43_WARN_ON(field > 4); 1639 1640 for (i = 0; i < 2; i++) { 1641 if ((core == 1 && i == 1) || (core == 2 && !i)) 1642 continue; 1643 1644 reg = (i == 0) ? 1645 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 1646 b43_phy_mask(dev, reg, 0xFBFF); 1647 1648 switch (field) { 1649 case 0: 1650 b43_phy_write(dev, reg, 0); 1651 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 1652 break; 1653 case 1: 1654 if (!i) { 1655 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, 1656 0xFC3F, (value << 6)); 1657 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, 1658 0xFFFE, 1); 1659 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1660 B43_NPHY_RFCTL_CMD_START); 1661 for (j = 0; j < 100; j++) { 1662 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) { 1663 j = 0; 1664 break; 1665 } 1666 udelay(10); 1667 } 1668 if (j) 1669 b43err(dev->wl, 1670 "intc override timeout\n"); 1671 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, 1672 0xFFFE); 1673 } else { 1674 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, 1675 0xFC3F, (value << 6)); 1676 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 1677 0xFFFE, 1); 1678 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1679 B43_NPHY_RFCTL_CMD_RXTX); 1680 for (j = 0; j < 100; j++) { 1681 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) { 1682 j = 0; 1683 break; 1684 } 1685 udelay(10); 1686 } 1687 if (j) 1688 b43err(dev->wl, 1689 "intc override timeout\n"); 1690 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 1691 0xFFFE); 1692 } 1693 break; 1694 case 2: 1695 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1696 tmp = 0x0020; 1697 val = value << 5; 1698 } else { 1699 tmp = 0x0010; 1700 val = value << 4; 1701 } 1702 b43_phy_maskset(dev, reg, ~tmp, val); 1703 break; 1704 case 3: 1705 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1706 tmp = 0x0001; 1707 val = value; 1708 } else { 1709 tmp = 0x0004; 1710 val = value << 2; 1711 } 1712 b43_phy_maskset(dev, reg, ~tmp, val); 1713 break; 1714 case 4: 1715 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1716 tmp = 0x0002; 1717 val = value << 1; 1718 } else { 1719 tmp = 0x0008; 1720 val = value << 3; 1721 } 1722 b43_phy_maskset(dev, reg, ~tmp, val); 1723 break; 1724 } 1725 } 1726} 1727 1728/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */ 1729static void b43_nphy_bphy_init(struct b43_wldev *dev) 1730{ 1731 unsigned int i; 1732 u16 val; 1733 1734 val = 0x1E1F; 1735 for (i = 0; i < 16; i++) { 1736 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); 1737 val -= 0x202; 1738 } 1739 val = 0x3E3F; 1740 for (i = 0; i < 16; i++) { 1741 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); 1742 val -= 0x202; 1743 } 1744 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); 1745} 1746 1747/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ 1748static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, 1749 s8 offset, u8 core, u8 rail, 1750 enum b43_nphy_rssi_type type) 1751{ 1752 u16 tmp; 1753 bool core1or5 = (core == 1) || (core == 5); 1754 bool core2or5 = (core == 2) || (core == 5); 1755 1756 offset = clamp_val(offset, -32, 31); 1757 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); 1758 1759 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) 1760 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); 1761 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) 1762 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); 1763 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) 1764 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); 1765 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) 1766 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); 1767 1768 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) 1769 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); 1770 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) 1771 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); 1772 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) 1773 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); 1774 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) 1775 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); 1776 1777 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) 1778 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); 1779 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) 1780 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); 1781 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) 1782 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); 1783 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) 1784 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); 1785 1786 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) 1787 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); 1788 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) 1789 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); 1790 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) 1791 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); 1792 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) 1793 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); 1794 1795 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) 1796 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); 1797 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) 1798 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); 1799 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) 1800 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); 1801 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) 1802 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); 1803 1804 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I)) 1805 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); 1806 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I)) 1807 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); 1808 1809 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q)) 1810 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); 1811 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q)) 1812 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); 1813} 1814 1815static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1816{ 1817 u16 val; 1818 1819 if (type < 3) 1820 val = 0; 1821 else if (type == 6) 1822 val = 1; 1823 else if (type == 3) 1824 val = 2; 1825 else 1826 val = 3; 1827 1828 val = (val << 12) | (val << 14); 1829 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); 1830 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); 1831 1832 if (type < 3) { 1833 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, 1834 (type + 1) << 4); 1835 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, 1836 (type + 1) << 4); 1837 } 1838 1839 if (code == 0) { 1840 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); 1841 if (type < 3) { 1842 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1843 ~(B43_NPHY_RFCTL_CMD_RXEN | 1844 B43_NPHY_RFCTL_CMD_CORESEL)); 1845 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 1846 ~(0x1 << 12 | 1847 0x1 << 5 | 1848 0x1 << 1 | 1849 0x1)); 1850 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1851 ~B43_NPHY_RFCTL_CMD_START); 1852 udelay(20); 1853 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); 1854 } 1855 } else { 1856 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); 1857 if (type < 3) { 1858 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 1859 ~(B43_NPHY_RFCTL_CMD_RXEN | 1860 B43_NPHY_RFCTL_CMD_CORESEL), 1861 (B43_NPHY_RFCTL_CMD_RXEN | 1862 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT)); 1863 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 1864 (0x1 << 12 | 1865 0x1 << 5 | 1866 0x1 << 1 | 1867 0x1)); 1868 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1869 B43_NPHY_RFCTL_CMD_START); 1870 udelay(20); 1871 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); 1872 } 1873 } 1874} 1875 1876static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1877{ 1878 struct b43_phy_n *nphy = dev->phy.n; 1879 u8 i; 1880 u16 reg, val; 1881 1882 if (code == 0) { 1883 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); 1884 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); 1885 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); 1886 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); 1887 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); 1888 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); 1889 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); 1890 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); 1891 } else { 1892 for (i = 0; i < 2; i++) { 1893 if ((code == 1 && i == 1) || (code == 2 && !i)) 1894 continue; 1895 1896 reg = (i == 0) ? 1897 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; 1898 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); 1899 1900 if (type < 3) { 1901 reg = (i == 0) ? 1902 B43_NPHY_AFECTL_C1 : 1903 B43_NPHY_AFECTL_C2; 1904 b43_phy_maskset(dev, reg, 0xFCFF, 0); 1905 1906 reg = (i == 0) ? 1907 B43_NPHY_RFCTL_LUT_TRSW_UP1 : 1908 B43_NPHY_RFCTL_LUT_TRSW_UP2; 1909 b43_phy_maskset(dev, reg, 0xFFC3, 0); 1910 1911 if (type == 0) 1912 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; 1913 else if (type == 1) 1914 val = 16; 1915 else 1916 val = 32; 1917 b43_phy_set(dev, reg, val); 1918 1919 reg = (i == 0) ? 1920 B43_NPHY_TXF_40CO_B1S0 : 1921 B43_NPHY_TXF_40CO_B32S1; 1922 b43_phy_set(dev, reg, 0x0020); 1923 } else { 1924 if (type == 6) 1925 val = 0x0100; 1926 else if (type == 3) 1927 val = 0x0200; 1928 else 1929 val = 0x0300; 1930 1931 reg = (i == 0) ? 1932 B43_NPHY_AFECTL_C1 : 1933 B43_NPHY_AFECTL_C2; 1934 1935 b43_phy_maskset(dev, reg, 0xFCFF, val); 1936 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); 1937 1938 if (type != 3 && type != 6) { 1939 enum ieee80211_band band = 1940 b43_current_band(dev->wl); 1941 1942 if ((nphy->ipa2g_on && 1943 band == IEEE80211_BAND_2GHZ) || 1944 (nphy->ipa5g_on && 1945 band == IEEE80211_BAND_5GHZ)) 1946 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; 1947 else 1948 val = 0x11; 1949 reg = (i == 0) ? 0x2000 : 0x3000; 1950 reg |= B2055_PADDRV; 1951 b43_radio_write16(dev, reg, val); 1952 1953 reg = (i == 0) ? 1954 B43_NPHY_AFECTL_OVER1 : 1955 B43_NPHY_AFECTL_OVER; 1956 b43_phy_set(dev, reg, 0x0200); 1957 } 1958 } 1959 } 1960 } 1961} 1962 1963/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ 1964static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1965{ 1966 if (dev->phy.rev >= 3) 1967 b43_nphy_rev3_rssi_select(dev, code, type); 1968 else 1969 b43_nphy_rev2_rssi_select(dev, code, type); 1970} 1971 1972/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ 1973static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) 1974{ 1975 int i; 1976 for (i = 0; i < 2; i++) { 1977 if (type == 2) { 1978 if (i == 0) { 1979 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, 1980 0xFC, buf[0]); 1981 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1982 0xFC, buf[1]); 1983 } else { 1984 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, 1985 0xFC, buf[2 * i]); 1986 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1987 0xFC, buf[2 * i + 1]); 1988 } 1989 } else { 1990 if (i == 0) 1991 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1992 0xF3, buf[0] << 2); 1993 else 1994 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1995 0xF3, buf[2 * i + 1] << 2); 1996 } 1997 } 1998} 1999 2000/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ 2001static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, 2002 u8 nsamp) 2003{ 2004 int i; 2005 int out; 2006 u16 save_regs_phy[9]; 2007 u16 s[2]; 2008 2009 if (dev->phy.rev >= 3) { 2010 save_regs_phy[0] = b43_phy_read(dev, 2011 B43_NPHY_RFCTL_LUT_TRSW_UP1); 2012 save_regs_phy[1] = b43_phy_read(dev, 2013 B43_NPHY_RFCTL_LUT_TRSW_UP2); 2014 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 2015 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 2016 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 2017 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2018 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); 2019 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); 2020 } else if (dev->phy.rev == 2) { 2021 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 2022 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 2023 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2024 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD); 2025 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); 2026 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); 2027 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); 2028 } 2029 2030 b43_nphy_rssi_select(dev, 5, type); 2031 2032 if (dev->phy.rev < 2) { 2033 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); 2034 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); 2035 } 2036 2037 for (i = 0; i < 4; i++) 2038 buf[i] = 0; 2039 2040 for (i = 0; i < nsamp; i++) { 2041 if (dev->phy.rev < 2) { 2042 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); 2043 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); 2044 } else { 2045 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); 2046 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); 2047 } 2048 2049 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; 2050 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; 2051 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; 2052 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; 2053 } 2054 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | 2055 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); 2056 2057 if (dev->phy.rev < 2) 2058 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); 2059 2060 if (dev->phy.rev >= 3) { 2061 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 2062 save_regs_phy[0]); 2063 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 2064 save_regs_phy[1]); 2065 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]); 2066 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]); 2067 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); 2068 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); 2069 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); 2070 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); 2071 } else if (dev->phy.rev == 2) { 2072 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); 2073 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); 2074 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]); 2075 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]); 2076 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]); 2077 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); 2078 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); 2079 } 2080 2081 return out; 2082} 2083 2084/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ 2085static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) 2086{ 2087 int i, j; 2088 u8 state[4]; 2089 u8 code, val; 2090 u16 class, override; 2091 u8 regs_save_radio[2]; 2092 u16 regs_save_phy[2]; 2093 2094 s8 offset[4]; 2095 u8 core; 2096 u8 rail; 2097 2098 u16 clip_state[2]; 2099 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; 2100 s32 results_min[4] = { }; 2101 u8 vcm_final[4] = { }; 2102 s32 results[4][4] = { }; 2103 s32 miniq[4][2] = { }; 2104 2105 if (type == 2) { 2106 code = 0; 2107 val = 6; 2108 } else if (type < 2) { 2109 code = 25; 2110 val = 4; 2111 } else { 2112 B43_WARN_ON(1); 2113 return; 2114 } 2115 2116 class = b43_nphy_classifier(dev, 0, 0); 2117 b43_nphy_classifier(dev, 7, 4); 2118 b43_nphy_read_clip_detection(dev, clip_state); 2119 b43_nphy_write_clip_detection(dev, clip_off); 2120 2121 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 2122 override = 0x140; 2123 else 2124 override = 0x110; 2125 2126 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2127 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); 2128 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); 2129 b43_radio_write16(dev, B2055_C1_PD_RXTX, val); 2130 2131 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2132 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); 2133 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); 2134 b43_radio_write16(dev, B2055_C2_PD_RXTX, val); 2135 2136 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; 2137 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; 2138 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); 2139 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); 2140 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; 2141 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; 2142 2143 b43_nphy_rssi_select(dev, 5, type); 2144 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); 2145 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); 2146 2147 for (i = 0; i < 4; i++) { 2148 u8 tmp[4]; 2149 for (j = 0; j < 4; j++) 2150 tmp[j] = i; 2151 if (type != 1) 2152 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); 2153 b43_nphy_poll_rssi(dev, type, results[i], 8); 2154 if (type < 2) 2155 for (j = 0; j < 2; j++) 2156 miniq[i][j] = min(results[i][2 * j], 2157 results[i][2 * j + 1]); 2158 } 2159 2160 for (i = 0; i < 4; i++) { 2161 s32 mind = 40; 2162 u8 minvcm = 0; 2163 s32 minpoll = 249; 2164 s32 curr; 2165 for (j = 0; j < 4; j++) { 2166 if (type == 2) 2167 curr = abs(results[j][i]); 2168 else 2169 curr = abs(miniq[j][i / 2] - code * 8); 2170 2171 if (curr < mind) { 2172 mind = curr; 2173 minvcm = j; 2174 } 2175 2176 if (results[j][i] < minpoll) 2177 minpoll = results[j][i]; 2178 } 2179 results_min[i] = minpoll; 2180 vcm_final[i] = minvcm; 2181 } 2182 2183 if (type != 1) 2184 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); 2185 2186 for (i = 0; i < 4; i++) { 2187 offset[i] = (code * 8) - results[vcm_final[i]][i]; 2188 2189 if (offset[i] < 0) 2190 offset[i] = -((abs(offset[i]) + 4) / 8); 2191 else 2192 offset[i] = (offset[i] + 4) / 8; 2193 2194 if (results_min[i] == 248) 2195 offset[i] = code - 32; 2196 2197 core = (i / 2) ? 2 : 1; 2198 rail = (i % 2) ? 1 : 0; 2199 2200 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, 2201 type); 2202 } 2203 2204 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); 2205 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); 2206 2207 switch (state[2]) { 2208 case 1: 2209 b43_nphy_rssi_select(dev, 1, 2); 2210 break; 2211 case 4: 2212 b43_nphy_rssi_select(dev, 1, 0); 2213 break; 2214 case 2: 2215 b43_nphy_rssi_select(dev, 1, 1); 2216 break; 2217 default: 2218 b43_nphy_rssi_select(dev, 1, 1); 2219 break; 2220 } 2221 2222 switch (state[3]) { 2223 case 1: 2224 b43_nphy_rssi_select(dev, 2, 2); 2225 break; 2226 case 4: 2227 b43_nphy_rssi_select(dev, 2, 0); 2228 break; 2229 default: 2230 b43_nphy_rssi_select(dev, 2, 1); 2231 break; 2232 } 2233 2234 b43_nphy_rssi_select(dev, 0, type); 2235 2236 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); 2237 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); 2238 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); 2239 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); 2240 2241 b43_nphy_classifier(dev, 7, class); 2242 b43_nphy_write_clip_detection(dev, clip_state); 2243 /* Specs don't say about reset here, but it makes wl and b43 dumps 2244 identical, it really seems wl performs this */ 2245 b43_nphy_reset_cca(dev); 2246} 2247 2248/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ 2249static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) 2250{ 2251 /* TODO */ 2252} 2253 2254/* 2255 * RSSI Calibration 2256 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal 2257 */ 2258static void b43_nphy_rssi_cal(struct b43_wldev *dev) 2259{ 2260 if (dev->phy.rev >= 3) { 2261 b43_nphy_rev3_rssi_cal(dev); 2262 } else { 2263 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z); 2264 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X); 2265 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y); 2266 } 2267} 2268 2269/* 2270 * Restore RSSI Calibration 2271 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal 2272 */ 2273static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) 2274{ 2275 struct b43_phy_n *nphy = dev->phy.n; 2276 2277 u16 *rssical_radio_regs = NULL; 2278 u16 *rssical_phy_regs = NULL; 2279 2280 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2281 if (!nphy->rssical_chanspec_2G.center_freq) 2282 return; 2283 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; 2284 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; 2285 } else { 2286 if (!nphy->rssical_chanspec_5G.center_freq) 2287 return; 2288 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 2289 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 2290 } 2291 2292 /* TODO use some definitions */ 2293 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); 2294 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); 2295 2296 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); 2297 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); 2298 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); 2299 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); 2300 2301 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); 2302 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); 2303 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); 2304 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); 2305 2306 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); 2307 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); 2308 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); 2309 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); 2310} 2311 2312/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ 2313static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) 2314{ 2315 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2316 if (dev->phy.rev >= 6) { 2317 /* TODO If the chip is 47162 2318 return txpwrctrl_tx_gain_ipa_rev5 */ 2319 return txpwrctrl_tx_gain_ipa_rev6; 2320 } else if (dev->phy.rev >= 5) { 2321 return txpwrctrl_tx_gain_ipa_rev5; 2322 } else { 2323 return txpwrctrl_tx_gain_ipa; 2324 } 2325 } else { 2326 return txpwrctrl_tx_gain_ipa_5g; 2327 } 2328} 2329 2330/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ 2331static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) 2332{ 2333 struct b43_phy_n *nphy = dev->phy.n; 2334 u16 *save = nphy->tx_rx_cal_radio_saveregs; 2335 u16 tmp; 2336 u8 offset, i; 2337 2338 if (dev->phy.rev >= 3) { 2339 for (i = 0; i < 2; i++) { 2340 tmp = (i == 0) ? 0x2000 : 0x3000; 2341 offset = i * 11; 2342 2343 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); 2344 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); 2345 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); 2346 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); 2347 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); 2348 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); 2349 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); 2350 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); 2351 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); 2352 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); 2353 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); 2354 2355 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2356 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); 2357 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 2358 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 2359 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 2360 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 2361 if (nphy->ipa5g_on) { 2362 b43_radio_write16(dev, tmp | B2055_PADDRV, 4); 2363 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); 2364 } else { 2365 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 2366 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); 2367 } 2368 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 2369 } else { 2370 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); 2371 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 2372 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 2373 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 2374 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 2375 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); 2376 if (nphy->ipa2g_on) { 2377 b43_radio_write16(dev, tmp | B2055_PADDRV, 6); 2378 b43_radio_write16(dev, tmp | B2055_XOCTL2, 2379 (dev->phy.rev < 5) ? 0x11 : 0x01); 2380 } else { 2381 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 2382 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 2383 } 2384 } 2385 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); 2386 b43_radio_write16(dev, tmp | B2055_XOMISC, 0); 2387 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); 2388 } 2389 } else { 2390 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); 2391 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); 2392 2393 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); 2394 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); 2395 2396 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); 2397 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); 2398 2399 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); 2400 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); 2401 2402 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); 2403 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); 2404 2405 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & 2406 B43_NPHY_BANDCTL_5GHZ)) { 2407 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); 2408 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); 2409 } else { 2410 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); 2411 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); 2412 } 2413 2414 if (dev->phy.rev < 2) { 2415 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); 2416 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); 2417 } else { 2418 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); 2419 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); 2420 } 2421 } 2422} 2423 2424/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ 2425static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, 2426 struct nphy_txgains target, 2427 struct nphy_iqcal_params *params) 2428{ 2429 int i, j, indx; 2430 u16 gain; 2431 2432 if (dev->phy.rev >= 3) { 2433 params->txgm = target.txgm[core]; 2434 params->pga = target.pga[core]; 2435 params->pad = target.pad[core]; 2436 params->ipa = target.ipa[core]; 2437 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | 2438 (params->pad << 4) | (params->ipa); 2439 for (j = 0; j < 5; j++) 2440 params->ncorr[j] = 0x79; 2441 } else { 2442 gain = (target.pad[core]) | (target.pga[core] << 4) | 2443 (target.txgm[core] << 8); 2444 2445 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 2446 1 : 0; 2447 for (i = 0; i < 9; i++) 2448 if (tbl_iqcal_gainparams[indx][i][0] == gain) 2449 break; 2450 i = min(i, 8); 2451 2452 params->txgm = tbl_iqcal_gainparams[indx][i][1]; 2453 params->pga = tbl_iqcal_gainparams[indx][i][2]; 2454 params->pad = tbl_iqcal_gainparams[indx][i][3]; 2455 params->cal_gain = (params->txgm << 7) | (params->pga << 4) | 2456 (params->pad << 2); 2457 for (j = 0; j < 4; j++) 2458 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; 2459 } 2460} 2461 2462/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ 2463static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) 2464{ 2465 struct b43_phy_n *nphy = dev->phy.n; 2466 int i; 2467 u16 scale, entry; 2468 2469 u16 tmp = nphy->txcal_bbmult; 2470 if (core == 0) 2471 tmp >>= 8; 2472 tmp &= 0xff; 2473 2474 for (i = 0; i < 18; i++) { 2475 scale = (ladder_lo[i].percent * tmp) / 100; 2476 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; 2477 b43_ntab_write(dev, B43_NTAB16(15, i), entry); 2478 2479 scale = (ladder_iq[i].percent * tmp) / 100; 2480 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; 2481 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); 2482 } 2483} 2484 2485/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ 2486static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) 2487{ 2488 int i; 2489 for (i = 0; i < 15; i++) 2490 b43_phy_write(dev, B43_PHY_N(0x2C5 + i), 2491 tbl_tx_filter_coef_rev4[2][i]); 2492} 2493 2494/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ 2495static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) 2496{ 2497 int i, j; 2498 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ 2499 static const u16 offset[] = { 0x186, 0x195, 0x2C5 }; 2500 2501 for (i = 0; i < 3; i++) 2502 for (j = 0; j < 15; j++) 2503 b43_phy_write(dev, B43_PHY_N(offset[i] + j), 2504 tbl_tx_filter_coef_rev4[i][j]); 2505 2506 if (dev->phy.is_40mhz) { 2507 for (j = 0; j < 15; j++) 2508 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2509 tbl_tx_filter_coef_rev4[3][j]); 2510 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2511 for (j = 0; j < 15; j++) 2512 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2513 tbl_tx_filter_coef_rev4[5][j]); 2514 } 2515 2516 if (dev->phy.channel == 14) 2517 for (j = 0; j < 15; j++) 2518 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 2519 tbl_tx_filter_coef_rev4[6][j]); 2520} 2521 2522/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ 2523static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) 2524{ 2525 struct b43_phy_n *nphy = dev->phy.n; 2526 2527 u16 curr_gain[2]; 2528 struct nphy_txgains target; 2529 const u32 *table = NULL; 2530 2531 if (!nphy->txpwrctrl) { 2532 int i; 2533 2534 if (nphy->hang_avoid) 2535 b43_nphy_stay_in_carrier_search(dev, true); 2536 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); 2537 if (nphy->hang_avoid) 2538 b43_nphy_stay_in_carrier_search(dev, false); 2539 2540 for (i = 0; i < 2; ++i) { 2541 if (dev->phy.rev >= 3) { 2542 target.ipa[i] = curr_gain[i] & 0x000F; 2543 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; 2544 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; 2545 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; 2546 } else { 2547 target.ipa[i] = curr_gain[i] & 0x0003; 2548 target.pad[i] = (curr_gain[i] & 0x000C) >> 2; 2549 target.pga[i] = (curr_gain[i] & 0x0070) >> 4; 2550 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; 2551 } 2552 } 2553 } else { 2554 int i; 2555 u16 index[2]; 2556 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & 2557 B43_NPHY_TXPCTL_STAT_BIDX) >> 2558 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 2559 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & 2560 B43_NPHY_TXPCTL_STAT_BIDX) >> 2561 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 2562 2563 for (i = 0; i < 2; ++i) { 2564 if (dev->phy.rev >= 3) { 2565 enum ieee80211_band band = 2566 b43_current_band(dev->wl); 2567 2568 if ((nphy->ipa2g_on && 2569 band == IEEE80211_BAND_2GHZ) || 2570 (nphy->ipa5g_on && 2571 band == IEEE80211_BAND_5GHZ)) { 2572 table = b43_nphy_get_ipa_gain_table(dev); 2573 } else { 2574 if (band == IEEE80211_BAND_5GHZ) { 2575 if (dev->phy.rev == 3) 2576 table = b43_ntab_tx_gain_rev3_5ghz; 2577 else if (dev->phy.rev == 4) 2578 table = b43_ntab_tx_gain_rev4_5ghz; 2579 else 2580 table = b43_ntab_tx_gain_rev5plus_5ghz; 2581 } else { 2582 table = b43_ntab_tx_gain_rev3plus_2ghz; 2583 } 2584 } 2585 2586 target.ipa[i] = (table[index[i]] >> 16) & 0xF; 2587 target.pad[i] = (table[index[i]] >> 20) & 0xF; 2588 target.pga[i] = (table[index[i]] >> 24) & 0xF; 2589 target.txgm[i] = (table[index[i]] >> 28) & 0xF; 2590 } else { 2591 table = b43_ntab_tx_gain_rev0_1_2; 2592 2593 target.ipa[i] = (table[index[i]] >> 16) & 0x3; 2594 target.pad[i] = (table[index[i]] >> 18) & 0x3; 2595 target.pga[i] = (table[index[i]] >> 20) & 0x7; 2596 target.txgm[i] = (table[index[i]] >> 23) & 0x7; 2597 } 2598 } 2599 } 2600 2601 return target; 2602} 2603 2604/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ 2605static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) 2606{ 2607 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 2608 2609 if (dev->phy.rev >= 3) { 2610 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); 2611 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 2612 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 2613 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); 2614 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); 2615 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); 2616 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); 2617 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); 2618 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); 2619 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 2620 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 2621 b43_nphy_reset_cca(dev); 2622 } else { 2623 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); 2624 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); 2625 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 2626 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); 2627 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); 2628 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); 2629 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); 2630 } 2631} 2632 2633/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ 2634static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) 2635{ 2636 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 2637 u16 tmp; 2638 2639 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 2640 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 2641 if (dev->phy.rev >= 3) { 2642 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); 2643 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); 2644 2645 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 2646 regs[2] = tmp; 2647 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); 2648 2649 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2650 regs[3] = tmp; 2651 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); 2652 2653 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); 2654 b43_phy_mask(dev, B43_NPHY_BBCFG, 2655 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); 2656 2657 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); 2658 regs[5] = tmp; 2659 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); 2660 2661 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); 2662 regs[6] = tmp; 2663 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); 2664 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2665 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2666 2667 b43_nphy_rf_control_intc_override(dev, 2, 1, 3); 2668 b43_nphy_rf_control_intc_override(dev, 1, 2, 1); 2669 b43_nphy_rf_control_intc_override(dev, 1, 8, 2); 2670 2671 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 2672 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 2673 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 2674 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 2675 } else { 2676 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); 2677 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); 2678 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 2679 regs[2] = tmp; 2680 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); 2681 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); 2682 regs[3] = tmp; 2683 tmp |= 0x2000; 2684 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); 2685 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); 2686 regs[4] = tmp; 2687 tmp |= 0x2000; 2688 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); 2689 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2690 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2691 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 2692 tmp = 0x0180; 2693 else 2694 tmp = 0x0120; 2695 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 2696 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 2697 } 2698} 2699 2700/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ 2701static void b43_nphy_save_cal(struct b43_wldev *dev) 2702{ 2703 struct b43_phy_n *nphy = dev->phy.n; 2704 2705 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 2706 u16 *txcal_radio_regs = NULL; 2707 struct b43_chanspec *iqcal_chanspec; 2708 u16 *table = NULL; 2709 2710 if (nphy->hang_avoid) 2711 b43_nphy_stay_in_carrier_search(dev, 1); 2712 2713 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2714 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 2715 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 2716 iqcal_chanspec = &nphy->iqcal_chanspec_2G; 2717 table = nphy->cal_cache.txcal_coeffs_2G; 2718 } else { 2719 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 2720 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 2721 iqcal_chanspec = &nphy->iqcal_chanspec_5G; 2722 table = nphy->cal_cache.txcal_coeffs_5G; 2723 } 2724 2725 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); 2726 /* TODO use some definitions */ 2727 if (dev->phy.rev >= 3) { 2728 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); 2729 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); 2730 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); 2731 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); 2732 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); 2733 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); 2734 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); 2735 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); 2736 } else { 2737 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); 2738 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); 2739 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); 2740 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); 2741 } 2742 iqcal_chanspec->center_freq = dev->phy.channel_freq; 2743 iqcal_chanspec->channel_type = dev->phy.channel_type; 2744 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table); 2745 2746 if (nphy->hang_avoid) 2747 b43_nphy_stay_in_carrier_search(dev, 0); 2748} 2749 2750/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ 2751static void b43_nphy_restore_cal(struct b43_wldev *dev) 2752{ 2753 struct b43_phy_n *nphy = dev->phy.n; 2754 2755 u16 coef[4]; 2756 u16 *loft = NULL; 2757 u16 *table = NULL; 2758 2759 int i; 2760 u16 *txcal_radio_regs = NULL; 2761 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 2762 2763 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2764 if (!nphy->iqcal_chanspec_2G.center_freq) 2765 return; 2766 table = nphy->cal_cache.txcal_coeffs_2G; 2767 loft = &nphy->cal_cache.txcal_coeffs_2G[5]; 2768 } else { 2769 if (!nphy->iqcal_chanspec_5G.center_freq) 2770 return; 2771 table = nphy->cal_cache.txcal_coeffs_5G; 2772 loft = &nphy->cal_cache.txcal_coeffs_5G[5]; 2773 } 2774 2775 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); 2776 2777 for (i = 0; i < 4; i++) { 2778 if (dev->phy.rev >= 3) 2779 table[i] = coef[i]; 2780 else 2781 coef[i] = 0; 2782 } 2783 2784 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); 2785 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); 2786 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); 2787 2788 if (dev->phy.rev < 2) 2789 b43_nphy_tx_iq_workaround(dev); 2790 2791 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2792 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 2793 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 2794 } else { 2795 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 2796 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 2797 } 2798 2799 /* TODO use some definitions */ 2800 if (dev->phy.rev >= 3) { 2801 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); 2802 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); 2803 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); 2804 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); 2805 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); 2806 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); 2807 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); 2808 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); 2809 } else { 2810 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); 2811 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); 2812 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); 2813 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); 2814 } 2815 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); 2816} 2817 2818/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ 2819static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, 2820 struct nphy_txgains target, 2821 bool full, bool mphase) 2822{ 2823 struct b43_phy_n *nphy = dev->phy.n; 2824 int i; 2825 int error = 0; 2826 int freq; 2827 bool avoid = false; 2828 u8 length; 2829 u16 tmp, core, type, count, max, numb, last, cmd; 2830 const u16 *table; 2831 bool phy6or5x; 2832 2833 u16 buffer[11]; 2834 u16 diq_start = 0; 2835 u16 save[2]; 2836 u16 gain[2]; 2837 struct nphy_iqcal_params params[2]; 2838 bool updated[2] = { }; 2839 2840 b43_nphy_stay_in_carrier_search(dev, true); 2841 2842 if (dev->phy.rev >= 4) { 2843 avoid = nphy->hang_avoid; 2844 nphy->hang_avoid = 0; 2845 } 2846 2847 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 2848 2849 for (i = 0; i < 2; i++) { 2850 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); 2851 gain[i] = params[i].cal_gain; 2852 } 2853 2854 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); 2855 2856 b43_nphy_tx_cal_radio_setup(dev); 2857 b43_nphy_tx_cal_phy_setup(dev); 2858 2859 phy6or5x = dev->phy.rev >= 6 || 2860 (dev->phy.rev == 5 && nphy->ipa2g_on && 2861 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); 2862 if (phy6or5x) { 2863 if (dev->phy.is_40mhz) { 2864 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 2865 tbl_tx_iqlo_cal_loft_ladder_40); 2866 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 2867 tbl_tx_iqlo_cal_iqimb_ladder_40); 2868 } else { 2869 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 2870 tbl_tx_iqlo_cal_loft_ladder_20); 2871 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 2872 tbl_tx_iqlo_cal_iqimb_ladder_20); 2873 } 2874 } 2875 2876 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); 2877 2878 if (!dev->phy.is_40mhz) 2879 freq = 2500; 2880 else 2881 freq = 5000; 2882 2883 if (nphy->mphase_cal_phase_id > 2) 2884 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8, 2885 0xFFFF, 0, true, false); 2886 else 2887 error = b43_nphy_tx_tone(dev, freq, 250, true, false); 2888 2889 if (error == 0) { 2890 if (nphy->mphase_cal_phase_id > 2) { 2891 table = nphy->mphase_txcal_bestcoeffs; 2892 length = 11; 2893 if (dev->phy.rev < 3) 2894 length -= 2; 2895 } else { 2896 if (!full && nphy->txiqlocal_coeffsvalid) { 2897 table = nphy->txiqlocal_bestc; 2898 length = 11; 2899 if (dev->phy.rev < 3) 2900 length -= 2; 2901 } else { 2902 full = true; 2903 if (dev->phy.rev >= 3) { 2904 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; 2905 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; 2906 } else { 2907 table = tbl_tx_iqlo_cal_startcoefs; 2908 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; 2909 } 2910 } 2911 } 2912 2913 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); 2914 2915 if (full) { 2916 if (dev->phy.rev >= 3) 2917 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; 2918 else 2919 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; 2920 } else { 2921 if (dev->phy.rev >= 3) 2922 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; 2923 else 2924 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; 2925 } 2926 2927 if (mphase) { 2928 count = nphy->mphase_txcal_cmdidx; 2929 numb = min(max, 2930 (u16)(count + nphy->mphase_txcal_numcmds)); 2931 } else { 2932 count = 0; 2933 numb = max; 2934 } 2935 2936 for (; count < numb; count++) { 2937 if (full) { 2938 if (dev->phy.rev >= 3) 2939 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; 2940 else 2941 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; 2942 } else { 2943 if (dev->phy.rev >= 3) 2944 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; 2945 else 2946 cmd = tbl_tx_iqlo_cal_cmds_recal[count]; 2947 } 2948 2949 core = (cmd & 0x3000) >> 12; 2950 type = (cmd & 0x0F00) >> 8; 2951 2952 if (phy6or5x && updated[core] == 0) { 2953 b43_nphy_update_tx_cal_ladder(dev, core); 2954 updated[core] = 1; 2955 } 2956 2957 tmp = (params[core].ncorr[type] << 8) | 0x66; 2958 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); 2959 2960 if (type == 1 || type == 3 || type == 4) { 2961 buffer[0] = b43_ntab_read(dev, 2962 B43_NTAB16(15, 69 + core)); 2963 diq_start = buffer[0]; 2964 buffer[0] = 0; 2965 b43_ntab_write(dev, B43_NTAB16(15, 69 + core), 2966 0); 2967 } 2968 2969 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); 2970 for (i = 0; i < 2000; i++) { 2971 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); 2972 if (tmp & 0xC000) 2973 break; 2974 udelay(10); 2975 } 2976 2977 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 2978 buffer); 2979 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, 2980 buffer); 2981 2982 if (type == 1 || type == 3 || type == 4) 2983 buffer[0] = diq_start; 2984 } 2985 2986 if (mphase) 2987 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; 2988 2989 last = (dev->phy.rev < 3) ? 6 : 7; 2990 2991 if (!mphase || nphy->mphase_cal_phase_id == last) { 2992 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); 2993 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); 2994 if (dev->phy.rev < 3) { 2995 buffer[0] = 0; 2996 buffer[1] = 0; 2997 buffer[2] = 0; 2998 buffer[3] = 0; 2999 } 3000 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 3001 buffer); 3002 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, 3003 buffer); 3004 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 3005 buffer); 3006 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 3007 buffer); 3008 length = 11; 3009 if (dev->phy.rev < 3) 3010 length -= 2; 3011 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 3012 nphy->txiqlocal_bestc); 3013 nphy->txiqlocal_coeffsvalid = true; 3014 nphy->txiqlocal_chanspec.center_freq = 3015 dev->phy.channel_freq; 3016 nphy->txiqlocal_chanspec.channel_type = 3017 dev->phy.channel_type; 3018 } else { 3019 length = 11; 3020 if (dev->phy.rev < 3) 3021 length -= 2; 3022 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 3023 nphy->mphase_txcal_bestcoeffs); 3024 } 3025 3026 b43_nphy_stop_playback(dev); 3027 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); 3028 } 3029 3030 b43_nphy_tx_cal_phy_cleanup(dev); 3031 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 3032 3033 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) 3034 b43_nphy_tx_iq_workaround(dev); 3035 3036 if (dev->phy.rev >= 4) 3037 nphy->hang_avoid = avoid; 3038 3039 b43_nphy_stay_in_carrier_search(dev, false); 3040 3041 return error; 3042} 3043 3044/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ 3045static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) 3046{ 3047 struct b43_phy_n *nphy = dev->phy.n; 3048 u8 i; 3049 u16 buffer[7]; 3050 bool equal = true; 3051 3052 if (!nphy->txiqlocal_coeffsvalid || 3053 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq || 3054 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type) 3055 return; 3056 3057 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 3058 for (i = 0; i < 4; i++) { 3059 if (buffer[i] != nphy->txiqlocal_bestc[i]) { 3060 equal = false; 3061 break; 3062 } 3063 } 3064 3065 if (!equal) { 3066 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, 3067 nphy->txiqlocal_bestc); 3068 for (i = 0; i < 4; i++) 3069 buffer[i] = 0; 3070 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 3071 buffer); 3072 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 3073 &nphy->txiqlocal_bestc[5]); 3074 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 3075 &nphy->txiqlocal_bestc[5]); 3076 } 3077} 3078 3079/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ 3080static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, 3081 struct nphy_txgains target, u8 type, bool debug) 3082{ 3083 struct b43_phy_n *nphy = dev->phy.n; 3084 int i, j, index; 3085 u8 rfctl[2]; 3086 u8 afectl_core; 3087 u16 tmp[6]; 3088 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna; 3089 u32 real, imag; 3090 enum ieee80211_band band; 3091 3092 u8 use; 3093 u16 cur_hpf; 3094 u16 lna[3] = { 3, 3, 1 }; 3095 u16 hpf1[3] = { 7, 2, 0 }; 3096 u16 hpf2[3] = { 2, 0, 0 }; 3097 u32 power[3] = { }; 3098 u16 gain_save[2]; 3099 u16 cal_gain[2]; 3100 struct nphy_iqcal_params cal_params[2]; 3101 struct nphy_iq_est est; 3102 int ret = 0; 3103 bool playtone = true; 3104 int desired = 13; 3105 3106 b43_nphy_stay_in_carrier_search(dev, 1); 3107 3108 if (dev->phy.rev < 2) 3109 b43_nphy_reapply_tx_cal_coeffs(dev); 3110 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 3111 for (i = 0; i < 2; i++) { 3112 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); 3113 cal_gain[i] = cal_params[i].cal_gain; 3114 } 3115 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); 3116 3117 for (i = 0; i < 2; i++) { 3118 if (i == 0) { 3119 rfctl[0] = B43_NPHY_RFCTL_INTC1; 3120 rfctl[1] = B43_NPHY_RFCTL_INTC2; 3121 afectl_core = B43_NPHY_AFECTL_C1; 3122 } else { 3123 rfctl[0] = B43_NPHY_RFCTL_INTC2; 3124 rfctl[1] = B43_NPHY_RFCTL_INTC1; 3125 afectl_core = B43_NPHY_AFECTL_C2; 3126 } 3127 3128 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 3129 tmp[2] = b43_phy_read(dev, afectl_core); 3130 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 3131 tmp[4] = b43_phy_read(dev, rfctl[0]); 3132 tmp[5] = b43_phy_read(dev, rfctl[1]); 3133 3134 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 3135 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 3136 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 3137 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 3138 (1 - i)); 3139 b43_phy_set(dev, afectl_core, 0x0006); 3140 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); 3141 3142 band = b43_current_band(dev->wl); 3143 3144 if (nphy->rxcalparams & 0xFF000000) { 3145 if (band == IEEE80211_BAND_5GHZ) 3146 b43_phy_write(dev, rfctl[0], 0x140); 3147 else 3148 b43_phy_write(dev, rfctl[0], 0x110); 3149 } else { 3150 if (band == IEEE80211_BAND_5GHZ) 3151 b43_phy_write(dev, rfctl[0], 0x180); 3152 else 3153 b43_phy_write(dev, rfctl[0], 0x120); 3154 } 3155 3156 if (band == IEEE80211_BAND_5GHZ) 3157 b43_phy_write(dev, rfctl[1], 0x148); 3158 else 3159 b43_phy_write(dev, rfctl[1], 0x114); 3160 3161 if (nphy->rxcalparams & 0x10000) { 3162 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, 3163 (i + 1)); 3164 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, 3165 (2 - i)); 3166 } 3167 3168 for (j = 0; j < 4; j++) { 3169 if (j < 3) { 3170 cur_lna = lna[j]; 3171 cur_hpf1 = hpf1[j]; 3172 cur_hpf2 = hpf2[j]; 3173 } else { 3174 if (power[1] > 10000) { 3175 use = 1; 3176 cur_hpf = cur_hpf1; 3177 index = 2; 3178 } else { 3179 if (power[0] > 10000) { 3180 use = 1; 3181 cur_hpf = cur_hpf1; 3182 index = 1; 3183 } else { 3184 index = 0; 3185 use = 2; 3186 cur_hpf = cur_hpf2; 3187 } 3188 } 3189 cur_lna = lna[index]; 3190 cur_hpf1 = hpf1[index]; 3191 cur_hpf2 = hpf2[index]; 3192 cur_hpf += desired - hweight32(power[index]); 3193 cur_hpf = clamp_val(cur_hpf, 0, 10); 3194 if (use == 1) 3195 cur_hpf1 = cur_hpf; 3196 else 3197 cur_hpf2 = cur_hpf; 3198 } 3199 3200 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | 3201 (cur_lna << 2)); 3202 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, 3203 false); 3204 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3205 b43_nphy_stop_playback(dev); 3206 3207 if (playtone) { 3208 ret = b43_nphy_tx_tone(dev, 4000, 3209 (nphy->rxcalparams & 0xFFFF), 3210 false, false); 3211 playtone = false; 3212 } else { 3213 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, 3214 false, false); 3215 } 3216 3217 if (ret == 0) { 3218 if (j < 3) { 3219 b43_nphy_rx_iq_est(dev, &est, 1024, 32, 3220 false); 3221 if (i == 0) { 3222 real = est.i0_pwr; 3223 imag = est.q0_pwr; 3224 } else { 3225 real = est.i1_pwr; 3226 imag = est.q1_pwr; 3227 } 3228 power[i] = ((real + imag) / 1024) + 1; 3229 } else { 3230 b43_nphy_calc_rx_iq_comp(dev, 1 << i); 3231 } 3232 b43_nphy_stop_playback(dev); 3233 } 3234 3235 if (ret != 0) 3236 break; 3237 } 3238 3239 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); 3240 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); 3241 b43_phy_write(dev, rfctl[1], tmp[5]); 3242 b43_phy_write(dev, rfctl[0], tmp[4]); 3243 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); 3244 b43_phy_write(dev, afectl_core, tmp[2]); 3245 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); 3246 3247 if (ret != 0) 3248 break; 3249 } 3250 3251 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); 3252 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3253 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 3254 3255 b43_nphy_stay_in_carrier_search(dev, 0); 3256 3257 return ret; 3258} 3259 3260static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, 3261 struct nphy_txgains target, u8 type, bool debug) 3262{ 3263 return -1; 3264} 3265 3266/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ 3267static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, 3268 struct nphy_txgains target, u8 type, bool debug) 3269{ 3270 if (dev->phy.rev >= 3) 3271 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); 3272 else 3273 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); 3274} 3275 3276/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 3277static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on) 3278{ 3279 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW); 3280 if (on) 3281 tmslow |= SSB_TMSLOW_PHYCLK; 3282 else 3283 tmslow &= ~SSB_TMSLOW_PHYCLK; 3284 ssb_write32(dev->dev, SSB_TMSLOW, tmslow); 3285} 3286 3287/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */ 3288static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) 3289{ 3290 struct b43_phy *phy = &dev->phy; 3291 struct b43_phy_n *nphy = phy->n; 3292 /* u16 buf[16]; it's rev3+ */ 3293 3294 nphy->phyrxchain = mask; 3295 3296 if (0 /* FIXME clk */) 3297 return; 3298 3299 b43_mac_suspend(dev); 3300 3301 if (nphy->hang_avoid) 3302 b43_nphy_stay_in_carrier_search(dev, true); 3303 3304 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 3305 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT); 3306 3307 if ((mask & 0x3) != 0x3) { 3308 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); 3309 if (dev->phy.rev >= 3) { 3310 /* TODO */ 3311 } 3312 } else { 3313 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); 3314 if (dev->phy.rev >= 3) { 3315 /* TODO */ 3316 } 3317 } 3318 3319 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3320 3321 if (nphy->hang_avoid) 3322 b43_nphy_stay_in_carrier_search(dev, false); 3323 3324 b43_mac_enable(dev); 3325} 3326 3327/* 3328 * Init N-PHY 3329 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N 3330 */ 3331int b43_phy_initn(struct b43_wldev *dev) 3332{ 3333 struct ssb_bus *bus = dev->dev->bus; 3334 struct b43_phy *phy = &dev->phy; 3335 struct b43_phy_n *nphy = phy->n; 3336 u8 tx_pwr_state; 3337 struct nphy_txgains target; 3338 u16 tmp; 3339 enum ieee80211_band tmp2; 3340 bool do_rssi_cal; 3341 3342 u16 clip[2]; 3343 bool do_cal = false; 3344 3345 if ((dev->phy.rev >= 3) && 3346 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) && 3347 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { 3348 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40); 3349 } 3350 nphy->deaf_count = 0; 3351 b43_nphy_tables_init(dev); 3352 nphy->crsminpwr_adjusted = false; 3353 nphy->noisevars_adjusted = false; 3354 3355 /* Clear all overrides */ 3356 if (dev->phy.rev >= 3) { 3357 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); 3358 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 3359 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); 3360 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); 3361 } else { 3362 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 3363 } 3364 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); 3365 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); 3366 if (dev->phy.rev < 6) { 3367 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); 3368 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); 3369 } 3370 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 3371 ~(B43_NPHY_RFSEQMODE_CAOVER | 3372 B43_NPHY_RFSEQMODE_TROVER)); 3373 if (dev->phy.rev >= 3) 3374 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); 3375 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); 3376 3377 if (dev->phy.rev <= 2) { 3378 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; 3379 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 3380 ~B43_NPHY_BPHY_CTL3_SCALE, 3381 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); 3382 } 3383 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); 3384 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); 3385 3386 if (bus->sprom.boardflags2_lo & 0x100 || 3387 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3388 bus->boardinfo.type == 0x8B)) 3389 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); 3390 else 3391 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); 3392 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); 3393 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); 3394 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); 3395 3396 b43_nphy_update_mimo_config(dev, nphy->preamble_override); 3397 b43_nphy_update_txrx_chain(dev); 3398 3399 if (phy->rev < 2) { 3400 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); 3401 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); 3402 } 3403 3404 tmp2 = b43_current_band(dev->wl); 3405 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) || 3406 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) { 3407 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); 3408 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, 3409 nphy->papd_epsilon_offset[0] << 7); 3410 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); 3411 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, 3412 nphy->papd_epsilon_offset[1] << 7); 3413 b43_nphy_int_pa_set_tx_dig_filters(dev); 3414 } else if (phy->rev >= 5) { 3415 b43_nphy_ext_pa_set_tx_dig_filters(dev); 3416 } 3417 3418 b43_nphy_workarounds(dev); 3419 3420 /* Reset CCA, in init code it differs a little from standard way */ 3421 b43_nphy_bmac_clock_fgc(dev, 1); 3422 tmp = b43_phy_read(dev, B43_NPHY_BBCFG); 3423 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); 3424 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); 3425 b43_nphy_bmac_clock_fgc(dev, 0); 3426 3427 b43_nphy_mac_phy_clock_set(dev, true); 3428 3429 b43_nphy_pa_override(dev, false); 3430 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 3431 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 3432 b43_nphy_pa_override(dev, true); 3433 3434 b43_nphy_classifier(dev, 0, 0); 3435 b43_nphy_read_clip_detection(dev, clip); 3436 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3437 b43_nphy_bphy_init(dev); 3438 3439 tx_pwr_state = nphy->txpwrctrl; 3440 b43_nphy_tx_power_ctrl(dev, false); 3441 b43_nphy_tx_power_fix(dev); 3442 /* TODO N PHY TX Power Control Idle TSSI */ 3443 /* TODO N PHY TX Power Control Setup */ 3444 3445 if (phy->rev >= 3) { 3446 /* TODO */ 3447 } else { 3448 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, 3449 b43_ntab_tx_gain_rev0_1_2); 3450 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, 3451 b43_ntab_tx_gain_rev0_1_2); 3452 } 3453 3454 if (nphy->phyrxchain != 3) 3455 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); 3456 if (nphy->mphase_cal_phase_id > 0) 3457 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ 3458 3459 do_rssi_cal = false; 3460 if (phy->rev >= 3) { 3461 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3462 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq; 3463 else 3464 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq; 3465 3466 if (do_rssi_cal) 3467 b43_nphy_rssi_cal(dev); 3468 else 3469 b43_nphy_restore_rssi_cal(dev); 3470 } else { 3471 b43_nphy_rssi_cal(dev); 3472 } 3473 3474 if (!((nphy->measure_hold & 0x6) != 0)) { 3475 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3476 do_cal = !nphy->iqcal_chanspec_2G.center_freq; 3477 else 3478 do_cal = !nphy->iqcal_chanspec_5G.center_freq; 3479 3480 if (nphy->mute) 3481 do_cal = false; 3482 3483 if (do_cal) { 3484 target = b43_nphy_get_tx_gains(dev); 3485 3486 if (nphy->antsel_type == 2) 3487 b43_nphy_superswitch_init(dev, true); 3488 if (nphy->perical != 2) { 3489 b43_nphy_rssi_cal(dev); 3490 if (phy->rev >= 3) { 3491 nphy->cal_orig_pwr_idx[0] = 3492 nphy->txpwrindex[0].index_internal; 3493 nphy->cal_orig_pwr_idx[1] = 3494 nphy->txpwrindex[1].index_internal; 3495 /* TODO N PHY Pre Calibrate TX Gain */ 3496 target = b43_nphy_get_tx_gains(dev); 3497 } 3498 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) 3499 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) 3500 b43_nphy_save_cal(dev); 3501 } else if (nphy->mphase_cal_phase_id == 0) 3502 ;/* N PHY Periodic Calibration with arg 3 */ 3503 } else { 3504 b43_nphy_restore_cal(dev); 3505 } 3506 } 3507 3508 b43_nphy_tx_pwr_ctrl_coef_setup(dev); 3509 b43_nphy_tx_power_ctrl(dev, tx_pwr_state); 3510 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); 3511 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); 3512 if (phy->rev >= 3 && phy->rev <= 6) 3513 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014); 3514 b43_nphy_tx_lp_fbw(dev); 3515 if (phy->rev >= 3) 3516 b43_nphy_spur_workaround(dev); 3517 3518 return 0; 3519} 3520 3521/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ 3522static void b43_nphy_channel_setup(struct b43_wldev *dev, 3523 const struct b43_phy_n_sfo_cfg *e, 3524 struct ieee80211_channel *new_channel) 3525{ 3526 struct b43_phy *phy = &dev->phy; 3527 struct b43_phy_n *nphy = dev->phy.n; 3528 3529 u16 old_band_5ghz; 3530 u32 tmp32; 3531 3532 old_band_5ghz = 3533 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ; 3534 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) { 3535 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR); 3536 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4); 3537 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000); 3538 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32); 3539 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); 3540 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) { 3541 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); 3542 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR); 3543 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4); 3544 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF); 3545 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32); 3546 } 3547 3548 b43_chantab_phy_upload(dev, e); 3549 3550 if (new_channel->hw_value == 14) { 3551 b43_nphy_classifier(dev, 2, 0); 3552 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); 3553 } else { 3554 b43_nphy_classifier(dev, 2, 2); 3555 if (new_channel->band == IEEE80211_BAND_2GHZ) 3556 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); 3557 } 3558 3559 if (!nphy->txpwrctrl) 3560 b43_nphy_tx_power_fix(dev); 3561 3562 if (dev->phy.rev < 3) 3563 b43_nphy_adjust_lna_gain_table(dev); 3564 3565 b43_nphy_tx_lp_fbw(dev); 3566 3567 if (dev->phy.rev >= 3 && 0) { 3568 /* TODO */ 3569 } 3570 3571 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); 3572 3573 if (phy->rev >= 3) 3574 b43_nphy_spur_workaround(dev); 3575} 3576 3577/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ 3578static int b43_nphy_set_channel(struct b43_wldev *dev, 3579 struct ieee80211_channel *channel, 3580 enum nl80211_channel_type channel_type) 3581{ 3582 struct b43_phy *phy = &dev->phy; 3583 3584 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2; 3585 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3; 3586 3587 u8 tmp; 3588 3589 if (dev->phy.rev >= 3) { 3590 tabent_r3 = b43_nphy_get_chantabent_rev3(dev, 3591 channel->center_freq); 3592 tabent_r3 = NULL; 3593 if (!tabent_r3) 3594 return -ESRCH; 3595 } else { 3596 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, 3597 channel->hw_value); 3598 if (!tabent_r2) 3599 return -ESRCH; 3600 } 3601 3602 /* Channel is set later in common code, but we need to set it on our 3603 own to let this function's subcalls work properly. */ 3604 phy->channel = channel->hw_value; 3605 phy->channel_freq = channel->center_freq; 3606 3607 if (b43_channel_type_is_40mhz(phy->channel_type) != 3608 b43_channel_type_is_40mhz(channel_type)) 3609 ; /* TODO: BMAC BW Set (channel_type) */ 3610 3611 if (channel_type == NL80211_CHAN_HT40PLUS) 3612 b43_phy_set(dev, B43_NPHY_RXCTL, 3613 B43_NPHY_RXCTL_BSELU20); 3614 else if (channel_type == NL80211_CHAN_HT40MINUS) 3615 b43_phy_mask(dev, B43_NPHY_RXCTL, 3616 ~B43_NPHY_RXCTL_BSELU20); 3617 3618 if (dev->phy.rev >= 3) { 3619 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0; 3620 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); 3621 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */ 3622 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel); 3623 } else { 3624 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050; 3625 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); 3626 b43_radio_2055_setup(dev, tabent_r2); 3627 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel); 3628 } 3629 3630 return 0; 3631} 3632 3633static int b43_nphy_op_allocate(struct b43_wldev *dev) 3634{ 3635 struct b43_phy_n *nphy; 3636 3637 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); 3638 if (!nphy) 3639 return -ENOMEM; 3640 dev->phy.n = nphy; 3641 3642 return 0; 3643} 3644 3645static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) 3646{ 3647 struct b43_phy *phy = &dev->phy; 3648 struct b43_phy_n *nphy = phy->n; 3649 3650 memset(nphy, 0, sizeof(*nphy)); 3651 3652 nphy->gain_boost = true; /* this way we follow wl, assume it is true */ 3653 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ 3654 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */ 3655 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */ 3656} 3657 3658static void b43_nphy_op_free(struct b43_wldev *dev) 3659{ 3660 struct b43_phy *phy = &dev->phy; 3661 struct b43_phy_n *nphy = phy->n; 3662 3663 kfree(nphy); 3664 phy->n = NULL; 3665} 3666 3667static int b43_nphy_op_init(struct b43_wldev *dev) 3668{ 3669 return b43_phy_initn(dev); 3670} 3671 3672static inline void check_phyreg(struct b43_wldev *dev, u16 offset) 3673{ 3674#if B43_DEBUG 3675 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { 3676 /* OFDM registers are onnly available on A/G-PHYs */ 3677 b43err(dev->wl, "Invalid OFDM PHY access at " 3678 "0x%04X on N-PHY\n", offset); 3679 dump_stack(); 3680 } 3681 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { 3682 /* Ext-G registers are only available on G-PHYs */ 3683 b43err(dev->wl, "Invalid EXT-G PHY access at " 3684 "0x%04X on N-PHY\n", offset); 3685 dump_stack(); 3686 } 3687#endif /* B43_DEBUG */ 3688} 3689 3690static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg) 3691{ 3692 check_phyreg(dev, reg); 3693 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); 3694 return b43_read16(dev, B43_MMIO_PHY_DATA); 3695} 3696 3697static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) 3698{ 3699 check_phyreg(dev, reg); 3700 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); 3701 b43_write16(dev, B43_MMIO_PHY_DATA, value); 3702} 3703 3704static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, 3705 u16 set) 3706{ 3707 check_phyreg(dev, reg); 3708 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); 3709 b43_write16(dev, B43_MMIO_PHY_DATA, 3710 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); 3711} 3712 3713static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) 3714{ 3715 /* Register 1 is a 32-bit register. */ 3716 B43_WARN_ON(reg == 1); 3717 /* N-PHY needs 0x100 for read access */ 3718 reg |= 0x100; 3719 3720 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); 3721 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 3722} 3723 3724static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) 3725{ 3726 /* Register 1 is a 32-bit register. */ 3727 B43_WARN_ON(reg == 1); 3728 3729 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); 3730 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); 3731} 3732 3733/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ 3734static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, 3735 bool blocked) 3736{ 3737 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) 3738 b43err(dev->wl, "MAC not suspended\n"); 3739 3740 if (blocked) { 3741 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 3742 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 3743 if (dev->phy.rev >= 3) { 3744 b43_radio_mask(dev, 0x09, ~0x2); 3745 3746 b43_radio_write(dev, 0x204D, 0); 3747 b43_radio_write(dev, 0x2053, 0); 3748 b43_radio_write(dev, 0x2058, 0); 3749 b43_radio_write(dev, 0x205E, 0); 3750 b43_radio_mask(dev, 0x2062, ~0xF0); 3751 b43_radio_write(dev, 0x2064, 0); 3752 3753 b43_radio_write(dev, 0x304D, 0); 3754 b43_radio_write(dev, 0x3053, 0); 3755 b43_radio_write(dev, 0x3058, 0); 3756 b43_radio_write(dev, 0x305E, 0); 3757 b43_radio_mask(dev, 0x3062, ~0xF0); 3758 b43_radio_write(dev, 0x3064, 0); 3759 } 3760 } else { 3761 if (dev->phy.rev >= 3) { 3762 b43_radio_init2056(dev); 3763 b43_switch_channel(dev, dev->phy.channel); 3764 } else { 3765 b43_radio_init2055(dev); 3766 } 3767 } 3768} 3769 3770static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) 3771{ 3772 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 3773 on ? 0 : 0x7FFF); 3774} 3775 3776static int b43_nphy_op_switch_channel(struct b43_wldev *dev, 3777 unsigned int new_channel) 3778{ 3779 struct ieee80211_channel *channel = dev->wl->hw->conf.channel; 3780 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type; 3781 3782 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 3783 if ((new_channel < 1) || (new_channel > 14)) 3784 return -EINVAL; 3785 } else { 3786 if (new_channel > 200) 3787 return -EINVAL; 3788 } 3789 3790 return b43_nphy_set_channel(dev, channel, channel_type); 3791} 3792 3793static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) 3794{ 3795 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3796 return 1; 3797 return 36; 3798} 3799 3800const struct b43_phy_operations b43_phyops_n = { 3801 .allocate = b43_nphy_op_allocate, 3802 .free = b43_nphy_op_free, 3803 .prepare_structs = b43_nphy_op_prepare_structs, 3804 .init = b43_nphy_op_init, 3805 .phy_read = b43_nphy_op_read, 3806 .phy_write = b43_nphy_op_write, 3807 .phy_maskset = b43_nphy_op_maskset, 3808 .radio_read = b43_nphy_op_radio_read, 3809 .radio_write = b43_nphy_op_radio_write, 3810 .software_rfkill = b43_nphy_op_software_rfkill, 3811 .switch_analog = b43_nphy_op_switch_analog, 3812 .switch_channel = b43_nphy_op_switch_channel, 3813 .get_default_chan = b43_nphy_op_get_default_chan, 3814 .recalc_txpower = b43_nphy_op_recalc_txpower, 3815 .adjust_txpower = b43_nphy_op_adjust_txpower, 3816}; 3817