1/* 2 * Broadcom HND chip & on-chip-interconnect-related definitions. 3 * 4 * Copyright (C) 1999-2012, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * $Id: hndsoc.h 309193 2012-01-19 00:03:57Z $ 25 */ 26 27#ifndef _HNDSOC_H 28#define _HNDSOC_H 29 30/* Include the soci specific files */ 31#include <sbconfig.h> 32#include <aidmp.h> 33 34/* 35 * SOC Interconnect Address Map. 36 * All regions may not exist on all chips. 37 */ 38#define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */ 39#define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 40#define SI_PCI_MEM_SZ (64 * 1024 * 1024) 41#define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 42#define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ 43#define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ 44 45#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */ 46 47#define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ 48#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ 49#define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software 50 * convenience and could be changed if we 51 * make any larger chips 52 */ 53 54#define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ 55#define SI_FASTRAM_SWAPPED 0x19800000 56 57#define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ 58#define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ 59#define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ 60#define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ 61#define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ 62#define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ 63#define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */ 64#define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ 65#define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ 66#define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ 67#define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ 68 69#define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 70#define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 71#define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ 72#define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 73 * (2 ZettaBytes), low 32 bits 74 */ 75#define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 76 * (2 ZettaBytes), high 32 bits 77 */ 78 79/* core codes */ 80#define NODEV_CORE_ID 0x700 /* Invalid coreid */ 81#define CC_CORE_ID 0x800 /* chipcommon core */ 82#define ILINE20_CORE_ID 0x801 /* iline20 core */ 83#define SRAM_CORE_ID 0x802 /* sram core */ 84#define SDRAM_CORE_ID 0x803 /* sdram core */ 85#define PCI_CORE_ID 0x804 /* pci core */ 86#define MIPS_CORE_ID 0x805 /* mips core */ 87#define ENET_CORE_ID 0x806 /* enet mac core */ 88#define CODEC_CORE_ID 0x807 /* v90 codec core */ 89#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ 90#define ADSL_CORE_ID 0x809 /* ADSL core */ 91#define ILINE100_CORE_ID 0x80a /* iline100 core */ 92#define IPSEC_CORE_ID 0x80b /* ipsec core */ 93#define UTOPIA_CORE_ID 0x80c /* utopia core */ 94#define PCMCIA_CORE_ID 0x80d /* pcmcia core */ 95#define SOCRAM_CORE_ID 0x80e /* internal memory core */ 96#define MEMC_CORE_ID 0x80f /* memc sdram core */ 97#define OFDM_CORE_ID 0x810 /* OFDM phy core */ 98#define EXTIF_CORE_ID 0x811 /* external interface core */ 99#define D11_CORE_ID 0x812 /* 802.11 MAC core */ 100#define APHY_CORE_ID 0x813 /* 802.11a phy core */ 101#define BPHY_CORE_ID 0x814 /* 802.11b phy core */ 102#define GPHY_CORE_ID 0x815 /* 802.11g phy core */ 103#define MIPS33_CORE_ID 0x816 /* mips3302 core */ 104#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ 105#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ 106#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ 107#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ 108#define SDIOH_CORE_ID 0x81b /* sdio host core */ 109#define ROBO_CORE_ID 0x81c /* roboswitch core */ 110#define ATA100_CORE_ID 0x81d /* parallel ATA core */ 111#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ 112#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ 113#define PCIE_CORE_ID 0x820 /* pci express core */ 114#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ 115#define SRAMC_CORE_ID 0x822 /* SRAM controller core */ 116#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ 117#define ARM11_CORE_ID 0x824 /* ARM 1176 core */ 118#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ 119#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ 120#define PMU_CORE_ID 0x827 /* PMU core */ 121#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ 122#define SDIOD_CORE_ID 0x829 /* SDIO device core */ 123#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ 124#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ 125#define MIPS74K_CORE_ID 0x82c /* mips 74k core */ 126#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ 127#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ 128#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ 129#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ 130#define SC_CORE_ID 0x831 /* shared common core */ 131#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ 132#define SPIH_CORE_ID 0x833 /* SPI host core */ 133#define I2S_CORE_ID 0x834 /* I2S core */ 134#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ 135#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ 136 137#define ACPHY_CORE_ID 0x83b /* Dot11 ACPHY */ 138#define PCIE2_CORE_ID 0x83c /* pci express Gen2 core */ 139#define USB30D_CORE_ID 0x83d /* usb 3.0 device core */ 140#define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */ 141#define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */ 142#define AXI_CORE_ID 0x301 /* AXI/GPV core ID */ 143#define EROM_CORE_ID 0x366 /* EROM core ID */ 144#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ 145#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all 146 * unused address ranges 147 */ 148 149#define CC_4706_CORE_ID 0x500 /* chipcommon core */ 150#define SOCRAM_4706_CORE_ID 0x50e /* internal memory core */ 151#define GMAC_COMMON_4706_CORE_ID 0x5dc /* Gigabit MAC core */ 152#define GMAC_4706_CORE_ID 0x52d /* Gigabit MAC core */ 153#define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */ 154#define ALTA_CORE_ID 0x534 /* I2S core */ 155#define DDR23_PHY_CORE_ID 0x5dd 156 157#define SI_PCI1_MEM 0x40000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 158#define SI_PCI1_CFG 0x44000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 159#define SI_PCIE1_DMA_H32 0xc0000000 /* PCIE Client Mode sb2pcitranslation2 160 * (2 ZettaBytes), high 32 bits 161 */ 162#define CC_4706B0_CORE_REV 0x8000001f /* chipcommon core */ 163#define SOCRAM_4706B0_CORE_REV 0x80000005 /* internal memory core */ 164#define GMAC_4706B0_CORE_REV 0x80000000 /* Gigabit MAC core */ 165 166/* There are TWO constants on all HND chips: SI_ENUM_BASE above, 167 * and chipcommon being the first core: 168 */ 169#define SI_CC_IDX 0 170 171/* SOC Interconnect types (aka chip types) */ 172#define SOCI_SB 0 173#define SOCI_AI 1 174#define SOCI_UBUS 2 175 176/* Common core control flags */ 177#define SICF_BIST_EN 0x8000 178#define SICF_PME_EN 0x4000 179#define SICF_CORE_BITS 0x3ffc 180#define SICF_FGC 0x0002 181#define SICF_CLOCK_EN 0x0001 182 183/* Common core status flags */ 184#define SISF_BIST_DONE 0x8000 185#define SISF_BIST_ERROR 0x4000 186#define SISF_GATED_CLK 0x2000 187#define SISF_DMA64 0x1000 188#define SISF_CORE_BITS 0x0fff 189 190/* A register that is common to all cores to 191 * communicate w/PMU regarding clock control. 192 */ 193#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ 194 195/* clk_ctl_st register */ 196#define CCS_FORCEALP 0x00000001 /* force ALP request */ 197#define CCS_FORCEHT 0x00000002 /* force HT request */ 198#define CCS_FORCEILP 0x00000004 /* force ILP request */ 199#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ 200#define CCS_HTAREQ 0x00000010 /* HT Avail Request */ 201#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ 202#define CCS_HQCLKREQ 0x00000040 /* HQ Clock Required */ 203#define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */ 204#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ 205#define CCS_ERSRC_REQ_SHIFT 8 206#define CCS_ALPAVAIL 0x00010000 /* ALP is available */ 207#define CCS_HTAVAIL 0x00020000 /* HT is available */ 208#define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ 209#define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ 210#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ 211#define CCS_ERSRC_STS_SHIFT 24 212 213#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ 214#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ 215 216/* Not really related to SOC Interconnect, but a couple of software 217 * conventions for the use the flash space: 218 */ 219 220/* Minumum amount of flash we support */ 221#define FLASH_MIN 0x00020000 /* Minimum flash size */ 222 223/* A boot/binary may have an embedded block that describes its size */ 224#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ 225#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ 226#define BISZ_MAGIC_IDX 0 /* Word 0: magic */ 227#define BISZ_TXTST_IDX 1 /* 1: text start */ 228#define BISZ_TXTEND_IDX 2 /* 2: text end */ 229#define BISZ_DATAST_IDX 3 /* 3: data start */ 230#define BISZ_DATAEND_IDX 4 /* 4: data end */ 231#define BISZ_BSSST_IDX 5 /* 5: bss start */ 232#define BISZ_BSSEND_IDX 6 /* 6: bss end */ 233#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ 234 235#endif /* _HNDSOC_H */ 236