1/****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Linux Wireless <ilw@linux.intel.com> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 *****************************************************************************/ 26 27#include <linux/kernel.h> 28#include <linux/module.h> 29#include <linux/init.h> 30#include <linux/slab.h> 31#include <linux/pci.h> 32#include <linux/dma-mapping.h> 33#include <linux/delay.h> 34#include <linux/sched.h> 35#include <linux/skbuff.h> 36#include <linux/netdevice.h> 37#include <linux/firmware.h> 38#include <linux/etherdevice.h> 39#include <asm/unaligned.h> 40#include <net/mac80211.h> 41 42#include "common.h" 43#include "3945.h" 44 45/* Send led command */ 46static int 47il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd) 48{ 49 struct il_host_cmd cmd = { 50 .id = C_LEDS, 51 .len = sizeof(struct il_led_cmd), 52 .data = led_cmd, 53 .flags = CMD_ASYNC, 54 .callback = NULL, 55 }; 56 57 return il_send_cmd(il, &cmd); 58} 59 60#define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \ 61 [RATE_##r##M_IDX] = { RATE_##r##M_PLCP, \ 62 RATE_##r##M_IEEE, \ 63 RATE_##ip##M_IDX, \ 64 RATE_##in##M_IDX, \ 65 RATE_##rp##M_IDX, \ 66 RATE_##rn##M_IDX, \ 67 RATE_##pp##M_IDX, \ 68 RATE_##np##M_IDX, \ 69 RATE_##r##M_IDX_TBL, \ 70 RATE_##ip##M_IDX_TBL } 71 72/* 73 * Parameter order: 74 * rate, prev rate, next rate, prev tgg rate, next tgg rate 75 * 76 * If there isn't a valid next or previous rate then INV is used which 77 * maps to RATE_INVALID 78 * 79 */ 80const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = { 81 IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */ 82 IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */ 83 IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */ 84 IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */ 85 IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */ 86 IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */ 87 IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */ 88 IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */ 89 IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */ 90 IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */ 91 IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */ 92 IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV), /* 54mbps */ 93}; 94 95static inline u8 96il3945_get_prev_ieee_rate(u8 rate_idx) 97{ 98 u8 rate = il3945_rates[rate_idx].prev_ieee; 99 100 if (rate == RATE_INVALID) 101 rate = rate_idx; 102 return rate; 103} 104 105/* 1 = enable the il3945_disable_events() function */ 106#define IL_EVT_DISABLE (0) 107#define IL_EVT_DISABLE_SIZE (1532/32) 108 109/** 110 * il3945_disable_events - Disable selected events in uCode event log 111 * 112 * Disable an event by writing "1"s into "disable" 113 * bitmap in SRAM. Bit position corresponds to Event # (id/type). 114 * Default values of 0 enable uCode events to be logged. 115 * Use for only special debugging. This function is just a placeholder as-is, 116 * you'll need to provide the special bits! ... 117 * ... and set IL_EVT_DISABLE to 1. */ 118void 119il3945_disable_events(struct il_priv *il) 120{ 121 int i; 122 u32 base; /* SRAM address of event log header */ 123 u32 disable_ptr; /* SRAM address of event-disable bitmap array */ 124 u32 array_size; /* # of u32 entries in array */ 125 static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = { 126 0x00000000, /* 31 - 0 Event id numbers */ 127 0x00000000, /* 63 - 32 */ 128 0x00000000, /* 95 - 64 */ 129 0x00000000, /* 127 - 96 */ 130 0x00000000, /* 159 - 128 */ 131 0x00000000, /* 191 - 160 */ 132 0x00000000, /* 223 - 192 */ 133 0x00000000, /* 255 - 224 */ 134 0x00000000, /* 287 - 256 */ 135 0x00000000, /* 319 - 288 */ 136 0x00000000, /* 351 - 320 */ 137 0x00000000, /* 383 - 352 */ 138 0x00000000, /* 415 - 384 */ 139 0x00000000, /* 447 - 416 */ 140 0x00000000, /* 479 - 448 */ 141 0x00000000, /* 511 - 480 */ 142 0x00000000, /* 543 - 512 */ 143 0x00000000, /* 575 - 544 */ 144 0x00000000, /* 607 - 576 */ 145 0x00000000, /* 639 - 608 */ 146 0x00000000, /* 671 - 640 */ 147 0x00000000, /* 703 - 672 */ 148 0x00000000, /* 735 - 704 */ 149 0x00000000, /* 767 - 736 */ 150 0x00000000, /* 799 - 768 */ 151 0x00000000, /* 831 - 800 */ 152 0x00000000, /* 863 - 832 */ 153 0x00000000, /* 895 - 864 */ 154 0x00000000, /* 927 - 896 */ 155 0x00000000, /* 959 - 928 */ 156 0x00000000, /* 991 - 960 */ 157 0x00000000, /* 1023 - 992 */ 158 0x00000000, /* 1055 - 1024 */ 159 0x00000000, /* 1087 - 1056 */ 160 0x00000000, /* 1119 - 1088 */ 161 0x00000000, /* 1151 - 1120 */ 162 0x00000000, /* 1183 - 1152 */ 163 0x00000000, /* 1215 - 1184 */ 164 0x00000000, /* 1247 - 1216 */ 165 0x00000000, /* 1279 - 1248 */ 166 0x00000000, /* 1311 - 1280 */ 167 0x00000000, /* 1343 - 1312 */ 168 0x00000000, /* 1375 - 1344 */ 169 0x00000000, /* 1407 - 1376 */ 170 0x00000000, /* 1439 - 1408 */ 171 0x00000000, /* 1471 - 1440 */ 172 0x00000000, /* 1503 - 1472 */ 173 }; 174 175 base = le32_to_cpu(il->card_alive.log_event_table_ptr); 176 if (!il3945_hw_valid_rtc_data_addr(base)) { 177 IL_ERR("Invalid event log pointer 0x%08X\n", base); 178 return; 179 } 180 181 disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32))); 182 array_size = il_read_targ_mem(il, base + (5 * sizeof(u32))); 183 184 if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) { 185 D_INFO("Disabling selected uCode log events at 0x%x\n", 186 disable_ptr); 187 for (i = 0; i < IL_EVT_DISABLE_SIZE; i++) 188 il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)), 189 evt_disable[i]); 190 191 } else { 192 D_INFO("Selected uCode log events may be disabled\n"); 193 D_INFO(" by writing \"1\"s into disable bitmap\n"); 194 D_INFO(" in SRAM at 0x%x, size %d u32s\n", disable_ptr, 195 array_size); 196 } 197 198} 199 200static int 201il3945_hwrate_to_plcp_idx(u8 plcp) 202{ 203 int idx; 204 205 for (idx = 0; idx < RATE_COUNT_3945; idx++) 206 if (il3945_rates[idx].plcp == plcp) 207 return idx; 208 return -1; 209} 210 211#ifdef CONFIG_IWLEGACY_DEBUG 212#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x 213 214static const char * 215il3945_get_tx_fail_reason(u32 status) 216{ 217 switch (status & TX_STATUS_MSK) { 218 case TX_3945_STATUS_SUCCESS: 219 return "SUCCESS"; 220 TX_STATUS_ENTRY(SHORT_LIMIT); 221 TX_STATUS_ENTRY(LONG_LIMIT); 222 TX_STATUS_ENTRY(FIFO_UNDERRUN); 223 TX_STATUS_ENTRY(MGMNT_ABORT); 224 TX_STATUS_ENTRY(NEXT_FRAG); 225 TX_STATUS_ENTRY(LIFE_EXPIRE); 226 TX_STATUS_ENTRY(DEST_PS); 227 TX_STATUS_ENTRY(ABORTED); 228 TX_STATUS_ENTRY(BT_RETRY); 229 TX_STATUS_ENTRY(STA_INVALID); 230 TX_STATUS_ENTRY(FRAG_DROPPED); 231 TX_STATUS_ENTRY(TID_DISABLE); 232 TX_STATUS_ENTRY(FRAME_FLUSHED); 233 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); 234 TX_STATUS_ENTRY(TX_LOCKED); 235 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); 236 } 237 238 return "UNKNOWN"; 239} 240#else 241static inline const char * 242il3945_get_tx_fail_reason(u32 status) 243{ 244 return ""; 245} 246#endif 247 248/* 249 * get ieee prev rate from rate scale table. 250 * for A and B mode we need to overright prev 251 * value 252 */ 253int 254il3945_rs_next_rate(struct il_priv *il, int rate) 255{ 256 int next_rate = il3945_get_prev_ieee_rate(rate); 257 258 switch (il->band) { 259 case IEEE80211_BAND_5GHZ: 260 if (rate == RATE_12M_IDX) 261 next_rate = RATE_9M_IDX; 262 else if (rate == RATE_6M_IDX) 263 next_rate = RATE_6M_IDX; 264 break; 265 case IEEE80211_BAND_2GHZ: 266 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) && 267 il_is_associated(il)) { 268 if (rate == RATE_11M_IDX) 269 next_rate = RATE_5M_IDX; 270 } 271 break; 272 273 default: 274 break; 275 } 276 277 return next_rate; 278} 279 280/** 281 * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd 282 * 283 * When FW advances 'R' idx, all entries between old and new 'R' idx 284 * need to be reclaimed. As result, some free space forms. If there is 285 * enough free space (> low mark), wake the stack that feeds us. 286 */ 287static void 288il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx) 289{ 290 struct il_tx_queue *txq = &il->txq[txq_id]; 291 struct il_queue *q = &txq->q; 292 struct sk_buff *skb; 293 294 BUG_ON(txq_id == IL39_CMD_QUEUE_NUM); 295 296 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; 297 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) { 298 299 skb = txq->skbs[txq->q.read_ptr]; 300 ieee80211_tx_status_irqsafe(il->hw, skb); 301 txq->skbs[txq->q.read_ptr] = NULL; 302 il->ops->txq_free_tfd(il, txq); 303 } 304 305 if (il_queue_space(q) > q->low_mark && txq_id >= 0 && 306 txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered) 307 il_wake_queue(il, txq); 308} 309 310/** 311 * il3945_hdl_tx - Handle Tx response 312 */ 313static void 314il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb) 315{ 316 struct il_rx_pkt *pkt = rxb_addr(rxb); 317 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 318 int txq_id = SEQ_TO_QUEUE(sequence); 319 int idx = SEQ_TO_IDX(sequence); 320 struct il_tx_queue *txq = &il->txq[txq_id]; 321 struct ieee80211_tx_info *info; 322 struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 323 u32 status = le32_to_cpu(tx_resp->status); 324 int rate_idx; 325 int fail; 326 327 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) { 328 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d " 329 "is out of range [0-%d] %d %d\n", txq_id, idx, 330 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr); 331 return; 332 } 333 334 txq->time_stamp = jiffies; 335 info = IEEE80211_SKB_CB(txq->skbs[txq->q.read_ptr]); 336 ieee80211_tx_info_clear_status(info); 337 338 /* Fill the MRR chain with some info about on-chip retransmissions */ 339 rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate); 340 if (info->band == IEEE80211_BAND_5GHZ) 341 rate_idx -= IL_FIRST_OFDM_RATE; 342 343 fail = tx_resp->failure_frame; 344 345 info->status.rates[0].idx = rate_idx; 346 info->status.rates[0].count = fail + 1; /* add final attempt */ 347 348 /* tx_status->rts_retry_count = tx_resp->failure_rts; */ 349 info->flags |= 350 ((status & TX_STATUS_MSK) == 351 TX_STATUS_SUCCESS) ? IEEE80211_TX_STAT_ACK : 0; 352 353 D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id, 354 il3945_get_tx_fail_reason(status), status, tx_resp->rate, 355 tx_resp->failure_frame); 356 357 D_TX_REPLY("Tx queue reclaim %d\n", idx); 358 il3945_tx_queue_reclaim(il, txq_id, idx); 359 360 if (status & TX_ABORT_REQUIRED_MSK) 361 IL_ERR("TODO: Implement Tx ABORT REQUIRED!!!\n"); 362} 363 364/***************************************************************************** 365 * 366 * Intel PRO/Wireless 3945ABG/BG Network Connection 367 * 368 * RX handler implementations 369 * 370 *****************************************************************************/ 371#ifdef CONFIG_IWLEGACY_DEBUGFS 372static void 373il3945_accumulative_stats(struct il_priv *il, __le32 * stats) 374{ 375 int i; 376 __le32 *prev_stats; 377 u32 *accum_stats; 378 u32 *delta, *max_delta; 379 380 prev_stats = (__le32 *) &il->_3945.stats; 381 accum_stats = (u32 *) &il->_3945.accum_stats; 382 delta = (u32 *) &il->_3945.delta_stats; 383 max_delta = (u32 *) &il->_3945.max_delta; 384 385 for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats); 386 i += 387 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++, 388 accum_stats++) { 389 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { 390 *delta = 391 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats)); 392 *accum_stats += *delta; 393 if (*delta > *max_delta) 394 *max_delta = *delta; 395 } 396 } 397 398 /* reset accumulative stats for "no-counter" type stats */ 399 il->_3945.accum_stats.general.temperature = 400 il->_3945.stats.general.temperature; 401 il->_3945.accum_stats.general.ttl_timestamp = 402 il->_3945.stats.general.ttl_timestamp; 403} 404#endif 405 406void 407il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb) 408{ 409 struct il_rx_pkt *pkt = rxb_addr(rxb); 410 411 D_RX("Statistics notification received (%d vs %d).\n", 412 (int)sizeof(struct il3945_notif_stats), 413 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK); 414#ifdef CONFIG_IWLEGACY_DEBUGFS 415 il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw); 416#endif 417 418 memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats)); 419} 420 421void 422il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb) 423{ 424 struct il_rx_pkt *pkt = rxb_addr(rxb); 425 __le32 *flag = (__le32 *) &pkt->u.raw; 426 427 if (le32_to_cpu(*flag) & UCODE_STATS_CLEAR_MSK) { 428#ifdef CONFIG_IWLEGACY_DEBUGFS 429 memset(&il->_3945.accum_stats, 0, 430 sizeof(struct il3945_notif_stats)); 431 memset(&il->_3945.delta_stats, 0, 432 sizeof(struct il3945_notif_stats)); 433 memset(&il->_3945.max_delta, 0, 434 sizeof(struct il3945_notif_stats)); 435#endif 436 D_RX("Statistics have been cleared\n"); 437 } 438 il3945_hdl_stats(il, rxb); 439} 440 441/****************************************************************************** 442 * 443 * Misc. internal state and helper functions 444 * 445 ******************************************************************************/ 446 447/* This is necessary only for a number of stats, see the caller. */ 448static int 449il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header) 450{ 451 /* Filter incoming packets to determine if they are targeted toward 452 * this network, discarding packets coming from ourselves */ 453 switch (il->iw_mode) { 454 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ 455 /* packets to our IBSS update information */ 456 return !compare_ether_addr(header->addr3, il->bssid); 457 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ 458 /* packets to our IBSS update information */ 459 return !compare_ether_addr(header->addr2, il->bssid); 460 default: 461 return 1; 462 } 463} 464 465static void 466il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb, 467 struct ieee80211_rx_status *stats) 468{ 469 struct il_rx_pkt *pkt = rxb_addr(rxb); 470 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt); 471 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt); 472 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt); 473 u16 len = le16_to_cpu(rx_hdr->len); 474 struct sk_buff *skb; 475 __le16 fc = hdr->frame_control; 476 477 /* We received data from the HW, so stop the watchdog */ 478 if (unlikely 479 (len + IL39_RX_FRAME_SIZE > 480 PAGE_SIZE << il->hw_params.rx_page_order)) { 481 D_DROP("Corruption detected!\n"); 482 return; 483 } 484 485 /* We only process data packets if the interface is open */ 486 if (unlikely(!il->is_open)) { 487 D_DROP("Dropping packet while interface is not open.\n"); 488 return; 489 } 490 491 skb = dev_alloc_skb(128); 492 if (!skb) { 493 IL_ERR("dev_alloc_skb failed\n"); 494 return; 495 } 496 497 if (!il3945_mod_params.sw_crypto) 498 il_set_decrypted_flag(il, (struct ieee80211_hdr *)rxb_addr(rxb), 499 le32_to_cpu(rx_end->status), stats); 500 501 skb_add_rx_frag(skb, 0, rxb->page, 502 (void *)rx_hdr->payload - (void *)pkt, len, 503 len); 504 505 il_update_stats(il, false, fc, len); 506 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); 507 508 ieee80211_rx(il->hw, skb); 509 il->alloc_rxb_page--; 510 rxb->page = NULL; 511} 512 513#define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) 514 515static void 516il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb) 517{ 518 struct ieee80211_hdr *header; 519 struct ieee80211_rx_status rx_status; 520 struct il_rx_pkt *pkt = rxb_addr(rxb); 521 struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt); 522 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt); 523 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt); 524 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg); 525 u16 rx_stats_noise_diff __maybe_unused = 526 le16_to_cpu(rx_stats->noise_diff); 527 u8 network_packet; 528 529 rx_status.flag = 0; 530 rx_status.mactime = le64_to_cpu(rx_end->timestamp); 531 rx_status.band = 532 (rx_hdr-> 533 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ : 534 IEEE80211_BAND_5GHZ; 535 rx_status.freq = 536 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel), 537 rx_status.band); 538 539 rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate); 540 if (rx_status.band == IEEE80211_BAND_5GHZ) 541 rx_status.rate_idx -= IL_FIRST_OFDM_RATE; 542 543 rx_status.antenna = 544 (le16_to_cpu(rx_hdr->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 545 4; 546 547 /* set the preamble flag if appropriate */ 548 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) 549 rx_status.flag |= RX_FLAG_SHORTPRE; 550 551 if ((unlikely(rx_stats->phy_count > 20))) { 552 D_DROP("dsp size out of range [0,20]: %d/n", 553 rx_stats->phy_count); 554 return; 555 } 556 557 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) || 558 !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { 559 D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status); 560 return; 561 } 562 563 /* Convert 3945's rssi indicator to dBm */ 564 rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET; 565 566 D_STATS("Rssi %d sig_avg %d noise_diff %d\n", rx_status.signal, 567 rx_stats_sig_avg, rx_stats_noise_diff); 568 569 header = (struct ieee80211_hdr *)IL_RX_DATA(pkt); 570 571 network_packet = il3945_is_network_packet(il, header); 572 573 D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n", 574 network_packet ? '*' : ' ', le16_to_cpu(rx_hdr->channel), 575 rx_status.signal, rx_status.signal, rx_status.rate_idx); 576 577 if (network_packet) { 578 il->_3945.last_beacon_time = 579 le32_to_cpu(rx_end->beacon_timestamp); 580 il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp); 581 il->_3945.last_rx_rssi = rx_status.signal; 582 } 583 584 il3945_pass_packet_to_mac80211(il, rxb, &rx_status); 585} 586 587int 588il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, 589 dma_addr_t addr, u16 len, u8 reset, u8 pad) 590{ 591 int count; 592 struct il_queue *q; 593 struct il3945_tfd *tfd, *tfd_tmp; 594 595 q = &txq->q; 596 tfd_tmp = (struct il3945_tfd *)txq->tfds; 597 tfd = &tfd_tmp[q->write_ptr]; 598 599 if (reset) 600 memset(tfd, 0, sizeof(*tfd)); 601 602 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); 603 604 if (count >= NUM_TFD_CHUNKS || count < 0) { 605 IL_ERR("Error can not send more than %d chunks\n", 606 NUM_TFD_CHUNKS); 607 return -EINVAL; 608 } 609 610 tfd->tbs[count].addr = cpu_to_le32(addr); 611 tfd->tbs[count].len = cpu_to_le32(len); 612 613 count++; 614 615 tfd->control_flags = 616 cpu_to_le32(TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad)); 617 618 return 0; 619} 620 621/** 622 * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr] 623 * 624 * Does NOT advance any idxes 625 */ 626void 627il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq) 628{ 629 struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds; 630 int idx = txq->q.read_ptr; 631 struct il3945_tfd *tfd = &tfd_tmp[idx]; 632 struct pci_dev *dev = il->pci_dev; 633 int i; 634 int counter; 635 636 /* sanity check */ 637 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); 638 if (counter > NUM_TFD_CHUNKS) { 639 IL_ERR("Too many chunks: %i\n", counter); 640 /* @todo issue fatal error, it is quite serious situation */ 641 return; 642 } 643 644 /* Unmap tx_cmd */ 645 if (counter) 646 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping), 647 dma_unmap_len(&txq->meta[idx], len), 648 PCI_DMA_TODEVICE); 649 650 /* unmap chunks if any */ 651 652 for (i = 1; i < counter; i++) 653 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr), 654 le32_to_cpu(tfd->tbs[i].len), 655 PCI_DMA_TODEVICE); 656 657 /* free SKB */ 658 if (txq->skbs) { 659 struct sk_buff *skb = txq->skbs[txq->q.read_ptr]; 660 661 /* can be called from irqs-disabled context */ 662 if (skb) { 663 dev_kfree_skb_any(skb); 664 txq->skbs[txq->q.read_ptr] = NULL; 665 } 666 } 667} 668 669/** 670 * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD: 671 * 672*/ 673void 674il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd, 675 struct ieee80211_tx_info *info, 676 struct ieee80211_hdr *hdr, int sta_id) 677{ 678 u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value; 679 u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945 - 1); 680 u16 rate_mask; 681 int rate; 682 const u8 rts_retry_limit = 7; 683 u8 data_retry_limit; 684 __le32 tx_flags; 685 __le16 fc = hdr->frame_control; 686 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload; 687 688 rate = il3945_rates[rate_idx].plcp; 689 tx_flags = tx_cmd->tx_flags; 690 691 /* We need to figure out how to get the sta->supp_rates while 692 * in this running context */ 693 rate_mask = RATES_MASK_3945; 694 695 /* Set retry limit on DATA packets and Probe Responses */ 696 if (ieee80211_is_probe_resp(fc)) 697 data_retry_limit = 3; 698 else 699 data_retry_limit = IL_DEFAULT_TX_RETRY; 700 tx_cmd->data_retry_limit = data_retry_limit; 701 /* Set retry limit on RTS packets */ 702 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit); 703 704 tx_cmd->rate = rate; 705 tx_cmd->tx_flags = tx_flags; 706 707 /* OFDM */ 708 tx_cmd->supp_rates[0] = 709 ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF; 710 711 /* CCK */ 712 tx_cmd->supp_rates[1] = (rate_mask & 0xF); 713 714 D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X " 715 "cck/ofdm mask: 0x%x/0x%x\n", sta_id, tx_cmd->rate, 716 le32_to_cpu(tx_cmd->tx_flags), tx_cmd->supp_rates[1], 717 tx_cmd->supp_rates[0]); 718} 719 720static u8 721il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate) 722{ 723 unsigned long flags_spin; 724 struct il_station_entry *station; 725 726 if (sta_id == IL_INVALID_STATION) 727 return IL_INVALID_STATION; 728 729 spin_lock_irqsave(&il->sta_lock, flags_spin); 730 station = &il->stations[sta_id]; 731 732 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK; 733 station->sta.rate_n_flags = cpu_to_le16(tx_rate); 734 station->sta.mode = STA_CONTROL_MODIFY_MSK; 735 il_send_add_sta(il, &station->sta, CMD_ASYNC); 736 spin_unlock_irqrestore(&il->sta_lock, flags_spin); 737 738 D_RATE("SCALE sync station %d to rate %d\n", sta_id, tx_rate); 739 return sta_id; 740} 741 742static void 743il3945_set_pwr_vmain(struct il_priv *il) 744{ 745/* 746 * (for documentation purposes) 747 * to set power to V_AUX, do 748 749 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) { 750 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 751 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 752 ~APMG_PS_CTRL_MSK_PWR_SRC); 753 754 _il_poll_bit(il, CSR_GPIO_IN, 755 CSR_GPIO_IN_VAL_VAUX_PWR_SRC, 756 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 757 } 758 */ 759 760 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 761 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 762 ~APMG_PS_CTRL_MSK_PWR_SRC); 763 764 _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, 765 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 766} 767 768static int 769il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq) 770{ 771 il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma); 772 il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma); 773 il_wr(il, FH39_RCSR_WPTR(0), 0); 774 il_wr(il, FH39_RCSR_CONFIG(0), 775 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | 776 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | 777 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | 778 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | (RX_QUEUE_SIZE_LOG 779 << 780 FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) 781 | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | (1 << 782 FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) 783 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); 784 785 /* fake read to flush all prev I/O */ 786 il_rd(il, FH39_RSSR_CTRL); 787 788 return 0; 789} 790 791static int 792il3945_tx_reset(struct il_priv *il) 793{ 794 /* bypass mode */ 795 il_wr_prph(il, ALM_SCD_MODE_REG, 0x2); 796 797 /* RA 0 is active */ 798 il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01); 799 800 /* all 6 fifo are active */ 801 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f); 802 803 il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000); 804 il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002); 805 il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004); 806 il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005); 807 808 il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys); 809 810 il_wr(il, FH39_TSSR_MSG_CONFIG, 811 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | 812 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | 813 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | 814 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON | 815 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON | 816 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | 817 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); 818 819 return 0; 820} 821 822/** 823 * il3945_txq_ctx_reset - Reset TX queue context 824 * 825 * Destroys all DMA structures and initialize them again 826 */ 827static int 828il3945_txq_ctx_reset(struct il_priv *il) 829{ 830 int rc, txq_id; 831 832 il3945_hw_txq_ctx_free(il); 833 834 /* allocate tx queue structure */ 835 rc = il_alloc_txq_mem(il); 836 if (rc) 837 return rc; 838 839 /* Tx CMD queue */ 840 rc = il3945_tx_reset(il); 841 if (rc) 842 goto error; 843 844 /* Tx queue(s) */ 845 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { 846 rc = il_tx_queue_init(il, txq_id); 847 if (rc) { 848 IL_ERR("Tx %d queue init failed\n", txq_id); 849 goto error; 850 } 851 } 852 853 return rc; 854 855error: 856 il3945_hw_txq_ctx_free(il); 857 return rc; 858} 859 860/* 861 * Start up 3945's basic functionality after it has been reset 862 * (e.g. after platform boot, or shutdown via il_apm_stop()) 863 * NOTE: This does not load uCode nor start the embedded processor 864 */ 865static int 866il3945_apm_init(struct il_priv *il) 867{ 868 int ret = il_apm_init(il); 869 870 /* Clear APMG (NIC's internal power management) interrupts */ 871 il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0); 872 il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF); 873 874 /* Reset radio chip */ 875 il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ); 876 udelay(5); 877 il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ); 878 879 return ret; 880} 881 882static void 883il3945_nic_config(struct il_priv *il) 884{ 885 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 886 unsigned long flags; 887 u8 rev_id = il->pci_dev->revision; 888 889 spin_lock_irqsave(&il->lock, flags); 890 891 /* Determine HW type */ 892 D_INFO("HW Revision ID = 0x%X\n", rev_id); 893 894 if (rev_id & PCI_CFG_REV_ID_BIT_RTP) 895 D_INFO("RTP type\n"); 896 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { 897 D_INFO("3945 RADIO-MB type\n"); 898 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 899 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB); 900 } else { 901 D_INFO("3945 RADIO-MM type\n"); 902 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 903 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM); 904 } 905 906 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) { 907 D_INFO("SKU OP mode is mrc\n"); 908 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 909 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC); 910 } else 911 D_INFO("SKU OP mode is basic\n"); 912 913 if ((eeprom->board_revision & 0xF0) == 0xD0) { 914 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision); 915 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 916 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 917 } else { 918 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision); 919 il_clear_bit(il, CSR_HW_IF_CONFIG_REG, 920 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 921 } 922 923 if (eeprom->almgor_m_version <= 1) { 924 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 925 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); 926 D_INFO("Card M type A version is 0x%X\n", 927 eeprom->almgor_m_version); 928 } else { 929 D_INFO("Card M type B version is 0x%X\n", 930 eeprom->almgor_m_version); 931 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 932 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); 933 } 934 spin_unlock_irqrestore(&il->lock, flags); 935 936 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE) 937 D_RF_KILL("SW RF KILL supported in EEPROM.\n"); 938 939 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE) 940 D_RF_KILL("HW RF KILL supported in EEPROM.\n"); 941} 942 943int 944il3945_hw_nic_init(struct il_priv *il) 945{ 946 int rc; 947 unsigned long flags; 948 struct il_rx_queue *rxq = &il->rxq; 949 950 spin_lock_irqsave(&il->lock, flags); 951 il3945_apm_init(il); 952 spin_unlock_irqrestore(&il->lock, flags); 953 954 il3945_set_pwr_vmain(il); 955 il3945_nic_config(il); 956 957 /* Allocate the RX queue, or reset if it is already allocated */ 958 if (!rxq->bd) { 959 rc = il_rx_queue_alloc(il); 960 if (rc) { 961 IL_ERR("Unable to initialize Rx queue\n"); 962 return -ENOMEM; 963 } 964 } else 965 il3945_rx_queue_reset(il, rxq); 966 967 il3945_rx_replenish(il); 968 969 il3945_rx_init(il, rxq); 970 971 /* Look at using this instead: 972 rxq->need_update = 1; 973 il_rx_queue_update_write_ptr(il, rxq); 974 */ 975 976 il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7); 977 978 rc = il3945_txq_ctx_reset(il); 979 if (rc) 980 return rc; 981 982 set_bit(S_INIT, &il->status); 983 984 return 0; 985} 986 987/** 988 * il3945_hw_txq_ctx_free - Free TXQ Context 989 * 990 * Destroy all TX DMA queues and structures 991 */ 992void 993il3945_hw_txq_ctx_free(struct il_priv *il) 994{ 995 int txq_id; 996 997 /* Tx queues */ 998 if (il->txq) 999 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 1000 if (txq_id == IL39_CMD_QUEUE_NUM) 1001 il_cmd_queue_free(il); 1002 else 1003 il_tx_queue_free(il, txq_id); 1004 1005 /* free tx queue structure */ 1006 il_free_txq_mem(il); 1007} 1008 1009void 1010il3945_hw_txq_ctx_stop(struct il_priv *il) 1011{ 1012 int txq_id; 1013 1014 /* stop SCD */ 1015 _il_wr_prph(il, ALM_SCD_MODE_REG, 0); 1016 _il_wr_prph(il, ALM_SCD_TXFACT_REG, 0); 1017 1018 /* reset TFD queues */ 1019 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { 1020 _il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0); 1021 _il_poll_bit(il, FH39_TSSR_TX_STATUS, 1022 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), 1023 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), 1024 1000); 1025 } 1026} 1027 1028/** 1029 * il3945_hw_reg_adjust_power_by_temp 1030 * return idx delta into power gain settings table 1031*/ 1032static int 1033il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading) 1034{ 1035 return (new_reading - old_reading) * (-11) / 100; 1036} 1037 1038/** 1039 * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range 1040 */ 1041static inline int 1042il3945_hw_reg_temp_out_of_range(int temperature) 1043{ 1044 return (temperature < -260 || temperature > 25) ? 1 : 0; 1045} 1046 1047int 1048il3945_hw_get_temperature(struct il_priv *il) 1049{ 1050 return _il_rd(il, CSR_UCODE_DRV_GP2); 1051} 1052 1053/** 1054 * il3945_hw_reg_txpower_get_temperature 1055 * get the current temperature by reading from NIC 1056*/ 1057static int 1058il3945_hw_reg_txpower_get_temperature(struct il_priv *il) 1059{ 1060 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1061 int temperature; 1062 1063 temperature = il3945_hw_get_temperature(il); 1064 1065 /* driver's okay range is -260 to +25. 1066 * human readable okay range is 0 to +285 */ 1067 D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT); 1068 1069 /* handle insane temp reading */ 1070 if (il3945_hw_reg_temp_out_of_range(temperature)) { 1071 IL_ERR("Error bad temperature value %d\n", temperature); 1072 1073 /* if really really hot(?), 1074 * substitute the 3rd band/group's temp measured at factory */ 1075 if (il->last_temperature > 100) 1076 temperature = eeprom->groups[2].temperature; 1077 else /* else use most recent "sane" value from driver */ 1078 temperature = il->last_temperature; 1079 } 1080 1081 return temperature; /* raw, not "human readable" */ 1082} 1083 1084/* Adjust Txpower only if temperature variance is greater than threshold. 1085 * 1086 * Both are lower than older versions' 9 degrees */ 1087#define IL_TEMPERATURE_LIMIT_TIMER 6 1088 1089/** 1090 * il3945_is_temp_calib_needed - determines if new calibration is needed 1091 * 1092 * records new temperature in tx_mgr->temperature. 1093 * replaces tx_mgr->last_temperature *only* if calib needed 1094 * (assumes caller will actually do the calibration!). */ 1095static int 1096il3945_is_temp_calib_needed(struct il_priv *il) 1097{ 1098 int temp_diff; 1099 1100 il->temperature = il3945_hw_reg_txpower_get_temperature(il); 1101 temp_diff = il->temperature - il->last_temperature; 1102 1103 /* get absolute value */ 1104 if (temp_diff < 0) { 1105 D_POWER("Getting cooler, delta %d,\n", temp_diff); 1106 temp_diff = -temp_diff; 1107 } else if (temp_diff == 0) 1108 D_POWER("Same temp,\n"); 1109 else 1110 D_POWER("Getting warmer, delta %d,\n", temp_diff); 1111 1112 /* if we don't need calibration, *don't* update last_temperature */ 1113 if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) { 1114 D_POWER("Timed thermal calib not needed\n"); 1115 return 0; 1116 } 1117 1118 D_POWER("Timed thermal calib needed\n"); 1119 1120 /* assume that caller will actually do calib ... 1121 * update the "last temperature" value */ 1122 il->last_temperature = il->temperature; 1123 return 1; 1124} 1125 1126#define IL_MAX_GAIN_ENTRIES 78 1127#define IL_CCK_FROM_OFDM_POWER_DIFF -5 1128#define IL_CCK_FROM_OFDM_IDX_DIFF (10) 1129 1130/* radio and DSP power table, each step is 1/2 dB. 1131 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */ 1132static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = { 1133 { 1134 {251, 127}, /* 2.4 GHz, highest power */ 1135 {251, 127}, 1136 {251, 127}, 1137 {251, 127}, 1138 {251, 125}, 1139 {251, 110}, 1140 {251, 105}, 1141 {251, 98}, 1142 {187, 125}, 1143 {187, 115}, 1144 {187, 108}, 1145 {187, 99}, 1146 {243, 119}, 1147 {243, 111}, 1148 {243, 105}, 1149 {243, 97}, 1150 {243, 92}, 1151 {211, 106}, 1152 {211, 100}, 1153 {179, 120}, 1154 {179, 113}, 1155 {179, 107}, 1156 {147, 125}, 1157 {147, 119}, 1158 {147, 112}, 1159 {147, 106}, 1160 {147, 101}, 1161 {147, 97}, 1162 {147, 91}, 1163 {115, 107}, 1164 {235, 121}, 1165 {235, 115}, 1166 {235, 109}, 1167 {203, 127}, 1168 {203, 121}, 1169 {203, 115}, 1170 {203, 108}, 1171 {203, 102}, 1172 {203, 96}, 1173 {203, 92}, 1174 {171, 110}, 1175 {171, 104}, 1176 {171, 98}, 1177 {139, 116}, 1178 {227, 125}, 1179 {227, 119}, 1180 {227, 113}, 1181 {227, 107}, 1182 {227, 101}, 1183 {227, 96}, 1184 {195, 113}, 1185 {195, 106}, 1186 {195, 102}, 1187 {195, 95}, 1188 {163, 113}, 1189 {163, 106}, 1190 {163, 102}, 1191 {163, 95}, 1192 {131, 113}, 1193 {131, 106}, 1194 {131, 102}, 1195 {131, 95}, 1196 {99, 113}, 1197 {99, 106}, 1198 {99, 102}, 1199 {99, 95}, 1200 {67, 113}, 1201 {67, 106}, 1202 {67, 102}, 1203 {67, 95}, 1204 {35, 113}, 1205 {35, 106}, 1206 {35, 102}, 1207 {35, 95}, 1208 {3, 113}, 1209 {3, 106}, 1210 {3, 102}, 1211 {3, 95} /* 2.4 GHz, lowest power */ 1212 }, 1213 { 1214 {251, 127}, /* 5.x GHz, highest power */ 1215 {251, 120}, 1216 {251, 114}, 1217 {219, 119}, 1218 {219, 101}, 1219 {187, 113}, 1220 {187, 102}, 1221 {155, 114}, 1222 {155, 103}, 1223 {123, 117}, 1224 {123, 107}, 1225 {123, 99}, 1226 {123, 92}, 1227 {91, 108}, 1228 {59, 125}, 1229 {59, 118}, 1230 {59, 109}, 1231 {59, 102}, 1232 {59, 96}, 1233 {59, 90}, 1234 {27, 104}, 1235 {27, 98}, 1236 {27, 92}, 1237 {115, 118}, 1238 {115, 111}, 1239 {115, 104}, 1240 {83, 126}, 1241 {83, 121}, 1242 {83, 113}, 1243 {83, 105}, 1244 {83, 99}, 1245 {51, 118}, 1246 {51, 111}, 1247 {51, 104}, 1248 {51, 98}, 1249 {19, 116}, 1250 {19, 109}, 1251 {19, 102}, 1252 {19, 98}, 1253 {19, 93}, 1254 {171, 113}, 1255 {171, 107}, 1256 {171, 99}, 1257 {139, 120}, 1258 {139, 113}, 1259 {139, 107}, 1260 {139, 99}, 1261 {107, 120}, 1262 {107, 113}, 1263 {107, 107}, 1264 {107, 99}, 1265 {75, 120}, 1266 {75, 113}, 1267 {75, 107}, 1268 {75, 99}, 1269 {43, 120}, 1270 {43, 113}, 1271 {43, 107}, 1272 {43, 99}, 1273 {11, 120}, 1274 {11, 113}, 1275 {11, 107}, 1276 {11, 99}, 1277 {131, 107}, 1278 {131, 99}, 1279 {99, 120}, 1280 {99, 113}, 1281 {99, 107}, 1282 {99, 99}, 1283 {67, 120}, 1284 {67, 113}, 1285 {67, 107}, 1286 {67, 99}, 1287 {35, 120}, 1288 {35, 113}, 1289 {35, 107}, 1290 {35, 99}, 1291 {3, 120} /* 5.x GHz, lowest power */ 1292 } 1293}; 1294 1295static inline u8 1296il3945_hw_reg_fix_power_idx(int idx) 1297{ 1298 if (idx < 0) 1299 return 0; 1300 if (idx >= IL_MAX_GAIN_ENTRIES) 1301 return IL_MAX_GAIN_ENTRIES - 1; 1302 return (u8) idx; 1303} 1304 1305/* Kick off thermal recalibration check every 60 seconds */ 1306#define REG_RECALIB_PERIOD (60) 1307 1308/** 1309 * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests 1310 * 1311 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK) 1312 * or 6 Mbit (OFDM) rates. 1313 */ 1314static void 1315il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx, 1316 const s8 *clip_pwrs, 1317 struct il_channel_info *ch_info, int band_idx) 1318{ 1319 struct il3945_scan_power_info *scan_power_info; 1320 s8 power; 1321 u8 power_idx; 1322 1323 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx]; 1324 1325 /* use this channel group's 6Mbit clipping/saturation pwr, 1326 * but cap at regulatory scan power restriction (set during init 1327 * based on eeprom channel data) for this channel. */ 1328 power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]); 1329 1330 power = min(power, il->tx_power_user_lmt); 1331 scan_power_info->requested_power = power; 1332 1333 /* find difference between new scan *power* and current "normal" 1334 * Tx *power* for 6Mb. Use this difference (x2) to adjust the 1335 * current "normal" temperature-compensated Tx power *idx* for 1336 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power 1337 * *idx*. */ 1338 power_idx = 1339 ch_info->power_info[rate_idx].power_table_idx - (power - 1340 ch_info-> 1341 power_info 1342 [RATE_6M_IDX_TBL]. 1343 requested_power) * 1344 2; 1345 1346 /* store reference idx that we use when adjusting *all* scan 1347 * powers. So we can accommodate user (all channel) or spectrum 1348 * management (single channel) power changes "between" temperature 1349 * feedback compensation procedures. 1350 * don't force fit this reference idx into gain table; it may be a 1351 * negative number. This will help avoid errors when we're at 1352 * the lower bounds (highest gains, for warmest temperatures) 1353 * of the table. */ 1354 1355 /* don't exceed table bounds for "real" setting */ 1356 power_idx = il3945_hw_reg_fix_power_idx(power_idx); 1357 1358 scan_power_info->power_table_idx = power_idx; 1359 scan_power_info->tpc.tx_gain = 1360 power_gain_table[band_idx][power_idx].tx_gain; 1361 scan_power_info->tpc.dsp_atten = 1362 power_gain_table[band_idx][power_idx].dsp_atten; 1363} 1364 1365/** 1366 * il3945_send_tx_power - fill in Tx Power command with gain settings 1367 * 1368 * Configures power settings for all rates for the current channel, 1369 * using values from channel info struct, and send to NIC 1370 */ 1371static int 1372il3945_send_tx_power(struct il_priv *il) 1373{ 1374 int rate_idx, i; 1375 const struct il_channel_info *ch_info = NULL; 1376 struct il3945_txpowertable_cmd txpower = { 1377 .channel = il->active.channel, 1378 }; 1379 u16 chan; 1380 1381 if (WARN_ONCE 1382 (test_bit(S_SCAN_HW, &il->status), 1383 "TX Power requested while scanning!\n")) 1384 return -EAGAIN; 1385 1386 chan = le16_to_cpu(il->active.channel); 1387 1388 txpower.band = (il->band == IEEE80211_BAND_5GHZ) ? 0 : 1; 1389 ch_info = il_get_channel_info(il, il->band, chan); 1390 if (!ch_info) { 1391 IL_ERR("Failed to get channel info for channel %d [%d]\n", chan, 1392 il->band); 1393 return -EINVAL; 1394 } 1395 1396 if (!il_is_channel_valid(ch_info)) { 1397 D_POWER("Not calling TX_PWR_TBL_CMD on " "non-Tx channel.\n"); 1398 return 0; 1399 } 1400 1401 /* fill cmd with power settings for all rates for current channel */ 1402 /* Fill OFDM rate */ 1403 for (rate_idx = IL_FIRST_OFDM_RATE, i = 0; 1404 rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) { 1405 1406 txpower.power[i].tpc = ch_info->power_info[i].tpc; 1407 txpower.power[i].rate = il3945_rates[rate_idx].plcp; 1408 1409 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", 1410 le16_to_cpu(txpower.channel), txpower.band, 1411 txpower.power[i].tpc.tx_gain, 1412 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate); 1413 } 1414 /* Fill CCK rates */ 1415 for (rate_idx = IL_FIRST_CCK_RATE; rate_idx <= IL_LAST_CCK_RATE; 1416 rate_idx++, i++) { 1417 txpower.power[i].tpc = ch_info->power_info[i].tpc; 1418 txpower.power[i].rate = il3945_rates[rate_idx].plcp; 1419 1420 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", 1421 le16_to_cpu(txpower.channel), txpower.band, 1422 txpower.power[i].tpc.tx_gain, 1423 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate); 1424 } 1425 1426 return il_send_cmd_pdu(il, C_TX_PWR_TBL, 1427 sizeof(struct il3945_txpowertable_cmd), 1428 &txpower); 1429 1430} 1431 1432/** 1433 * il3945_hw_reg_set_new_power - Configures power tables at new levels 1434 * @ch_info: Channel to update. Uses power_info.requested_power. 1435 * 1436 * Replace requested_power and base_power_idx ch_info fields for 1437 * one channel. 1438 * 1439 * Called if user or spectrum management changes power preferences. 1440 * Takes into account h/w and modulation limitations (clip power). 1441 * 1442 * This does *not* send anything to NIC, just sets up ch_info for one channel. 1443 * 1444 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to 1445 * properly fill out the scan powers, and actual h/w gain settings, 1446 * and send changes to NIC 1447 */ 1448static int 1449il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info) 1450{ 1451 struct il3945_channel_power_info *power_info; 1452 int power_changed = 0; 1453 int i; 1454 const s8 *clip_pwrs; 1455 int power; 1456 1457 /* Get this chnlgrp's rate-to-max/clip-powers table */ 1458 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers; 1459 1460 /* Get this channel's rate-to-current-power settings table */ 1461 power_info = ch_info->power_info; 1462 1463 /* update OFDM Txpower settings */ 1464 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++, ++power_info) { 1465 int delta_idx; 1466 1467 /* limit new power to be no more than h/w capability */ 1468 power = min(ch_info->curr_txpow, clip_pwrs[i]); 1469 if (power == power_info->requested_power) 1470 continue; 1471 1472 /* find difference between old and new requested powers, 1473 * update base (non-temp-compensated) power idx */ 1474 delta_idx = (power - power_info->requested_power) * 2; 1475 power_info->base_power_idx -= delta_idx; 1476 1477 /* save new requested power value */ 1478 power_info->requested_power = power; 1479 1480 power_changed = 1; 1481 } 1482 1483 /* update CCK Txpower settings, based on OFDM 12M setting ... 1484 * ... all CCK power settings for a given channel are the *same*. */ 1485 if (power_changed) { 1486 power = 1487 ch_info->power_info[RATE_12M_IDX_TBL].requested_power + 1488 IL_CCK_FROM_OFDM_POWER_DIFF; 1489 1490 /* do all CCK rates' il3945_channel_power_info structures */ 1491 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) { 1492 power_info->requested_power = power; 1493 power_info->base_power_idx = 1494 ch_info->power_info[RATE_12M_IDX_TBL]. 1495 base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF; 1496 ++power_info; 1497 } 1498 } 1499 1500 return 0; 1501} 1502 1503/** 1504 * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel 1505 * 1506 * NOTE: Returned power limit may be less (but not more) than requested, 1507 * based strictly on regulatory (eeprom and spectrum mgt) limitations 1508 * (no consideration for h/w clipping limitations). 1509 */ 1510static int 1511il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info) 1512{ 1513 s8 max_power; 1514 1515#if 0 1516 /* if we're using TGd limits, use lower of TGd or EEPROM */ 1517 if (ch_info->tgd_data.max_power != 0) 1518 max_power = 1519 min(ch_info->tgd_data.max_power, 1520 ch_info->eeprom.max_power_avg); 1521 1522 /* else just use EEPROM limits */ 1523 else 1524#endif 1525 max_power = ch_info->eeprom.max_power_avg; 1526 1527 return min(max_power, ch_info->max_power_avg); 1528} 1529 1530/** 1531 * il3945_hw_reg_comp_txpower_temp - Compensate for temperature 1532 * 1533 * Compensate txpower settings of *all* channels for temperature. 1534 * This only accounts for the difference between current temperature 1535 * and the factory calibration temperatures, and bases the new settings 1536 * on the channel's base_power_idx. 1537 * 1538 * If RxOn is "associated", this sends the new Txpower to NIC! 1539 */ 1540static int 1541il3945_hw_reg_comp_txpower_temp(struct il_priv *il) 1542{ 1543 struct il_channel_info *ch_info = NULL; 1544 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1545 int delta_idx; 1546 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */ 1547 u8 a_band; 1548 u8 rate_idx; 1549 u8 scan_tbl_idx; 1550 u8 i; 1551 int ref_temp; 1552 int temperature = il->temperature; 1553 1554 if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) { 1555 /* do not perform tx power calibration */ 1556 return 0; 1557 } 1558 /* set up new Tx power info for each and every channel, 2.4 and 5.x */ 1559 for (i = 0; i < il->channel_count; i++) { 1560 ch_info = &il->channel_info[i]; 1561 a_band = il_is_channel_a_band(ch_info); 1562 1563 /* Get this chnlgrp's factory calibration temperature */ 1564 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature; 1565 1566 /* get power idx adjustment based on current and factory 1567 * temps */ 1568 delta_idx = 1569 il3945_hw_reg_adjust_power_by_temp(temperature, ref_temp); 1570 1571 /* set tx power value for all rates, OFDM and CCK */ 1572 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; rate_idx++) { 1573 int power_idx = 1574 ch_info->power_info[rate_idx].base_power_idx; 1575 1576 /* temperature compensate */ 1577 power_idx += delta_idx; 1578 1579 /* stay within table range */ 1580 power_idx = il3945_hw_reg_fix_power_idx(power_idx); 1581 ch_info->power_info[rate_idx].power_table_idx = 1582 (u8) power_idx; 1583 ch_info->power_info[rate_idx].tpc = 1584 power_gain_table[a_band][power_idx]; 1585 } 1586 1587 /* Get this chnlgrp's rate-to-max/clip-powers table */ 1588 clip_pwrs = 1589 il->_3945.clip_groups[ch_info->group_idx].clip_powers; 1590 1591 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ 1592 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES; 1593 scan_tbl_idx++) { 1594 s32 actual_idx = 1595 (scan_tbl_idx == 1596 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL; 1597 il3945_hw_reg_set_scan_power(il, scan_tbl_idx, 1598 actual_idx, clip_pwrs, 1599 ch_info, a_band); 1600 } 1601 } 1602 1603 /* send Txpower command for current channel to ucode */ 1604 return il->ops->send_tx_power(il); 1605} 1606 1607int 1608il3945_hw_reg_set_txpower(struct il_priv *il, s8 power) 1609{ 1610 struct il_channel_info *ch_info; 1611 s8 max_power; 1612 u8 a_band; 1613 u8 i; 1614 1615 if (il->tx_power_user_lmt == power) { 1616 D_POWER("Requested Tx power same as current " "limit: %ddBm.\n", 1617 power); 1618 return 0; 1619 } 1620 1621 D_POWER("Setting upper limit clamp to %ddBm.\n", power); 1622 il->tx_power_user_lmt = power; 1623 1624 /* set up new Tx powers for each and every channel, 2.4 and 5.x */ 1625 1626 for (i = 0; i < il->channel_count; i++) { 1627 ch_info = &il->channel_info[i]; 1628 a_band = il_is_channel_a_band(ch_info); 1629 1630 /* find minimum power of all user and regulatory constraints 1631 * (does not consider h/w clipping limitations) */ 1632 max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info); 1633 max_power = min(power, max_power); 1634 if (max_power != ch_info->curr_txpow) { 1635 ch_info->curr_txpow = max_power; 1636 1637 /* this considers the h/w clipping limitations */ 1638 il3945_hw_reg_set_new_power(il, ch_info); 1639 } 1640 } 1641 1642 /* update txpower settings for all channels, 1643 * send to NIC if associated. */ 1644 il3945_is_temp_calib_needed(il); 1645 il3945_hw_reg_comp_txpower_temp(il); 1646 1647 return 0; 1648} 1649 1650static int 1651il3945_send_rxon_assoc(struct il_priv *il) 1652{ 1653 int rc = 0; 1654 struct il_rx_pkt *pkt; 1655 struct il3945_rxon_assoc_cmd rxon_assoc; 1656 struct il_host_cmd cmd = { 1657 .id = C_RXON_ASSOC, 1658 .len = sizeof(rxon_assoc), 1659 .flags = CMD_WANT_SKB, 1660 .data = &rxon_assoc, 1661 }; 1662 const struct il_rxon_cmd *rxon1 = &il->staging; 1663 const struct il_rxon_cmd *rxon2 = &il->active; 1664 1665 if (rxon1->flags == rxon2->flags && 1666 rxon1->filter_flags == rxon2->filter_flags && 1667 rxon1->cck_basic_rates == rxon2->cck_basic_rates && 1668 rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) { 1669 D_INFO("Using current RXON_ASSOC. Not resending.\n"); 1670 return 0; 1671 } 1672 1673 rxon_assoc.flags = il->staging.flags; 1674 rxon_assoc.filter_flags = il->staging.filter_flags; 1675 rxon_assoc.ofdm_basic_rates = il->staging.ofdm_basic_rates; 1676 rxon_assoc.cck_basic_rates = il->staging.cck_basic_rates; 1677 rxon_assoc.reserved = 0; 1678 1679 rc = il_send_cmd_sync(il, &cmd); 1680 if (rc) 1681 return rc; 1682 1683 pkt = (struct il_rx_pkt *)cmd.reply_page; 1684 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { 1685 IL_ERR("Bad return from C_RXON_ASSOC command\n"); 1686 rc = -EIO; 1687 } 1688 1689 il_free_pages(il, cmd.reply_page); 1690 1691 return rc; 1692} 1693 1694/** 1695 * il3945_commit_rxon - commit staging_rxon to hardware 1696 * 1697 * The RXON command in staging_rxon is committed to the hardware and 1698 * the active_rxon structure is updated with the new data. This 1699 * function correctly transitions out of the RXON_ASSOC_MSK state if 1700 * a HW tune is required based on the RXON structure changes. 1701 */ 1702int 1703il3945_commit_rxon(struct il_priv *il) 1704{ 1705 /* cast away the const for active_rxon in this function */ 1706 struct il3945_rxon_cmd *active_rxon = (void *)&il->active; 1707 struct il3945_rxon_cmd *staging_rxon = (void *)&il->staging; 1708 int rc = 0; 1709 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK); 1710 1711 if (test_bit(S_EXIT_PENDING, &il->status)) 1712 return -EINVAL; 1713 1714 if (!il_is_alive(il)) 1715 return -1; 1716 1717 /* always get timestamp with Rx frame */ 1718 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK; 1719 1720 /* select antenna */ 1721 staging_rxon->flags &= ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK); 1722 staging_rxon->flags |= il3945_get_antenna_flags(il); 1723 1724 rc = il_check_rxon_cmd(il); 1725 if (rc) { 1726 IL_ERR("Invalid RXON configuration. Not committing.\n"); 1727 return -EINVAL; 1728 } 1729 1730 /* If we don't need to send a full RXON, we can use 1731 * il3945_rxon_assoc_cmd which is used to reconfigure filter 1732 * and other flags for the current radio configuration. */ 1733 if (!il_full_rxon_required(il)) { 1734 rc = il_send_rxon_assoc(il); 1735 if (rc) { 1736 IL_ERR("Error setting RXON_ASSOC " 1737 "configuration (%d).\n", rc); 1738 return rc; 1739 } 1740 1741 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon)); 1742 /* 1743 * We do not commit tx power settings while channel changing, 1744 * do it now if tx power changed. 1745 */ 1746 il_set_tx_power(il, il->tx_power_next, false); 1747 return 0; 1748 } 1749 1750 /* If we are currently associated and the new config requires 1751 * an RXON_ASSOC and the new config wants the associated mask enabled, 1752 * we must clear the associated from the active configuration 1753 * before we apply the new config */ 1754 if (il_is_associated(il) && new_assoc) { 1755 D_INFO("Toggling associated bit on current RXON\n"); 1756 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 1757 1758 /* 1759 * reserved4 and 5 could have been filled by the iwlcore code. 1760 * Let's clear them before pushing to the 3945. 1761 */ 1762 active_rxon->reserved4 = 0; 1763 active_rxon->reserved5 = 0; 1764 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd), 1765 &il->active); 1766 1767 /* If the mask clearing failed then we set 1768 * active_rxon back to what it was previously */ 1769 if (rc) { 1770 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; 1771 IL_ERR("Error clearing ASSOC_MSK on current " 1772 "configuration (%d).\n", rc); 1773 return rc; 1774 } 1775 il_clear_ucode_stations(il); 1776 il_restore_stations(il); 1777 } 1778 1779 D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n" 1780 "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"), 1781 le16_to_cpu(staging_rxon->channel), staging_rxon->bssid_addr); 1782 1783 /* 1784 * reserved4 and 5 could have been filled by the iwlcore code. 1785 * Let's clear them before pushing to the 3945. 1786 */ 1787 staging_rxon->reserved4 = 0; 1788 staging_rxon->reserved5 = 0; 1789 1790 il_set_rxon_hwcrypto(il, !il3945_mod_params.sw_crypto); 1791 1792 /* Apply the new configuration */ 1793 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd), 1794 staging_rxon); 1795 if (rc) { 1796 IL_ERR("Error setting new configuration (%d).\n", rc); 1797 return rc; 1798 } 1799 1800 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon)); 1801 1802 if (!new_assoc) { 1803 il_clear_ucode_stations(il); 1804 il_restore_stations(il); 1805 } 1806 1807 /* If we issue a new RXON command which required a tune then we must 1808 * send a new TXPOWER command or we won't be able to Tx any frames */ 1809 rc = il_set_tx_power(il, il->tx_power_next, true); 1810 if (rc) { 1811 IL_ERR("Error setting Tx power (%d).\n", rc); 1812 return rc; 1813 } 1814 1815 /* Init the hardware's rate fallback order based on the band */ 1816 rc = il3945_init_hw_rate_table(il); 1817 if (rc) { 1818 IL_ERR("Error setting HW rate table: %02X\n", rc); 1819 return -EIO; 1820 } 1821 1822 return 0; 1823} 1824 1825/** 1826 * il3945_reg_txpower_periodic - called when time to check our temperature. 1827 * 1828 * -- reset periodic timer 1829 * -- see if temp has changed enough to warrant re-calibration ... if so: 1830 * -- correct coeffs for temp (can reset temp timer) 1831 * -- save this temp as "last", 1832 * -- send new set of gain settings to NIC 1833 * NOTE: This should continue working, even when we're not associated, 1834 * so we can keep our internal table of scan powers current. */ 1835void 1836il3945_reg_txpower_periodic(struct il_priv *il) 1837{ 1838 /* This will kick in the "brute force" 1839 * il3945_hw_reg_comp_txpower_temp() below */ 1840 if (!il3945_is_temp_calib_needed(il)) 1841 goto reschedule; 1842 1843 /* Set up a new set of temp-adjusted TxPowers, send to NIC. 1844 * This is based *only* on current temperature, 1845 * ignoring any previous power measurements */ 1846 il3945_hw_reg_comp_txpower_temp(il); 1847 1848reschedule: 1849 queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic, 1850 REG_RECALIB_PERIOD * HZ); 1851} 1852 1853static void 1854il3945_bg_reg_txpower_periodic(struct work_struct *work) 1855{ 1856 struct il_priv *il = container_of(work, struct il_priv, 1857 _3945.thermal_periodic.work); 1858 1859 mutex_lock(&il->mutex); 1860 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL) 1861 goto out; 1862 1863 il3945_reg_txpower_periodic(il); 1864out: 1865 mutex_unlock(&il->mutex); 1866} 1867 1868/** 1869 * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4) for channel. 1870 * 1871 * This function is used when initializing channel-info structs. 1872 * 1873 * NOTE: These channel groups do *NOT* match the bands above! 1874 * These channel groups are based on factory-tested channels; 1875 * on A-band, EEPROM's "group frequency" entries represent the top 1876 * channel in each group 1-4. Group 5 All B/G channels are in group 0. 1877 */ 1878static u16 1879il3945_hw_reg_get_ch_grp_idx(struct il_priv *il, 1880 const struct il_channel_info *ch_info) 1881{ 1882 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1883 struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0]; 1884 u8 group; 1885 u16 group_idx = 0; /* based on factory calib frequencies */ 1886 u8 grp_channel; 1887 1888 /* Find the group idx for the channel ... don't use idx 1(?) */ 1889 if (il_is_channel_a_band(ch_info)) { 1890 for (group = 1; group < 5; group++) { 1891 grp_channel = ch_grp[group].group_channel; 1892 if (ch_info->channel <= grp_channel) { 1893 group_idx = group; 1894 break; 1895 } 1896 } 1897 /* group 4 has a few channels *above* its factory cal freq */ 1898 if (group == 5) 1899 group_idx = 4; 1900 } else 1901 group_idx = 0; /* 2.4 GHz, group 0 */ 1902 1903 D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx); 1904 return group_idx; 1905} 1906 1907/** 1908 * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx 1909 * 1910 * Interpolate to get nominal (i.e. at factory calibration temperature) idx 1911 * into radio/DSP gain settings table for requested power. 1912 */ 1913static int 1914il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power, 1915 s32 setting_idx, s32 *new_idx) 1916{ 1917 const struct il3945_eeprom_txpower_group *chnl_grp = NULL; 1918 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1919 s32 idx0, idx1; 1920 s32 power = 2 * requested_power; 1921 s32 i; 1922 const struct il3945_eeprom_txpower_sample *samples; 1923 s32 gains0, gains1; 1924 s32 res; 1925 s32 denominator; 1926 1927 chnl_grp = &eeprom->groups[setting_idx]; 1928 samples = chnl_grp->samples; 1929 for (i = 0; i < 5; i++) { 1930 if (power == samples[i].power) { 1931 *new_idx = samples[i].gain_idx; 1932 return 0; 1933 } 1934 } 1935 1936 if (power > samples[1].power) { 1937 idx0 = 0; 1938 idx1 = 1; 1939 } else if (power > samples[2].power) { 1940 idx0 = 1; 1941 idx1 = 2; 1942 } else if (power > samples[3].power) { 1943 idx0 = 2; 1944 idx1 = 3; 1945 } else { 1946 idx0 = 3; 1947 idx1 = 4; 1948 } 1949 1950 denominator = (s32) samples[idx1].power - (s32) samples[idx0].power; 1951 if (denominator == 0) 1952 return -EINVAL; 1953 gains0 = (s32) samples[idx0].gain_idx * (1 << 19); 1954 gains1 = (s32) samples[idx1].gain_idx * (1 << 19); 1955 res = 1956 gains0 + (gains1 - gains0) * ((s32) power - 1957 (s32) samples[idx0].power) / 1958 denominator + (1 << 18); 1959 *new_idx = res >> 19; 1960 return 0; 1961} 1962 1963static void 1964il3945_hw_reg_init_channel_groups(struct il_priv *il) 1965{ 1966 u32 i; 1967 s32 rate_idx; 1968 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 1969 const struct il3945_eeprom_txpower_group *group; 1970 1971 D_POWER("Initializing factory calib info from EEPROM\n"); 1972 1973 for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) { 1974 s8 *clip_pwrs; /* table of power levels for each rate */ 1975 s8 satur_pwr; /* saturation power for each chnl group */ 1976 group = &eeprom->groups[i]; 1977 1978 /* sanity check on factory saturation power value */ 1979 if (group->saturation_power < 40) { 1980 IL_WARN("Error: saturation power is %d, " 1981 "less than minimum expected 40\n", 1982 group->saturation_power); 1983 return; 1984 } 1985 1986 /* 1987 * Derive requested power levels for each rate, based on 1988 * hardware capabilities (saturation power for band). 1989 * Basic value is 3dB down from saturation, with further 1990 * power reductions for highest 3 data rates. These 1991 * backoffs provide headroom for high rate modulation 1992 * power peaks, without too much distortion (clipping). 1993 */ 1994 /* we'll fill in this array with h/w max power levels */ 1995 clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers; 1996 1997 /* divide factory saturation power by 2 to find -3dB level */ 1998 satur_pwr = (s8) (group->saturation_power >> 1); 1999 2000 /* fill in channel group's nominal powers for each rate */ 2001 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; 2002 rate_idx++, clip_pwrs++) { 2003 switch (rate_idx) { 2004 case RATE_36M_IDX_TBL: 2005 if (i == 0) /* B/G */ 2006 *clip_pwrs = satur_pwr; 2007 else /* A */ 2008 *clip_pwrs = satur_pwr - 5; 2009 break; 2010 case RATE_48M_IDX_TBL: 2011 if (i == 0) 2012 *clip_pwrs = satur_pwr - 7; 2013 else 2014 *clip_pwrs = satur_pwr - 10; 2015 break; 2016 case RATE_54M_IDX_TBL: 2017 if (i == 0) 2018 *clip_pwrs = satur_pwr - 9; 2019 else 2020 *clip_pwrs = satur_pwr - 12; 2021 break; 2022 default: 2023 *clip_pwrs = satur_pwr; 2024 break; 2025 } 2026 } 2027 } 2028} 2029 2030/** 2031 * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM 2032 * 2033 * Second pass (during init) to set up il->channel_info 2034 * 2035 * Set up Tx-power settings in our channel info database for each VALID 2036 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values 2037 * and current temperature. 2038 * 2039 * Since this is based on current temperature (at init time), these values may 2040 * not be valid for very long, but it gives us a starting/default point, 2041 * and allows us to active (i.e. using Tx) scan. 2042 * 2043 * This does *not* write values to NIC, just sets up our internal table. 2044 */ 2045int 2046il3945_txpower_set_from_eeprom(struct il_priv *il) 2047{ 2048 struct il_channel_info *ch_info = NULL; 2049 struct il3945_channel_power_info *pwr_info; 2050 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom; 2051 int delta_idx; 2052 u8 rate_idx; 2053 u8 scan_tbl_idx; 2054 const s8 *clip_pwrs; /* array of power levels for each rate */ 2055 u8 gain, dsp_atten; 2056 s8 power; 2057 u8 pwr_idx, base_pwr_idx, a_band; 2058 u8 i; 2059 int temperature; 2060 2061 /* save temperature reference, 2062 * so we can determine next time to calibrate */ 2063 temperature = il3945_hw_reg_txpower_get_temperature(il); 2064 il->last_temperature = temperature; 2065 2066 il3945_hw_reg_init_channel_groups(il); 2067 2068 /* initialize Tx power info for each and every channel, 2.4 and 5.x */ 2069 for (i = 0, ch_info = il->channel_info; i < il->channel_count; 2070 i++, ch_info++) { 2071 a_band = il_is_channel_a_band(ch_info); 2072 if (!il_is_channel_valid(ch_info)) 2073 continue; 2074 2075 /* find this channel's channel group (*not* "band") idx */ 2076 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info); 2077 2078 /* Get this chnlgrp's rate->max/clip-powers table */ 2079 clip_pwrs = 2080 il->_3945.clip_groups[ch_info->group_idx].clip_powers; 2081 2082 /* calculate power idx *adjustment* value according to 2083 * diff between current temperature and factory temperature */ 2084 delta_idx = 2085 il3945_hw_reg_adjust_power_by_temp(temperature, 2086 eeprom->groups[ch_info-> 2087 group_idx]. 2088 temperature); 2089 2090 D_POWER("Delta idx for channel %d: %d [%d]\n", ch_info->channel, 2091 delta_idx, temperature + IL_TEMP_CONVERT); 2092 2093 /* set tx power value for all OFDM rates */ 2094 for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) { 2095 s32 uninitialized_var(power_idx); 2096 int rc; 2097 2098 /* use channel group's clip-power table, 2099 * but don't exceed channel's max power */ 2100 s8 pwr = min(ch_info->max_power_avg, 2101 clip_pwrs[rate_idx]); 2102 2103 pwr_info = &ch_info->power_info[rate_idx]; 2104 2105 /* get base (i.e. at factory-measured temperature) 2106 * power table idx for this rate's power */ 2107 rc = il3945_hw_reg_get_matched_power_idx(il, pwr, 2108 ch_info-> 2109 group_idx, 2110 &power_idx); 2111 if (rc) { 2112 IL_ERR("Invalid power idx\n"); 2113 return rc; 2114 } 2115 pwr_info->base_power_idx = (u8) power_idx; 2116 2117 /* temperature compensate */ 2118 power_idx += delta_idx; 2119 2120 /* stay within range of gain table */ 2121 power_idx = il3945_hw_reg_fix_power_idx(power_idx); 2122 2123 /* fill 1 OFDM rate's il3945_channel_power_info struct */ 2124 pwr_info->requested_power = pwr; 2125 pwr_info->power_table_idx = (u8) power_idx; 2126 pwr_info->tpc.tx_gain = 2127 power_gain_table[a_band][power_idx].tx_gain; 2128 pwr_info->tpc.dsp_atten = 2129 power_gain_table[a_band][power_idx].dsp_atten; 2130 } 2131 2132 /* set tx power for CCK rates, based on OFDM 12 Mbit settings */ 2133 pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL]; 2134 power = pwr_info->requested_power + IL_CCK_FROM_OFDM_POWER_DIFF; 2135 pwr_idx = pwr_info->power_table_idx + IL_CCK_FROM_OFDM_IDX_DIFF; 2136 base_pwr_idx = 2137 pwr_info->base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF; 2138 2139 /* stay within table range */ 2140 pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx); 2141 gain = power_gain_table[a_band][pwr_idx].tx_gain; 2142 dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten; 2143 2144 /* fill each CCK rate's il3945_channel_power_info structure 2145 * NOTE: All CCK-rate Txpwrs are the same for a given chnl! 2146 * NOTE: CCK rates start at end of OFDM rates! */ 2147 for (rate_idx = 0; rate_idx < IL_CCK_RATES; rate_idx++) { 2148 pwr_info = 2149 &ch_info->power_info[rate_idx + IL_OFDM_RATES]; 2150 pwr_info->requested_power = power; 2151 pwr_info->power_table_idx = pwr_idx; 2152 pwr_info->base_power_idx = base_pwr_idx; 2153 pwr_info->tpc.tx_gain = gain; 2154 pwr_info->tpc.dsp_atten = dsp_atten; 2155 } 2156 2157 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ 2158 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES; 2159 scan_tbl_idx++) { 2160 s32 actual_idx = 2161 (scan_tbl_idx == 2162 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL; 2163 il3945_hw_reg_set_scan_power(il, scan_tbl_idx, 2164 actual_idx, clip_pwrs, 2165 ch_info, a_band); 2166 } 2167 } 2168 2169 return 0; 2170} 2171 2172int 2173il3945_hw_rxq_stop(struct il_priv *il) 2174{ 2175 int ret; 2176 2177 _il_wr(il, FH39_RCSR_CONFIG(0), 0); 2178 ret = _il_poll_bit(il, FH39_RSSR_STATUS, 2179 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 2180 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 2181 1000); 2182 if (ret < 0) 2183 IL_ERR("Can't stop Rx DMA.\n"); 2184 2185 return 0; 2186} 2187 2188int 2189il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) 2190{ 2191 int txq_id = txq->q.id; 2192 2193 struct il3945_shared *shared_data = il->_3945.shared_virt; 2194 2195 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr); 2196 2197 il_wr(il, FH39_CBCC_CTRL(txq_id), 0); 2198 il_wr(il, FH39_CBCC_BASE(txq_id), 0); 2199 2200 il_wr(il, FH39_TCSR_CONFIG(txq_id), 2201 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | 2202 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | 2203 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | 2204 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | 2205 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); 2206 2207 /* fake read to flush all prev. writes */ 2208 _il_rd(il, FH39_TSSR_CBB_BASE); 2209 2210 return 0; 2211} 2212 2213/* 2214 * HCMD utils 2215 */ 2216static u16 2217il3945_get_hcmd_size(u8 cmd_id, u16 len) 2218{ 2219 switch (cmd_id) { 2220 case C_RXON: 2221 return sizeof(struct il3945_rxon_cmd); 2222 case C_POWER_TBL: 2223 return sizeof(struct il3945_powertable_cmd); 2224 default: 2225 return len; 2226 } 2227} 2228 2229static u16 2230il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data) 2231{ 2232 struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data; 2233 addsta->mode = cmd->mode; 2234 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify)); 2235 memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo)); 2236 addsta->station_flags = cmd->station_flags; 2237 addsta->station_flags_msk = cmd->station_flags_msk; 2238 addsta->tid_disable_tx = cpu_to_le16(0); 2239 addsta->rate_n_flags = cmd->rate_n_flags; 2240 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid; 2241 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid; 2242 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn; 2243 2244 return (u16) sizeof(struct il3945_addsta_cmd); 2245} 2246 2247static int 2248il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r) 2249{ 2250 int ret; 2251 u8 sta_id; 2252 unsigned long flags; 2253 2254 if (sta_id_r) 2255 *sta_id_r = IL_INVALID_STATION; 2256 2257 ret = il_add_station_common(il, addr, 0, NULL, &sta_id); 2258 if (ret) { 2259 IL_ERR("Unable to add station %pM\n", addr); 2260 return ret; 2261 } 2262 2263 if (sta_id_r) 2264 *sta_id_r = sta_id; 2265 2266 spin_lock_irqsave(&il->sta_lock, flags); 2267 il->stations[sta_id].used |= IL_STA_LOCAL; 2268 spin_unlock_irqrestore(&il->sta_lock, flags); 2269 2270 return 0; 2271} 2272 2273static int 2274il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, 2275 bool add) 2276{ 2277 struct il_vif_priv *vif_priv = (void *)vif->drv_priv; 2278 int ret; 2279 2280 if (add) { 2281 ret = 2282 il3945_add_bssid_station(il, vif->bss_conf.bssid, 2283 &vif_priv->ibss_bssid_sta_id); 2284 if (ret) 2285 return ret; 2286 2287 il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id, 2288 (il->band == 2289 IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : 2290 RATE_1M_PLCP); 2291 il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id); 2292 2293 return 0; 2294 } 2295 2296 return il_remove_station(il, vif_priv->ibss_bssid_sta_id, 2297 vif->bss_conf.bssid); 2298} 2299 2300/** 2301 * il3945_init_hw_rate_table - Initialize the hardware rate fallback table 2302 */ 2303int 2304il3945_init_hw_rate_table(struct il_priv *il) 2305{ 2306 int rc, i, idx, prev_idx; 2307 struct il3945_rate_scaling_cmd rate_cmd = { 2308 .reserved = {0, 0, 0}, 2309 }; 2310 struct il3945_rate_scaling_info *table = rate_cmd.table; 2311 2312 for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) { 2313 idx = il3945_rates[i].table_rs_idx; 2314 2315 table[idx].rate_n_flags = cpu_to_le16(il3945_rates[i].plcp); 2316 table[idx].try_cnt = il->retry_rate; 2317 prev_idx = il3945_get_prev_ieee_rate(i); 2318 table[idx].next_rate_idx = il3945_rates[prev_idx].table_rs_idx; 2319 } 2320 2321 switch (il->band) { 2322 case IEEE80211_BAND_5GHZ: 2323 D_RATE("Select A mode rate scale\n"); 2324 /* If one of the following CCK rates is used, 2325 * have it fall back to the 6M OFDM rate */ 2326 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) 2327 table[i].next_rate_idx = 2328 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx; 2329 2330 /* Don't fall back to CCK rates */ 2331 table[RATE_12M_IDX_TBL].next_rate_idx = RATE_9M_IDX_TBL; 2332 2333 /* Don't drop out of OFDM rates */ 2334 table[RATE_6M_IDX_TBL].next_rate_idx = 2335 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx; 2336 break; 2337 2338 case IEEE80211_BAND_2GHZ: 2339 D_RATE("Select B/G mode rate scale\n"); 2340 /* If an OFDM rate is used, have it fall back to the 2341 * 1M CCK rates */ 2342 2343 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) && 2344 il_is_associated(il)) { 2345 2346 idx = IL_FIRST_CCK_RATE; 2347 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++) 2348 table[i].next_rate_idx = 2349 il3945_rates[idx].table_rs_idx; 2350 2351 idx = RATE_11M_IDX_TBL; 2352 /* CCK shouldn't fall back to OFDM... */ 2353 table[idx].next_rate_idx = RATE_5M_IDX_TBL; 2354 } 2355 break; 2356 2357 default: 2358 WARN_ON(1); 2359 break; 2360 } 2361 2362 /* Update the rate scaling for control frame Tx */ 2363 rate_cmd.table_id = 0; 2364 rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd); 2365 if (rc) 2366 return rc; 2367 2368 /* Update the rate scaling for data frame Tx */ 2369 rate_cmd.table_id = 1; 2370 return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd); 2371} 2372 2373/* Called when initializing driver */ 2374int 2375il3945_hw_set_hw_params(struct il_priv *il) 2376{ 2377 memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params)); 2378 2379 il->_3945.shared_virt = 2380 dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared), 2381 &il->_3945.shared_phys, GFP_KERNEL); 2382 if (!il->_3945.shared_virt) { 2383 IL_ERR("failed to allocate pci memory\n"); 2384 return -ENOMEM; 2385 } 2386 2387 il->hw_params.bcast_id = IL3945_BROADCAST_ID; 2388 2389 /* Assign number of Usable TX queues */ 2390 il->hw_params.max_txq_num = il->cfg->num_of_queues; 2391 2392 il->hw_params.tfd_size = sizeof(struct il3945_tfd); 2393 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K); 2394 il->hw_params.max_rxq_size = RX_QUEUE_SIZE; 2395 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; 2396 il->hw_params.max_stations = IL3945_STATION_COUNT; 2397 2398 il->sta_key_max_num = STA_KEY_MAX_NUM; 2399 2400 il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR; 2401 il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL; 2402 il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS; 2403 2404 return 0; 2405} 2406 2407unsigned int 2408il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame, 2409 u8 rate) 2410{ 2411 struct il3945_tx_beacon_cmd *tx_beacon_cmd; 2412 unsigned int frame_size; 2413 2414 tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u; 2415 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); 2416 2417 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id; 2418 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 2419 2420 frame_size = 2421 il3945_fill_beacon_frame(il, tx_beacon_cmd->frame, 2422 sizeof(frame->u) - sizeof(*tx_beacon_cmd)); 2423 2424 BUG_ON(frame_size > MAX_MPDU_SIZE); 2425 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size); 2426 2427 tx_beacon_cmd->tx.rate = rate; 2428 tx_beacon_cmd->tx.tx_flags = 2429 (TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK); 2430 2431 /* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE */ 2432 tx_beacon_cmd->tx.supp_rates[0] = 2433 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF; 2434 2435 tx_beacon_cmd->tx.supp_rates[1] = (IL_CCK_BASIC_RATES_MASK & 0xF); 2436 2437 return sizeof(struct il3945_tx_beacon_cmd) + frame_size; 2438} 2439 2440void 2441il3945_hw_handler_setup(struct il_priv *il) 2442{ 2443 il->handlers[C_TX] = il3945_hdl_tx; 2444 il->handlers[N_3945_RX] = il3945_hdl_rx; 2445} 2446 2447void 2448il3945_hw_setup_deferred_work(struct il_priv *il) 2449{ 2450 INIT_DELAYED_WORK(&il->_3945.thermal_periodic, 2451 il3945_bg_reg_txpower_periodic); 2452} 2453 2454void 2455il3945_hw_cancel_deferred_work(struct il_priv *il) 2456{ 2457 cancel_delayed_work(&il->_3945.thermal_periodic); 2458} 2459 2460/* check contents of special bootstrap uCode SRAM */ 2461static int 2462il3945_verify_bsm(struct il_priv *il) 2463{ 2464 __le32 *image = il->ucode_boot.v_addr; 2465 u32 len = il->ucode_boot.len; 2466 u32 reg; 2467 u32 val; 2468 2469 D_INFO("Begin verify bsm\n"); 2470 2471 /* verify BSM SRAM contents */ 2472 val = il_rd_prph(il, BSM_WR_DWCOUNT_REG); 2473 for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len; 2474 reg += sizeof(u32), image++) { 2475 val = il_rd_prph(il, reg); 2476 if (val != le32_to_cpu(*image)) { 2477 IL_ERR("BSM uCode verification failed at " 2478 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", 2479 BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND, 2480 len, val, le32_to_cpu(*image)); 2481 return -EIO; 2482 } 2483 } 2484 2485 D_INFO("BSM bootstrap uCode image OK\n"); 2486 2487 return 0; 2488} 2489 2490/****************************************************************************** 2491 * 2492 * EEPROM related functions 2493 * 2494 ******************************************************************************/ 2495 2496/* 2497 * Clear the OWNER_MSK, to establish driver (instead of uCode running on 2498 * embedded controller) as EEPROM reader; each read is a series of pulses 2499 * to/from the EEPROM chip, not a single event, so even reads could conflict 2500 * if they weren't arbitrated by some ownership mechanism. Here, the driver 2501 * simply claims ownership, which should be safe when this function is called 2502 * (i.e. before loading uCode!). 2503 */ 2504static int 2505il3945_eeprom_acquire_semaphore(struct il_priv *il) 2506{ 2507 _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); 2508 return 0; 2509} 2510 2511static void 2512il3945_eeprom_release_semaphore(struct il_priv *il) 2513{ 2514 return; 2515} 2516 2517 /** 2518 * il3945_load_bsm - Load bootstrap instructions 2519 * 2520 * BSM operation: 2521 * 2522 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program 2523 * in special SRAM that does not power down during RFKILL. When powering back 2524 * up after power-saving sleeps (or during initial uCode load), the BSM loads 2525 * the bootstrap program into the on-board processor, and starts it. 2526 * 2527 * The bootstrap program loads (via DMA) instructions and data for a new 2528 * program from host DRAM locations indicated by the host driver in the 2529 * BSM_DRAM_* registers. Once the new program is loaded, it starts 2530 * automatically. 2531 * 2532 * When initializing the NIC, the host driver points the BSM to the 2533 * "initialize" uCode image. This uCode sets up some internal data, then 2534 * notifies host via "initialize alive" that it is complete. 2535 * 2536 * The host then replaces the BSM_DRAM_* pointer values to point to the 2537 * normal runtime uCode instructions and a backup uCode data cache buffer 2538 * (filled initially with starting data values for the on-board processor), 2539 * then triggers the "initialize" uCode to load and launch the runtime uCode, 2540 * which begins normal operation. 2541 * 2542 * When doing a power-save shutdown, runtime uCode saves data SRAM into 2543 * the backup data cache in DRAM before SRAM is powered down. 2544 * 2545 * When powering back up, the BSM loads the bootstrap program. This reloads 2546 * the runtime uCode instructions and the backup data cache into SRAM, 2547 * and re-launches the runtime uCode from where it left off. 2548 */ 2549static int 2550il3945_load_bsm(struct il_priv *il) 2551{ 2552 __le32 *image = il->ucode_boot.v_addr; 2553 u32 len = il->ucode_boot.len; 2554 dma_addr_t pinst; 2555 dma_addr_t pdata; 2556 u32 inst_len; 2557 u32 data_len; 2558 int rc; 2559 int i; 2560 u32 done; 2561 u32 reg_offset; 2562 2563 D_INFO("Begin load bsm\n"); 2564 2565 /* make sure bootstrap program is no larger than BSM's SRAM size */ 2566 if (len > IL39_MAX_BSM_SIZE) 2567 return -EINVAL; 2568 2569 /* Tell bootstrap uCode where to find the "Initialize" uCode 2570 * in host DRAM ... host DRAM physical address bits 31:0 for 3945. 2571 * NOTE: il3945_initialize_alive_start() will replace these values, 2572 * after the "initialize" uCode has run, to point to 2573 * runtime/protocol instructions and backup data cache. */ 2574 pinst = il->ucode_init.p_addr; 2575 pdata = il->ucode_init_data.p_addr; 2576 inst_len = il->ucode_init.len; 2577 data_len = il->ucode_init_data.len; 2578 2579 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst); 2580 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata); 2581 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 2582 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); 2583 2584 /* Fill BSM memory with bootstrap instructions */ 2585 for (reg_offset = BSM_SRAM_LOWER_BOUND; 2586 reg_offset < BSM_SRAM_LOWER_BOUND + len; 2587 reg_offset += sizeof(u32), image++) 2588 _il_wr_prph(il, reg_offset, le32_to_cpu(*image)); 2589 2590 rc = il3945_verify_bsm(il); 2591 if (rc) 2592 return rc; 2593 2594 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 2595 il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0); 2596 il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND); 2597 il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); 2598 2599 /* Load bootstrap code into instruction SRAM now, 2600 * to prepare to load "initialize" uCode */ 2601 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START); 2602 2603 /* Wait for load of bootstrap uCode to finish */ 2604 for (i = 0; i < 100; i++) { 2605 done = il_rd_prph(il, BSM_WR_CTRL_REG); 2606 if (!(done & BSM_WR_CTRL_REG_BIT_START)) 2607 break; 2608 udelay(10); 2609 } 2610 if (i < 100) 2611 D_INFO("BSM write complete, poll %d iterations\n", i); 2612 else { 2613 IL_ERR("BSM write did not complete!\n"); 2614 return -EIO; 2615 } 2616 2617 /* Enable future boot loads whenever power management unit triggers it 2618 * (e.g. when powering back up after power-save shutdown) */ 2619 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN); 2620 2621 return 0; 2622} 2623 2624const struct il_ops il3945_ops = { 2625 .txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd, 2626 .txq_free_tfd = il3945_hw_txq_free_tfd, 2627 .txq_init = il3945_hw_tx_queue_init, 2628 .load_ucode = il3945_load_bsm, 2629 .dump_nic_error_log = il3945_dump_nic_error_log, 2630 .apm_init = il3945_apm_init, 2631 .send_tx_power = il3945_send_tx_power, 2632 .is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr, 2633 .eeprom_acquire_semaphore = il3945_eeprom_acquire_semaphore, 2634 .eeprom_release_semaphore = il3945_eeprom_release_semaphore, 2635 2636 .rxon_assoc = il3945_send_rxon_assoc, 2637 .commit_rxon = il3945_commit_rxon, 2638 2639 .get_hcmd_size = il3945_get_hcmd_size, 2640 .build_addsta_hcmd = il3945_build_addsta_hcmd, 2641 .request_scan = il3945_request_scan, 2642 .post_scan = il3945_post_scan, 2643 2644 .post_associate = il3945_post_associate, 2645 .config_ap = il3945_config_ap, 2646 .manage_ibss_station = il3945_manage_ibss_station, 2647 2648 .send_led_cmd = il3945_send_led_cmd, 2649}; 2650 2651static struct il_cfg il3945_bg_cfg = { 2652 .name = "3945BG", 2653 .fw_name_pre = IL3945_FW_PRE, 2654 .ucode_api_max = IL3945_UCODE_API_MAX, 2655 .ucode_api_min = IL3945_UCODE_API_MIN, 2656 .sku = IL_SKU_G, 2657 .eeprom_ver = EEPROM_3945_EEPROM_VERSION, 2658 .mod_params = &il3945_mod_params, 2659 .led_mode = IL_LED_BLINK, 2660 2661 .eeprom_size = IL3945_EEPROM_IMG_SIZE, 2662 .num_of_queues = IL39_NUM_QUEUES, 2663 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL, 2664 .set_l0s = false, 2665 .use_bsm = true, 2666 .led_compensation = 64, 2667 .wd_timeout = IL_DEF_WD_TIMEOUT, 2668 2669 .regulatory_bands = { 2670 EEPROM_REGULATORY_BAND_1_CHANNELS, 2671 EEPROM_REGULATORY_BAND_2_CHANNELS, 2672 EEPROM_REGULATORY_BAND_3_CHANNELS, 2673 EEPROM_REGULATORY_BAND_4_CHANNELS, 2674 EEPROM_REGULATORY_BAND_5_CHANNELS, 2675 EEPROM_REGULATORY_BAND_NO_HT40, 2676 EEPROM_REGULATORY_BAND_NO_HT40, 2677 }, 2678}; 2679 2680static struct il_cfg il3945_abg_cfg = { 2681 .name = "3945ABG", 2682 .fw_name_pre = IL3945_FW_PRE, 2683 .ucode_api_max = IL3945_UCODE_API_MAX, 2684 .ucode_api_min = IL3945_UCODE_API_MIN, 2685 .sku = IL_SKU_A | IL_SKU_G, 2686 .eeprom_ver = EEPROM_3945_EEPROM_VERSION, 2687 .mod_params = &il3945_mod_params, 2688 .led_mode = IL_LED_BLINK, 2689 2690 .eeprom_size = IL3945_EEPROM_IMG_SIZE, 2691 .num_of_queues = IL39_NUM_QUEUES, 2692 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL, 2693 .set_l0s = false, 2694 .use_bsm = true, 2695 .led_compensation = 64, 2696 .wd_timeout = IL_DEF_WD_TIMEOUT, 2697 2698 .regulatory_bands = { 2699 EEPROM_REGULATORY_BAND_1_CHANNELS, 2700 EEPROM_REGULATORY_BAND_2_CHANNELS, 2701 EEPROM_REGULATORY_BAND_3_CHANNELS, 2702 EEPROM_REGULATORY_BAND_4_CHANNELS, 2703 EEPROM_REGULATORY_BAND_5_CHANNELS, 2704 EEPROM_REGULATORY_BAND_NO_HT40, 2705 EEPROM_REGULATORY_BAND_NO_HT40, 2706 }, 2707}; 2708 2709DEFINE_PCI_DEVICE_TABLE(il3945_hw_card_ids) = { 2710 {IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)}, 2711 {IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)}, 2712 {IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)}, 2713 {IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)}, 2714 {IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)}, 2715 {IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)}, 2716 {0} 2717}; 2718 2719MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids); 2720