iwl-5000.c revision 7c616cba240cd0d579c996be3f3603456acfb0ad
1/****************************************************************************** 2 * 3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/version.h> 29#include <linux/init.h> 30#include <linux/pci.h> 31#include <linux/dma-mapping.h> 32#include <linux/delay.h> 33#include <linux/skbuff.h> 34#include <linux/netdevice.h> 35#include <linux/wireless.h> 36#include <net/mac80211.h> 37#include <linux/etherdevice.h> 38#include <asm/unaligned.h> 39 40#include "iwl-eeprom.h" 41#include "iwl-dev.h" 42#include "iwl-core.h" 43#include "iwl-io.h" 44#include "iwl-helpers.h" 45#include "iwl-5000-hw.h" 46 47#define IWL5000_UCODE_API "-1" 48 49static const u16 iwl5000_default_queue_to_tx_fifo[] = { 50 IWL_TX_FIFO_AC3, 51 IWL_TX_FIFO_AC2, 52 IWL_TX_FIFO_AC1, 53 IWL_TX_FIFO_AC0, 54 IWL50_CMD_FIFO_NUM, 55 IWL_TX_FIFO_HCCA_1, 56 IWL_TX_FIFO_HCCA_2 57}; 58 59/* FIXME: same implementation as 4965 */ 60static int iwl5000_apm_stop_master(struct iwl_priv *priv) 61{ 62 int ret = 0; 63 unsigned long flags; 64 65 spin_lock_irqsave(&priv->lock, flags); 66 67 /* set stop master bit */ 68 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 69 70 ret = iwl_poll_bit(priv, CSR_RESET, 71 CSR_RESET_REG_FLAG_MASTER_DISABLED, 72 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 73 if (ret < 0) 74 goto out; 75 76out: 77 spin_unlock_irqrestore(&priv->lock, flags); 78 IWL_DEBUG_INFO("stop master\n"); 79 80 return ret; 81} 82 83 84static int iwl5000_apm_init(struct iwl_priv *priv) 85{ 86 int ret = 0; 87 88 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 89 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 90 91 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ 92 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 93 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 94 95 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 96 97 /* set "initialization complete" bit to move adapter 98 * D0U* --> D0A* state */ 99 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 100 101 /* wait for clock stabilization */ 102 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 103 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 104 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 105 if (ret < 0) { 106 IWL_DEBUG_INFO("Failed to init the card\n"); 107 return ret; 108 } 109 110 ret = iwl_grab_nic_access(priv); 111 if (ret) 112 return ret; 113 114 /* enable DMA */ 115 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 116 117 udelay(20); 118 119 /* disable L1-Active */ 120 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 121 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 122 123 iwl_release_nic_access(priv); 124 125 return ret; 126} 127 128/* FIXME: this is indentical to 4965 */ 129static void iwl5000_apm_stop(struct iwl_priv *priv) 130{ 131 unsigned long flags; 132 133 iwl5000_apm_stop_master(priv); 134 135 spin_lock_irqsave(&priv->lock, flags); 136 137 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 138 139 udelay(10); 140 141 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 142 143 spin_unlock_irqrestore(&priv->lock, flags); 144} 145 146 147static int iwl5000_apm_reset(struct iwl_priv *priv) 148{ 149 int ret = 0; 150 unsigned long flags; 151 152 iwl5000_apm_stop_master(priv); 153 154 spin_lock_irqsave(&priv->lock, flags); 155 156 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 157 158 udelay(10); 159 160 161 /* FIXME: put here L1A -L0S w/a */ 162 163 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 164 165 /* set "initialization complete" bit to move adapter 166 * D0U* --> D0A* state */ 167 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 168 169 /* wait for clock stabilization */ 170 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 171 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 172 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 173 if (ret < 0) { 174 IWL_DEBUG_INFO("Failed to init the card\n"); 175 goto out; 176 } 177 178 ret = iwl_grab_nic_access(priv); 179 if (ret) 180 goto out; 181 182 /* enable DMA */ 183 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 184 185 udelay(20); 186 187 /* disable L1-Active */ 188 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 189 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 190 191 iwl_release_nic_access(priv); 192 193out: 194 spin_unlock_irqrestore(&priv->lock, flags); 195 196 return ret; 197} 198 199 200static void iwl5000_nic_config(struct iwl_priv *priv) 201{ 202 unsigned long flags; 203 u16 radio_cfg; 204 u8 val_link; 205 206 spin_lock_irqsave(&priv->lock, flags); 207 208 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link); 209 210 /* L1 is enabled by BIOS */ 211 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN) 212 /* diable L0S disabled L1A enabled */ 213 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 214 else 215 /* L0S enabled L1A disabled */ 216 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 217 218 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 219 220 /* write radio config values to register */ 221 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) 222 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 223 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 224 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 225 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 226 227 /* set CSR_HW_CONFIG_REG for uCode use */ 228 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 229 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 230 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 231 232 spin_unlock_irqrestore(&priv->lock, flags); 233} 234 235 236 237/* 238 * EEPROM 239 */ 240static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 241{ 242 u16 offset = 0; 243 244 if ((address & INDIRECT_ADDRESS) == 0) 245 return address; 246 247 switch (address & INDIRECT_TYPE_MSK) { 248 case INDIRECT_HOST: 249 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 250 break; 251 case INDIRECT_GENERAL: 252 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 253 break; 254 case INDIRECT_REGULATORY: 255 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 256 break; 257 case INDIRECT_CALIBRATION: 258 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 259 break; 260 case INDIRECT_PROCESS_ADJST: 261 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 262 break; 263 case INDIRECT_OTHERS: 264 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 265 break; 266 default: 267 IWL_ERROR("illegal indirect type: 0x%X\n", 268 address & INDIRECT_TYPE_MSK); 269 break; 270 } 271 272 /* translate the offset from words to byte */ 273 return (address & ADDRESS_MSK) + (offset << 1); 274} 275 276static int iwl5000_eeprom_check_version(struct iwl_priv *priv) 277{ 278 u16 eeprom_ver; 279 struct iwl_eeprom_calib_hdr { 280 u8 version; 281 u8 pa_type; 282 u16 voltage; 283 } *hdr; 284 285 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); 286 287 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 288 EEPROM_5000_CALIB_ALL); 289 290 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION || 291 hdr->version < EEPROM_5000_TX_POWER_VERSION) 292 goto err; 293 294 return 0; 295err: 296 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n", 297 eeprom_ver, EEPROM_5000_EEPROM_VERSION, 298 hdr->version, EEPROM_5000_TX_POWER_VERSION); 299 return -EINVAL; 300 301} 302 303#ifdef CONFIG_IWL5000_RUN_TIME_CALIB 304 305static void iwl5000_gain_computation(struct iwl_priv *priv, 306 u32 average_noise[NUM_RX_CHAINS], 307 u16 min_average_noise_antenna_i, 308 u32 min_average_noise) 309{ 310 int i; 311 s32 delta_g; 312 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 313 314 /* Find Gain Code for the antennas B and C */ 315 for (i = 1; i < NUM_RX_CHAINS; i++) { 316 if ((data->disconn_array[i])) { 317 data->delta_gain_code[i] = 0; 318 continue; 319 } 320 delta_g = (1000 * ((s32)average_noise[0] - 321 (s32)average_noise[i])) / 1500; 322 /* bound gain by 2 bits value max, 3rd bit is sign */ 323 data->delta_gain_code[i] = 324 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 325 326 if (delta_g < 0) 327 /* set negative sign */ 328 data->delta_gain_code[i] |= (1 << 2); 329 } 330 331 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", 332 data->delta_gain_code[1], data->delta_gain_code[2]); 333 334 if (!data->radio_write) { 335 struct iwl5000_calibration_chain_noise_gain_cmd cmd; 336 memset(&cmd, 0, sizeof(cmd)); 337 338 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 339 cmd.delta_gain_1 = data->delta_gain_code[1]; 340 cmd.delta_gain_2 = data->delta_gain_code[2]; 341 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 342 sizeof(cmd), &cmd, NULL); 343 344 data->radio_write = 1; 345 data->state = IWL_CHAIN_NOISE_CALIBRATED; 346 } 347 348 data->chain_noise_a = 0; 349 data->chain_noise_b = 0; 350 data->chain_noise_c = 0; 351 data->chain_signal_a = 0; 352 data->chain_signal_b = 0; 353 data->chain_signal_c = 0; 354 data->beacon_count = 0; 355} 356 357 358static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 359{ 360 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 361 362 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 363 struct iwl5000_calibration_chain_noise_reset_cmd cmd; 364 365 memset(&cmd, 0, sizeof(cmd)); 366 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 367 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 368 sizeof(cmd), &cmd)) 369 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); 370 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 371 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); 372 } 373} 374 375static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 376 .min_nrg_cck = 95, 377 .max_nrg_cck = 0, 378 .auto_corr_min_ofdm = 90, 379 .auto_corr_min_ofdm_mrc = 170, 380 .auto_corr_min_ofdm_x1 = 120, 381 .auto_corr_min_ofdm_mrc_x1 = 240, 382 383 .auto_corr_max_ofdm = 120, 384 .auto_corr_max_ofdm_mrc = 210, 385 .auto_corr_max_ofdm_x1 = 155, 386 .auto_corr_max_ofdm_mrc_x1 = 290, 387 388 .auto_corr_min_cck = 125, 389 .auto_corr_max_cck = 200, 390 .auto_corr_min_cck_mrc = 170, 391 .auto_corr_max_cck_mrc = 400, 392 .nrg_th_cck = 95, 393 .nrg_th_ofdm = 95, 394}; 395 396#endif /* CONFIG_IWL5000_RUN_TIME_CALIB */ 397 398 399 400static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 401 size_t offset) 402{ 403 u32 address = eeprom_indirect_address(priv, offset); 404 BUG_ON(address >= priv->cfg->eeprom_size); 405 return &priv->eeprom[address]; 406} 407 408/* 409 * Calibration 410 */ 411static int iwl5000_send_Xtal_calib(struct iwl_priv *priv) 412{ 413 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 414 415 struct iwl5000_calibration cal_cmd = { 416 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD, 417 .data = { 418 (u8)xtal_calib[0], 419 (u8)xtal_calib[1], 420 } 421 }; 422 423 return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 424 sizeof(cal_cmd), &cal_cmd); 425} 426 427static int iwl5000_send_calib_results(struct iwl_priv *priv) 428{ 429 int ret = 0; 430 431 if (priv->calib_results.lo_res) 432 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 433 priv->calib_results.lo_res_len, 434 priv->calib_results.lo_res); 435 if (ret) 436 goto err; 437 438 439 if (priv->calib_results.tx_iq_res) 440 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 441 priv->calib_results.tx_iq_res_len, 442 priv->calib_results.tx_iq_res); 443 444 if (ret) 445 goto err; 446 447 if (priv->calib_results.tx_iq_perd_res) 448 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 449 priv->calib_results.tx_iq_perd_res_len, 450 priv->calib_results.tx_iq_perd_res); 451 if (ret) 452 goto err; 453 454 return 0; 455err: 456 IWL_ERROR("Error %d\n", ret); 457 return ret; 458} 459 460static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 461{ 462 struct iwl5000_calib_cfg_cmd calib_cfg_cmd; 463 struct iwl_host_cmd cmd = { 464 .id = CALIBRATION_CFG_CMD, 465 .len = sizeof(struct iwl5000_calib_cfg_cmd), 466 .data = &calib_cfg_cmd, 467 }; 468 469 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 470 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 471 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 472 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 473 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 474 475 return iwl_send_cmd(priv, &cmd); 476} 477 478static void iwl5000_rx_calib_result(struct iwl_priv *priv, 479 struct iwl_rx_mem_buffer *rxb) 480{ 481 struct iwl_rx_packet *pkt = (void *)rxb->skb->data; 482 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw; 483 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; 484 485 iwl_free_calib_results(priv); 486 487 /* reduce the size of the length field itself */ 488 len -= 4; 489 490 switch (hdr->op_code) { 491 case IWL5000_PHY_CALIBRATE_LO_CMD: 492 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC); 493 priv->calib_results.lo_res_len = len; 494 memcpy(priv->calib_results.lo_res, pkt->u.raw, len); 495 break; 496 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD: 497 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC); 498 priv->calib_results.tx_iq_res_len = len; 499 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len); 500 break; 501 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD: 502 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC); 503 priv->calib_results.tx_iq_perd_res_len = len; 504 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len); 505 break; 506 default: 507 IWL_ERROR("Unknown calibration notification %d\n", 508 hdr->op_code); 509 return; 510 } 511} 512 513static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 514 struct iwl_rx_mem_buffer *rxb) 515{ 516 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); 517 queue_work(priv->workqueue, &priv->restart); 518} 519 520/* 521 * ucode 522 */ 523static int iwl5000_load_section(struct iwl_priv *priv, 524 struct fw_desc *image, 525 u32 dst_addr) 526{ 527 int ret = 0; 528 unsigned long flags; 529 530 dma_addr_t phy_addr = image->p_addr; 531 u32 byte_cnt = image->len; 532 533 spin_lock_irqsave(&priv->lock, flags); 534 ret = iwl_grab_nic_access(priv); 535 if (ret) { 536 spin_unlock_irqrestore(&priv->lock, flags); 537 return ret; 538 } 539 540 iwl_write_direct32(priv, 541 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 542 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 543 544 iwl_write_direct32(priv, 545 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 546 547 iwl_write_direct32(priv, 548 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 549 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 550 551 /* FIME: write the MSB of the phy_addr in CTRL1 552 * iwl_write_direct32(priv, 553 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL), 554 ((phy_addr & MSB_MSK) 555 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count); 556 */ 557 iwl_write_direct32(priv, 558 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt); 559 iwl_write_direct32(priv, 560 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 561 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 562 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 563 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 564 565 iwl_write_direct32(priv, 566 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 567 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 568 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL | 569 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 570 571 iwl_release_nic_access(priv); 572 spin_unlock_irqrestore(&priv->lock, flags); 573 return 0; 574} 575 576static int iwl5000_load_given_ucode(struct iwl_priv *priv, 577 struct fw_desc *inst_image, 578 struct fw_desc *data_image) 579{ 580 int ret = 0; 581 582 ret = iwl5000_load_section( 583 priv, inst_image, RTC_INST_LOWER_BOUND); 584 if (ret) 585 return ret; 586 587 IWL_DEBUG_INFO("INST uCode section being loaded...\n"); 588 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 589 priv->ucode_write_complete, 5 * HZ); 590 if (ret == -ERESTARTSYS) { 591 IWL_ERROR("Could not load the INST uCode section due " 592 "to interrupt\n"); 593 return ret; 594 } 595 if (!ret) { 596 IWL_ERROR("Could not load the INST uCode section\n"); 597 return -ETIMEDOUT; 598 } 599 600 priv->ucode_write_complete = 0; 601 602 ret = iwl5000_load_section( 603 priv, data_image, RTC_DATA_LOWER_BOUND); 604 if (ret) 605 return ret; 606 607 IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); 608 609 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 610 priv->ucode_write_complete, 5 * HZ); 611 if (ret == -ERESTARTSYS) { 612 IWL_ERROR("Could not load the INST uCode section due " 613 "to interrupt\n"); 614 return ret; 615 } else if (!ret) { 616 IWL_ERROR("Could not load the DATA uCode section\n"); 617 return -ETIMEDOUT; 618 } else 619 ret = 0; 620 621 priv->ucode_write_complete = 0; 622 623 return ret; 624} 625 626static int iwl5000_load_ucode(struct iwl_priv *priv) 627{ 628 int ret = 0; 629 630 /* check whether init ucode should be loaded, or rather runtime ucode */ 631 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 632 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); 633 ret = iwl5000_load_given_ucode(priv, 634 &priv->ucode_init, &priv->ucode_init_data); 635 if (!ret) { 636 IWL_DEBUG_INFO("Init ucode load complete.\n"); 637 priv->ucode_type = UCODE_INIT; 638 } 639 } else { 640 IWL_DEBUG_INFO("Init ucode not found, or already loaded. " 641 "Loading runtime ucode...\n"); 642 ret = iwl5000_load_given_ucode(priv, 643 &priv->ucode_code, &priv->ucode_data); 644 if (!ret) { 645 IWL_DEBUG_INFO("Runtime ucode load complete.\n"); 646 priv->ucode_type = UCODE_RT; 647 } 648 } 649 650 return ret; 651} 652 653static void iwl5000_init_alive_start(struct iwl_priv *priv) 654{ 655 int ret = 0; 656 657 /* Check alive response for "valid" sign from uCode */ 658 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 659 /* We had an error bringing up the hardware, so take it 660 * all the way back down so we can try again */ 661 IWL_DEBUG_INFO("Initialize Alive failed.\n"); 662 goto restart; 663 } 664 665 /* initialize uCode was loaded... verify inst image. 666 * This is a paranoid check, because we would not have gotten the 667 * "initialize" alive if code weren't properly loaded. */ 668 if (iwl_verify_ucode(priv)) { 669 /* Runtime instruction load was bad; 670 * take it all the way back down so we can try again */ 671 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); 672 goto restart; 673 } 674 675 iwlcore_clear_stations_table(priv); 676 ret = priv->cfg->ops->lib->alive_notify(priv); 677 if (ret) { 678 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); 679 goto restart; 680 } 681 682 iwl5000_send_calib_cfg(priv); 683 return; 684 685restart: 686 /* real restart (first load init_ucode) */ 687 queue_work(priv->workqueue, &priv->restart); 688} 689 690static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 691 int txq_id, u32 index) 692{ 693 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 694 (index & 0xff) | (txq_id << 8)); 695 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 696} 697 698static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 699 struct iwl_tx_queue *txq, 700 int tx_fifo_id, int scd_retry) 701{ 702 int txq_id = txq->q.id; 703 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; 704 705 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 706 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 707 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 708 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 709 IWL50_SCD_QUEUE_STTS_REG_MSK); 710 711 txq->sched_retry = scd_retry; 712 713 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", 714 active ? "Activate" : "Deactivate", 715 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 716} 717 718static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 719{ 720 struct iwl_wimax_coex_cmd coex_cmd; 721 722 memset(&coex_cmd, 0, sizeof(coex_cmd)); 723 724 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 725 sizeof(coex_cmd), &coex_cmd); 726} 727 728static int iwl5000_alive_notify(struct iwl_priv *priv) 729{ 730 u32 a; 731 int i = 0; 732 unsigned long flags; 733 int ret; 734 735 spin_lock_irqsave(&priv->lock, flags); 736 737 ret = iwl_grab_nic_access(priv); 738 if (ret) { 739 spin_unlock_irqrestore(&priv->lock, flags); 740 return ret; 741 } 742 743 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 744 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 745 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 746 a += 4) 747 iwl_write_targ_mem(priv, a, 0); 748 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 749 a += 4) 750 iwl_write_targ_mem(priv, a, 0); 751 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) 752 iwl_write_targ_mem(priv, a, 0); 753 754 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 755 (priv->shared_phys + 756 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10); 757 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 758 IWL50_SCD_QUEUECHAIN_SEL_ALL( 759 priv->hw_params.max_txq_num)); 760 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 761 762 /* initiate the queues */ 763 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 764 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 765 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 766 iwl_write_targ_mem(priv, priv->scd_base_addr + 767 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 768 iwl_write_targ_mem(priv, priv->scd_base_addr + 769 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 770 sizeof(u32), 771 ((SCD_WIN_SIZE << 772 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 773 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 774 ((SCD_FRAME_LIMIT << 775 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 776 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 777 } 778 779 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 780 IWL_MASK(0, priv->hw_params.max_txq_num)); 781 782 /* Activate all Tx DMA/FIFO channels */ 783 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 784 785 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 786 /* map qos queues to fifos one-to-one */ 787 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 788 int ac = iwl5000_default_queue_to_tx_fifo[i]; 789 iwl_txq_ctx_activate(priv, i); 790 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 791 } 792 /* TODO - need to initialize those FIFOs inside the loop above, 793 * not only mark them as active */ 794 iwl_txq_ctx_activate(priv, 4); 795 iwl_txq_ctx_activate(priv, 7); 796 iwl_txq_ctx_activate(priv, 8); 797 iwl_txq_ctx_activate(priv, 9); 798 799 iwl_release_nic_access(priv); 800 spin_unlock_irqrestore(&priv->lock, flags); 801 802 803 iwl5000_send_wimax_coex(priv); 804 805 iwl5000_send_Xtal_calib(priv); 806 807 if (priv->ucode_type == UCODE_RT) 808 iwl5000_send_calib_results(priv); 809 810 return 0; 811} 812 813static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 814{ 815 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || 816 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 817 IWL_ERROR("invalid queues_num, should be between %d and %d\n", 818 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); 819 return -EINVAL; 820 } 821 822 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 823 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto; 824 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; 825 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; 826 if (priv->cfg->mod_params->amsdu_size_8K) 827 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K; 828 else 829 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K; 830 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256; 831 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 832 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 833 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 834 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 835 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE; 836 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | 837 BIT(IEEE80211_BAND_5GHZ); 838#ifdef CONFIG_IWL5000_RUN_TIME_CALIB 839 priv->hw_params.sens = &iwl5000_sensitivity; 840#endif 841 842 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 843 case CSR_HW_REV_TYPE_5100: 844 case CSR_HW_REV_TYPE_5150: 845 priv->hw_params.tx_chains_num = 1; 846 priv->hw_params.rx_chains_num = 2; 847 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */ 848 priv->hw_params.valid_tx_ant = ANT_A; 849 priv->hw_params.valid_rx_ant = ANT_AB; 850 break; 851 case CSR_HW_REV_TYPE_5300: 852 case CSR_HW_REV_TYPE_5350: 853 priv->hw_params.tx_chains_num = 3; 854 priv->hw_params.rx_chains_num = 3; 855 priv->hw_params.valid_tx_ant = ANT_ABC; 856 priv->hw_params.valid_rx_ant = ANT_ABC; 857 break; 858 } 859 860 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 861 case CSR_HW_REV_TYPE_5100: 862 case CSR_HW_REV_TYPE_5300: 863 /* 5X00 wants in Celsius */ 864 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; 865 break; 866 case CSR_HW_REV_TYPE_5150: 867 case CSR_HW_REV_TYPE_5350: 868 /* 5X50 wants in Kelvin */ 869 priv->hw_params.ct_kill_threshold = 870 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); 871 break; 872 } 873 874 return 0; 875} 876 877static int iwl5000_alloc_shared_mem(struct iwl_priv *priv) 878{ 879 priv->shared_virt = pci_alloc_consistent(priv->pci_dev, 880 sizeof(struct iwl5000_shared), 881 &priv->shared_phys); 882 if (!priv->shared_virt) 883 return -ENOMEM; 884 885 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared)); 886 887 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed); 888 889 return 0; 890} 891 892static void iwl5000_free_shared_mem(struct iwl_priv *priv) 893{ 894 if (priv->shared_virt) 895 pci_free_consistent(priv->pci_dev, 896 sizeof(struct iwl5000_shared), 897 priv->shared_virt, 898 priv->shared_phys); 899} 900 901static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv) 902{ 903 struct iwl5000_shared *s = priv->shared_virt; 904 return le32_to_cpu(s->rb_closed) & 0xFFF; 905} 906 907/** 908 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 909 */ 910static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 911 struct iwl_tx_queue *txq, 912 u16 byte_cnt) 913{ 914 struct iwl5000_shared *shared_data = priv->shared_virt; 915 int txq_id = txq->q.id; 916 u8 sec_ctl = 0; 917 u8 sta = 0; 918 int len; 919 920 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 921 922 if (txq_id != IWL_CMD_QUEUE_NUM) { 923 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id; 924 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl; 925 926 switch (sec_ctl & TX_CMD_SEC_MSK) { 927 case TX_CMD_SEC_CCM: 928 len += CCMP_MIC_LEN; 929 break; 930 case TX_CMD_SEC_TKIP: 931 len += TKIP_ICV_LEN; 932 break; 933 case TX_CMD_SEC_WEP: 934 len += WEP_IV_LEN + WEP_ICV_LEN; 935 break; 936 } 937 } 938 939 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 940 tfd_offset[txq->q.write_ptr], byte_cnt, len); 941 942 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 943 tfd_offset[txq->q.write_ptr], sta_id, sta); 944 945 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 946 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 947 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 948 byte_cnt, len); 949 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 950 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 951 sta_id, sta); 952 } 953} 954 955static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 956{ 957 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 958 memcpy(data, cmd, size); 959 return size; 960} 961 962 963/* 964 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask 965 * must be called under priv->lock and mac access 966 */ 967static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 968{ 969 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 970} 971 972/* Currently 5000 is the supperset of everything */ 973static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 974{ 975 return len; 976} 977 978static void iwl5000_rx_handler_setup(struct iwl_priv *priv) 979{ 980 /* init calibration handlers */ 981 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 982 iwl5000_rx_calib_result; 983 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 984 iwl5000_rx_calib_complete; 985} 986 987 988static int iwl5000_hw_valid_rtc_data_addr(u32 addr) 989{ 990 return (addr >= RTC_DATA_LOWER_BOUND) && 991 (addr < IWL50_RTC_DATA_UPPER_BOUND); 992} 993 994static struct iwl_hcmd_ops iwl5000_hcmd = { 995}; 996 997static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 998 .get_hcmd_size = iwl5000_get_hcmd_size, 999 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1000#ifdef CONFIG_IWL5000_RUN_TIME_CALIB 1001 .gain_computation = iwl5000_gain_computation, 1002 .chain_noise_reset = iwl5000_chain_noise_reset, 1003#endif 1004}; 1005 1006static struct iwl_lib_ops iwl5000_lib = { 1007 .set_hw_params = iwl5000_hw_set_hw_params, 1008 .alloc_shared_mem = iwl5000_alloc_shared_mem, 1009 .free_shared_mem = iwl5000_free_shared_mem, 1010 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx, 1011 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1012 .txq_set_sched = iwl5000_txq_set_sched, 1013 .rx_handler_setup = iwl5000_rx_handler_setup, 1014 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1015 .load_ucode = iwl5000_load_ucode, 1016 .init_alive_start = iwl5000_init_alive_start, 1017 .alive_notify = iwl5000_alive_notify, 1018 .apm_ops = { 1019 .init = iwl5000_apm_init, 1020 .reset = iwl5000_apm_reset, 1021 .stop = iwl5000_apm_stop, 1022 .config = iwl5000_nic_config, 1023 .set_pwr_src = iwl4965_set_pwr_src, 1024 }, 1025 .eeprom_ops = { 1026 .regulatory_bands = { 1027 EEPROM_5000_REG_BAND_1_CHANNELS, 1028 EEPROM_5000_REG_BAND_2_CHANNELS, 1029 EEPROM_5000_REG_BAND_3_CHANNELS, 1030 EEPROM_5000_REG_BAND_4_CHANNELS, 1031 EEPROM_5000_REG_BAND_5_CHANNELS, 1032 EEPROM_5000_REG_BAND_24_FAT_CHANNELS, 1033 EEPROM_5000_REG_BAND_52_FAT_CHANNELS 1034 }, 1035 .verify_signature = iwlcore_eeprom_verify_signature, 1036 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1037 .release_semaphore = iwlcore_eeprom_release_semaphore, 1038 .check_version = iwl5000_eeprom_check_version, 1039 .query_addr = iwl5000_eeprom_query_addr, 1040 }, 1041}; 1042 1043static struct iwl_ops iwl5000_ops = { 1044 .lib = &iwl5000_lib, 1045 .hcmd = &iwl5000_hcmd, 1046 .utils = &iwl5000_hcmd_utils, 1047}; 1048 1049static struct iwl_mod_params iwl50_mod_params = { 1050 .num_of_queues = IWL50_NUM_QUEUES, 1051 .enable_qos = 1, 1052 .amsdu_size_8K = 1, 1053 .restart_fw = 1, 1054 /* the rest are 0 by default */ 1055}; 1056 1057 1058struct iwl_cfg iwl5300_agn_cfg = { 1059 .name = "5300AGN", 1060 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1061 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1062 .ops = &iwl5000_ops, 1063 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1064 .mod_params = &iwl50_mod_params, 1065}; 1066 1067struct iwl_cfg iwl5100_agn_cfg = { 1068 .name = "5100AGN", 1069 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1070 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1071 .ops = &iwl5000_ops, 1072 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1073 .mod_params = &iwl50_mod_params, 1074}; 1075 1076struct iwl_cfg iwl5350_agn_cfg = { 1077 .name = "5350AGN", 1078 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1079 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1080 .ops = &iwl5000_ops, 1081 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1082 .mod_params = &iwl50_mod_params, 1083}; 1084 1085module_param_named(disable50, iwl50_mod_params.disable, int, 0444); 1086MODULE_PARM_DESC(disable50, 1087 "manually disable the 50XX radio (default 0 [radio on])"); 1088module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); 1089MODULE_PARM_DESC(swcrypto50, 1090 "using software crypto engine (default 0 [hardware])\n"); 1091module_param_named(debug50, iwl50_mod_params.debug, int, 0444); 1092MODULE_PARM_DESC(debug50, "50XX debug output mask"); 1093module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); 1094MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1095module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444); 1096MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality"); 1097module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); 1098MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1099module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); 1100MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1101