16f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/****************************************************************************** 26f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 36f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * This file is provided under a dual BSD/GPLv2 license. When using or 46f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * redistributing this file, you may do so under either license. 56f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 66f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * GPL LICENSE SUMMARY 76f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 8fb4961dbc27d40cdbed297aa9bd74fa4a0e2ba6cWey-Yi Guy * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. 96f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 106f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * This program is free software; you can redistribute it and/or modify 116f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * it under the terms of version 2 of the GNU General Public License as 126f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * published by the Free Software Foundation. 136f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 146f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * This program is distributed in the hope that it will be useful, but 156f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * WITHOUT ANY WARRANTY; without even the implied warranty of 166f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 176f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * General Public License for more details. 186f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 196f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * You should have received a copy of the GNU General Public License 206f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * along with this program; if not, write to the Free Software 216f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 226f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * USA 236f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 246f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * The full GNU General Public License is included in this distribution 256f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * in the file called LICENSE.GPL. 266f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 276f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Contact Information: 28759ef89fb096c4a6ef078d3cfd5682ac037bd789Winkler, Tomas * Intel Linux Wireless <ilw@linux.intel.com> 296f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 306f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 316f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * BSD LICENSE 326f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 33fb4961dbc27d40cdbed297aa9bd74fa4a0e2ba6cWey-Yi Guy * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. 346f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * All rights reserved. 356f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 366f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Redistribution and use in source and binary forms, with or without 376f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * modification, are permitted provided that the following conditions 386f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * are met: 396f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 406f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * * Redistributions of source code must retain the above copyright 416f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * notice, this list of conditions and the following disclaimer. 426f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * * Redistributions in binary form must reproduce the above copyright 436f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * notice, this list of conditions and the following disclaimer in 446f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * the documentation and/or other materials provided with the 456f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * distribution. 466f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * * Neither the name Intel Corporation nor the names of its 476f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * contributors may be used to endorse or promote products derived 486f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * from this software without specific prior written permission. 496f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 506f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 516f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 526f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 536f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 546f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 556f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 566f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 576f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 586f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 596f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 606f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 616f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 626f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler *****************************************************************************/ 6365a0667b43ff746b2964b2a257ffff1a4747e19dTomas Winkler#ifndef __iwl_csr_h__ 6465a0667b43ff746b2964b2a257ffff1a4747e19dTomas Winkler#define __iwl_csr_h__ 659e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* 669e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * CSR (control and status registers) 679e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 689e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * CSR registers are mapped directly into PCI bus space, and are accessible 699e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * whenever platform supplies power to device, even when device is in 709e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * low power states due to driver-invoked device resets 719e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 729e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 739e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Use iwl_write32() and iwl_read32() family to access these registers; 749e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * these provide simple PCI bus access, without waking up the MAC. 759e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Do not use iwl_write_direct32() family for these registers; 769e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 779e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * The MAC (uCode processor, etc.) does not need to be powered up for accessing 789e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * the CSR registers. 799e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 80f8701fe3aec24fcfb0dfa19aab47904611f96dafReinette Chatre * NOTE: Device does need to be awake in order to read this memory 819e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * via CSR_EEPROM and CSR_OTP registers 829e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill */ 836f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_BASE (0x000) 846f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 856f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 869e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 876f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 886f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 896f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ 906f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 916f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ 926f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL (CSR_BASE+0x024) 936f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 949e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ 959e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) 969e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 976f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* 986f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Hardware revision info 996f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Bit fields: 1006f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 31-8: Reserved 1019e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions 1026f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 1039e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 1-0: "Dash" (-) value, as in A-1, etc. 1046f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 1056f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * NOTE: Revision step affects calculation of CCK txpower for 4965. 1069e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * NOTE: See also CSR_HW_REV_WA_REG (work-around for bug in 4965). 1076f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler */ 1086f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_HW_REV (CSR_BASE+0x028) 1096f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1109e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* 1119e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * EEPROM and OTP (one-time-programmable) memory reads 1129e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 113f8701fe3aec24fcfb0dfa19aab47904611f96dafReinette Chatre * NOTE: Device must be awake, initialized via apm_ops.init(), 114f8701fe3aec24fcfb0dfa19aab47904611f96dafReinette Chatre * in order to read. 1159e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill */ 1166f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_REG (CSR_BASE+0x02c) 1176f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_GP (CSR_BASE+0x030) 1180848e297c2107dbc12a91a1709c879c73bd188d8Wey-Yi Guy#define CSR_OTP_GP_REG (CSR_BASE+0x034) 1199e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 1208f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler#define CSR_GIO_REG (CSR_BASE+0x03C) 12165b7998a9be418482493e9448bb83ff2914ed050Wey-Yi Guy#define CSR_GP_UCODE_REG (CSR_BASE+0x048) 12265b7998a9be418482493e9448bb83ff2914ed050Wey-Yi Guy#define CSR_GP_DRIVER_REG (CSR_BASE+0x050) 1239e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 1249e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* 1259e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * UCODE-DRIVER GP (general purpose) mailbox registers. 1269e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * SET/CLR registers set/clear bit(s) if "1" is written. 1279e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill */ 1286f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 1296f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 1306f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 1316f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 1329e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 133ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas#define CSR_LED_REG (CSR_BASE+0x094) 134ef850d7cb301bda9155c096269557a4586b58071Mohamed Abbas#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) 135f81c1f48384d398dbe8f6c5b10377c7158086791Wey-Yi Guy#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */ 136f81c1f48384d398dbe8f6c5b10377c7158086791Wey-Yi Guy 1379e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 1389e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* GIO Chicken Bits (PCI Express bus link power management) */ 1398f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 1406f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 141a693f187facbf25925bbcf201db88c5384468646Tomas Winkler/* Analog phase-lock-loop configuration */ 1426f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 1439e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 1446f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* 1459e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * CSR Hardware Revision Workaround Register. Indicates hardware rev; 1469e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 1479e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * See also CSR_HW_REV register. 1486f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Bit fields: 1496f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 1509e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 1-0: "Dash" (-) value, as in C-1, etc. 1516f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler */ 15232004ee42fced8b2372dd2f93e65cc9d71e8c4bfWey-Yi Guy#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 1539e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 15432004ee42fced8b2372dd2f93e65cc9d71e8c4bfWey-Yi Guy#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 15532004ee42fced8b2372dd2f93e65cc9d71e8c4bfWey-Yi Guy#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) 1566f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1576f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* Bits for CSR_HW_IF_CONFIG_REG */ 158a395b92024d9b8f9403c06f9ea8d425f1883d7d8Tomas Winkler#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) 159a395b92024d9b8f9403c06f9ea8d425f1883d7d8Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 160a395b92024d9b8f9403c06f9ea8d425f1883d7d8Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 1616f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1629e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 1639e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 1649e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 1659e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 1669e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 1674c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler 16874ba67edfcb235c0415a62d37493866c8380dc1dBen M Cahill#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 16974ba67edfcb235c0415a62d37493866c8380dc1dBen M Cahill#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 1706f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1716f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 1726f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * acknowledged (reset) by host writing "1" to flagged bits. */ 1736f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 1746f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 17540cefda9ce11c44a2531d07af812900aa5f3ce9dMohamed Abbas#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 1766f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 1776f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 1786f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 1796f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 1806f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 181f7d046f91bd165e747b9a95d089a4168b6f9796aWey-Yi Guy#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 1826f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 1836f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 1846f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1856f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 1866f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_HW_ERR | \ 1876f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_FH_TX | \ 1886f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_SW_ERR | \ 1896f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_RF_KILL | \ 1906f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_SW_RX | \ 1916f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_WAKEUP | \ 1926f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_ALIVE) 1936f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1946f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 1956f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 1966f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 1976f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 1986f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 1996f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 2006f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 2016f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 202f7d046f91bd165e747b9a95d089a4168b6f9796aWey-Yi Guy#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 203f7d046f91bd165e747b9a95d089a4168b6f9796aWey-Yi Guy CSR_FH_INT_BIT_RX_CHNL1 | \ 204f7d046f91bd165e747b9a95d089a4168b6f9796aWey-Yi Guy CSR_FH_INT_BIT_RX_CHNL0) 2056f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 206f7d046f91bd165e747b9a95d089a4168b6f9796aWey-Yi Guy#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 207f7d046f91bd165e747b9a95d089a4168b6f9796aWey-Yi Guy CSR_FH_INT_BIT_TX_CHNL0) 2086f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2096f4083aadd57e3da12fa4e67fcadaec23138a315Tomas Winkler/* GPIO */ 2106f4083aadd57e3da12fa4e67fcadaec23138a315Tomas Winkler#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 2116f4083aadd57e3da12fa4e67fcadaec23138a315Tomas Winkler#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 2126f4083aadd57e3da12fa4e67fcadaec23138a315Tomas Winkler#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 2136f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2146f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* RESET */ 2156f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 2166f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 2176f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 2186f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 2196f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 22032004ee42fced8b2372dd2f93e65cc9d71e8c4bfWey-Yi Guy#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 2216f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2229e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* 2239e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * GP (general purpose) CONTROL REGISTER 2249e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Bit fields: 2259e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 27: HW_RF_KILL_SW 2269e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Indicates state of (platform's) hardware RF-Kill switch 2279e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 26-24: POWER_SAVE_TYPE 2289e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Indicates current power-saving mode: 2299e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 000 -- No power saving 2309e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 001 -- MAC power-down 2319e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 010 -- PHY (radio) power-down 2329e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 011 -- Error 2339e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 9-6: SYS_CONFIG 2349e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Indicates current system configuration, reflecting pins on chip 2359e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * as forced high/low by device circuit board. 2369e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 4: GOING_TO_SLEEP 2379e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Indicates MAC is entering a power-saving sleep power-down. 2389e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Not a good time to access device-internal resources. 2399e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 3: MAC_ACCESS_REQ 2409e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Host sets this to request and maintain MAC wakeup, to allow host 2419e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * access to device-internal resources. Host must wait for 2429e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 2439e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * device registers. 2449e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 2: INIT_DONE 2459e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Host sets this to put device into fully operational D0 power mode. 2469e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Host resets this after SW_RESET to put device into low power mode. 2479e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 0: MAC_CLOCK_READY 2489e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Indicates MAC (ucode processor, etc.) is powered up and can run. 2499e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Internal resources are accessible. 2509e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * NOTE: This does not indicate that the processor is actually running. 251f7d046f91bd165e747b9a95d089a4168b6f9796aWey-Yi Guy * NOTE: This does not indicate that device has completed 2529e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * init or post-power-down restore of internal SRAM memory. 2539e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 2549e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * SRAM is restored and uCode is in normal operation mode. 2559e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 2569e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * do not need to save/restore it. 2579e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * NOTE: After device reset, this bit remains "0" until host sets 2589e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * INIT_DONE 2599e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill */ 2606f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 2616f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 2626f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 2636f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 2646f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2656f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 2666f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2676f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 2686f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 2696f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 2706f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2716f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 272b661c8190e91c0baeebf813fec7ff8e99e155a54Tomas Winkler/* HW REV */ 273fcdf1f73fe913c5f16b7f0547cc3df1b0796689fWey-Yi Guy#define CSR_HW_REV_TYPE_MSK (0x00001F0) 274fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_5300 (0x0000020) 275fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_5350 (0x0000030) 276fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_5100 (0x0000050) 277fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_5150 (0x0000040) 27877dcb6a9526b1e0d159a9300e512c7271bff3163Jay Sternberg#define CSR_HW_REV_TYPE_1000 (0x0000060) 2792264596d6d0a5c1e569af809625c11f8f2d89435Jay Sternberg#define CSR_HW_REV_TYPE_6x00 (0x0000070) 2802264596d6d0a5c1e569af809625c11f8f2d89435Jay Sternberg#define CSR_HW_REV_TYPE_6x50 (0x0000080) 28114a75766f38d44ca715d9e9ccb0a69e065e4a24eWey-Yi Guy#define CSR_HW_REV_TYPE_6150 (0x0000084) 28214a75766f38d44ca715d9e9ccb0a69e065e4a24eWey-Yi Guy#define CSR_HW_REV_TYPE_6x05 (0x00000B0) 28314a75766f38d44ca715d9e9ccb0a69e065e4a24eWey-Yi Guy#define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 284fcdf1f73fe913c5f16b7f0547cc3df1b0796689fWey-Yi Guy#define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 285fcdf1f73fe913c5f16b7f0547cc3df1b0796689fWey-Yi Guy#define CSR_HW_REV_TYPE_2x30 (0x00000C0) 286fcdf1f73fe913c5f16b7f0547cc3df1b0796689fWey-Yi Guy#define CSR_HW_REV_TYPE_2x00 (0x0000100) 2878c3d11617d61c0b69e029fd4087370bc8cb2218dWey-Yi Guy#define CSR_HW_REV_TYPE_105 (0x0000110) 2888c3d11617d61c0b69e029fd4087370bc8cb2218dWey-Yi Guy#define CSR_HW_REV_TYPE_135 (0x0000120) 289fcdf1f73fe913c5f16b7f0547cc3df1b0796689fWey-Yi Guy#define CSR_HW_REV_TYPE_NONE (0x00001F0) 290b661c8190e91c0baeebf813fec7ff8e99e155a54Tomas Winkler 2916f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* EEPROM REG */ 2926f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 2936f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_REG_BIT_CMD (0x00000002) 2943d5717ade01ce22511f2992f150bf6644b21c377Zhu, Yi#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 2953d5717ade01ce22511f2992f150bf6644b21c377Zhu, Yi#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 2966f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2976f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* EEPROM GP */ 2989e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 2996f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 3009e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 3019e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 3029e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 3039e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 3049e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 3059e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* One-time-programmable memory general purpose reg */ 3060848e297c2107dbc12a91a1709c879c73bd188d8Wey-Yi Guy#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 3070848e297c2107dbc12a91a1709c879c73bd188d8Wey-Yi Guy#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 3080848e297c2107dbc12a91a1709c879c73bd188d8Wey-Yi Guy#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 3090848e297c2107dbc12a91a1709c879c73bd188d8Wey-Yi Guy#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 3109e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 3119e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* GP REG */ 312c09430abed4159e5c56aaea257d040f7452daba6Wey-Yi Guy#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 313c09430abed4159e5c56aaea257d040f7452daba6Wey-Yi Guy#define CSR_GP_REG_NO_POWER_SAVE (0x00000000) 314c09430abed4159e5c56aaea257d040f7452daba6Wey-Yi Guy#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 315c09430abed4159e5c56aaea257d040f7452daba6Wey-Yi Guy#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 316c09430abed4159e5c56aaea257d040f7452daba6Wey-Yi Guy#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 3176f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 318f41bb897f202d23a7d896c716002a3d6050b991eWey-Yi Guy 3198f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler/* CSR GIO */ 3208f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 3218f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler 3229e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* 3239e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * UCODE-DRIVER GP (general purpose) mailbox register 1 3249e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Host driver and uCode write and/or read this register to communicate with 3259e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * each other. 3269e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Bit fields: 3279e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 4: UCODE_DISABLE 3289e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Host sets this to request permanent halt of uCode, same as 3299e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * sending CARD_STATE command with "halt" bit set. 3309e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 3: CT_KILL_EXIT 3319e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Host sets this to request exit from CT_KILL state, i.e. host thinks 3329e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * device temperature is low enough to continue normal operation. 3339e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 2: CMD_BLOCKED 3349e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 3359e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * to release uCode to clear all Tx and command queues, enter 3369e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * unassociated mode, and power down. 3379e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 3389e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 1: SW_BIT_RFKILL 3399e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Host sets this when issuing CARD_STATE command to request 3409e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * device sleep. 3419e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 0: MAC_SLEEP 3429e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * uCode sets this when preparing a power-saving power-down. 3439e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * uCode resets this when power-up is complete and SRAM is sane. 344f7d046f91bd165e747b9a95d089a4168b6f9796aWey-Yi Guy * NOTE: device saves internal SRAM data to host when powering down, 3459e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * and must restore this data after powering back up. 3469e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * MAC_SLEEP is the best indication that restore is complete. 3479e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 3489e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * do not need to save/restore it. 3499e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill */ 3506f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 3516f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 3526f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 3536f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 354c8ac61cf6e53fefb3b439fc58390fb65d2730e63Johannes Berg#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 3556f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 35665b7998a9be418482493e9448bb83ff2914ed050Wey-Yi Guy/* GP Driver */ 35765b7998a9be418482493e9448bb83ff2914ed050Wey-Yi Guy#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 35865b7998a9be418482493e9448bb83ff2914ed050Wey-Yi Guy#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 35965b7998a9be418482493e9448bb83ff2914ed050Wey-Yi Guy#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 36065b7998a9be418482493e9448bb83ff2914ed050Wey-Yi Guy#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 36102796d77cb4cfb64b9465eabbdb13b3b7d1679e9Shanyu Zhao#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 36202796d77cb4cfb64b9465eabbdb13b3b7d1679e9Shanyu Zhao#define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 36365b7998a9be418482493e9448bb83ff2914ed050Wey-Yi Guy 36452e6b85fe07ed1d2b5c76fd42ce1d77f1a190c72Wey-Yi Guy#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 36552e6b85fe07ed1d2b5c76fd42ce1d77f1a190c72Wey-Yi Guy 3669e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* GIO Chicken Bits (PCI Express bus link power management) */ 3676f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 3686f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 3696f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 370ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas/* LED */ 371ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 372ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas#define CSR_LED_REG_TRUN_ON (0x78) 373ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas#define CSR_LED_REG_TRUN_OFF (0x38) 374ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas 375a693f187facbf25925bbcf201db88c5384468646Tomas Winkler/* ANA_PLL */ 376a693f187facbf25925bbcf201db88c5384468646Tomas Winkler#define CSR50_ANA_PLL_CFG_VAL (0x00880300) 377a693f187facbf25925bbcf201db88c5384468646Tomas Winkler 3784c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler/* HPET MEM debug */ 3794c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 380ef850d7cb301bda9155c096269557a4586b58071Mohamed Abbas 381ef850d7cb301bda9155c096269557a4586b58071Mohamed Abbas/* DRAM INT TABLE */ 382ef850d7cb301bda9155c096269557a4586b58071Mohamed Abbas#define CSR_DRAM_INT_TBL_ENABLE (1 << 31) 383ef850d7cb301bda9155c096269557a4586b58071Mohamed Abbas#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 384ef850d7cb301bda9155c096269557a4586b58071Mohamed Abbas 3859e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* 3869e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * HBUS (Host-side Bus) 3879e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 3889e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * HBUS registers are mapped directly into PCI bus space, but are used 3899e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * to indirectly access device's internal memory or registers that 3909e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * may be powered-down. 3919e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 3929e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 3939e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 3949e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * to make sure the MAC (uCode processor, etc.) is powered up for accessing 3959e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * internal resources. 3969e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * 3979e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Do not use iwl_write32()/iwl_read32() family to access these registers; 3989e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * these provide only simple PCI bus access, without waking up the MAC. 3999e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill */ 400750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_BASE (0x400) 4019e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 402750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler/* 403750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 404750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * structures, error log, event log, verifying uCode load). 405750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * First write to address register, then read from or write to data register 406750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * to complete the job. Once the address register is set up, accesses to 407750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * data registers auto-increment the address by one dword. 408750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Bit usage for address registers (read or write): 409750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 0-31: memory address within device 410750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler */ 411750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 412750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 413750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 414750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 415750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler 4169e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 4179e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 4189e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 4199e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill 420750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler/* 421750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Registers for accessing device's internal peripheral registers 422750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * (e.g. SCD, BSM, etc.). First write to address register, 423750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * then read from or write to data register to complete the job. 424750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Bit usage for address registers (read or write): 425750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 0-15: register address (offset) within device 426750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 427750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler */ 428750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 429750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 430750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 431750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 432750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler 433750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler/* 4349e595d24b13a021ead42bedd5edba8801b0da6cdBen M Cahill * Per-Tx-queue write pointer (index, really!) 435750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Indicates index to next TFD that driver will fill (1 past latest filled). 436750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Bit usage: 437750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 0-7: queue write index 438750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 11-8: queue selector 439750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler */ 440750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 441750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler 4427a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach/********************************************************** 4437a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach * CSR values 4447a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach **********************************************************/ 4457a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach /* 4467a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach * host interrupt timeout value 4477a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach * used with setting interrupt coalescing timer 4487a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 4497a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach * 4507a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach * default interrupt coalescing timer is 64 x 32 = 2048 usecs 4517a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs 4527a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach */ 4537a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach#define IWL_HOST_INT_TIMEOUT_MAX (0xFF) 4547a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach#define IWL_HOST_INT_TIMEOUT_DEF (0x40) 4557a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach#define IWL_HOST_INT_TIMEOUT_MIN (0x0) 4567a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) 4577a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) 4587a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) 4597a10e3e4076d09779da5a02b0ab6ce551d964d48Emmanuel Grumbach 46065a0667b43ff746b2964b2a257ffff1a4747e19dTomas Winkler#endif /* !__iwl_csr_h__ */ 461