iwl-csr.h revision 2264596d6d0a5c1e569af809625c11f8f2d89435
16f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/****************************************************************************** 26f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 36f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * This file is provided under a dual BSD/GPLv2 license. When using or 46f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * redistributing this file, you may do so under either license. 56f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 66f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * GPL LICENSE SUMMARY 76f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 801f8162a854df7f9c259c839ad3c1168ac13b7b8Reinette Chatre * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. 96f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 106f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * This program is free software; you can redistribute it and/or modify 116f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * it under the terms of version 2 of the GNU General Public License as 126f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * published by the Free Software Foundation. 136f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 146f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * This program is distributed in the hope that it will be useful, but 156f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * WITHOUT ANY WARRANTY; without even the implied warranty of 166f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 176f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * General Public License for more details. 186f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 196f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * You should have received a copy of the GNU General Public License 206f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * along with this program; if not, write to the Free Software 216f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 226f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * USA 236f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 246f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * The full GNU General Public License is included in this distribution 256f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * in the file called LICENSE.GPL. 266f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 276f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Contact Information: 28759ef89fb096c4a6ef078d3cfd5682ac037bd789Winkler, Tomas * Intel Linux Wireless <ilw@linux.intel.com> 296f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 306f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 316f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * BSD LICENSE 326f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 3301f8162a854df7f9c259c839ad3c1168ac13b7b8Reinette Chatre * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. 346f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * All rights reserved. 356f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 366f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Redistribution and use in source and binary forms, with or without 376f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * modification, are permitted provided that the following conditions 386f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * are met: 396f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 406f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * * Redistributions of source code must retain the above copyright 416f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * notice, this list of conditions and the following disclaimer. 426f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * * Redistributions in binary form must reproduce the above copyright 436f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * notice, this list of conditions and the following disclaimer in 446f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * the documentation and/or other materials provided with the 456f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * distribution. 466f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * * Neither the name Intel Corporation nor the names of its 476f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * contributors may be used to endorse or promote products derived 486f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * from this software without specific prior written permission. 496f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 506f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 516f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 526f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 536f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 546f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 556f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 566f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 576f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 586f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 596f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 606f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 616f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 626f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler *****************************************************************************/ 6365a0667b43ff746b2964b2a257ffff1a4747e19dTomas Winkler#ifndef __iwl_csr_h__ 6465a0667b43ff746b2964b2a257ffff1a4747e19dTomas Winkler#define __iwl_csr_h__ 656f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/*=== CSR (control and status registers) ===*/ 666f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_BASE (0x000) 676f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 686f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 698cd519e89616057c8a433a54a3e60883e4893017Winkler, Tomas#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 706f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 716f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 726f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ 736f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 746f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ 756f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL (CSR_BASE+0x024) 766f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 776f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* 786f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Hardware revision info 796f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Bit fields: 806f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 31-8: Reserved 816f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 7-4: Type of device: 0x0 = 4965, 0xd = 3945 826f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 836f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 1-0: "Dash" value, as in A-1, etc. 846f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 856f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * NOTE: Revision step affects calculation of CCK txpower for 4965. 866f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler */ 876f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_HW_REV (CSR_BASE+0x028) 886f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 896f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* EEPROM reads */ 906f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_REG (CSR_BASE+0x02c) 916f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_GP (CSR_BASE+0x030) 928f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler#define CSR_GIO_REG (CSR_BASE+0x03C) 936f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_UCODE (CSR_BASE+0x044) 946f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 956f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 966f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 976f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 98ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas#define CSR_LED_REG (CSR_BASE+0x094) 998f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 1006f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 101a693f187facbf25925bbcf201db88c5384468646Tomas Winkler/* Analog phase-lock-loop configuration */ 1026f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 1036f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* 1046f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Indicates hardware rev, to determine CCK backoff for txpower calculation. 1056f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * Bit fields: 1066f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 1076f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler */ 1086f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 1094c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 1106f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1116f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* Bits for CSR_HW_IF_CONFIG_REG */ 1126f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) 113a395b92024d9b8f9403c06f9ea8d425f1883d7d8Tomas Winkler#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) 114a395b92024d9b8f9403c06f9ea8d425f1883d7d8Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 115a395b92024d9b8f9403c06f9ea8d425f1883d7d8Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 1166f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1176f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100) 1186f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200) 1196f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) 1206f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) 1216f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) 1226f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) 1236f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1244c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 1254c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 1264c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_PCI_OWN_SEM (0x00400000) 1274c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_ME_OWN (0x02000000) 1284c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler#define CSR_HW_IF_CONFIG_REG_BIT_WAKE_ME (0x08000000) 1294c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler 1306f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1316f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 1326f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler * acknowledged (reset) by host writing "1" to flagged bits. */ 1336f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 1346f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 1356f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */ 1366f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 1376f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 1386f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 1396f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 1406f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 1416f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */ 1426f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 1436f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 1446f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1456f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 1466f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_HW_ERR | \ 1476f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_FH_TX | \ 1486f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_SW_ERR | \ 1496f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_RF_KILL | \ 1506f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_SW_RX | \ 1516f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_WAKEUP | \ 1526f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_INT_BIT_ALIVE) 1536f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1546f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 1556f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 1566f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 1576f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */ 1586f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 1596f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 1606f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */ 1616f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 1626f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 1636f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1646f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 1656f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR39_FH_INT_BIT_RX_CHNL2 | \ 1666f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_FH_INT_BIT_RX_CHNL1 | \ 1676f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_FH_INT_BIT_RX_CHNL0) 1686f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1696f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1706f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 | \ 1716f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_FH_INT_BIT_TX_CHNL1 | \ 1726f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_FH_INT_BIT_TX_CHNL0) 1736f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1746f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 1756f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_FH_INT_BIT_RX_CHNL1 | \ 1766f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_FH_INT_BIT_RX_CHNL0) 1776f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1786f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 1796f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler CSR_FH_INT_BIT_TX_CHNL0) 1806f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1816f4083aadd57e3da12fa4e67fcadaec23138a315Tomas Winkler/* GPIO */ 1826f4083aadd57e3da12fa4e67fcadaec23138a315Tomas Winkler#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 1836f4083aadd57e3da12fa4e67fcadaec23138a315Tomas Winkler#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 1846f4083aadd57e3da12fa4e67fcadaec23138a315Tomas Winkler#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 1856f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1866f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* RESET */ 1876f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 1886f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 1896f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 1906f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 1916f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 1926f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1936f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* GP (general purpose) CONTROL */ 1946f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 1956f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 1966f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 1976f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 1986f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 1996f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 2006f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2016f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 2026f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 2036f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 2046f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2056f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 206b661c8190e91c0baeebf813fec7ff8e99e155a54Tomas Winkler/* HW REV */ 207b661c8190e91c0baeebf813fec7ff8e99e155a54Tomas Winkler#define CSR_HW_REV_TYPE_MSK (0x00000F0) 208b661c8190e91c0baeebf813fec7ff8e99e155a54Tomas Winkler#define CSR_HW_REV_TYPE_3945 (0x00000D0) 209b661c8190e91c0baeebf813fec7ff8e99e155a54Tomas Winkler#define CSR_HW_REV_TYPE_4965 (0x0000000) 210fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_5300 (0x0000020) 211fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_5350 (0x0000030) 212fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_5100 (0x0000050) 213fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_5150 (0x0000040) 2142264596d6d0a5c1e569af809625c11f8f2d89435Jay Sternberg#define CSR_HW_REV_TYPE_100 (0x0000060) 2152264596d6d0a5c1e569af809625c11f8f2d89435Jay Sternberg#define CSR_HW_REV_TYPE_6x00 (0x0000070) 2162264596d6d0a5c1e569af809625c11f8f2d89435Jay Sternberg#define CSR_HW_REV_TYPE_6x50 (0x0000080) 217fcf623df17197adf10e22ddeba90c56504edce0fTomas Winkler#define CSR_HW_REV_TYPE_NONE (0x00000F0) 218b661c8190e91c0baeebf813fec7ff8e99e155a54Tomas Winkler 2196f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* EEPROM REG */ 2206f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 2216f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_REG_BIT_CMD (0x00000002) 2223d5717ade01ce22511f2992f150bf6644b21c377Zhu, Yi#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 2233d5717ade01ce22511f2992f150bf6644b21c377Zhu, Yi#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 2246f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2256f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* EEPROM GP */ 2266f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_GP_VALID_MSK (0x00000006) 2276f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000) 2286f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 2296f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2308f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler/* CSR GIO */ 2318f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 2328f0618914e02c62c5cf2482f8acc7eb8e9afb816Tomas Winkler 2336f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* UCODE DRV GP */ 2346f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 2356f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 2366f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 2376f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 2386f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 2396f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler/* GI Chicken Bits */ 2406f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 2416f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 2426f83eaa170c05324fb33668eace007ea24c277d2Tomas Winkler 243ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas/* LED */ 244ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 245ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas#define CSR_LED_REG_TRUN_ON (0x78) 246ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas#define CSR_LED_REG_TRUN_OFF (0x38) 247ab53d8af6772b22d4d68b1bcd74f7a5dba693983Mohamed Abbas 248a693f187facbf25925bbcf201db88c5384468646Tomas Winkler/* ANA_PLL */ 249a693f187facbf25925bbcf201db88c5384468646Tomas Winkler#define CSR39_ANA_PLL_CFG_VAL (0x01000000) 250a693f187facbf25925bbcf201db88c5384468646Tomas Winkler#define CSR50_ANA_PLL_CFG_VAL (0x00880300) 251a693f187facbf25925bbcf201db88c5384468646Tomas Winkler 2524c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler/* HPET MEM debug */ 2534c43e0d0ecd5196ed5c67f64ed2f1860770eed34Tomas Winkler#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 254750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler/*=== HBUS (Host-side Bus) ===*/ 255750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_BASE (0x400) 256750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler/* 257750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 258750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * structures, error log, event log, verifying uCode load). 259750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * First write to address register, then read from or write to data register 260750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * to complete the job. Once the address register is set up, accesses to 261750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * data registers auto-increment the address by one dword. 262750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Bit usage for address registers (read or write): 263750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 0-31: memory address within device 264750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler */ 265750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 266750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 267750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 268750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 269750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler 270750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler/* 271750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Registers for accessing device's internal peripheral registers 272750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * (e.g. SCD, BSM, etc.). First write to address register, 273750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * then read from or write to data register to complete the job. 274750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Bit usage for address registers (read or write): 275750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 0-15: register address (offset) within device 276750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 277750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler */ 278750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 279750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 280750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 281750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 282750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler 283750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler/* 284750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Per-Tx-queue write pointer (index, really!) (3945 and 4965). 285750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Indicates index to next TFD that driver will fill (1 past latest filled). 286750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * Bit usage: 287750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 0-7: queue write index 288750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler * 11-8: queue selector 289750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler */ 290750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 291750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 292750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler 293750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 294750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler 295750fe6396614e267aeec0e2ff636740e2688d4d9Tomas Winkler 29665a0667b43ff746b2964b2a257ffff1a4747e19dTomas Winkler#endif /* !__iwl_csr_h__ */ 297