p54spi.c revision 2ac710720c523dd243662746da4381dd4f1772f8
1/* 2 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de> 3 * Copyright 2008 Johannes Berg <johannes@sipsolutions.net> 4 * 5 * This driver is a port from stlc45xx: 6 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies). 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 */ 22 23#include <linux/module.h> 24#include <linux/platform_device.h> 25#include <linux/interrupt.h> 26#include <linux/firmware.h> 27#include <linux/delay.h> 28#include <linux/irq.h> 29#include <linux/spi/spi.h> 30#include <linux/etherdevice.h> 31#include <linux/gpio.h> 32 33#include "p54spi.h" 34#include "p54spi_eeprom.h" 35#include "p54.h" 36 37#include "p54common.h" 38 39MODULE_FIRMWARE("3826.arm"); 40MODULE_ALIAS("stlc45xx"); 41 42/* 43 * gpios should be handled in board files and provided via platform data, 44 * but because it's currently impossible for p54spi to have a header file 45 * in include/linux, let's use module paramaters for now 46 */ 47 48static int p54spi_gpio_power = 97; 49module_param(p54spi_gpio_power, int, 0444); 50MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line"); 51 52static int p54spi_gpio_irq = 87; 53module_param(p54spi_gpio_irq, int, 0444); 54MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line"); 55 56static void p54spi_spi_read(struct p54s_priv *priv, u8 address, 57 void *buf, size_t len) 58{ 59 struct spi_transfer t[2]; 60 struct spi_message m; 61 __le16 addr; 62 63 /* We first push the address */ 64 addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15); 65 66 spi_message_init(&m); 67 memset(t, 0, sizeof(t)); 68 69 t[0].tx_buf = &addr; 70 t[0].len = sizeof(addr); 71 spi_message_add_tail(&t[0], &m); 72 73 t[1].rx_buf = buf; 74 t[1].len = len; 75 spi_message_add_tail(&t[1], &m); 76 77 spi_sync(priv->spi, &m); 78} 79 80 81static void p54spi_spi_write(struct p54s_priv *priv, u8 address, 82 const void *buf, size_t len) 83{ 84 struct spi_transfer t[3]; 85 struct spi_message m; 86 __le16 addr; 87 88 /* We first push the address */ 89 addr = cpu_to_le16(address << 8); 90 91 spi_message_init(&m); 92 memset(t, 0, sizeof(t)); 93 94 t[0].tx_buf = &addr; 95 t[0].len = sizeof(addr); 96 spi_message_add_tail(&t[0], &m); 97 98 t[1].tx_buf = buf; 99 t[1].len = len; 100 spi_message_add_tail(&t[1], &m); 101 102 if (len % 2) { 103 __le16 last_word; 104 last_word = cpu_to_le16(((u8 *)buf)[len - 1]); 105 106 t[2].tx_buf = &last_word; 107 t[2].len = sizeof(last_word); 108 spi_message_add_tail(&t[2], &m); 109 } 110 111 spi_sync(priv->spi, &m); 112} 113 114static u16 p54spi_read16(struct p54s_priv *priv, u8 addr) 115{ 116 __le16 val; 117 118 p54spi_spi_read(priv, addr, &val, sizeof(val)); 119 120 return le16_to_cpu(val); 121} 122 123static u32 p54spi_read32(struct p54s_priv *priv, u8 addr) 124{ 125 __le32 val; 126 127 p54spi_spi_read(priv, addr, &val, sizeof(val)); 128 129 return le32_to_cpu(val); 130} 131 132static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val) 133{ 134 p54spi_spi_write(priv, addr, &val, sizeof(val)); 135} 136 137static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val) 138{ 139 p54spi_spi_write(priv, addr, &val, sizeof(val)); 140} 141 142struct p54spi_spi_reg { 143 u16 address; /* __le16 ? */ 144 u16 length; 145 char *name; 146}; 147 148static const struct p54spi_spi_reg p54spi_registers_array[] = 149{ 150 { SPI_ADRS_ARM_INTERRUPTS, 32, "ARM_INT " }, 151 { SPI_ADRS_ARM_INT_EN, 32, "ARM_INT_ENA " }, 152 { SPI_ADRS_HOST_INTERRUPTS, 32, "HOST_INT " }, 153 { SPI_ADRS_HOST_INT_EN, 32, "HOST_INT_ENA" }, 154 { SPI_ADRS_HOST_INT_ACK, 32, "HOST_INT_ACK" }, 155 { SPI_ADRS_GEN_PURP_1, 32, "GP1_COMM " }, 156 { SPI_ADRS_GEN_PURP_2, 32, "GP2_COMM " }, 157 { SPI_ADRS_DEV_CTRL_STAT, 32, "DEV_CTRL_STA" }, 158 { SPI_ADRS_DMA_DATA, 16, "DMA_DATA " }, 159 { SPI_ADRS_DMA_WRITE_CTRL, 16, "DMA_WR_CTRL " }, 160 { SPI_ADRS_DMA_WRITE_LEN, 16, "DMA_WR_LEN " }, 161 { SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_WR_BASE " }, 162 { SPI_ADRS_DMA_READ_CTRL, 16, "DMA_RD_CTRL " }, 163 { SPI_ADRS_DMA_READ_LEN, 16, "DMA_RD_LEN " }, 164 { SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_RD_BASE " } 165}; 166 167static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, __le32 bits) 168{ 169 int i; 170 __le32 buffer; 171 172 for (i = 0; i < 2000; i++) { 173 p54spi_spi_read(priv, reg, &buffer, sizeof(buffer)); 174 if (buffer == bits) 175 return 1; 176 177 msleep(1); 178 } 179 return 0; 180} 181 182static int p54spi_request_firmware(struct ieee80211_hw *dev) 183{ 184 struct p54s_priv *priv = dev->priv; 185 int ret; 186 187 /* FIXME: should driver use it's own struct device? */ 188 ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev); 189 190 if (ret < 0) { 191 dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret); 192 return ret; 193 } 194 195 ret = p54_parse_firmware(dev, priv->firmware); 196 if (ret) { 197 release_firmware(priv->firmware); 198 return ret; 199 } 200 201 return 0; 202} 203 204static int p54spi_request_eeprom(struct ieee80211_hw *dev) 205{ 206 struct p54s_priv *priv = dev->priv; 207 const struct firmware *eeprom; 208 int ret; 209 210 /* 211 * allow users to customize their eeprom. 212 */ 213 214 ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev); 215 if (ret < 0) { 216 dev_info(&priv->spi->dev, "loading default eeprom...\n"); 217 ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom, 218 sizeof(p54spi_eeprom)); 219 } else { 220 dev_info(&priv->spi->dev, "loading user eeprom...\n"); 221 ret = p54_parse_eeprom(dev, (void *) eeprom->data, 222 (int)eeprom->size); 223 release_firmware(eeprom); 224 } 225 return ret; 226} 227 228static int p54spi_upload_firmware(struct ieee80211_hw *dev) 229{ 230 struct p54s_priv *priv = dev->priv; 231 unsigned long fw_len, fw_addr; 232 long _fw_len; 233 234 /* stop the device */ 235 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( 236 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET | 237 SPI_CTRL_STAT_START_HALTED)); 238 239 msleep(TARGET_BOOT_SLEEP); 240 241 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( 242 SPI_CTRL_STAT_HOST_OVERRIDE | 243 SPI_CTRL_STAT_START_HALTED)); 244 245 msleep(TARGET_BOOT_SLEEP); 246 247 fw_addr = ISL38XX_DEV_FIRMWARE_ADDR; 248 fw_len = priv->firmware->size; 249 250 while (fw_len > 0) { 251 _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE); 252 253 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL, 254 cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE)); 255 256 if (p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, 257 cpu_to_le32(HOST_ALLOWED)) == 0) { 258 dev_err(&priv->spi->dev, "fw_upload not allowed " 259 "to DMA write."); 260 return -EAGAIN; 261 } 262 263 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, 264 cpu_to_le16(_fw_len)); 265 p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, 266 cpu_to_le32(fw_addr)); 267 268 p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, 269 &priv->firmware->data, _fw_len); 270 271 fw_len -= _fw_len; 272 fw_addr += _fw_len; 273 274 /* FIXME: I think this doesn't work if firmware is large, 275 * this loop goes to second round. fw->data is not 276 * increased at all! */ 277 } 278 279 BUG_ON(fw_len != 0); 280 281 /* enable host interrupts */ 282 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, 283 cpu_to_le32(SPI_HOST_INTS_DEFAULT)); 284 285 /* boot the device */ 286 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( 287 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET | 288 SPI_CTRL_STAT_RAM_BOOT)); 289 290 msleep(TARGET_BOOT_SLEEP); 291 292 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16( 293 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT)); 294 msleep(TARGET_BOOT_SLEEP); 295 return 0; 296} 297 298static void p54spi_power_off(struct p54s_priv *priv) 299{ 300 disable_irq(gpio_to_irq(p54spi_gpio_irq)); 301 gpio_set_value(p54spi_gpio_power, 0); 302} 303 304static void p54spi_power_on(struct p54s_priv *priv) 305{ 306 gpio_set_value(p54spi_gpio_power, 1); 307 enable_irq(gpio_to_irq(p54spi_gpio_irq)); 308 309 /* 310 * need to wait a while before device can be accessed, the lenght 311 * is just a guess 312 */ 313 msleep(10); 314} 315 316static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val) 317{ 318 p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val)); 319} 320 321static void p54spi_wakeup(struct p54s_priv *priv) 322{ 323 unsigned long timeout; 324 u32 ints; 325 326 /* wake the chip */ 327 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS, 328 cpu_to_le32(SPI_TARGET_INT_WAKEUP)); 329 330 /* And wait for the READY interrupt */ 331 timeout = jiffies + HZ; 332 333 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS); 334 while (!(ints & SPI_HOST_INT_READY)) { 335 if (time_after(jiffies, timeout)) 336 goto out; 337 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS); 338 } 339 340 p54spi_int_ack(priv, SPI_HOST_INT_READY); 341 342out: 343 return; 344} 345 346static inline void p54spi_sleep(struct p54s_priv *priv) 347{ 348 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS, 349 cpu_to_le32(SPI_TARGET_INT_SLEEP)); 350} 351 352static void p54spi_int_ready(struct p54s_priv *priv) 353{ 354 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32( 355 SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE)); 356 357 switch (priv->fw_state) { 358 case FW_STATE_BOOTING: 359 priv->fw_state = FW_STATE_READY; 360 complete(&priv->fw_comp); 361 break; 362 case FW_STATE_RESETTING: 363 priv->fw_state = FW_STATE_READY; 364 /* TODO: reinitialize state */ 365 break; 366 default: 367 break; 368 } 369} 370 371static int p54spi_rx(struct p54s_priv *priv) 372{ 373 struct sk_buff *skb; 374 u16 len; 375 376 p54spi_wakeup(priv); 377 378 /* dummy read to flush SPI DMA controller bug */ 379 p54spi_read16(priv, SPI_ADRS_GEN_PURP_1); 380 381 len = p54spi_read16(priv, SPI_ADRS_DMA_DATA); 382 383 if (len == 0) { 384 dev_err(&priv->spi->dev, "rx request of zero bytes"); 385 return 0; 386 } 387 388 skb = dev_alloc_skb(len); 389 if (!skb) { 390 dev_err(&priv->spi->dev, "could not alloc skb"); 391 return 0; 392 } 393 394 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, skb_put(skb, len), len); 395 p54spi_sleep(priv); 396 397 if (p54_rx(priv->hw, skb) == 0) 398 dev_kfree_skb(skb); 399 400 return 0; 401} 402 403 404static irqreturn_t p54spi_interrupt(int irq, void *config) 405{ 406 struct spi_device *spi = config; 407 struct p54s_priv *priv = dev_get_drvdata(&spi->dev); 408 409 queue_work(priv->hw->workqueue, &priv->work); 410 411 return IRQ_HANDLED; 412} 413 414static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb) 415{ 416 struct p54_hdr *hdr = (struct p54_hdr *) skb->data; 417 struct p54s_dma_regs dma_regs; 418 unsigned long timeout; 419 int ret = 0; 420 u32 ints; 421 422 p54spi_wakeup(priv); 423 424 dma_regs.cmd = cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE); 425 dma_regs.len = cpu_to_le16(skb->len); 426 dma_regs.addr = hdr->req_id; 427 428 p54spi_spi_write(priv, SPI_ADRS_DMA_WRITE_CTRL, &dma_regs, 429 sizeof(dma_regs)); 430 431 p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, skb->data, skb->len); 432 433 timeout = jiffies + 2 * HZ; 434 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS); 435 while (!(ints & SPI_HOST_INT_WR_READY)) { 436 if (time_after(jiffies, timeout)) { 437 dev_err(&priv->spi->dev, "WR_READY timeout"); 438 ret = -1; 439 goto out; 440 } 441 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS); 442 } 443 444 p54spi_int_ack(priv, SPI_HOST_INT_WR_READY); 445 p54spi_sleep(priv); 446 447out: 448 if (FREE_AFTER_TX(skb)) 449 p54_free_skb(priv->hw, skb); 450 return ret; 451} 452 453static int p54spi_wq_tx(struct p54s_priv *priv) 454{ 455 struct p54s_tx_info *entry; 456 struct sk_buff *skb; 457 struct ieee80211_tx_info *info; 458 struct p54_tx_info *minfo; 459 struct p54s_tx_info *dinfo; 460 int ret = 0; 461 462 spin_lock_bh(&priv->tx_lock); 463 464 while (!list_empty(&priv->tx_pending)) { 465 entry = list_entry(priv->tx_pending.next, 466 struct p54s_tx_info, tx_list); 467 468 list_del_init(&entry->tx_list); 469 470 spin_unlock_bh(&priv->tx_lock); 471 472 dinfo = container_of((void *) entry, struct p54s_tx_info, 473 tx_list); 474 minfo = container_of((void *) dinfo, struct p54_tx_info, 475 data); 476 info = container_of((void *) minfo, struct ieee80211_tx_info, 477 rate_driver_data); 478 skb = container_of((void *) info, struct sk_buff, cb); 479 480 ret = p54spi_tx_frame(priv, skb); 481 482 spin_lock_bh(&priv->tx_lock); 483 484 if (ret < 0) { 485 p54_free_skb(priv->hw, skb); 486 goto out; 487 } 488 } 489 490out: 491 spin_unlock_bh(&priv->tx_lock); 492 return ret; 493} 494 495static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb) 496{ 497 struct p54s_priv *priv = dev->priv; 498 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 499 struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data; 500 struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data; 501 502 BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data))); 503 504 spin_lock_bh(&priv->tx_lock); 505 list_add_tail(&di->tx_list, &priv->tx_pending); 506 spin_unlock_bh(&priv->tx_lock); 507 508 queue_work(priv->hw->workqueue, &priv->work); 509} 510 511static void p54spi_work(struct work_struct *work) 512{ 513 struct p54s_priv *priv = container_of(work, struct p54s_priv, work); 514 u32 ints; 515 int ret; 516 517 mutex_lock(&priv->mutex); 518 519 if (priv->fw_state == FW_STATE_OFF && 520 priv->fw_state == FW_STATE_RESET) 521 goto out; 522 523 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS); 524 525 if (ints & SPI_HOST_INT_READY) { 526 p54spi_int_ready(priv); 527 p54spi_int_ack(priv, SPI_HOST_INT_READY); 528 } 529 530 if (priv->fw_state != FW_STATE_READY) 531 goto out; 532 533 if (ints & SPI_HOST_INT_UPDATE) { 534 p54spi_int_ack(priv, SPI_HOST_INT_UPDATE); 535 ret = p54spi_rx(priv); 536 if (ret < 0) 537 goto out; 538 } 539 if (ints & SPI_HOST_INT_SW_UPDATE) { 540 p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE); 541 ret = p54spi_rx(priv); 542 if (ret < 0) 543 goto out; 544 } 545 546 ret = p54spi_wq_tx(priv); 547 if (ret < 0) 548 goto out; 549 550 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS); 551 552out: 553 mutex_unlock(&priv->mutex); 554} 555 556static int p54spi_op_start(struct ieee80211_hw *dev) 557{ 558 struct p54s_priv *priv = dev->priv; 559 unsigned long timeout; 560 int ret = 0; 561 562 if (mutex_lock_interruptible(&priv->mutex)) { 563 ret = -EINTR; 564 goto out; 565 } 566 567 priv->fw_state = FW_STATE_BOOTING; 568 569 p54spi_power_on(priv); 570 571 ret = p54spi_upload_firmware(dev); 572 if (ret < 0) { 573 p54spi_power_off(priv); 574 goto out_unlock; 575 } 576 577 mutex_unlock(&priv->mutex); 578 579 timeout = msecs_to_jiffies(2000); 580 timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp, 581 timeout); 582 if (!timeout) { 583 dev_err(&priv->spi->dev, "firmware boot failed"); 584 p54spi_power_off(priv); 585 ret = -1; 586 goto out; 587 } 588 589 if (mutex_lock_interruptible(&priv->mutex)) { 590 ret = -EINTR; 591 p54spi_power_off(priv); 592 goto out; 593 } 594 595 WARN_ON(priv->fw_state != FW_STATE_READY); 596 597out_unlock: 598 mutex_unlock(&priv->mutex); 599 600out: 601 return ret; 602} 603 604static void p54spi_op_stop(struct ieee80211_hw *dev) 605{ 606 struct p54s_priv *priv = dev->priv; 607 608 if (mutex_lock_interruptible(&priv->mutex)) { 609 /* FIXME: how to handle this error? */ 610 return; 611 } 612 613 WARN_ON(priv->fw_state != FW_STATE_READY); 614 615 cancel_work_sync(&priv->work); 616 617 p54spi_power_off(priv); 618 spin_lock_bh(&priv->tx_lock); 619 INIT_LIST_HEAD(&priv->tx_pending); 620 spin_unlock_bh(&priv->tx_lock); 621 622 priv->fw_state = FW_STATE_OFF; 623 mutex_unlock(&priv->mutex); 624} 625 626static int __devinit p54spi_probe(struct spi_device *spi) 627{ 628 struct p54s_priv *priv = NULL; 629 struct ieee80211_hw *hw; 630 int ret = -EINVAL; 631 632 hw = p54_init_common(sizeof(*priv)); 633 if (!hw) { 634 dev_err(&priv->spi->dev, "could not alloc ieee80211_hw"); 635 return -ENOMEM; 636 } 637 638 priv = hw->priv; 639 priv->hw = hw; 640 dev_set_drvdata(&spi->dev, priv); 641 priv->spi = spi; 642 643 spi->bits_per_word = 16; 644 spi->max_speed_hz = 24000000; 645 646 ret = spi_setup(spi); 647 if (ret < 0) { 648 dev_err(&priv->spi->dev, "spi_setup failed"); 649 goto err_free_common; 650 } 651 652 ret = gpio_request(p54spi_gpio_power, "p54spi power"); 653 if (ret < 0) { 654 dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret); 655 goto err_free_common; 656 } 657 658 ret = gpio_request(p54spi_gpio_irq, "p54spi irq"); 659 if (ret < 0) { 660 dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret); 661 goto err_free_common; 662 } 663 664 gpio_direction_output(p54spi_gpio_power, 0); 665 gpio_direction_input(p54spi_gpio_irq); 666 667 ret = request_irq(gpio_to_irq(p54spi_gpio_irq), 668 p54spi_interrupt, IRQF_DISABLED, "p54spi", 669 priv->spi); 670 if (ret < 0) { 671 dev_err(&priv->spi->dev, "request_irq() failed"); 672 goto err_free_common; 673 } 674 675 set_irq_type(gpio_to_irq(p54spi_gpio_irq), 676 IRQ_TYPE_EDGE_RISING); 677 678 disable_irq(gpio_to_irq(p54spi_gpio_irq)); 679 680 INIT_WORK(&priv->work, p54spi_work); 681 init_completion(&priv->fw_comp); 682 INIT_LIST_HEAD(&priv->tx_pending); 683 mutex_init(&priv->mutex); 684 SET_IEEE80211_DEV(hw, &spi->dev); 685 priv->common.open = p54spi_op_start; 686 priv->common.stop = p54spi_op_stop; 687 priv->common.tx = p54spi_op_tx; 688 689 ret = p54spi_request_firmware(hw); 690 if (ret < 0) 691 goto err_free_common; 692 693 ret = p54spi_request_eeprom(hw); 694 if (ret) 695 goto err_free_common; 696 697 ret = p54_register_common(hw, &priv->spi->dev); 698 if (ret) 699 goto err_free_common; 700 701 return 0; 702 703err_free_common: 704 p54_free_common(priv->hw); 705 return ret; 706} 707 708static int __devexit p54spi_remove(struct spi_device *spi) 709{ 710 struct p54s_priv *priv = dev_get_drvdata(&spi->dev); 711 712 ieee80211_unregister_hw(priv->hw); 713 714 free_irq(gpio_to_irq(p54spi_gpio_irq), spi); 715 716 gpio_free(p54spi_gpio_power); 717 gpio_free(p54spi_gpio_irq); 718 release_firmware(priv->firmware); 719 720 mutex_destroy(&priv->mutex); 721 722 p54_free_common(priv->hw); 723 ieee80211_free_hw(priv->hw); 724 725 return 0; 726} 727 728 729static struct spi_driver p54spi_driver = { 730 .driver = { 731 /* use cx3110x name because board-n800.c uses that for the 732 * SPI port */ 733 .name = "cx3110x", 734 .bus = &spi_bus_type, 735 .owner = THIS_MODULE, 736 }, 737 738 .probe = p54spi_probe, 739 .remove = __devexit_p(p54spi_remove), 740}; 741 742static int __init p54spi_init(void) 743{ 744 int ret; 745 746 ret = spi_register_driver(&p54spi_driver); 747 if (ret < 0) { 748 printk(KERN_ERR "failed to register SPI driver: %d", ret); 749 goto out; 750 } 751 752out: 753 return ret; 754} 755 756static void __exit p54spi_exit(void) 757{ 758 spi_unregister_driver(&p54spi_driver); 759} 760 761module_init(p54spi_init); 762module_exit(p54spi_exit); 763 764MODULE_LICENSE("GPL"); 765MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>"); 766