1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012  Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#ifndef	__RTL_92S_DM_H__
30#define __RTL_92S_DM_H__
31
32struct dig_t {
33	u8 dig_enable_flag;
34	u8 dig_algorithm;
35	u8 dig_twoport_algorithm;
36	u8 dig_ext_port_stage;
37	u8 dig_dbgmode;
38	u8 dig_slgorithm_switch;
39
40	long rssi_lowthresh;
41	long rssi_highthresh;
42
43	u32 fa_lowthresh;
44	u32 fa_highthresh;
45
46	long rssi_highpower_lowthresh;
47	long rssi_highpower_highthresh;
48
49	u8 dig_state;
50	u8 dig_highpwrstate;
51	u8 cur_sta_connectstate;
52	u8 pre_sta_connectstate;
53	u8 cur_ap_connectstate;
54	u8 pre_ap_connectstate;
55
56	u8 cur_pd_thstate;
57	u8 pre_pd_thstate;
58	u8 cur_cs_ratiostate;
59	u8 pre_cs_ratiostate;
60
61	u32 pre_igvalue;
62	u32	cur_igvalue;
63
64	u8 backoff_enable_flag;
65	char backoff_val;
66	char backoffval_range_max;
67	char backoffval_range_min;
68	u8 rx_gain_range_max;
69	u8 rx_gain_range_min;
70
71	long rssi_val;
72};
73
74enum dm_dig_alg {
75	DIG_ALGO_BY_FALSE_ALARM = 0,
76	DIG_ALGO_BY_RSSI	= 1,
77	DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2,
78	DIG_ALGO_BY_TOW_PORT = 3,
79	DIG_ALGO_MAX
80};
81
82enum dm_dig_two_port_alg {
83	DIG_TWO_PORT_ALGO_RSSI = 0,
84	DIG_TWO_PORT_ALGO_FALSE_ALARM = 1,
85};
86
87enum dm_dig_dbg {
88	DM_DBG_OFF = 0,
89	DM_DBG_ON = 1,
90	DM_DBG_MAX
91};
92
93enum dm_dig_sta {
94	DM_STA_DIG_OFF = 0,
95	DM_STA_DIG_ON,
96	DM_STA_DIG_MAX
97};
98
99enum dm_dig_connect {
100	DIG_STA_DISCONNECT = 0,
101	DIG_STA_CONNECT = 1,
102	DIG_STA_BEFORE_CONNECT = 2,
103	DIG_AP_DISCONNECT = 3,
104	DIG_AP_CONNECT = 4,
105	DIG_AP_ADD_STATION = 5,
106	DIG_CONNECT_MAX
107};
108
109enum dm_dig_ext_port_alg {
110	DIG_EXT_PORT_STAGE_0 = 0,
111	DIG_EXT_PORT_STAGE_1 = 1,
112	DIG_EXT_PORT_STAGE_2 = 2,
113	DIG_EXT_PORT_STAGE_3 = 3,
114	DIG_EXT_PORT_STAGE_MAX = 4,
115};
116
117enum dm_ratr_sta {
118	DM_RATR_STA_HIGH = 0,
119	DM_RATR_STA_MIDDLEHIGH = 1,
120	DM_RATR_STA_MIDDLE = 2,
121	DM_RATR_STA_MIDDLELOW = 3,
122	DM_RATR_STA_LOW = 4,
123	DM_RATR_STA_ULTRALOW = 5,
124	DM_RATR_STA_MAX
125};
126
127#define DM_TYPE_BYFW			0
128#define DM_TYPE_BYDRIVER		1
129
130#define	TX_HIGH_PWR_LEVEL_NORMAL	0
131#define	TX_HIGH_PWR_LEVEL_LEVEL1	1
132#define	TX_HIGH_PWR_LEVEL_LEVEL2	2
133
134#define	HAL_DM_DIG_DISABLE		BIT(0)	/* Disable Dig */
135#define	HAL_DM_HIPWR_DISABLE		BIT(1)	/* Disable High Power */
136
137#define	TX_HIGHPWR_LEVEL_NORMAL		0
138#define	TX_HIGHPWR_LEVEL_NORMAL1	1
139#define	TX_HIGHPWR_LEVEL_NORMAL2	2
140
141#define	TX_POWER_NEAR_FIELD_THRESH_LVL2	74
142#define	TX_POWER_NEAR_FIELD_THRESH_LVL1	67
143
144#define DM_DIG_THRESH_HIGH		40
145#define DM_DIG_THRESH_LOW		35
146#define	DM_FALSEALARM_THRESH_LOW	40
147#define	DM_FALSEALARM_THRESH_HIGH	1000
148#define	DM_DIG_HIGH_PWR_THRESH_HIGH	75
149#define	DM_DIG_HIGH_PWR_THRESH_LOW	70
150#define	DM_DIG_BACKOFF			12
151#define	DM_DIG_MAX			0x3e
152#define	DM_DIG_MIN			0x1c
153#define	DM_DIG_MIN_Netcore		0x12
154#define	DM_DIG_BACKOFF_MAX		12
155#define	DM_DIG_BACKOFF_MIN		-4
156
157extern struct dig_t digtable;
158
159void rtl92s_dm_watchdog(struct ieee80211_hw *hw);
160void rtl92s_dm_init(struct ieee80211_hw *hw);
161void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw);
162
163#endif
164
165