12f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo/* 280301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valo * This file is part of wl1251 32f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 42f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Copyright (c) 1998-2007 Texas Instruments Incorporated 52f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Copyright (C) 2008 Nokia Corporation 62f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 72f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * This program is free software; you can redistribute it and/or 82f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * modify it under the terms of the GNU General Public License 92f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * version 2 as published by the Free Software Foundation. 102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * This program is distributed in the hope that it will be useful, but 122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * General Public License for more details. 152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * You should have received a copy of the GNU General Public License 172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * along with this program; if not, write to the Free Software 182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 02110-1301 USA 202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 2380301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valo#ifndef __WL1251_ACX_H__ 2480301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valo#define __WL1251_ACX_H__ 252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 261367411858d5fc60b632a3f488f2b4adc73d12d7Kalle Valo#include "wl1251.h" 279bc6772e15d25f58c1be638031280e04514287d4Kalle Valo#include "cmd.h" 282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo/* Target's information element */ 302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_header { 3180301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valo struct wl1251_cmd_header cmd; 32ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valo 33ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valo /* acx (or information element) header */ 342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 id; 35ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valo 36ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valo /* payload length (not including headers */ 372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 len; 388d5ad08525f1a8e0484d125ba155dbd3c3282ab8Grazvydas Ignotas} __packed; 392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_error_counter { 412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* The number of PLCP errors since the last time this */ 442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* information element was interrogated. This field is */ 452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* automatically cleared when it is interrogated.*/ 462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 PLCP_error; 472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* The number of FCS errors since the last time this */ 492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* information element was interrogated. This field is */ 502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* automatically cleared when it is interrogated.*/ 512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 FCS_error; 522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* The number of MPDUs without PLCP header errors received*/ 542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* since the last time this information element was interrogated. */ 552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* This field is automatically cleared when it is interrogated.*/ 562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 valid_frame; 572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the number of missed sequence numbers in the squentially */ 592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* values of frames seq numbers */ 602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 seq_num_miss; 61ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_revision { 642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The WiLink firmware version, an ASCII string x.x.x.x, 682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * that uniquely identifies the current firmware. 692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The left most digit is incremented each time a 702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * significant change is made to the firmware, such as 712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * code redesign or new platform support. 722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The second digit is incremented when major enhancements 732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * are added or major fixes are made. 742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The third digit is incremented for each GA release. 752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The fourth digit is incremented for each build. 762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The first two digits identify a firmware release version, 772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * in other words, a unique set of features. 782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The first three digits identify a GA release. 792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo char fw_version[20]; 812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * This 4 byte field specifies the WiLink hardware version. 842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * bits 0 - 15: Reserved. 852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * bits 16 - 23: Version ID - The WiLink version ID 862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * (1 = first spin, 2 = second spin, and so on). 872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * bits 24 - 31: Chip ID - The WiLink chip ID. 882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 hw_version; 90ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9280301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoenum wl1251_psm_mode { 932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Active mode */ 9480301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valo WL1251_PSM_CAM = 0, 952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Power save mode */ 9780301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valo WL1251_PSM_PS = 1, 982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Extreme low power */ 10080301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valo WL1251_PSM_ELP = 2, 1012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 1022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_sleep_auth { 1042f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 1052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* The sleep level authorization of the device. */ 1072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 0 - Always active*/ 1082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 1 - Power down mode: light / fast sleep*/ 1092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 2 - ELP mode: Deep / Max sleep*/ 1102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 sleep_auth; 1112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 padding[3]; 112ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 1132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valoenum { 1152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo HOSTIF_PCI_MASTER_HOST_INDIRECT, 1162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo HOSTIF_PCI_MASTER_HOST_DIRECT, 1172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo HOSTIF_SLAVE, 1182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo HOSTIF_PKT_RING, 1192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo HOSTIF_DONTCARE = 0xFF 1202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 1212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DEFAULT_UCAST_PRIORITY 0 1232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DEFAULT_RX_Q_PRIORITY 0 1242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DEFAULT_NUM_STATIONS 1 1252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ 1262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ 1272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define TRACE_BUFFER_MAX_SIZE 256 1282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DP_RX_PACKET_RING_CHUNK_SIZE 1600 1302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DP_TX_PACKET_RING_CHUNK_SIZE 1600 1312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DP_RX_PACKET_RING_CHUNK_NUM 2 1322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DP_TX_PACKET_RING_CHUNK_NUM 2 1332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define DP_TX_COMPLETE_TIME_OUT 20 1342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define FW_TX_CMPLT_BLOCK_SIZE 16 1352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_data_path_params { 1372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 1382f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 rx_packet_ring_chunk_size; 1402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 tx_packet_ring_chunk_size; 1412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 rx_packet_ring_chunk_num; 1432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_packet_ring_chunk_num; 1442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 1462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Maximum number of packets that can be gathered 1472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * in the TX complete ring before an interrupt 1482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * is generated. 1492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 1502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_complete_threshold; 1512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Number of pending TX complete entries in cyclic ring.*/ 1532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_complete_ring_depth; 1542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 1562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Max num microseconds since a packet enters the TX 1572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * complete ring until an interrupt is generated. 1582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 1592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_complete_timeout; 160ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 1612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_data_path_params_resp { 1642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 1652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 rx_packet_ring_chunk_size; 1672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 tx_packet_ring_chunk_size; 1682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 rx_packet_ring_chunk_num; 1702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_packet_ring_chunk_num; 1712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[2]; 1732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_packet_ring_addr; 1752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_packet_ring_addr; 1762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_control_addr; 1782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_control_addr; 1792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_complete_addr; 181ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 1822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define TX_MSDU_LIFETIME_MIN 0 1842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define TX_MSDU_LIFETIME_MAX 3000 1852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define TX_MSDU_LIFETIME_DEF 512 1862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_MSDU_LIFETIME_MIN 0 1872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF 1882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_MSDU_LIFETIME_DEF 512000 1892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 190ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valostruct acx_rx_msdu_lifetime { 1912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 1922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 1932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 1942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The maximum amount of time, in TU, before the 1952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * firmware discards the MSDU. 1962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 1972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 lifetime; 198ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 1992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 2002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo/* 2012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * RX Config Options Table 2022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Bit Definition 2032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * === ========== 2042f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 31:14 Reserved 2052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 13 Copy RX Status - when set, write three receive status words 2062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * to top of rx'd MPDUs. 2072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When cleared, do not write three status words (added rev 1.5) 2082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 12 Reserved 2092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 11 RX Complete upon FCS error - when set, give rx complete 2102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * interrupt for FCS errors, after the rx filtering, e.g. unicast 2112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * frames not to us with FCS error will not generate an interrupt. 2122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 10 SSID Filter Enable - When set, the WiLink discards all beacon, 2132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * probe request, and probe response frames with an SSID that does 2142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * not match the SSID specified by the host in the START/JOIN 2152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * command. 2162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, the WiLink receives frames with any SSID. 2172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 9 Broadcast Filter Enable - When set, the WiLink discards all 2182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * broadcast frames. When clear, the WiLink receives all received 2192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * broadcast frames. 2202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 8:6 Reserved 2212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 5 BSSID Filter Enable - When set, the WiLink discards any frames 2222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * with a BSSID that does not match the BSSID specified by the 2232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * host. 2242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, the WiLink receives frames from any BSSID. 2252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 4 MAC Addr Filter - When set, the WiLink discards any frames 2262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * with a destination address that does not match the MAC address 2272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * of the adaptor. 2282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, the WiLink receives frames destined to any MAC 2292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * address. 2302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 3 Promiscuous - When set, the WiLink receives all valid frames 2312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * (i.e., all frames that pass the FCS check). 2322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, only frames that pass the other filters specified 2332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * are received. 2342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 2 FCS - When set, the WiLink includes the FCS with the received 2352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * frame. 2362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When cleared, the FCS is discarded. 2372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 1 PLCP header - When set, write all data from baseband to frame 2382f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * buffer including PHY header. 2392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 0 Reserved - Always equal to 0. 2402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 2412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * RX Filter Options Table 2422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Bit Definition 2432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * === ========== 2442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 31:12 Reserved - Always equal to 0. 2452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 11 Association - When set, the WiLink receives all association 2462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * related frames (association request/response, reassocation 2472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * request/response, and disassociation). When clear, these frames 2482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * are discarded. 2492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 10 Auth/De auth - When set, the WiLink receives all authentication 2502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * and de-authentication frames. When clear, these frames are 2512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * discarded. 2522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 9 Beacon - When set, the WiLink receives all beacon frames. 2532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 8 Contention Free - When set, the WiLink receives all contention 2552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * free frames. 2562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 7 Control - When set, the WiLink receives all control frames. 2582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 6 Data - When set, the WiLink receives all data frames. 2602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 5 FCS Error - When set, the WiLink receives frames that have FCS 2622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * errors. 2632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 4 Management - When set, the WiLink receives all management 2652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * frames. 2662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 3 Probe Request - When set, the WiLink receives all probe request 2682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * frames. 2692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 2 Probe Response - When set, the WiLink receives all probe 2712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * response frames. 2722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK 2742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * frames. 2752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames 2772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * that have reserved frame types and sub types as defined by the 2782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 802.11 specification. 2792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When clear, these frames are discarded. 2802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 2812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_rx_config { 2822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 2832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 2842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 config_options; 2852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 filter_options; 286ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 2872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 2882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valoenum { 2892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo QOS_AC_BE = 0, 2902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo QOS_AC_BK, 2912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo QOS_AC_VI, 2922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo QOS_AC_VO, 2932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo QOS_HIGHEST_AC_INDEX = QOS_AC_VO, 2942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 2952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 2962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define MAX_NUM_OF_AC (QOS_HIGHEST_AC_INDEX+1) 2972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define FIRST_AC_INDEX QOS_AC_BE 2982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define MAX_NUM_OF_802_1d_TAGS 8 2992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define AC_PARAMS_MAX_TSID 15 3002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define MAX_APSD_CONF 0xffff 3012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_HIGH_MIN (0) 3032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_HIGH_MAX (100) 3042f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_HIGH_BK_DEF (25) 3062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_HIGH_BE_DEF (35) 3072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_HIGH_VI_DEF (35) 3082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_HIGH_VO_DEF (35) 3092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_LOW_BK_DEF (15) 3112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_LOW_BE_DEF (25) 3122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_LOW_VI_DEF (25) 3132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define QOS_TX_LOW_VO_DEF (25) 3142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_tx_queue_qos_config { 3162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 3172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 qid; 3192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[3]; 3202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Max number of blocks allowd in the queue */ 3222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 high_threshold; 3232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Lowest memory blocks guaranteed for this queue */ 3252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 low_threshold; 326ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 3272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_packet_detection { 3292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 3302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 threshold; 332ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 3332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valoenum acx_slot_type { 3362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo SLOT_TIME_LONG = 0, 3372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo SLOT_TIME_SHORT = 1, 3382f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, 3392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo MAX_SLOT_TIMES = 0xFF 3402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 3412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define STATION_WONE_INDEX 0 3432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_slot { 3452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 3462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 wone_index; /* Reserved */ 3482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 slot_time; 3492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 reserved[6]; 350ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 3512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define ADDRESS_GROUP_MAX (8) 3542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ADDRESS_GROUP_MAX) 3552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 356ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valostruct acx_dot11_grp_addr_tbl { 3572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 3582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 enabled; 3602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 num_groups; 3612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[2]; 3622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 mac_table[ADDRESS_GROUP_MAX_LEN]; 363ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 3642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_TIMEOUT_PS_POLL_MIN 0 3672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_TIMEOUT_PS_POLL_MAX (200000) 3682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_TIMEOUT_PS_POLL_DEF (15) 3692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_TIMEOUT_UPSD_MIN 0 3702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_TIMEOUT_UPSD_MAX (200000) 3712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_TIMEOUT_UPSD_DEF (15) 3722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_rx_timeout { 3742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 3752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 3772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The longest time the STA will wait to receive 3782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * traffic from the AP after a PS-poll has been 3792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * transmitted. 3802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 3812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 ps_poll_timeout; 3822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 3842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The longest time the STA will wait to receive 3852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * traffic from the AP after a frame has been sent 3862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * from an UPSD enabled queue. 3872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 3882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 upsd_timeout; 389ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 3902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RTS_THRESHOLD_MIN 0 3922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RTS_THRESHOLD_MAX 4096 3932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RTS_THRESHOLD_DEF 2347 3942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_rts_threshold { 3962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 3972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 3982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 threshold; 3992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[2]; 400ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 4012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 4028964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedtenum wl1251_acx_low_rssi_type { 4038964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt /* 4048964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * The event is a "Level" indication which keeps triggering 4058964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * as long as the average RSSI is below the threshold. 4068964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt */ 4078964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt WL1251_ACX_LOW_RSSI_TYPE_LEVEL = 0, 4088964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt 4098964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt /* 4108964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * The event is an "Edge" indication which triggers 4118964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * only when the RSSI threshold is crossed from above. 4128964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt */ 4138964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt WL1251_ACX_LOW_RSSI_TYPE_EDGE = 1, 4148964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt}; 4158964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt 4168964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedtstruct acx_low_rssi { 4178964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt struct acx_header header; 4188964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt 4198964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt /* 4208964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * The threshold (in dBm) below (or above after low rssi 4218964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * indication) which the firmware generates an interrupt to the 4228964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * host. This parameter is signed. 4238964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt */ 4248964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt s8 threshold; 4258964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt 4268964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt /* 4278964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * The weight of the current RSSI sample, before adding the new 4288964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * sample, that is used to calculate the average RSSI. 4298964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt */ 4308964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt u8 weight; 4318964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt 4328964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt /* 4338964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * The number of Beacons/Probe response frames that will be 4348964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * received before issuing the Low or Regained RSSI event. 4358964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt */ 4368964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt u8 depth; 4378964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt 4388964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt /* 4398964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * Configures how the Low RSSI Event is triggered. Refer to 4408964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt * enum wl1251_acx_low_rssi_type for more. 4418964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt */ 4428964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt u8 type; 4438964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt} __packed; 4448964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt 4452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_beacon_filter_option { 4462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 4472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 4482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 enable; 4492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 4502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 4512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The number of beacons without the unicast TIM 4522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * bit set that the firmware buffers before 4532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * signaling the host about ready frames. 4542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When set to 0 and the filter is enabled, beacons 4552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * without the unicast TIM bit set are dropped. 4562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 4572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 max_num_beacons; 4582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[2]; 459ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 4602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 4612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo/* 4622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * ACXBeaconFilterEntry (not 221) 4632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Byte Offset Size (Bytes) Definition 4642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * =========== ============ ========== 4652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 0 1 IE identifier 4662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 1 1 Treatment bit mask 4672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 4682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * ACXBeaconFilterEntry (221) 4692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Byte Offset Size (Bytes) Definition 4702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * =========== ============ ========== 4712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 0 1 IE identifier 4722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 1 1 Treatment bit mask 4732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 2 3 OUI 4742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 5 1 Type 4752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 6 2 Version 4762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 4772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 4782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Treatment bit mask - The information element handling: 4792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * bit 0 - The information element is compared and transferred 4802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * in case of change. 4812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * bit 1 - The information element is transferred to the host 4822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * with each appearance or disappearance. 4832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Note that both bits can be set at the same time. 4842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 4852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define BEACON_FILTER_TABLE_MAX_IE_NUM (32) 4862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) 4872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) 4882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) 4892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ 4902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ 4912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ 4922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) 4932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 4946b21a2cd315e2e56a1748bd3ef9d910fe4f2e711Juuso Oikarinen#define BEACON_RULE_PASS_ON_CHANGE BIT(0) 4956b21a2cd315e2e56a1748bd3ef9d910fe4f2e711Juuso Oikarinen#define BEACON_RULE_PASS_ON_APPEARANCE BIT(1) 4966b21a2cd315e2e56a1748bd3ef9d910fe4f2e711Juuso Oikarinen 4976b21a2cd315e2e56a1748bd3ef9d910fe4f2e711Juuso Oikarinen#define BEACON_FILTER_IE_ID_CHANNEL_SWITCH_ANN (37) 4986b21a2cd315e2e56a1748bd3ef9d910fe4f2e711Juuso Oikarinen 4992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_beacon_filter_ie_table { 5002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 5012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 num_ie; 5032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[3]; 5045b44a1b5164c69cb274215fc79a9f4f5a1203c4dGrazvydas Ignotas u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; 505ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 5062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 50733d51facad8360cb9c55fd696431e2a477f16cc1Vidhya Govindan#define SYNCH_FAIL_DEFAULT_THRESHOLD 10 /* number of beacons */ 50833d51facad8360cb9c55fd696431e2a477f16cc1Vidhya Govindan#define NO_BEACON_DEFAULT_TIMEOUT (500) /* in microseconds */ 509474c48c9f2118e637477b3b1c70003cb5cbda983Juuso Oikarinen 510474c48c9f2118e637477b3b1c70003cb5cbda983Juuso Oikarinenstruct acx_conn_monit_params { 511474c48c9f2118e637477b3b1c70003cb5cbda983Juuso Oikarinen struct acx_header header; 512474c48c9f2118e637477b3b1c70003cb5cbda983Juuso Oikarinen 513474c48c9f2118e637477b3b1c70003cb5cbda983Juuso Oikarinen u32 synch_fail_thold; /* number of beacons missed */ 514474c48c9f2118e637477b3b1c70003cb5cbda983Juuso Oikarinen u32 bss_lose_timeout; /* number of TU's from synch fail */ 5158d5ad08525f1a8e0484d125ba155dbd3c3282ab8Grazvydas Ignotas} __packed; 516474c48c9f2118e637477b3b1c70003cb5cbda983Juuso Oikarinen 5172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valoenum { 5182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo SG_ENABLE = 0, 5192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo SG_DISABLE, 5202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo SG_SENSE_NO_ACTIVITY, 5212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo SG_SENSE_ACTIVE 5222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 5232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_bt_wlan_coex { 5252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 5262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 5282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 0 -> PTA enabled 5292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 1 -> PTA disabled 5302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 2 -> sense no active mode, i.e. 5312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * an interrupt is sent upon 5322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * BT activity. 5332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 3 -> PTA is switched on in response 5342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * to the interrupt sending. 5352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 5362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 enable; 5372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[3]; 538ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 5392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_ANTENNA_TYPE_DEF (0) 5412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_BT_HP_MAXTIME_DEF (2000) 5422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_WLAN_HP_MAX_TIME_DEF (5000) 5432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_SENSE_DISABLE_TIMER_DEF (1350) 5442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_PROTECTIVE_RX_TIME_DEF (1500) 5452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_PROTECTIVE_TX_TIME_DEF (1500) 5462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000) 5472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_SIGNALING_TYPE_DEF (1) 5482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_AFH_LEVERAGE_ON_DEF (0) 5492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_NUMBER_QUIET_CYCLE_DEF (0) 5502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_MAX_NUM_CTS_DEF (3) 5512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2) 5522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_NUMBER_OF_BT_PACKETS_DEF (2) 5532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500) 5542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000) 5552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_CYCLE_TIME_FAST_DEF (8700) 5562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_RX_FOR_AVALANCHE_DEF (5) 5572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_ELP_HP_DEF (0) 5582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_ANTI_STARVE_PERIOD_DEF (500) 5592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4) 5602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_ALLOW_PA_SD_DEF (1) 5612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_TIME_BEFORE_BEACON_DEF (6300) 5622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_HPDM_MAX_TIME_DEF (1600) 5632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_TIME_OUT_NEXT_WLAN_DEF (2550) 5642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_AUTO_MODE_NO_CTS_DEF (0) 5652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_BT_HP_RESPECTED_DEF (3) 5662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_WLAN_RX_MIN_RATE_DEF (24) 5672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define PTA_ACK_MODE_DEF (1) 5682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_bt_wlan_coex_param { 5702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 5712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 5732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The minimum rate of a received WLAN packet in the STA, 5742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * during protective mode, of which a new BT-HP request 5752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * during this Rx will always be respected and gain the antenna. 5762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 5772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 min_rate; 5782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Max time the BT HP will be respected. */ 5802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 bt_hp_max_time; 5812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Max time the WLAN HP will be respected. */ 5832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 wlan_hp_max_time; 5842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 5862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The time between the last BT activity 5872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * and the moment when the sense mode returns 5882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * to SENSE_INACTIVE. 5892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 5902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 sense_disable_timer; 5912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Time before the next BT HP instance */ 5932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 rx_time_bt_hp; 5942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 tx_time_bt_hp; 5952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 5962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range: 10-20000 default: 1500 */ 5972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 rx_time_bt_hp_fast; 5982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 tx_time_bt_hp_fast; 5992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range: 2000-65535 default: 8700 */ 6012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 wlan_cycle_fast; 6022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range: 0 - 15000 (Msec) default: 1000 */ 6042f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 bt_anti_starvation_period; 6052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range 400-10000(Usec) default: 3000 */ 6072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 next_bt_lp_packet; 6082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Deafult: worst case for BT DH5 traffic */ 6102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 wake_up_beacon; 6112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range: 0-50000(Usec) default: 1050 */ 6132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 hp_dm_max_guard_time; 6142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * This is to prevent both BT & WLAN antenna 6172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * starvation. 6182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Range: 100-50000(Usec) default:2550 6192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 next_wlan_packet; 6212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 0 -> shared antenna */ 6232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 antenna_type; 6242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 0 -> TI legacy 6272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 1 -> Palau 6282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 signal_type; 6302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * BT AFH status 6332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 0 -> no AFH 6342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 1 -> from dedicated GPIO 6352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * 2 -> AFH on (from host) 6362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 afh_leverage_on; 6382f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The number of cycles during which no 6412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * TX will be sent after 1 cycle of RX 6422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * transaction in protective mode 6432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 quiet_cycle_num; 6452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The maximum number of CTSs that will 6482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * be sent for receiving RX packet in 6492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * protective mode 6502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 max_cts; 6522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The number of WLAN packets 6552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * transferred in common mode before 6562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * switching to BT. 6572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 wlan_packets_num; 6592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The number of BT packets 6622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * transferred in common mode before 6632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * switching to WLAN. 6642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 bt_packets_num; 6662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range: 1-255 default: 5 */ 6682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 missed_rx_avalanche; 6692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range: 0-1 default: 1 */ 6712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 wlan_elp_hp; 6722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range: 0 - 15 default: 4 */ 6742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 bt_anti_starvation_cycles; 6752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 ack_mode_dual_ant; 6772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Allow PA_SD assertion/de-assertion 6802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * during enabled BT activity. 6812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pa_sd_enable; 6832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 6852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Enable/Disable PTA in auto mode: 6862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * Support Both Active & P.S modes 6872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 6882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pta_auto_mode_enable; 6892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* range: 0 - 20 default: 1 */ 6912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 bt_hp_respected_num; 692ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 6932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CCA_THRSH_ENABLE_ENERGY_D 0x140A 6952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CCA_THRSH_DISABLE_ENERGY_D 0xFFEF 6962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 6972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_energy_detection { 6982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 6992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* The RX Clear Channel Assessment threshold in the PHY */ 7012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 rx_cca_threshold; 7022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_energy_detection; 7032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad; 704ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 7052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define BCN_RX_TIMEOUT_DEF_VALUE 10000 7072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define BROADCAST_RX_TIMEOUT_DEF_VALUE 20000 7082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define RX_BROADCAST_IN_PS_DEF_VALUE 1 7092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CONSECUTIVE_PS_POLL_FAILURE_DEF 4 7102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_beacon_broadcast { 7122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 7132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 beacon_rx_timeout; 7152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 broadcast_timeout; 7162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Enables receiving of broadcast packets in PS mode */ 7182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 rx_broadcast_in_ps; 7192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Consecutive PS Poll failures before updating the host */ 7212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 ps_poll_threshold; 7222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[2]; 723ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 7242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_event_mask { 7262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 7272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 event_mask; 7292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 high_event_mask; /* Unused */ 730ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 7312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_FCS BIT(2) 7332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_ALL_GOOD BIT(3) 7342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_UNI_FILTER_EN BIT(4) 7352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_BSSID_FILTER_EN BIT(5) 7362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_MC_FILTER_EN BIT(6) 7372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_MC_ADDR0_EN BIT(7) 7382f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_MC_ADDR1_EN BIT(8) 7392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_BC_REJECT_EN BIT(9) 7402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_SSID_FILTER_EN BIT(10) 7412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_INT_FCS_ERROR BIT(11) 7422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_INT_ENCRYPTED BIT(12) 7432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_WR_RX_STATUS BIT(13) 7442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_FILTER_NULTI BIT(14) 7452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_RESERVE BIT(15) 7462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_TIMESTAMP_TSF BIT(16) 7472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_RSV_EN BIT(0) 7492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_RCTS_ACK BIT(1) 7502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_PRSP_EN BIT(2) 7512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_PREQ_EN BIT(3) 7522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_MGMT_EN BIT(4) 7532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_FCS_ERROR BIT(5) 7542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_DATA_EN BIT(6) 7552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_CTL_EN BIT(7) 7562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_CF_EN BIT(8) 7572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_BCN_EN BIT(9) 7582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_AUTH_EN BIT(10) 7592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define CFG_RX_ASSOC_EN BIT(11) 7602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define SCAN_PASSIVE BIT(0) 7622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define SCAN_5GHZ_BAND BIT(1) 7632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define SCAN_TRIGGERED BIT(2) 7642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define SCAN_PRIORITY_HIGH BIT(3) 7652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_fw_gen_frame_rates { 7672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 7682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_ctrl_frame_rate; /* RATE_* */ 7702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_ctrl_frame_mod; /* CCK_* or PBCC_* */ 7712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_mgt_frame_rate; 7722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 tx_mgt_frame_mod; 773ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 7742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo/* STA MAC */ 776ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valostruct acx_dot11_station_id { 7772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 7782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 mac[ETH_ALEN]; 7802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[2]; 781ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 7822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_feature_config { 7842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 7852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 options; 7872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 data_flow_options; 788ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 7892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_current_tx_power { 7912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 7922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 current_tx_power; 7942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 padding[3]; 795ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 7962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 7972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_dot11_default_key { 7982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 7992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 id; 8012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[3]; 802ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8042f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_tsf_info { 8052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 8062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 current_tsf_msb; 8082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 current_tsf_lsb; 8092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 last_TBTT_msb; 8102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 last_TBTT_lsb; 8112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 last_dtim_count; 8122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[3]; 813ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valoenum acx_wake_up_event { 8162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo WAKE_UP_EVENT_BEACON_BITMAP = 0x01, /* Wake on every Beacon*/ 8172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo WAKE_UP_EVENT_DTIM_BITMAP = 0x02, /* Wake on every DTIM*/ 8182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo WAKE_UP_EVENT_N_DTIM_BITMAP = 0x04, /* Wake on every Nth DTIM */ 8192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo WAKE_UP_EVENT_N_BEACONS_BITMAP = 0x08, /* Wake on every Nth Beacon */ 8202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo WAKE_UP_EVENT_BITS_MASK = 0x0F 8212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 8222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_wake_up_condition { 8242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 8252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 wake_up_event; /* Only one bit can be set */ 8272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 listen_interval; 8282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[2]; 829ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_aid { 8322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 8332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 8352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * To be set when associated with an AP. 8362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 8372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 aid; 8382f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 pad[2]; 839ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valoenum acx_preamble_type { 8422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_PREAMBLE_LONG = 0, 8432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_PREAMBLE_SHORT = 1 8442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 8452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_preamble { 8472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 848ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valo 8492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 8502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * When set, the WiLink transmits the frames with a short preamble and 8512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * when cleared, the WiLink transmits the frames with a long preamble. 8522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 8532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 preamble; 8542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 padding[3]; 855ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valoenum acx_ctsprotect_type { 8582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo CTSPROTECT_DISABLE = 0, 8592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo CTSPROTECT_ENABLE = 1 8602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 8612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_ctsprotect { 8632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 8642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 ctsprotect; 8652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 padding[3]; 866ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_tx_statistics { 8692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 internal_desc_overflow; 870ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_rx_statistics { 8732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 out_of_mem; 8742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 hdr_overflow; 8752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 hw_stuck; 8762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 dropped; 8772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 fcs_err; 8782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 xfr_hint_trig; 8792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 path_reset; 8802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 reset_counter; 881ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_dma_statistics { 8842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_requested; 8852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_errors; 8862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_requested; 8872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_errors; 888ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 8892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_isr_statistics { 8912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* host command complete */ 8922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 cmd_cmplt; 8932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* fiqisr() */ 8952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 fiqs; 8962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 8972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_RX_HEADER) */ 8982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_headers; 8992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */ 9012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_completes; 9022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */ 9042f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_mem_overflow; 9052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */ 9072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_rdys; 9082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* irqisr() */ 9102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 irqs; 9112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_TX_PROC) */ 9132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_procs; 9142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */ 9162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 decrypt_done; 9172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_DMA0) */ 9192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 dma0_done; 9202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_DMA1) */ 9222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 dma1_done; 9232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */ 9252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_exch_complete; 9262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_COMMAND) */ 9282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 commands; 9292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_RX_PROC) */ 9312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_procs; 9322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_PM_802) */ 9342f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 hw_pm_mode_changes; 9352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */ 9372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 host_acknowledges; 9382f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_PM_PCI) */ 9402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 pci_pm; 9412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */ 9432f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 wakeups; 9442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */ 9462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 low_rssi; 947ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 9482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_wep_statistics { 9502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* WEP address keys configured */ 9512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 addr_key_count; 9522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* default keys configured */ 9542f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 default_key_count; 9552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 reserved; 9572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* number of times that WEP key not found on lookup */ 9592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 key_not_found; 9602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* number of times that WEP key decryption failed */ 9622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 decrypt_fail; 9632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* WEP packets decrypted */ 9652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 packets; 9662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* WEP decrypt interrupts */ 9682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 interrupt; 969ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 9702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#define ACX_MISSED_BEACONS_SPREAD 10 9722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_pwr_statistics { 9742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the amount of enters into power save mode (both PD & ELP) */ 9752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 ps_enter; 9762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the amount of enters into ELP mode */ 9782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 elp_enter; 9792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the amount of missing beacon interrupts to the host */ 9812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 missing_bcns; 9822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the amount of wake on host-access times */ 9842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 wake_on_host; 9852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the amount of wake on timer-expire */ 9872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 wake_on_timer_exp; 9882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the number of packets that were transmitted with PS bit set */ 9902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_with_ps; 9912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the number of packets that were transmitted with PS bit clear */ 9932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_without_ps; 9942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the number of received beacons */ 9962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rcvd_beacons; 9972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 9982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the number of entering into PowerOn (power save off) */ 9992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 power_save_off; 10002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the number of entries into power save mode */ 10022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 enable_ps; 10032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10042f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 10052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * the number of exits from power save, not including failed PS 10062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * transitions 10072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 10082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u16 disable_ps; 10092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* 10112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * the number of times the TSF counter was adjusted because 10122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * of drift 10132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 10142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 fix_tsf_ps; 10152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* Gives statistics about the spread continuous missed beacons. 10172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The 16 LSB are dedicated for the PS mode. 10182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * The 16 MSB are dedicated for the PS mode. 10192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * cont_miss_bcns_spread[0] - single missed beacon. 10202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * cont_miss_bcns_spread[1] - two continuous missed beacons. 10212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * cont_miss_bcns_spread[2] - three continuous missed beacons. 10222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * ... 10232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo * cont_miss_bcns_spread[9] - ten and more continuous missed beacons. 10242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo */ 10252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD]; 10262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo /* the number of beacons in awake mode */ 10282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rcvd_awake_beacons; 1029ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 10302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_mic_statistics { 10322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_pkts; 10332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 calc_failure; 1034ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 10352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10362f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_aes_statistics { 10372f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 encrypt_fail; 10382f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 decrypt_fail; 10392f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 encrypt_packets; 10402f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 decrypt_packets; 10412f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 encrypt_interrupt; 10422f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 decrypt_interrupt; 1043ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 10442f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10452f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_event_statistics { 10462f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 heart_beat; 10472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 calibration; 10482f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_mismatch; 10492f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_mem_empty; 10502f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_pool; 10512f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 oom_late; 10522f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 phy_transmit_error; 10532f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_stuck; 1054ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 10552f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10562f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_ps_statistics { 10572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 pspoll_timeouts; 10582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 upsd_timeouts; 10592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 upsd_max_sptime; 10602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 upsd_max_apturn; 10612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 pspoll_max_apturn; 10622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 pspoll_utilization; 10632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 upsd_utilization; 1064ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 10652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_rxpipe_statistics { 10672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 rx_prep_beacon_drop; 10682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 descr_host_int_trig_rx_data; 10692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 beacon_buffer_thres_host_int_trig_rx_data; 10702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 missed_beacon_host_int_trig_rx_data; 10712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u32 tx_xfr_host_int_trig_rx_data; 1072ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 10732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valostruct acx_statistics { 10752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_header header; 10762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_tx_statistics tx; 10782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_rx_statistics rx; 10792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_dma_statistics dma; 10802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_isr_statistics isr; 10812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_wep_statistics wep; 10822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_pwr_statistics pwr; 10832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_aes_statistics aes; 10842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_mic_statistics mic; 10852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_event_statistics event; 10862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_ps_statistics ps; 10872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_rxpipe_statistics rxpipe; 1088ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 10892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 10900e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_MAX_RATE_CLASSES 8 10910e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_RATE_MASK_UNSPECIFIED 0 10920e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_RATE_RETRY_LIMIT 10 10930e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 10940e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valostruct acx_rate_class { 10950e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u32 enabled_rates; 10960e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 short_retry_limit; 10970e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 long_retry_limit; 10980e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 aflags; 10990e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 reserved; 11008d5ad08525f1a8e0484d125ba155dbd3c3282ab8Grazvydas Ignotas} __packed; 11010e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11020e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valostruct acx_rate_policy { 11030e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo struct acx_header header; 11040e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11050e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u32 rate_class_cnt; 11060e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES]; 1107ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 11080e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11090e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valostruct wl1251_acx_memory { 11100e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo __le16 num_stations; /* number of STAs to be supported. */ 11110e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u16 reserved_1; 11120e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11130e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo /* 11140e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo * Nmber of memory buffers for the RX mem pool. 11150e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo * The actual number may be less if there are 11160e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo * not enough blocks left for the minimum num 11170e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo * of TX ones. 11180e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo */ 11190e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 rx_mem_block_num; 11200e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 reserved_2; 11210e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 num_tx_queues; /* From 1 to 16 */ 11220e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 host_if_options; /* HOST_IF* */ 11230e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 tx_min_mem_block_num; 11240e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 num_ssid_profiles; 11250e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo __le16 debug_buffer_size; 1126ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 11270e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11280e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11290e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_RX_DESC_MIN 1 11300e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_RX_DESC_MAX 127 11310e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_RX_DESC_DEF 32 11320e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valostruct wl1251_acx_rx_queue_config { 11330e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 num_descs; 11340e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 pad; 11350e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 type; 11360e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 priority; 11370e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo __le32 dma_address; 1138ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 11390e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11400e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_TX_DESC_MIN 1 11410e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_TX_DESC_MAX 127 11420e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define ACX_TX_DESC_DEF 16 11430e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valostruct wl1251_acx_tx_queue_config { 11440e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 num_descs; 11450e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 pad[2]; 11460e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u8 attributes; 1147ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 11480e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11490e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define MAX_TX_QUEUE_CONFIGS 5 11500e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define MAX_TX_QUEUES 4 11510e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valostruct wl1251_acx_config_memory { 11520e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo struct acx_header header; 11530e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11540e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo struct wl1251_acx_memory mem_config; 11550e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo struct wl1251_acx_rx_queue_config rx_queue_config; 11560e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS]; 1157ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 11580e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11590e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valostruct wl1251_acx_mem_map { 11600e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo struct acx_header header; 11610e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11620e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *code_start; 11630e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *code_end; 11640e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11650e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *wep_defkey_start; 11660e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *wep_defkey_end; 11670e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11680e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *sta_table_start; 11690e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *sta_table_end; 11700e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11710e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *packet_template_start; 11720e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *packet_template_end; 11730e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11740e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *queue_memory_start; 11750e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *queue_memory_end; 11760e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11770e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *packet_memory_pool_start; 11780e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *packet_memory_pool_end; 11790e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11800e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *debug_buffer1_start; 11810e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *debug_buffer1_end; 11820e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11830e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *debug_buffer2_start; 11840e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo void *debug_buffer2_end; 11850e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11860e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo /* Number of blocks FW allocated for TX packets */ 11870e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u32 num_tx_mem_blocks; 11880e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 11890e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo /* Number of blocks FW allocated for RX packets */ 11900e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo u32 num_rx_mem_blocks; 1191ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 11920e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 1193d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan 1194d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindanstruct wl1251_acx_wr_tbtt_and_dtim { 1195d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan 1196d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan struct acx_header header; 1197d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan 1198d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan /* Time in TUs between two consecutive beacons */ 1199d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan u16 tbtt; 1200d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan 1201d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan /* 1202d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan * DTIM period 1203d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan * For BSS: Number of TBTTs in a DTIM period (range: 1-10) 1204d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan * For IBSS: value shall be set to 1 1205d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan */ 1206d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan u8 dtim; 1207d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan u8 padding; 1208ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 1209d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindan 1210c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedtenum wl1251_acx_bet_mode { 1211c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt WL1251_ACX_BET_DISABLE = 0, 1212c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt WL1251_ACX_BET_ENABLE = 1, 1213c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt}; 1214c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt 1215c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedtstruct wl1251_acx_bet_enable { 1216c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt struct acx_header header; 1217c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt 1218c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt /* 1219c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt * Specifies if beacon early termination procedure is enabled or 1220c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt * disabled, see enum wl1251_acx_bet_mode. 1221c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt */ 1222c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt u8 enable; 1223c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt 1224c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt /* 1225c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt * Specifies the maximum number of consecutive beacons that may be 1226c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt * early terminated. After this number is reached at least one full 1227c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt * beacon must be correctly received in FW before beacon ET 1228c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt * resumes. Range 0 - 255. 1229c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt */ 1230c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt u8 max_consecutive; 1231c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt 1232c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt u8 padding[2]; 1233c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt} __packed; 1234c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt 123586dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valostruct wl1251_acx_ac_cfg { 123686dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo struct acx_header header; 123786dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo 123886dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo /* 123986dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo * Access Category - The TX queue's access category 124086dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo * (refer to AccessCategory_enum) 124186dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo */ 124286dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo u8 ac; 124386dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo 124486dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo /* 124586dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo * The contention window minimum size (in slots) for 124686dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo * the access class. 124786dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo */ 124886dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo u8 cw_min; 124986dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo 125086dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo /* 125186dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo * The contention window maximum size (in slots) for 125286dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo * the access class. 125386dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo */ 125486dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo u16 cw_max; 125586dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo 125686dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo /* The AIF value (in slots) for the access class. */ 125786dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo u8 aifsn; 125886dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo 125986dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo u8 reserved; 126086dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo 126186dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo /* The TX Op Limit (in microseconds) for the access class. */ 126286dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo u16 txop_limit; 1263ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 126486dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo 126527336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 126627336f1c0cd68fb9ae45493321f0d6980144230eKalle Valoenum wl1251_acx_channel_type { 126727336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo CHANNEL_TYPE_DCF = 0, 126827336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo CHANNEL_TYPE_EDCF = 1, 126927336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo CHANNEL_TYPE_HCCA = 2, 127027336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo}; 127127336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 127227336f1c0cd68fb9ae45493321f0d6980144230eKalle Valoenum wl1251_acx_ps_scheme { 127327336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* regular ps: simple sending of packets */ 127427336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo WL1251_ACX_PS_SCHEME_LEGACY = 0, 127527336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 127627336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* sending a packet triggers a unscheduled apsd downstream */ 127727336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo WL1251_ACX_PS_SCHEME_UPSD_TRIGGER = 1, 127827336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 127927336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* a pspoll packet will be sent before every data packet */ 128027336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo WL1251_ACX_PS_SCHEME_LEGACY_PSPOLL = 2, 128127336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 128227336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* scheduled apsd mode */ 128327336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo WL1251_ACX_PS_SCHEME_SAPSD = 3, 128427336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo}; 128527336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 128627336f1c0cd68fb9ae45493321f0d6980144230eKalle Valoenum wl1251_acx_ack_policy { 128727336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo WL1251_ACX_ACK_POLICY_LEGACY = 0, 128827336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo WL1251_ACX_ACK_POLICY_NO_ACK = 1, 128927336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo WL1251_ACX_ACK_POLICY_BLOCK = 2, 129027336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo}; 129127336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 129227336f1c0cd68fb9ae45493321f0d6980144230eKalle Valostruct wl1251_acx_tid_cfg { 129327336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo struct acx_header header; 129427336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 129527336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* tx queue id number (0-7) */ 129627336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo u8 queue; 129727336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 129827336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* channel access type for the queue, enum wl1251_acx_channel_type */ 129927336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo u8 type; 130027336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 130127336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* EDCA: ac index (0-3), HCCA: traffic stream id (8-15) */ 130227336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo u8 tsid; 130327336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 130427336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* ps scheme of the specified queue, enum wl1251_acx_ps_scheme */ 130527336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo u8 ps_scheme; 130627336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 130727336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* the tx queue ack policy, enum wl1251_acx_ack_policy */ 130827336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo u8 ack_policy; 130927336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 131027336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo u8 padding[3]; 131127336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 131227336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo /* not supported */ 131327336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo u32 apsdconf[2]; 1314ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 131527336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo 13160e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/************************************************************************* 13170e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13180e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo Host Interrupt Register (WiLink -> Host) 13190e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13200e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo**************************************************************************/ 13210e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13220e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* RX packet is ready in Xfer buffer #0 */ 13230e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_RX0_DATA BIT(0) 13240e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13250e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* TX result(s) are in the TX complete buffer */ 13260e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_TX_RESULT BIT(1) 13270e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13280e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* OBSOLETE */ 13290e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_TX_XFR BIT(2) 13300e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13310e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* RX packet is ready in Xfer buffer #1 */ 13320e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_RX1_DATA BIT(3) 13330e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13340e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* Event was entered to Event MBOX #A */ 13350e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_EVENT_A BIT(4) 13360e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13370e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* Event was entered to Event MBOX #B */ 13380e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_EVENT_B BIT(5) 13390e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13400e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* OBSOLETE */ 13410e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6) 13420e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 1343e8a8b252fb37489f881957ab0f2f8ea9a2341dd1Stefan Weil/* Trace message on MBOX #A */ 13440e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_TRACE_A BIT(7) 13450e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 1346e8a8b252fb37489f881957ab0f2f8ea9a2341dd1Stefan Weil/* Trace message on MBOX #B */ 13470e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_TRACE_B BIT(8) 13480e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13490e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* Command processing completion */ 13500e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_CMD_COMPLETE BIT(9) 13510e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13520e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo/* Init sequence is done */ 13530e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_INIT_COMPLETE BIT(14) 13540e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13550e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo#define WL1251_ACX_INTR_ALL 0xFFFFFFFF 13560e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valo 13572f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valoenum { 13582f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_WAKE_UP_CONDITIONS = 0x0002, 13592f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_MEM_CFG = 0x0003, 13602f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_SLOT = 0x0004, 13612f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_QUEUE_HEAD = 0x0005, /* for MASTER mode only */ 13622f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_AC_CFG = 0x0007, 13632f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_MEM_MAP = 0x0008, 13642f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_AID = 0x000A, 13652f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_RADIO_PARAM = 0x000B, /* Not used */ 13662f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_CFG = 0x000C, /* Not used */ 13672f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_FW_REV = 0x000D, 13682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_MEDIUM_USAGE = 0x000F, 13692f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_RX_CFG = 0x0010, 13702f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */ 13712f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_BSS_IN_PS = 0x0012, /* for AP only */ 13722f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_STATISTICS = 0x0013, /* Debug API */ 13732f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_FEATURE_CFG = 0x0015, 13742f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_MISC_CFG = 0x0017, /* Not used */ 13752f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_TID_CFG = 0x001A, 13762f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_BEACON_FILTER_OPT = 0x001F, 13772f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_LOW_RSSI = 0x0020, 13782f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_NOISE_HIST = 0x0021, 13792f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_HDK_VERSION = 0x0022, /* ??? */ 13802f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_PD_THRESHOLD = 0x0023, 13812f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_DATA_PATH_PARAMS = 0x0024, /* WO */ 13822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_DATA_PATH_RESP_PARAMS = 0x0024, /* RO */ 13832f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_CCA_THRESHOLD = 0x0025, 13842f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_EVENT_MBOX_MASK = 0x0026, 13852f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#ifdef FW_RUNNING_AS_AP 13862f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_DTIM_PERIOD = 0x0027, /* for AP only */ 13872f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#else 13882f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_WR_TBTT_AND_DTIM = 0x0027, /* STA only */ 13892f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo#endif 13902f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_ACI_OPTION_CFG = 0x0029, /* OBSOLETE (for 1251)*/ 13912f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_GPIO_CFG = 0x002A, /* Not used */ 13922f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_GPIO_SET = 0x002B, /* Not used */ 13932f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_PM_CFG = 0x002C, /* To Be Documented */ 13942f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_CONN_MONIT_PARAMS = 0x002D, 13952f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_AVERAGE_RSSI = 0x002E, /* Not used */ 13962f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_CONS_TX_FAILURE = 0x002F, 13972f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_BCN_DTIM_OPTIONS = 0x0031, 13982f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_SG_ENABLE = 0x0032, 13992f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_SG_CFG = 0x0033, 14002f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_ANTENNA_DIVERSITY_CFG = 0x0035, /* To Be Documented */ 14012f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_LOW_SNR = 0x0037, /* To Be Documented */ 14022f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_BEACON_FILTER_TABLE = 0x0038, 14032f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_ARP_IP_FILTER = 0x0039, 14042f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_ROAMING_STATISTICS_TBL = 0x003B, 14052f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_RATE_POLICY = 0x003D, 14062f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_CTS_PROTECTION = 0x003E, 14072f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_SLEEP_AUTH = 0x003F, 14082f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_PREAMBLE_TYPE = 0x0040, 14092f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_ERROR_CNT = 0x0041, 14102f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_FW_GEN_FRAME_RATES = 0x0042, 14112f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_IBSS_FILTER = 0x0044, 14122f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_SERVICE_PERIOD_TIMEOUT = 0x0045, 14132f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_TSF_INFO = 0x0046, 14142f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_CONFIG_PS_WMM = 0x0049, 14152f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_ENABLE_RX_DATA_FILTER = 0x004A, 14162f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_SET_RX_DATA_FILTER = 0x004B, 14172f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_GET_DATA_FILTER_STATISTICS = 0x004C, 14182f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_POWER_LEVEL_TABLE = 0x004D, 14192f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo ACX_BET_ENABLE = 0x0050, 14202f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo DOT11_STATION_ID = 0x1001, 14212f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo DOT11_RX_MSDU_LIFE_TIME = 0x1004, 14222f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo DOT11_CUR_TX_PWR = 0x100D, 14232f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo DOT11_DEFAULT_KEY = 0x1010, 14242f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo DOT11_RX_DOT11_MODE = 0x1012, 14252f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo DOT11_RTS_THRESHOLD = 0x1013, 14262f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo DOT11_GROUP_ADDRESS_TBL = 0x1014, 14272f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 14282f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL, 14292f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 14302f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo MAX_IE = 0xFFFF 14312f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo}; 14322f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 14332f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 143480301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_frame_rates(struct wl1251 *wl, u8 ctrl_rate, u8 ctrl_mod, 14352f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo u8 mgt_rate, u8 mgt_mod); 143680301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_station_id(struct wl1251 *wl); 143780301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_default_key(struct wl1251 *wl, u8 key_id); 143880301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_wake_up_conditions(struct wl1251 *wl, u8 wake_up_event, 14399f483dc3d1b0b1695c8177c1dea2e721954b10fbLuciano Coelho u8 listen_interval); 144080301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_sleep_auth(struct wl1251 *wl, u8 sleep_auth); 144180301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_fw_version(struct wl1251 *wl, char *buf, size_t len); 144280301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_tx_power(struct wl1251 *wl, int power); 144380301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_feature_cfg(struct wl1251 *wl); 144480301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_mem_map(struct wl1251 *wl, 1445ff25839bf0c99e828c26864a24417a36a6b6a31eKalle Valo struct acx_header *mem_map, size_t len); 144680301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_data_path_params(struct wl1251 *wl, 14472f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo struct acx_data_path_params_resp *data_path); 144880301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_rx_msdu_life_time(struct wl1251 *wl, u32 life_time); 144980301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_rx_config(struct wl1251 *wl, u32 config, u32 filter); 145080301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_pd_threshold(struct wl1251 *wl); 145180301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_slot(struct wl1251 *wl, enum acx_slot_type slot_time); 145280301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_group_address_tbl(struct wl1251 *wl); 145380301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_service_period_timeout(struct wl1251 *wl); 145480301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_rts_threshold(struct wl1251 *wl, u16 rts_threshold); 14556b21a2cd315e2e56a1748bd3ef9d910fe4f2e711Juuso Oikarinenint wl1251_acx_beacon_filter_opt(struct wl1251 *wl, bool enable_filter); 145680301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_beacon_filter_table(struct wl1251 *wl); 1457474c48c9f2118e637477b3b1c70003cb5cbda983Juuso Oikarinenint wl1251_acx_conn_monit_params(struct wl1251 *wl); 145880301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_sg_enable(struct wl1251 *wl); 145980301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_sg_cfg(struct wl1251 *wl); 146080301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_cca_threshold(struct wl1251 *wl); 146180301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_bcn_dtim_options(struct wl1251 *wl); 146280301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_aid(struct wl1251 *wl, u16 aid); 146380301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_event_mbox_mask(struct wl1251 *wl, u32 event_mask); 14648964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedtint wl1251_acx_low_rssi(struct wl1251 *wl, s8 threshold, u8 weight, 14658964e492b5740dae0f4f68e08f4a9a45d4b57620David Gnedt u8 depth, enum wl1251_acx_low_rssi_type type); 146680301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_set_preamble(struct wl1251 *wl, enum acx_preamble_type preamble); 146780301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_cts_protect(struct wl1251 *wl, 14682f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo enum acx_ctsprotect_type ctsprotect); 146980301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_statistics(struct wl1251 *wl, struct acx_statistics *stats); 147080301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valoint wl1251_acx_tsf_info(struct wl1251 *wl, u64 *mactime); 14710e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valoint wl1251_acx_rate_policies(struct wl1251 *wl); 14720e71bb084adc4986b9a4be3581897f0ee703cbd5Kalle Valoint wl1251_acx_mem_cfg(struct wl1251 *wl); 1473d531cf303f765bf3477330e58fbeab75da668931Vidhya Govindanint wl1251_acx_wr_tbtt_and_dtim(struct wl1251 *wl, u16 tbtt, u8 dtim); 1474c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedtint wl1251_acx_bet_enable(struct wl1251 *wl, enum wl1251_acx_bet_mode mode, 1475c3e334d29484423e78009790a3d3fa78da8b43a1David Gnedt u8 max_consecutive); 147686dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valoint wl1251_acx_ac_cfg(struct wl1251 *wl, u8 ac, u8 cw_min, u16 cw_max, 147786dff7a7955f1e14c1f2c142312462fae70ea7e4Kalle Valo u8 aifs, u16 txop); 147827336f1c0cd68fb9ae45493321f0d6980144230eKalle Valoint wl1251_acx_tid_cfg(struct wl1251 *wl, u8 queue, 147927336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo enum wl1251_acx_channel_type type, 148027336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo u8 tsid, enum wl1251_acx_ps_scheme ps_scheme, 148127336f1c0cd68fb9ae45493321f0d6980144230eKalle Valo enum wl1251_acx_ack_policy ack_policy); 14822f01a1f58889fbfeb68b1bc1b52e4197f3333490Kalle Valo 148380301cdcfe44e3533175be23d7d52a9fc8c3fdb0Kalle Valo#endif /* __WL1251_ACX_H__ */ 1484