msi.c revision 0366f8f7137deb072991e4c50769c6da31f8940c
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/mm.h> 10#include <linux/irq.h> 11#include <linux/interrupt.h> 12#include <linux/init.h> 13#include <linux/ioport.h> 14#include <linux/smp_lock.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17 18#include <asm/errno.h> 19#include <asm/io.h> 20#include <asm/smp.h> 21 22#include "pci.h" 23#include "msi.h" 24 25static DEFINE_SPINLOCK(msi_lock); 26static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; 27static kmem_cache_t* msi_cachep; 28 29static int pci_msi_enable = 1; 30static int last_alloc_vector; 31static int nr_released_vectors; 32static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS; 33static int nr_msix_devices; 34 35#ifndef CONFIG_X86_IO_APIC 36int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1}; 37#endif 38 39static struct msi_ops *msi_ops; 40 41int 42msi_register(struct msi_ops *ops) 43{ 44 msi_ops = ops; 45 return 0; 46} 47 48static int msi_cache_init(void) 49{ 50 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), 51 0, SLAB_HWCACHE_ALIGN, NULL, NULL); 52 if (!msi_cachep) 53 return -ENOMEM; 54 55 return 0; 56} 57 58static void msi_set_mask_bit(unsigned int vector, int flag) 59{ 60 struct msi_desc *entry; 61 62 entry = (struct msi_desc *)msi_desc[vector]; 63 if (!entry || !entry->dev || !entry->mask_base) 64 return; 65 switch (entry->msi_attrib.type) { 66 case PCI_CAP_ID_MSI: 67 { 68 int pos; 69 u32 mask_bits; 70 71 pos = (long)entry->mask_base; 72 pci_read_config_dword(entry->dev, pos, &mask_bits); 73 mask_bits &= ~(1); 74 mask_bits |= flag; 75 pci_write_config_dword(entry->dev, pos, mask_bits); 76 break; 77 } 78 case PCI_CAP_ID_MSIX: 79 { 80 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 81 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 82 writel(flag, entry->mask_base + offset); 83 break; 84 } 85 default: 86 break; 87 } 88} 89 90static void read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) 91{ 92 switch(entry->msi_attrib.type) { 93 case PCI_CAP_ID_MSI: 94 { 95 struct pci_dev *dev = entry->dev; 96 int pos = entry->msi_attrib.pos; 97 u16 data; 98 99 pci_read_config_dword(dev, msi_lower_address_reg(pos), 100 &msg->address_lo); 101 if (entry->msi_attrib.is_64) { 102 pci_read_config_dword(dev, msi_upper_address_reg(pos), 103 &msg->address_hi); 104 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 105 } else { 106 msg->address_hi = 0; 107 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 108 } 109 msg->data = data; 110 break; 111 } 112 case PCI_CAP_ID_MSIX: 113 { 114 void __iomem *base; 115 base = entry->mask_base + 116 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 117 118 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 119 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 120 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 121 break; 122 } 123 default: 124 BUG(); 125 } 126} 127 128static void write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) 129{ 130 switch (entry->msi_attrib.type) { 131 case PCI_CAP_ID_MSI: 132 { 133 struct pci_dev *dev = entry->dev; 134 int pos = entry->msi_attrib.pos; 135 136 pci_write_config_dword(dev, msi_lower_address_reg(pos), 137 msg->address_lo); 138 if (entry->msi_attrib.is_64) { 139 pci_write_config_dword(dev, msi_upper_address_reg(pos), 140 msg->address_hi); 141 pci_write_config_word(dev, msi_data_reg(pos, 1), 142 msg->data); 143 } else { 144 pci_write_config_word(dev, msi_data_reg(pos, 0), 145 msg->data); 146 } 147 break; 148 } 149 case PCI_CAP_ID_MSIX: 150 { 151 void __iomem *base; 152 base = entry->mask_base + 153 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 154 155 writel(msg->address_lo, 156 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 157 writel(msg->address_hi, 158 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 159 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 160 break; 161 } 162 default: 163 BUG(); 164 } 165} 166 167#ifdef CONFIG_SMP 168static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask) 169{ 170 struct msi_desc *entry; 171 struct msi_msg msg; 172 unsigned int irq = vector; 173 unsigned int dest_cpu = first_cpu(cpu_mask); 174 175 entry = (struct msi_desc *)msi_desc[vector]; 176 if (!entry || !entry->dev) 177 return; 178 179 read_msi_msg(entry, &msg); 180 msi_ops->target(vector, dest_cpu, &msg.address_hi, &msg.address_lo); 181 write_msi_msg(entry, &msg); 182 set_native_irq_info(irq, cpu_mask); 183} 184#else 185#define set_msi_affinity NULL 186#endif /* CONFIG_SMP */ 187 188static void mask_MSI_irq(unsigned int vector) 189{ 190 msi_set_mask_bit(vector, 1); 191} 192 193static void unmask_MSI_irq(unsigned int vector) 194{ 195 msi_set_mask_bit(vector, 0); 196} 197 198static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector) 199{ 200 struct msi_desc *entry; 201 unsigned long flags; 202 203 spin_lock_irqsave(&msi_lock, flags); 204 entry = msi_desc[vector]; 205 if (!entry || !entry->dev) { 206 spin_unlock_irqrestore(&msi_lock, flags); 207 return 0; 208 } 209 entry->msi_attrib.state = 1; /* Mark it active */ 210 spin_unlock_irqrestore(&msi_lock, flags); 211 212 return 0; /* never anything pending */ 213} 214 215static unsigned int startup_msi_irq_w_maskbit(unsigned int vector) 216{ 217 startup_msi_irq_wo_maskbit(vector); 218 unmask_MSI_irq(vector); 219 return 0; /* never anything pending */ 220} 221 222static void shutdown_msi_irq(unsigned int vector) 223{ 224 struct msi_desc *entry; 225 unsigned long flags; 226 227 spin_lock_irqsave(&msi_lock, flags); 228 entry = msi_desc[vector]; 229 if (entry && entry->dev) 230 entry->msi_attrib.state = 0; /* Mark it not active */ 231 spin_unlock_irqrestore(&msi_lock, flags); 232} 233 234static void end_msi_irq_wo_maskbit(unsigned int vector) 235{ 236 move_native_irq(vector); 237 ack_APIC_irq(); 238} 239 240static void end_msi_irq_w_maskbit(unsigned int vector) 241{ 242 move_native_irq(vector); 243 unmask_MSI_irq(vector); 244 ack_APIC_irq(); 245} 246 247static void do_nothing(unsigned int vector) 248{ 249} 250 251/* 252 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices, 253 * which implement the MSI-X Capability Structure. 254 */ 255static struct hw_interrupt_type msix_irq_type = { 256 .typename = "PCI-MSI-X", 257 .startup = startup_msi_irq_w_maskbit, 258 .shutdown = shutdown_msi_irq, 259 .enable = unmask_MSI_irq, 260 .disable = mask_MSI_irq, 261 .ack = mask_MSI_irq, 262 .end = end_msi_irq_w_maskbit, 263 .set_affinity = set_msi_affinity 264}; 265 266/* 267 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, 268 * which implement the MSI Capability Structure with 269 * Mask-and-Pending Bits. 270 */ 271static struct hw_interrupt_type msi_irq_w_maskbit_type = { 272 .typename = "PCI-MSI", 273 .startup = startup_msi_irq_w_maskbit, 274 .shutdown = shutdown_msi_irq, 275 .enable = unmask_MSI_irq, 276 .disable = mask_MSI_irq, 277 .ack = mask_MSI_irq, 278 .end = end_msi_irq_w_maskbit, 279 .set_affinity = set_msi_affinity 280}; 281 282/* 283 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, 284 * which implement the MSI Capability Structure without 285 * Mask-and-Pending Bits. 286 */ 287static struct hw_interrupt_type msi_irq_wo_maskbit_type = { 288 .typename = "PCI-MSI", 289 .startup = startup_msi_irq_wo_maskbit, 290 .shutdown = shutdown_msi_irq, 291 .enable = do_nothing, 292 .disable = do_nothing, 293 .ack = do_nothing, 294 .end = end_msi_irq_wo_maskbit, 295 .set_affinity = set_msi_affinity 296}; 297 298static int msi_free_vector(struct pci_dev* dev, int vector, int reassign); 299static int assign_msi_vector(void) 300{ 301 static int new_vector_avail = 1; 302 int vector; 303 unsigned long flags; 304 305 /* 306 * msi_lock is provided to ensure that successful allocation of MSI 307 * vector is assigned unique among drivers. 308 */ 309 spin_lock_irqsave(&msi_lock, flags); 310 311 if (!new_vector_avail) { 312 int free_vector = 0; 313 314 /* 315 * vector_irq[] = -1 indicates that this specific vector is: 316 * - assigned for MSI (since MSI have no associated IRQ) or 317 * - assigned for legacy if less than 16, or 318 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping 319 * vector_irq[] = 0 indicates that this vector, previously 320 * assigned for MSI, is freed by hotplug removed operations. 321 * This vector will be reused for any subsequent hotplug added 322 * operations. 323 * vector_irq[] > 0 indicates that this vector is assigned for 324 * IOxAPIC IRQs. This vector and its value provides a 1-to-1 325 * vector-to-IOxAPIC IRQ mapping. 326 */ 327 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { 328 if (vector_irq[vector] != 0) 329 continue; 330 free_vector = vector; 331 if (!msi_desc[vector]) 332 break; 333 else 334 continue; 335 } 336 if (!free_vector) { 337 spin_unlock_irqrestore(&msi_lock, flags); 338 return -EBUSY; 339 } 340 vector_irq[free_vector] = -1; 341 nr_released_vectors--; 342 spin_unlock_irqrestore(&msi_lock, flags); 343 if (msi_desc[free_vector] != NULL) { 344 struct pci_dev *dev; 345 int tail; 346 347 /* free all linked vectors before re-assign */ 348 do { 349 spin_lock_irqsave(&msi_lock, flags); 350 dev = msi_desc[free_vector]->dev; 351 tail = msi_desc[free_vector]->link.tail; 352 spin_unlock_irqrestore(&msi_lock, flags); 353 msi_free_vector(dev, tail, 1); 354 } while (free_vector != tail); 355 } 356 357 return free_vector; 358 } 359 vector = assign_irq_vector(AUTO_ASSIGN); 360 last_alloc_vector = vector; 361 if (vector == LAST_DEVICE_VECTOR) 362 new_vector_avail = 0; 363 364 spin_unlock_irqrestore(&msi_lock, flags); 365 return vector; 366} 367 368static int get_new_vector(void) 369{ 370 int vector = assign_msi_vector(); 371 372 if (vector > 0) 373 set_intr_gate(vector, interrupt[vector]); 374 375 return vector; 376} 377 378static int msi_init(void) 379{ 380 static int status = -ENOMEM; 381 382 if (!status) 383 return status; 384 385 if (pci_msi_quirk) { 386 pci_msi_enable = 0; 387 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n"); 388 status = -EINVAL; 389 return status; 390 } 391 392 status = msi_arch_init(); 393 if (status < 0) { 394 pci_msi_enable = 0; 395 printk(KERN_WARNING 396 "PCI: MSI arch init failed. MSI disabled.\n"); 397 return status; 398 } 399 400 if (! msi_ops) { 401 printk(KERN_WARNING 402 "PCI: MSI ops not registered. MSI disabled.\n"); 403 status = -EINVAL; 404 return status; 405 } 406 407 last_alloc_vector = assign_irq_vector(AUTO_ASSIGN); 408 status = msi_cache_init(); 409 if (status < 0) { 410 pci_msi_enable = 0; 411 printk(KERN_WARNING "PCI: MSI cache init failed\n"); 412 return status; 413 } 414 415 if (last_alloc_vector < 0) { 416 pci_msi_enable = 0; 417 printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n"); 418 status = -EBUSY; 419 return status; 420 } 421 vector_irq[last_alloc_vector] = 0; 422 nr_released_vectors++; 423 424 return status; 425} 426 427static int get_msi_vector(struct pci_dev *dev) 428{ 429 return get_new_vector(); 430} 431 432static struct msi_desc* alloc_msi_entry(void) 433{ 434 struct msi_desc *entry; 435 436 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); 437 if (!entry) 438 return NULL; 439 440 entry->link.tail = entry->link.head = 0; /* single message */ 441 entry->dev = NULL; 442 443 return entry; 444} 445 446static void attach_msi_entry(struct msi_desc *entry, int vector) 447{ 448 unsigned long flags; 449 450 spin_lock_irqsave(&msi_lock, flags); 451 msi_desc[vector] = entry; 452 spin_unlock_irqrestore(&msi_lock, flags); 453} 454 455static void irq_handler_init(int cap_id, int pos, int mask) 456{ 457 unsigned long flags; 458 459 spin_lock_irqsave(&irq_desc[pos].lock, flags); 460 if (cap_id == PCI_CAP_ID_MSIX) 461 irq_desc[pos].chip = &msix_irq_type; 462 else { 463 if (!mask) 464 irq_desc[pos].chip = &msi_irq_wo_maskbit_type; 465 else 466 irq_desc[pos].chip = &msi_irq_w_maskbit_type; 467 } 468 spin_unlock_irqrestore(&irq_desc[pos].lock, flags); 469} 470 471static void enable_msi_mode(struct pci_dev *dev, int pos, int type) 472{ 473 u16 control; 474 475 pci_read_config_word(dev, msi_control_reg(pos), &control); 476 if (type == PCI_CAP_ID_MSI) { 477 /* Set enabled bits to single MSI & enable MSI_enable bit */ 478 msi_enable(control, 1); 479 pci_write_config_word(dev, msi_control_reg(pos), control); 480 dev->msi_enabled = 1; 481 } else { 482 msix_enable(control); 483 pci_write_config_word(dev, msi_control_reg(pos), control); 484 dev->msix_enabled = 1; 485 } 486 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 487 /* PCI Express Endpoint device detected */ 488 pci_intx(dev, 0); /* disable intx */ 489 } 490} 491 492void disable_msi_mode(struct pci_dev *dev, int pos, int type) 493{ 494 u16 control; 495 496 pci_read_config_word(dev, msi_control_reg(pos), &control); 497 if (type == PCI_CAP_ID_MSI) { 498 /* Set enabled bits to single MSI & enable MSI_enable bit */ 499 msi_disable(control); 500 pci_write_config_word(dev, msi_control_reg(pos), control); 501 dev->msi_enabled = 0; 502 } else { 503 msix_disable(control); 504 pci_write_config_word(dev, msi_control_reg(pos), control); 505 dev->msix_enabled = 0; 506 } 507 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 508 /* PCI Express Endpoint device detected */ 509 pci_intx(dev, 1); /* enable intx */ 510 } 511} 512 513static int msi_lookup_vector(struct pci_dev *dev, int type) 514{ 515 int vector; 516 unsigned long flags; 517 518 spin_lock_irqsave(&msi_lock, flags); 519 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { 520 if (!msi_desc[vector] || msi_desc[vector]->dev != dev || 521 msi_desc[vector]->msi_attrib.type != type || 522 msi_desc[vector]->msi_attrib.default_vector != dev->irq) 523 continue; 524 spin_unlock_irqrestore(&msi_lock, flags); 525 /* This pre-assigned MSI vector for this device 526 already exits. Override dev->irq with this vector */ 527 dev->irq = vector; 528 return 0; 529 } 530 spin_unlock_irqrestore(&msi_lock, flags); 531 532 return -EACCES; 533} 534 535void pci_scan_msi_device(struct pci_dev *dev) 536{ 537 if (!dev) 538 return; 539 540 if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0) 541 nr_msix_devices++; 542 else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0) 543 nr_reserved_vectors++; 544} 545 546#ifdef CONFIG_PM 547int pci_save_msi_state(struct pci_dev *dev) 548{ 549 int pos, i = 0; 550 u16 control; 551 struct pci_cap_saved_state *save_state; 552 u32 *cap; 553 554 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 555 if (pos <= 0 || dev->no_msi) 556 return 0; 557 558 pci_read_config_word(dev, msi_control_reg(pos), &control); 559 if (!(control & PCI_MSI_FLAGS_ENABLE)) 560 return 0; 561 562 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, 563 GFP_KERNEL); 564 if (!save_state) { 565 printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); 566 return -ENOMEM; 567 } 568 cap = &save_state->data[0]; 569 570 pci_read_config_dword(dev, pos, &cap[i++]); 571 control = cap[0] >> 16; 572 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); 573 if (control & PCI_MSI_FLAGS_64BIT) { 574 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); 575 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); 576 } else 577 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); 578 if (control & PCI_MSI_FLAGS_MASKBIT) 579 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); 580 save_state->cap_nr = PCI_CAP_ID_MSI; 581 pci_add_saved_cap(dev, save_state); 582 return 0; 583} 584 585void pci_restore_msi_state(struct pci_dev *dev) 586{ 587 int i = 0, pos; 588 u16 control; 589 struct pci_cap_saved_state *save_state; 590 u32 *cap; 591 592 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); 593 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 594 if (!save_state || pos <= 0) 595 return; 596 cap = &save_state->data[0]; 597 598 control = cap[i++] >> 16; 599 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); 600 if (control & PCI_MSI_FLAGS_64BIT) { 601 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); 602 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); 603 } else 604 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); 605 if (control & PCI_MSI_FLAGS_MASKBIT) 606 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); 607 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 608 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 609 pci_remove_saved_cap(save_state); 610 kfree(save_state); 611} 612 613int pci_save_msix_state(struct pci_dev *dev) 614{ 615 int pos; 616 int temp; 617 int vector, head, tail = 0; 618 u16 control; 619 struct pci_cap_saved_state *save_state; 620 621 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 622 if (pos <= 0 || dev->no_msi) 623 return 0; 624 625 /* save the capability */ 626 pci_read_config_word(dev, msi_control_reg(pos), &control); 627 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 628 return 0; 629 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), 630 GFP_KERNEL); 631 if (!save_state) { 632 printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); 633 return -ENOMEM; 634 } 635 *((u16 *)&save_state->data[0]) = control; 636 637 /* save the table */ 638 temp = dev->irq; 639 if (msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 640 kfree(save_state); 641 return -EINVAL; 642 } 643 644 vector = head = dev->irq; 645 while (head != tail) { 646 struct msi_desc *entry; 647 648 entry = msi_desc[vector]; 649 read_msi_msg(entry, &entry->msg_save); 650 651 tail = msi_desc[vector]->link.tail; 652 vector = tail; 653 } 654 dev->irq = temp; 655 656 save_state->cap_nr = PCI_CAP_ID_MSIX; 657 pci_add_saved_cap(dev, save_state); 658 return 0; 659} 660 661void pci_restore_msix_state(struct pci_dev *dev) 662{ 663 u16 save; 664 int pos; 665 int vector, head, tail = 0; 666 struct msi_desc *entry; 667 int temp; 668 struct pci_cap_saved_state *save_state; 669 670 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); 671 if (!save_state) 672 return; 673 save = *((u16 *)&save_state->data[0]); 674 pci_remove_saved_cap(save_state); 675 kfree(save_state); 676 677 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 678 if (pos <= 0) 679 return; 680 681 /* route the table */ 682 temp = dev->irq; 683 if (msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) 684 return; 685 vector = head = dev->irq; 686 while (head != tail) { 687 entry = msi_desc[vector]; 688 write_msi_msg(entry, &entry->msg_save); 689 690 tail = msi_desc[vector]->link.tail; 691 vector = tail; 692 } 693 dev->irq = temp; 694 695 pci_write_config_word(dev, msi_control_reg(pos), save); 696 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 697} 698#endif 699 700static int msi_register_init(struct pci_dev *dev, struct msi_desc *entry) 701{ 702 int status; 703 struct msi_msg msg; 704 int pos, vector = dev->irq; 705 u16 control; 706 707 pos = entry->msi_attrib.pos; 708 pci_read_config_word(dev, msi_control_reg(pos), &control); 709 710 /* Configure MSI capability structure */ 711 status = msi_ops->setup(dev, vector, &msg.address_hi, &msg.address_lo, &msg.data); 712 if (status < 0) 713 return status; 714 715 write_msi_msg(entry, &msg); 716 if (entry->msi_attrib.maskbit) { 717 unsigned int maskbits, temp; 718 /* All MSIs are unmasked by default, Mask them all */ 719 pci_read_config_dword(dev, 720 msi_mask_bits_reg(pos, is_64bit_address(control)), 721 &maskbits); 722 temp = (1 << multi_msi_capable(control)); 723 temp = ((temp - 1) & ~temp); 724 maskbits |= temp; 725 pci_write_config_dword(dev, 726 msi_mask_bits_reg(pos, is_64bit_address(control)), 727 maskbits); 728 } 729 730 return 0; 731} 732 733/** 734 * msi_capability_init - configure device's MSI capability structure 735 * @dev: pointer to the pci_dev data structure of MSI device function 736 * 737 * Setup the MSI capability structure of device function with a single 738 * MSI vector, regardless of device function is capable of handling 739 * multiple messages. A return of zero indicates the successful setup 740 * of an entry zero with the new MSI vector or non-zero for otherwise. 741 **/ 742static int msi_capability_init(struct pci_dev *dev) 743{ 744 int status; 745 struct msi_desc *entry; 746 int pos, vector; 747 u16 control; 748 749 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 750 pci_read_config_word(dev, msi_control_reg(pos), &control); 751 /* MSI Entry Initialization */ 752 entry = alloc_msi_entry(); 753 if (!entry) 754 return -ENOMEM; 755 756 vector = get_msi_vector(dev); 757 if (vector < 0) { 758 kmem_cache_free(msi_cachep, entry); 759 return -EBUSY; 760 } 761 entry->link.head = vector; 762 entry->link.tail = vector; 763 entry->msi_attrib.type = PCI_CAP_ID_MSI; 764 entry->msi_attrib.state = 0; /* Mark it not active */ 765 entry->msi_attrib.is_64 = is_64bit_address(control); 766 entry->msi_attrib.entry_nr = 0; 767 entry->msi_attrib.maskbit = is_mask_bit_support(control); 768 entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */ 769 entry->msi_attrib.pos = pos; 770 dev->irq = vector; 771 entry->dev = dev; 772 if (is_mask_bit_support(control)) { 773 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, 774 is_64bit_address(control)); 775 } 776 /* Replace with MSI handler */ 777 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit); 778 /* Configure MSI capability structure */ 779 status = msi_register_init(dev, entry); 780 if (status != 0) { 781 dev->irq = entry->msi_attrib.default_vector; 782 kmem_cache_free(msi_cachep, entry); 783 return status; 784 } 785 786 attach_msi_entry(entry, vector); 787 /* Set MSI enabled bits */ 788 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 789 790 return 0; 791} 792 793/** 794 * msix_capability_init - configure device's MSI-X capability 795 * @dev: pointer to the pci_dev data structure of MSI-X device function 796 * @entries: pointer to an array of struct msix_entry entries 797 * @nvec: number of @entries 798 * 799 * Setup the MSI-X capability structure of device function with a 800 * single MSI-X vector. A return of zero indicates the successful setup of 801 * requested MSI-X entries with allocated vectors or non-zero for otherwise. 802 **/ 803static int msix_capability_init(struct pci_dev *dev, 804 struct msix_entry *entries, int nvec) 805{ 806 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; 807 struct msi_msg msg; 808 int status; 809 int vector, pos, i, j, nr_entries, temp = 0; 810 unsigned long phys_addr; 811 u32 table_offset; 812 u16 control; 813 u8 bir; 814 void __iomem *base; 815 816 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 817 /* Request & Map MSI-X table region */ 818 pci_read_config_word(dev, msi_control_reg(pos), &control); 819 nr_entries = multi_msix_capable(control); 820 821 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 822 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 823 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 824 phys_addr = pci_resource_start (dev, bir) + table_offset; 825 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 826 if (base == NULL) 827 return -ENOMEM; 828 829 /* MSI-X Table Initialization */ 830 for (i = 0; i < nvec; i++) { 831 entry = alloc_msi_entry(); 832 if (!entry) 833 break; 834 vector = get_msi_vector(dev); 835 if (vector < 0) { 836 kmem_cache_free(msi_cachep, entry); 837 break; 838 } 839 840 j = entries[i].entry; 841 entries[i].vector = vector; 842 entry->msi_attrib.type = PCI_CAP_ID_MSIX; 843 entry->msi_attrib.state = 0; /* Mark it not active */ 844 entry->msi_attrib.is_64 = 1; 845 entry->msi_attrib.entry_nr = j; 846 entry->msi_attrib.maskbit = 1; 847 entry->msi_attrib.default_vector = dev->irq; 848 entry->msi_attrib.pos = pos; 849 entry->dev = dev; 850 entry->mask_base = base; 851 if (!head) { 852 entry->link.head = vector; 853 entry->link.tail = vector; 854 head = entry; 855 } else { 856 entry->link.head = temp; 857 entry->link.tail = tail->link.tail; 858 tail->link.tail = vector; 859 head->link.head = vector; 860 } 861 temp = vector; 862 tail = entry; 863 /* Replace with MSI-X handler */ 864 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1); 865 /* Configure MSI-X capability structure */ 866 status = msi_ops->setup(dev, vector, 867 &msg.address_hi, 868 &msg.address_lo, 869 &msg.data); 870 if (status < 0) 871 break; 872 873 write_msi_msg(entry, &msg); 874 attach_msi_entry(entry, vector); 875 } 876 if (i != nvec) { 877 i--; 878 for (; i >= 0; i--) { 879 vector = (entries + i)->vector; 880 msi_free_vector(dev, vector, 0); 881 (entries + i)->vector = 0; 882 } 883 return -EBUSY; 884 } 885 /* Set MSI-X enabled bits */ 886 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 887 888 return 0; 889} 890 891/** 892 * pci_msi_supported - check whether MSI may be enabled on device 893 * @dev: pointer to the pci_dev data structure of MSI device function 894 * 895 * MSI must be globally enabled and supported by the device and its root 896 * bus. But, the root bus is not easy to find since some architectures 897 * have virtual busses on top of the PCI hierarchy (for instance the 898 * hypertransport bus), while the actual bus where MSI must be supported 899 * is below. So we test the MSI flag on all parent busses and assume 900 * that no quirk will ever set the NO_MSI flag on a non-root bus. 901 **/ 902static 903int pci_msi_supported(struct pci_dev * dev) 904{ 905 struct pci_bus *bus; 906 907 if (!pci_msi_enable || !dev || dev->no_msi) 908 return -EINVAL; 909 910 /* check MSI flags of all parent busses */ 911 for (bus = dev->bus; bus; bus = bus->parent) 912 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 913 return -EINVAL; 914 915 return 0; 916} 917 918/** 919 * pci_enable_msi - configure device's MSI capability structure 920 * @dev: pointer to the pci_dev data structure of MSI device function 921 * 922 * Setup the MSI capability structure of device function with 923 * a single MSI vector upon its software driver call to request for 924 * MSI mode enabled on its hardware device function. A return of zero 925 * indicates the successful setup of an entry zero with the new MSI 926 * vector or non-zero for otherwise. 927 **/ 928int pci_enable_msi(struct pci_dev* dev) 929{ 930 int pos, temp, status; 931 932 if (pci_msi_supported(dev) < 0) 933 return -EINVAL; 934 935 temp = dev->irq; 936 937 status = msi_init(); 938 if (status < 0) 939 return status; 940 941 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 942 if (!pos) 943 return -EINVAL; 944 945 WARN_ON(!msi_lookup_vector(dev, PCI_CAP_ID_MSI)); 946 947 /* Check whether driver already requested for MSI-X vectors */ 948 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 949 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 950 printk(KERN_INFO "PCI: %s: Can't enable MSI. " 951 "Device already has MSI-X vectors assigned\n", 952 pci_name(dev)); 953 dev->irq = temp; 954 return -EINVAL; 955 } 956 status = msi_capability_init(dev); 957 if (!status) { 958 if (!pos) 959 nr_reserved_vectors--; /* Only MSI capable */ 960 else if (nr_msix_devices > 0) 961 nr_msix_devices--; /* Both MSI and MSI-X capable, 962 but choose enabling MSI */ 963 } 964 965 return status; 966} 967 968void pci_disable_msi(struct pci_dev* dev) 969{ 970 struct msi_desc *entry; 971 int pos, default_vector; 972 u16 control; 973 unsigned long flags; 974 975 if (!pci_msi_enable) 976 return; 977 if (!dev) 978 return; 979 980 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 981 if (!pos) 982 return; 983 984 pci_read_config_word(dev, msi_control_reg(pos), &control); 985 if (!(control & PCI_MSI_FLAGS_ENABLE)) 986 return; 987 988 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 989 990 spin_lock_irqsave(&msi_lock, flags); 991 entry = msi_desc[dev->irq]; 992 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { 993 spin_unlock_irqrestore(&msi_lock, flags); 994 return; 995 } 996 if (entry->msi_attrib.state) { 997 spin_unlock_irqrestore(&msi_lock, flags); 998 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " 999 "free_irq() on MSI vector %d\n", 1000 pci_name(dev), dev->irq); 1001 BUG_ON(entry->msi_attrib.state > 0); 1002 } else { 1003 default_vector = entry->msi_attrib.default_vector; 1004 spin_unlock_irqrestore(&msi_lock, flags); 1005 msi_free_vector(dev, dev->irq, 0); 1006 1007 /* Restore dev->irq to its default pin-assertion vector */ 1008 dev->irq = default_vector; 1009 } 1010} 1011 1012static int msi_free_vector(struct pci_dev* dev, int vector, int reassign) 1013{ 1014 struct msi_desc *entry; 1015 int head, entry_nr, type; 1016 void __iomem *base; 1017 unsigned long flags; 1018 1019 msi_ops->teardown(vector); 1020 1021 spin_lock_irqsave(&msi_lock, flags); 1022 entry = msi_desc[vector]; 1023 if (!entry || entry->dev != dev) { 1024 spin_unlock_irqrestore(&msi_lock, flags); 1025 return -EINVAL; 1026 } 1027 type = entry->msi_attrib.type; 1028 entry_nr = entry->msi_attrib.entry_nr; 1029 head = entry->link.head; 1030 base = entry->mask_base; 1031 msi_desc[entry->link.head]->link.tail = entry->link.tail; 1032 msi_desc[entry->link.tail]->link.head = entry->link.head; 1033 entry->dev = NULL; 1034 if (!reassign) { 1035 vector_irq[vector] = 0; 1036 nr_released_vectors++; 1037 } 1038 msi_desc[vector] = NULL; 1039 spin_unlock_irqrestore(&msi_lock, flags); 1040 1041 kmem_cache_free(msi_cachep, entry); 1042 1043 if (type == PCI_CAP_ID_MSIX) { 1044 if (!reassign) 1045 writel(1, base + 1046 entry_nr * PCI_MSIX_ENTRY_SIZE + 1047 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 1048 1049 if (head == vector) 1050 iounmap(base); 1051 } 1052 1053 return 0; 1054} 1055 1056/** 1057 * pci_enable_msix - configure device's MSI-X capability structure 1058 * @dev: pointer to the pci_dev data structure of MSI-X device function 1059 * @entries: pointer to an array of MSI-X entries 1060 * @nvec: number of MSI-X vectors requested for allocation by device driver 1061 * 1062 * Setup the MSI-X capability structure of device function with the number 1063 * of requested vectors upon its software driver call to request for 1064 * MSI-X mode enabled on its hardware device function. A return of zero 1065 * indicates the successful configuration of MSI-X capability structure 1066 * with new allocated MSI-X vectors. A return of < 0 indicates a failure. 1067 * Or a return of > 0 indicates that driver request is exceeding the number 1068 * of vectors available. Driver should use the returned value to re-send 1069 * its request. 1070 **/ 1071int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 1072{ 1073 int status, pos, nr_entries, free_vectors; 1074 int i, j, temp; 1075 u16 control; 1076 unsigned long flags; 1077 1078 if (!entries || pci_msi_supported(dev) < 0) 1079 return -EINVAL; 1080 1081 status = msi_init(); 1082 if (status < 0) 1083 return status; 1084 1085 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1086 if (!pos) 1087 return -EINVAL; 1088 1089 pci_read_config_word(dev, msi_control_reg(pos), &control); 1090 nr_entries = multi_msix_capable(control); 1091 if (nvec > nr_entries) 1092 return -EINVAL; 1093 1094 /* Check for any invalid entries */ 1095 for (i = 0; i < nvec; i++) { 1096 if (entries[i].entry >= nr_entries) 1097 return -EINVAL; /* invalid entry */ 1098 for (j = i + 1; j < nvec; j++) { 1099 if (entries[i].entry == entries[j].entry) 1100 return -EINVAL; /* duplicate entry */ 1101 } 1102 } 1103 temp = dev->irq; 1104 WARN_ON(!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)); 1105 1106 /* Check whether driver already requested for MSI vector */ 1107 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && 1108 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { 1109 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " 1110 "Device already has an MSI vector assigned\n", 1111 pci_name(dev)); 1112 dev->irq = temp; 1113 return -EINVAL; 1114 } 1115 1116 spin_lock_irqsave(&msi_lock, flags); 1117 /* 1118 * msi_lock is provided to ensure that enough vectors resources are 1119 * available before granting. 1120 */ 1121 free_vectors = pci_vector_resources(last_alloc_vector, 1122 nr_released_vectors); 1123 /* Ensure that each MSI/MSI-X device has one vector reserved by 1124 default to avoid any MSI-X driver to take all available 1125 resources */ 1126 free_vectors -= nr_reserved_vectors; 1127 /* Find the average of free vectors among MSI-X devices */ 1128 if (nr_msix_devices > 0) 1129 free_vectors /= nr_msix_devices; 1130 spin_unlock_irqrestore(&msi_lock, flags); 1131 1132 if (nvec > free_vectors) { 1133 if (free_vectors > 0) 1134 return free_vectors; 1135 else 1136 return -EBUSY; 1137 } 1138 1139 status = msix_capability_init(dev, entries, nvec); 1140 if (!status && nr_msix_devices > 0) 1141 nr_msix_devices--; 1142 1143 return status; 1144} 1145 1146void pci_disable_msix(struct pci_dev* dev) 1147{ 1148 int pos, temp; 1149 u16 control; 1150 1151 if (!pci_msi_enable) 1152 return; 1153 if (!dev) 1154 return; 1155 1156 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1157 if (!pos) 1158 return; 1159 1160 pci_read_config_word(dev, msi_control_reg(pos), &control); 1161 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 1162 return; 1163 1164 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 1165 1166 temp = dev->irq; 1167 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 1168 int state, vector, head, tail = 0, warning = 0; 1169 unsigned long flags; 1170 1171 vector = head = dev->irq; 1172 dev->irq = temp; /* Restore pin IRQ */ 1173 while (head != tail) { 1174 spin_lock_irqsave(&msi_lock, flags); 1175 state = msi_desc[vector]->msi_attrib.state; 1176 tail = msi_desc[vector]->link.tail; 1177 spin_unlock_irqrestore(&msi_lock, flags); 1178 if (state) 1179 warning = 1; 1180 else if (vector != head) /* Release MSI-X vector */ 1181 msi_free_vector(dev, vector, 0); 1182 vector = tail; 1183 } 1184 msi_free_vector(dev, vector, 0); 1185 if (warning) { 1186 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " 1187 "free_irq() on all MSI-X vectors\n", 1188 pci_name(dev)); 1189 BUG_ON(warning > 0); 1190 } 1191 } 1192} 1193 1194/** 1195 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state 1196 * @dev: pointer to the pci_dev data structure of MSI(X) device function 1197 * 1198 * Being called during hotplug remove, from which the device function 1199 * is hot-removed. All previous assigned MSI/MSI-X vectors, if 1200 * allocated for this device function, are reclaimed to unused state, 1201 * which may be used later on. 1202 **/ 1203void msi_remove_pci_irq_vectors(struct pci_dev* dev) 1204{ 1205 int state, pos, temp; 1206 unsigned long flags; 1207 1208 if (!pci_msi_enable || !dev) 1209 return; 1210 1211 temp = dev->irq; /* Save IOAPIC IRQ */ 1212 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 1213 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { 1214 spin_lock_irqsave(&msi_lock, flags); 1215 state = msi_desc[dev->irq]->msi_attrib.state; 1216 spin_unlock_irqrestore(&msi_lock, flags); 1217 if (state) { 1218 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 1219 "called without free_irq() on MSI vector %d\n", 1220 pci_name(dev), dev->irq); 1221 BUG_ON(state > 0); 1222 } else /* Release MSI vector assigned to this device */ 1223 msi_free_vector(dev, dev->irq, 0); 1224 dev->irq = temp; /* Restore IOAPIC IRQ */ 1225 } 1226 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1227 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 1228 int vector, head, tail = 0, warning = 0; 1229 void __iomem *base = NULL; 1230 1231 vector = head = dev->irq; 1232 while (head != tail) { 1233 spin_lock_irqsave(&msi_lock, flags); 1234 state = msi_desc[vector]->msi_attrib.state; 1235 tail = msi_desc[vector]->link.tail; 1236 base = msi_desc[vector]->mask_base; 1237 spin_unlock_irqrestore(&msi_lock, flags); 1238 if (state) 1239 warning = 1; 1240 else if (vector != head) /* Release MSI-X vector */ 1241 msi_free_vector(dev, vector, 0); 1242 vector = tail; 1243 } 1244 msi_free_vector(dev, vector, 0); 1245 if (warning) { 1246 iounmap(base); 1247 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 1248 "called without free_irq() on all MSI-X vectors\n", 1249 pci_name(dev)); 1250 BUG_ON(warning > 0); 1251 } 1252 dev->irq = temp; /* Restore IOAPIC IRQ */ 1253 } 1254} 1255 1256void pci_no_msi(void) 1257{ 1258 pci_msi_enable = 0; 1259} 1260 1261EXPORT_SYMBOL(pci_enable_msi); 1262EXPORT_SYMBOL(pci_disable_msi); 1263EXPORT_SYMBOL(pci_enable_msix); 1264EXPORT_SYMBOL(pci_disable_msix); 1265