msi.c revision 110828c9cdce6e8ec68479ced4ca0bdc1135bb91
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17#include <linux/msi.h> 18#include <linux/smp.h> 19 20#include <asm/errno.h> 21#include <asm/io.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static int pci_msi_enable = 1; 27 28/* Arch hooks */ 29 30#ifndef arch_msi_check_device 31int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) 32{ 33 return 0; 34} 35#endif 36 37#ifndef arch_setup_msi_irqs 38int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 39{ 40 struct msi_desc *entry; 41 int ret; 42 43 /* 44 * If an architecture wants to support multiple MSI, it needs to 45 * override arch_setup_msi_irqs() 46 */ 47 if (type == PCI_CAP_ID_MSI && nvec > 1) 48 return 1; 49 50 list_for_each_entry(entry, &dev->msi_list, list) { 51 ret = arch_setup_msi_irq(dev, entry); 52 if (ret < 0) 53 return ret; 54 if (ret > 0) 55 return -ENOSPC; 56 } 57 58 return 0; 59} 60#endif 61 62#ifndef arch_teardown_msi_irqs 63void arch_teardown_msi_irqs(struct pci_dev *dev) 64{ 65 struct msi_desc *entry; 66 67 list_for_each_entry(entry, &dev->msi_list, list) { 68 int i, nvec; 69 if (entry->irq == 0) 70 continue; 71 nvec = 1 << entry->msi_attrib.multiple; 72 for (i = 0; i < nvec; i++) 73 arch_teardown_msi_irq(entry->irq + i); 74 } 75} 76#endif 77 78static void msi_set_enable(struct pci_dev *dev, int pos, int enable) 79{ 80 u16 control; 81 82 BUG_ON(!pos); 83 84 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 85 control &= ~PCI_MSI_FLAGS_ENABLE; 86 if (enable) 87 control |= PCI_MSI_FLAGS_ENABLE; 88 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 89} 90 91static void msix_set_enable(struct pci_dev *dev, int enable) 92{ 93 int pos; 94 u16 control; 95 96 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 97 if (pos) { 98 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 99 control &= ~PCI_MSIX_FLAGS_ENABLE; 100 if (enable) 101 control |= PCI_MSIX_FLAGS_ENABLE; 102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 103 } 104} 105 106static inline __attribute_const__ u32 msi_mask(unsigned x) 107{ 108 /* Don't shift by >= width of type */ 109 if (x >= 5) 110 return 0xffffffff; 111 return (1 << (1 << x)) - 1; 112} 113 114static inline __attribute_const__ u32 msi_capable_mask(u16 control) 115{ 116 return msi_mask((control >> 1) & 7); 117} 118 119static inline __attribute_const__ u32 msi_enabled_mask(u16 control) 120{ 121 return msi_mask((control >> 4) & 7); 122} 123 124/* 125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to 126 * mask all MSI interrupts by clearing the MSI enable bit does not work 127 * reliably as devices without an INTx disable bit will then generate a 128 * level IRQ which will never be cleared. 129 */ 130static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) 131{ 132 u32 mask_bits = desc->masked; 133 134 if (!desc->msi_attrib.maskbit) 135 return; 136 137 mask_bits &= ~mask; 138 mask_bits |= flag; 139 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); 140 desc->masked = mask_bits; 141} 142 143/* 144 * This internal function does not flush PCI writes to the device. 145 * All users must ensure that they read from the device before either 146 * assuming that the device state is up to date, or returning out of this 147 * file. This saves a few milliseconds when initialising devices with lots 148 * of MSI-X interrupts. 149 */ 150static void msix_mask_irq(struct msi_desc *desc, u32 flag) 151{ 152 u32 mask_bits = desc->masked; 153 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 154 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 155 mask_bits &= ~1; 156 mask_bits |= flag; 157 writel(mask_bits, desc->mask_base + offset); 158 desc->masked = mask_bits; 159} 160 161static void msi_set_mask_bit(unsigned irq, u32 flag) 162{ 163 struct msi_desc *desc = get_irq_msi(irq); 164 165 if (desc->msi_attrib.is_msix) { 166 msix_mask_irq(desc, flag); 167 readl(desc->mask_base); /* Flush write to device */ 168 } else { 169 unsigned offset = irq - desc->dev->irq; 170 msi_mask_irq(desc, 1 << offset, flag << offset); 171 } 172} 173 174void mask_msi_irq(unsigned int irq) 175{ 176 msi_set_mask_bit(irq, 1); 177} 178 179void unmask_msi_irq(unsigned int irq) 180{ 181 msi_set_mask_bit(irq, 0); 182} 183 184void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 185{ 186 struct msi_desc *entry = get_irq_desc_msi(desc); 187 if (entry->msi_attrib.is_msix) { 188 void __iomem *base = entry->mask_base + 189 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 190 191 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 192 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 193 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 194 } else { 195 struct pci_dev *dev = entry->dev; 196 int pos = entry->msi_attrib.pos; 197 u16 data; 198 199 pci_read_config_dword(dev, msi_lower_address_reg(pos), 200 &msg->address_lo); 201 if (entry->msi_attrib.is_64) { 202 pci_read_config_dword(dev, msi_upper_address_reg(pos), 203 &msg->address_hi); 204 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 205 } else { 206 msg->address_hi = 0; 207 pci_read_config_word(dev, msi_data_reg(pos, 0), &data); 208 } 209 msg->data = data; 210 } 211} 212 213void read_msi_msg(unsigned int irq, struct msi_msg *msg) 214{ 215 struct irq_desc *desc = irq_to_desc(irq); 216 217 read_msi_msg_desc(desc, msg); 218} 219 220void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 221{ 222 struct msi_desc *entry = get_irq_desc_msi(desc); 223 if (entry->msi_attrib.is_msix) { 224 void __iomem *base; 225 base = entry->mask_base + 226 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 227 228 writel(msg->address_lo, 229 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 230 writel(msg->address_hi, 231 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 232 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 233 } else { 234 struct pci_dev *dev = entry->dev; 235 int pos = entry->msi_attrib.pos; 236 u16 msgctl; 237 238 pci_read_config_word(dev, msi_control_reg(pos), &msgctl); 239 msgctl &= ~PCI_MSI_FLAGS_QSIZE; 240 msgctl |= entry->msi_attrib.multiple << 4; 241 pci_write_config_word(dev, msi_control_reg(pos), msgctl); 242 243 pci_write_config_dword(dev, msi_lower_address_reg(pos), 244 msg->address_lo); 245 if (entry->msi_attrib.is_64) { 246 pci_write_config_dword(dev, msi_upper_address_reg(pos), 247 msg->address_hi); 248 pci_write_config_word(dev, msi_data_reg(pos, 1), 249 msg->data); 250 } else { 251 pci_write_config_word(dev, msi_data_reg(pos, 0), 252 msg->data); 253 } 254 } 255 entry->msg = *msg; 256} 257 258void write_msi_msg(unsigned int irq, struct msi_msg *msg) 259{ 260 struct irq_desc *desc = irq_to_desc(irq); 261 262 write_msi_msg_desc(desc, msg); 263} 264 265static int msi_free_irqs(struct pci_dev* dev); 266 267static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) 268{ 269 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); 270 if (!desc) 271 return NULL; 272 273 INIT_LIST_HEAD(&desc->list); 274 desc->dev = dev; 275 276 return desc; 277} 278 279static void pci_intx_for_msi(struct pci_dev *dev, int enable) 280{ 281 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) 282 pci_intx(dev, enable); 283} 284 285static void __pci_restore_msi_state(struct pci_dev *dev) 286{ 287 int pos; 288 u16 control; 289 struct msi_desc *entry; 290 291 if (!dev->msi_enabled) 292 return; 293 294 entry = get_irq_msi(dev->irq); 295 pos = entry->msi_attrib.pos; 296 297 pci_intx_for_msi(dev, 0); 298 msi_set_enable(dev, pos, 0); 299 write_msi_msg(dev->irq, &entry->msg); 300 301 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 302 msi_mask_irq(entry, msi_capable_mask(control), entry->masked); 303 control &= ~PCI_MSI_FLAGS_QSIZE; 304 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; 305 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 306} 307 308static void __pci_restore_msix_state(struct pci_dev *dev) 309{ 310 int pos; 311 struct msi_desc *entry; 312 u16 control; 313 314 if (!dev->msix_enabled) 315 return; 316 317 /* route the table */ 318 pci_intx_for_msi(dev, 0); 319 msix_set_enable(dev, 0); 320 321 list_for_each_entry(entry, &dev->msi_list, list) { 322 write_msi_msg(entry->irq, &entry->msg); 323 msix_mask_irq(entry, entry->masked); 324 } 325 326 BUG_ON(list_empty(&dev->msi_list)); 327 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 328 pos = entry->msi_attrib.pos; 329 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 330 control &= ~PCI_MSIX_FLAGS_MASKALL; 331 control |= PCI_MSIX_FLAGS_ENABLE; 332 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 333} 334 335void pci_restore_msi_state(struct pci_dev *dev) 336{ 337 __pci_restore_msi_state(dev); 338 __pci_restore_msix_state(dev); 339} 340EXPORT_SYMBOL_GPL(pci_restore_msi_state); 341 342/** 343 * msi_capability_init - configure device's MSI capability structure 344 * @dev: pointer to the pci_dev data structure of MSI device function 345 * @nvec: number of interrupts to allocate 346 * 347 * Setup the MSI capability structure of the device with the requested 348 * number of interrupts. A return value of zero indicates the successful 349 * setup of an entry with the new MSI irq. A negative return value indicates 350 * an error, and a positive return value indicates the number of interrupts 351 * which could have been allocated. 352 */ 353static int msi_capability_init(struct pci_dev *dev, int nvec) 354{ 355 struct msi_desc *entry; 356 int pos, ret; 357 u16 control; 358 unsigned mask; 359 360 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 361 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ 362 363 pci_read_config_word(dev, msi_control_reg(pos), &control); 364 /* MSI Entry Initialization */ 365 entry = alloc_msi_entry(dev); 366 if (!entry) 367 return -ENOMEM; 368 369 entry->msi_attrib.is_msix = 0; 370 entry->msi_attrib.is_64 = is_64bit_address(control); 371 entry->msi_attrib.entry_nr = 0; 372 entry->msi_attrib.maskbit = is_mask_bit_support(control); 373 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 374 entry->msi_attrib.pos = pos; 375 376 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); 377 /* All MSIs are unmasked by default, Mask them all */ 378 if (entry->msi_attrib.maskbit) 379 pci_read_config_dword(dev, entry->mask_pos, &entry->masked); 380 mask = msi_capable_mask(control); 381 msi_mask_irq(entry, mask, mask); 382 383 list_add_tail(&entry->list, &dev->msi_list); 384 385 /* Configure MSI capability structure */ 386 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); 387 if (ret) { 388 msi_free_irqs(dev); 389 return ret; 390 } 391 392 /* Set MSI enabled bits */ 393 pci_intx_for_msi(dev, 0); 394 msi_set_enable(dev, pos, 1); 395 dev->msi_enabled = 1; 396 397 dev->irq = entry->irq; 398 return 0; 399} 400 401/** 402 * msix_capability_init - configure device's MSI-X capability 403 * @dev: pointer to the pci_dev data structure of MSI-X device function 404 * @entries: pointer to an array of struct msix_entry entries 405 * @nvec: number of @entries 406 * 407 * Setup the MSI-X capability structure of device function with a 408 * single MSI-X irq. A return of zero indicates the successful setup of 409 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 410 **/ 411static int msix_capability_init(struct pci_dev *dev, 412 struct msix_entry *entries, int nvec) 413{ 414 struct msi_desc *entry; 415 int pos, i, j, nr_entries, ret; 416 unsigned long phys_addr; 417 u32 table_offset; 418 u16 control; 419 u8 bir; 420 void __iomem *base; 421 422 msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ 423 424 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 425 /* Request & Map MSI-X table region */ 426 pci_read_config_word(dev, msi_control_reg(pos), &control); 427 nr_entries = multi_msix_capable(control); 428 429 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 430 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 431 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 432 phys_addr = pci_resource_start (dev, bir) + table_offset; 433 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 434 if (base == NULL) 435 return -ENOMEM; 436 437 /* MSI-X Table Initialization */ 438 for (i = 0; i < nvec; i++) { 439 entry = alloc_msi_entry(dev); 440 if (!entry) 441 break; 442 443 j = entries[i].entry; 444 entry->msi_attrib.is_msix = 1; 445 entry->msi_attrib.is_64 = 1; 446 entry->msi_attrib.entry_nr = j; 447 entry->msi_attrib.default_irq = dev->irq; 448 entry->msi_attrib.pos = pos; 449 entry->mask_base = base; 450 msix_mask_irq(entry, 1); 451 452 list_add_tail(&entry->list, &dev->msi_list); 453 } 454 455 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); 456 if (ret < 0) { 457 /* If we had some success report the number of irqs 458 * we succeeded in setting up. */ 459 int avail = 0; 460 list_for_each_entry(entry, &dev->msi_list, list) { 461 if (entry->irq != 0) { 462 avail++; 463 } 464 } 465 466 if (avail != 0) 467 ret = avail; 468 } 469 470 if (ret) { 471 msi_free_irqs(dev); 472 return ret; 473 } 474 475 i = 0; 476 list_for_each_entry(entry, &dev->msi_list, list) { 477 entries[i].vector = entry->irq; 478 set_irq_msi(entry->irq, entry); 479 i++; 480 } 481 /* Set MSI-X enabled bits */ 482 pci_intx_for_msi(dev, 0); 483 msix_set_enable(dev, 1); 484 dev->msix_enabled = 1; 485 486 list_for_each_entry(entry, &dev->msi_list, list) { 487 int vector = entry->msi_attrib.entry_nr; 488 entry->masked = readl(base + vector * PCI_MSIX_ENTRY_SIZE + 489 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 490 } 491 492 return 0; 493} 494 495/** 496 * pci_msi_check_device - check whether MSI may be enabled on a device 497 * @dev: pointer to the pci_dev data structure of MSI device function 498 * @nvec: how many MSIs have been requested ? 499 * @type: are we checking for MSI or MSI-X ? 500 * 501 * Look at global flags, the device itself, and its parent busses 502 * to determine if MSI/-X are supported for the device. If MSI/-X is 503 * supported return 0, else return an error code. 504 **/ 505static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) 506{ 507 struct pci_bus *bus; 508 int ret; 509 510 /* MSI must be globally enabled and supported by the device */ 511 if (!pci_msi_enable || !dev || dev->no_msi) 512 return -EINVAL; 513 514 /* 515 * You can't ask to have 0 or less MSIs configured. 516 * a) it's stupid .. 517 * b) the list manipulation code assumes nvec >= 1. 518 */ 519 if (nvec < 1) 520 return -ERANGE; 521 522 /* Any bridge which does NOT route MSI transactions from it's 523 * secondary bus to it's primary bus must set NO_MSI flag on 524 * the secondary pci_bus. 525 * We expect only arch-specific PCI host bus controller driver 526 * or quirks for specific PCI bridges to be setting NO_MSI. 527 */ 528 for (bus = dev->bus; bus; bus = bus->parent) 529 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 530 return -EINVAL; 531 532 ret = arch_msi_check_device(dev, nvec, type); 533 if (ret) 534 return ret; 535 536 if (!pci_find_capability(dev, type)) 537 return -EINVAL; 538 539 return 0; 540} 541 542/** 543 * pci_enable_msi_block - configure device's MSI capability structure 544 * @dev: device to configure 545 * @nvec: number of interrupts to configure 546 * 547 * Allocate IRQs for a device with the MSI capability. 548 * This function returns a negative errno if an error occurs. If it 549 * is unable to allocate the number of interrupts requested, it returns 550 * the number of interrupts it might be able to allocate. If it successfully 551 * allocates at least the number of interrupts requested, it returns 0 and 552 * updates the @dev's irq member to the lowest new interrupt number; the 553 * other interrupt numbers allocated to this device are consecutive. 554 */ 555int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 556{ 557 int status, pos, maxvec; 558 u16 msgctl; 559 560 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 561 if (!pos) 562 return -EINVAL; 563 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); 564 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); 565 if (nvec > maxvec) 566 return maxvec; 567 568 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); 569 if (status) 570 return status; 571 572 WARN_ON(!!dev->msi_enabled); 573 574 /* Check whether driver already requested MSI-X irqs */ 575 if (dev->msix_enabled) { 576 dev_info(&dev->dev, "can't enable MSI " 577 "(MSI-X already enabled)\n"); 578 return -EINVAL; 579 } 580 581 status = msi_capability_init(dev, nvec); 582 return status; 583} 584EXPORT_SYMBOL(pci_enable_msi_block); 585 586void pci_msi_shutdown(struct pci_dev *dev) 587{ 588 struct msi_desc *desc; 589 u32 mask; 590 u16 ctrl; 591 unsigned pos; 592 593 if (!pci_msi_enable || !dev || !dev->msi_enabled) 594 return; 595 596 BUG_ON(list_empty(&dev->msi_list)); 597 desc = list_first_entry(&dev->msi_list, struct msi_desc, list); 598 pos = desc->msi_attrib.pos; 599 600 msi_set_enable(dev, pos, 0); 601 pci_intx_for_msi(dev, 1); 602 dev->msi_enabled = 0; 603 604 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); 605 mask = msi_capable_mask(ctrl); 606 msi_mask_irq(desc, mask, ~mask); 607 608 /* Restore dev->irq to its default pin-assertion irq */ 609 dev->irq = desc->msi_attrib.default_irq; 610} 611 612void pci_disable_msi(struct pci_dev* dev) 613{ 614 struct msi_desc *entry; 615 616 if (!pci_msi_enable || !dev || !dev->msi_enabled) 617 return; 618 619 pci_msi_shutdown(dev); 620 621 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 622 if (entry->msi_attrib.is_msix) 623 return; 624 625 msi_free_irqs(dev); 626} 627EXPORT_SYMBOL(pci_disable_msi); 628 629static int msi_free_irqs(struct pci_dev* dev) 630{ 631 struct msi_desc *entry, *tmp; 632 633 list_for_each_entry(entry, &dev->msi_list, list) { 634 int i, nvec; 635 if (!entry->irq) 636 continue; 637 nvec = 1 << entry->msi_attrib.multiple; 638 for (i = 0; i < nvec; i++) 639 BUG_ON(irq_has_action(entry->irq + i)); 640 } 641 642 arch_teardown_msi_irqs(dev); 643 644 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { 645 if (entry->msi_attrib.is_msix) { 646 writel(1, entry->mask_base + entry->msi_attrib.entry_nr 647 * PCI_MSIX_ENTRY_SIZE 648 + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 649 650 if (list_is_last(&entry->list, &dev->msi_list)) 651 iounmap(entry->mask_base); 652 } 653 list_del(&entry->list); 654 kfree(entry); 655 } 656 657 return 0; 658} 659 660/** 661 * pci_msix_table_size - return the number of device's MSI-X table entries 662 * @dev: pointer to the pci_dev data structure of MSI-X device function 663 */ 664int pci_msix_table_size(struct pci_dev *dev) 665{ 666 int pos; 667 u16 control; 668 669 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 670 if (!pos) 671 return 0; 672 673 pci_read_config_word(dev, msi_control_reg(pos), &control); 674 return multi_msix_capable(control); 675} 676 677/** 678 * pci_enable_msix - configure device's MSI-X capability structure 679 * @dev: pointer to the pci_dev data structure of MSI-X device function 680 * @entries: pointer to an array of MSI-X entries 681 * @nvec: number of MSI-X irqs requested for allocation by device driver 682 * 683 * Setup the MSI-X capability structure of device function with the number 684 * of requested irqs upon its software driver call to request for 685 * MSI-X mode enabled on its hardware device function. A return of zero 686 * indicates the successful configuration of MSI-X capability structure 687 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 688 * Or a return of > 0 indicates that driver request is exceeding the number 689 * of irqs or MSI-X vectors available. Driver should use the returned value to 690 * re-send its request. 691 **/ 692int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 693{ 694 int status, nr_entries; 695 int i, j; 696 697 if (!entries) 698 return -EINVAL; 699 700 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); 701 if (status) 702 return status; 703 704 nr_entries = pci_msix_table_size(dev); 705 if (nvec > nr_entries) 706 return nr_entries; 707 708 /* Check for any invalid entries */ 709 for (i = 0; i < nvec; i++) { 710 if (entries[i].entry >= nr_entries) 711 return -EINVAL; /* invalid entry */ 712 for (j = i + 1; j < nvec; j++) { 713 if (entries[i].entry == entries[j].entry) 714 return -EINVAL; /* duplicate entry */ 715 } 716 } 717 WARN_ON(!!dev->msix_enabled); 718 719 /* Check whether driver already requested for MSI irq */ 720 if (dev->msi_enabled) { 721 dev_info(&dev->dev, "can't enable MSI-X " 722 "(MSI IRQ already assigned)\n"); 723 return -EINVAL; 724 } 725 status = msix_capability_init(dev, entries, nvec); 726 return status; 727} 728EXPORT_SYMBOL(pci_enable_msix); 729 730static void msix_free_all_irqs(struct pci_dev *dev) 731{ 732 msi_free_irqs(dev); 733} 734 735void pci_msix_shutdown(struct pci_dev* dev) 736{ 737 if (!pci_msi_enable || !dev || !dev->msix_enabled) 738 return; 739 740 msix_set_enable(dev, 0); 741 pci_intx_for_msi(dev, 1); 742 dev->msix_enabled = 0; 743} 744void pci_disable_msix(struct pci_dev* dev) 745{ 746 if (!pci_msi_enable || !dev || !dev->msix_enabled) 747 return; 748 749 pci_msix_shutdown(dev); 750 751 msix_free_all_irqs(dev); 752} 753EXPORT_SYMBOL(pci_disable_msix); 754 755/** 756 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 757 * @dev: pointer to the pci_dev data structure of MSI(X) device function 758 * 759 * Being called during hotplug remove, from which the device function 760 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 761 * allocated for this device function, are reclaimed to unused state, 762 * which may be used later on. 763 **/ 764void msi_remove_pci_irq_vectors(struct pci_dev* dev) 765{ 766 if (!pci_msi_enable || !dev) 767 return; 768 769 if (dev->msi_enabled) 770 msi_free_irqs(dev); 771 772 if (dev->msix_enabled) 773 msix_free_all_irqs(dev); 774} 775 776void pci_no_msi(void) 777{ 778 pci_msi_enable = 0; 779} 780 781/** 782 * pci_msi_enabled - is MSI enabled? 783 * 784 * Returns true if MSI has not been disabled by the command-line option 785 * pci=nomsi. 786 **/ 787int pci_msi_enabled(void) 788{ 789 return pci_msi_enable; 790} 791EXPORT_SYMBOL(pci_msi_enabled); 792 793void pci_msi_init_pci_dev(struct pci_dev *dev) 794{ 795 INIT_LIST_HEAD(&dev->msi_list); 796} 797