msi.c revision 24d27553390c69d11cdbd930d635193956fc295f
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17#include <linux/msi.h> 18#include <linux/smp.h> 19 20#include <asm/errno.h> 21#include <asm/io.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static int pci_msi_enable = 1; 27 28/* Arch hooks */ 29 30#ifndef arch_msi_check_device 31int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) 32{ 33 return 0; 34} 35#endif 36 37#ifndef arch_setup_msi_irqs 38int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 39{ 40 struct msi_desc *entry; 41 int ret; 42 43 list_for_each_entry(entry, &dev->msi_list, list) { 44 ret = arch_setup_msi_irq(dev, entry); 45 if (ret < 0) 46 return ret; 47 if (ret > 0) 48 return -ENOSPC; 49 } 50 51 return 0; 52} 53#endif 54 55#ifndef arch_teardown_msi_irqs 56void arch_teardown_msi_irqs(struct pci_dev *dev) 57{ 58 struct msi_desc *entry; 59 60 list_for_each_entry(entry, &dev->msi_list, list) { 61 if (entry->irq != 0) 62 arch_teardown_msi_irq(entry->irq); 63 } 64} 65#endif 66 67static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) 68{ 69 u16 control; 70 71 if (pos) { 72 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 73 control &= ~PCI_MSI_FLAGS_ENABLE; 74 if (enable) 75 control |= PCI_MSI_FLAGS_ENABLE; 76 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 77 } 78} 79 80static void msi_set_enable(struct pci_dev *dev, int enable) 81{ 82 __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); 83} 84 85static void msix_set_enable(struct pci_dev *dev, int enable) 86{ 87 int pos; 88 u16 control; 89 90 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 91 if (pos) { 92 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 93 control &= ~PCI_MSIX_FLAGS_ENABLE; 94 if (enable) 95 control |= PCI_MSIX_FLAGS_ENABLE; 96 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 97 } 98} 99 100static inline __attribute_const__ u32 msi_mask(unsigned x) 101{ 102 /* Don't shift by >= width of type */ 103 if (x >= 5) 104 return 0xffffffff; 105 return (1 << (1 << x)) - 1; 106} 107 108static void msix_flush_writes(struct irq_desc *desc) 109{ 110 struct msi_desc *entry; 111 112 entry = get_irq_desc_msi(desc); 113 BUG_ON(!entry || !entry->dev); 114 if (entry->msi_attrib.is_msix) { 115 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 116 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 117 readl(entry->mask_base + offset); 118 } 119} 120 121/* 122 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to 123 * mask all MSI interrupts by clearing the MSI enable bit does not work 124 * reliably as devices without an INTx disable bit will then generate a 125 * level IRQ which will never be cleared. 126 * 127 * Returns 1 if it succeeded in masking the interrupt and 0 if the device 128 * doesn't support MSI masking. 129 */ 130static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag) 131{ 132 struct msi_desc *entry; 133 134 entry = get_irq_desc_msi(desc); 135 BUG_ON(!entry || !entry->dev); 136 if (entry->msi_attrib.is_msix) { 137 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 138 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 139 writel(flag, entry->mask_base + offset); 140 readl(entry->mask_base + offset); 141 } else { 142 int pos; 143 u32 mask_bits; 144 145 if (!entry->msi_attrib.maskbit) 146 return 0; 147 148 pos = (long)entry->mask_base; 149 pci_read_config_dword(entry->dev, pos, &mask_bits); 150 mask_bits &= ~mask; 151 mask_bits |= flag & mask; 152 pci_write_config_dword(entry->dev, pos, mask_bits); 153 } 154 entry->msi_attrib.masked = !!flag; 155 return 1; 156} 157 158void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 159{ 160 struct msi_desc *entry = get_irq_desc_msi(desc); 161 if (entry->msi_attrib.is_msix) { 162 void __iomem *base = entry->mask_base + 163 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 164 165 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 166 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 167 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 168 } else { 169 struct pci_dev *dev = entry->dev; 170 int pos = entry->msi_attrib.pos; 171 u16 data; 172 173 pci_read_config_dword(dev, msi_lower_address_reg(pos), 174 &msg->address_lo); 175 if (entry->msi_attrib.is_64) { 176 pci_read_config_dword(dev, msi_upper_address_reg(pos), 177 &msg->address_hi); 178 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 179 } else { 180 msg->address_hi = 0; 181 pci_read_config_word(dev, msi_data_reg(pos, 0), &data); 182 } 183 msg->data = data; 184 } 185} 186 187void read_msi_msg(unsigned int irq, struct msi_msg *msg) 188{ 189 struct irq_desc *desc = irq_to_desc(irq); 190 191 read_msi_msg_desc(desc, msg); 192} 193 194void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 195{ 196 struct msi_desc *entry = get_irq_desc_msi(desc); 197 if (entry->msi_attrib.is_msix) { 198 void __iomem *base; 199 base = entry->mask_base + 200 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 201 202 writel(msg->address_lo, 203 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 204 writel(msg->address_hi, 205 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 206 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 207 } else { 208 struct pci_dev *dev = entry->dev; 209 int pos = entry->msi_attrib.pos; 210 211 pci_write_config_dword(dev, msi_lower_address_reg(pos), 212 msg->address_lo); 213 if (entry->msi_attrib.is_64) { 214 pci_write_config_dword(dev, msi_upper_address_reg(pos), 215 msg->address_hi); 216 pci_write_config_word(dev, msi_data_reg(pos, 1), 217 msg->data); 218 } else { 219 pci_write_config_word(dev, msi_data_reg(pos, 0), 220 msg->data); 221 } 222 } 223 entry->msg = *msg; 224} 225 226void write_msi_msg(unsigned int irq, struct msi_msg *msg) 227{ 228 struct irq_desc *desc = irq_to_desc(irq); 229 230 write_msi_msg_desc(desc, msg); 231} 232 233void mask_msi_irq(unsigned int irq) 234{ 235 struct irq_desc *desc = irq_to_desc(irq); 236 237 msi_set_mask_bits(desc, 1, 1); 238 msix_flush_writes(desc); 239} 240 241void unmask_msi_irq(unsigned int irq) 242{ 243 struct irq_desc *desc = irq_to_desc(irq); 244 245 msi_set_mask_bits(desc, 1, 0); 246 msix_flush_writes(desc); 247} 248 249static int msi_free_irqs(struct pci_dev* dev); 250 251static struct msi_desc* alloc_msi_entry(void) 252{ 253 struct msi_desc *entry; 254 255 entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); 256 if (!entry) 257 return NULL; 258 259 INIT_LIST_HEAD(&entry->list); 260 entry->irq = 0; 261 entry->dev = NULL; 262 263 return entry; 264} 265 266static void pci_intx_for_msi(struct pci_dev *dev, int enable) 267{ 268 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) 269 pci_intx(dev, enable); 270} 271 272static void __pci_restore_msi_state(struct pci_dev *dev) 273{ 274 int pos; 275 u16 control; 276 struct msi_desc *entry; 277 278 if (!dev->msi_enabled) 279 return; 280 281 entry = get_irq_msi(dev->irq); 282 pos = entry->msi_attrib.pos; 283 284 pci_intx_for_msi(dev, 0); 285 msi_set_enable(dev, 0); 286 write_msi_msg(dev->irq, &entry->msg); 287 if (entry->msi_attrib.maskbit) { 288 struct irq_desc *desc = irq_to_desc(dev->irq); 289 msi_set_mask_bits(desc, entry->msi_attrib.maskbits_mask, 290 entry->msi_attrib.masked); 291 } 292 293 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 294 control &= ~PCI_MSI_FLAGS_QSIZE; 295 control |= PCI_MSI_FLAGS_ENABLE; 296 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 297} 298 299static void __pci_restore_msix_state(struct pci_dev *dev) 300{ 301 int pos; 302 struct msi_desc *entry; 303 u16 control; 304 305 if (!dev->msix_enabled) 306 return; 307 308 /* route the table */ 309 pci_intx_for_msi(dev, 0); 310 msix_set_enable(dev, 0); 311 312 list_for_each_entry(entry, &dev->msi_list, list) { 313 struct irq_desc *desc = irq_to_desc(entry->irq); 314 write_msi_msg(entry->irq, &entry->msg); 315 msi_set_mask_bits(desc, 1, entry->msi_attrib.masked); 316 } 317 318 BUG_ON(list_empty(&dev->msi_list)); 319 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 320 pos = entry->msi_attrib.pos; 321 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 322 control &= ~PCI_MSIX_FLAGS_MASKALL; 323 control |= PCI_MSIX_FLAGS_ENABLE; 324 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 325} 326 327void pci_restore_msi_state(struct pci_dev *dev) 328{ 329 __pci_restore_msi_state(dev); 330 __pci_restore_msix_state(dev); 331} 332EXPORT_SYMBOL_GPL(pci_restore_msi_state); 333 334/** 335 * msi_capability_init - configure device's MSI capability structure 336 * @dev: pointer to the pci_dev data structure of MSI device function 337 * 338 * Setup the MSI capability structure of device function with a single 339 * MSI irq, regardless of device function is capable of handling 340 * multiple messages. A return of zero indicates the successful setup 341 * of an entry zero with the new MSI irq or non-zero for otherwise. 342 **/ 343static int msi_capability_init(struct pci_dev *dev) 344{ 345 struct msi_desc *entry; 346 int pos, ret; 347 u16 control; 348 349 msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ 350 351 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 352 pci_read_config_word(dev, msi_control_reg(pos), &control); 353 /* MSI Entry Initialization */ 354 entry = alloc_msi_entry(); 355 if (!entry) 356 return -ENOMEM; 357 358 entry->msi_attrib.is_msix = 0; 359 entry->msi_attrib.is_64 = is_64bit_address(control); 360 entry->msi_attrib.entry_nr = 0; 361 entry->msi_attrib.maskbit = is_mask_bit_support(control); 362 entry->msi_attrib.masked = 1; 363 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 364 entry->msi_attrib.pos = pos; 365 entry->dev = dev; 366 if (entry->msi_attrib.maskbit) { 367 unsigned int base, maskbits, temp; 368 369 base = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); 370 entry->mask_base = (void __iomem *)(long)base; 371 372 /* All MSIs are unmasked by default, Mask them all */ 373 pci_read_config_dword(dev, base, &maskbits); 374 temp = msi_mask((control & PCI_MSI_FLAGS_QMASK) >> 1); 375 maskbits |= temp; 376 pci_write_config_dword(dev, base, maskbits); 377 entry->msi_attrib.maskbits_mask = temp; 378 } 379 list_add_tail(&entry->list, &dev->msi_list); 380 381 /* Configure MSI capability structure */ 382 ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); 383 if (ret) { 384 msi_free_irqs(dev); 385 return ret; 386 } 387 388 /* Set MSI enabled bits */ 389 pci_intx_for_msi(dev, 0); 390 msi_set_enable(dev, 1); 391 dev->msi_enabled = 1; 392 393 dev->irq = entry->irq; 394 return 0; 395} 396 397/** 398 * msix_capability_init - configure device's MSI-X capability 399 * @dev: pointer to the pci_dev data structure of MSI-X device function 400 * @entries: pointer to an array of struct msix_entry entries 401 * @nvec: number of @entries 402 * 403 * Setup the MSI-X capability structure of device function with a 404 * single MSI-X irq. A return of zero indicates the successful setup of 405 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 406 **/ 407static int msix_capability_init(struct pci_dev *dev, 408 struct msix_entry *entries, int nvec) 409{ 410 struct msi_desc *entry; 411 int pos, i, j, nr_entries, ret; 412 unsigned long phys_addr; 413 u32 table_offset; 414 u16 control; 415 u8 bir; 416 void __iomem *base; 417 418 msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ 419 420 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 421 /* Request & Map MSI-X table region */ 422 pci_read_config_word(dev, msi_control_reg(pos), &control); 423 nr_entries = multi_msix_capable(control); 424 425 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 426 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 427 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 428 phys_addr = pci_resource_start (dev, bir) + table_offset; 429 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 430 if (base == NULL) 431 return -ENOMEM; 432 433 /* MSI-X Table Initialization */ 434 for (i = 0; i < nvec; i++) { 435 entry = alloc_msi_entry(); 436 if (!entry) 437 break; 438 439 j = entries[i].entry; 440 entry->msi_attrib.is_msix = 1; 441 entry->msi_attrib.is_64 = 1; 442 entry->msi_attrib.entry_nr = j; 443 entry->msi_attrib.maskbit = 1; 444 entry->msi_attrib.masked = 1; 445 entry->msi_attrib.default_irq = dev->irq; 446 entry->msi_attrib.pos = pos; 447 entry->dev = dev; 448 entry->mask_base = base; 449 450 list_add_tail(&entry->list, &dev->msi_list); 451 } 452 453 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); 454 if (ret < 0) { 455 /* If we had some success report the number of irqs 456 * we succeeded in setting up. */ 457 int avail = 0; 458 list_for_each_entry(entry, &dev->msi_list, list) { 459 if (entry->irq != 0) { 460 avail++; 461 } 462 } 463 464 if (avail != 0) 465 ret = avail; 466 } 467 468 if (ret) { 469 msi_free_irqs(dev); 470 return ret; 471 } 472 473 i = 0; 474 list_for_each_entry(entry, &dev->msi_list, list) { 475 entries[i].vector = entry->irq; 476 set_irq_msi(entry->irq, entry); 477 i++; 478 } 479 /* Set MSI-X enabled bits */ 480 pci_intx_for_msi(dev, 0); 481 msix_set_enable(dev, 1); 482 dev->msix_enabled = 1; 483 484 return 0; 485} 486 487/** 488 * pci_msi_check_device - check whether MSI may be enabled on a device 489 * @dev: pointer to the pci_dev data structure of MSI device function 490 * @nvec: how many MSIs have been requested ? 491 * @type: are we checking for MSI or MSI-X ? 492 * 493 * Look at global flags, the device itself, and its parent busses 494 * to determine if MSI/-X are supported for the device. If MSI/-X is 495 * supported return 0, else return an error code. 496 **/ 497static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) 498{ 499 struct pci_bus *bus; 500 int ret; 501 502 /* MSI must be globally enabled and supported by the device */ 503 if (!pci_msi_enable || !dev || dev->no_msi) 504 return -EINVAL; 505 506 /* 507 * You can't ask to have 0 or less MSIs configured. 508 * a) it's stupid .. 509 * b) the list manipulation code assumes nvec >= 1. 510 */ 511 if (nvec < 1) 512 return -ERANGE; 513 514 /* Any bridge which does NOT route MSI transactions from it's 515 * secondary bus to it's primary bus must set NO_MSI flag on 516 * the secondary pci_bus. 517 * We expect only arch-specific PCI host bus controller driver 518 * or quirks for specific PCI bridges to be setting NO_MSI. 519 */ 520 for (bus = dev->bus; bus; bus = bus->parent) 521 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 522 return -EINVAL; 523 524 ret = arch_msi_check_device(dev, nvec, type); 525 if (ret) 526 return ret; 527 528 if (!pci_find_capability(dev, type)) 529 return -EINVAL; 530 531 return 0; 532} 533 534/** 535 * pci_enable_msi - configure device's MSI capability structure 536 * @dev: pointer to the pci_dev data structure of MSI device function 537 * 538 * Setup the MSI capability structure of device function with 539 * a single MSI irq upon its software driver call to request for 540 * MSI mode enabled on its hardware device function. A return of zero 541 * indicates the successful setup of an entry zero with the new MSI 542 * irq or non-zero for otherwise. 543 **/ 544int pci_enable_msi(struct pci_dev* dev) 545{ 546 int status; 547 548 status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); 549 if (status) 550 return status; 551 552 WARN_ON(!!dev->msi_enabled); 553 554 /* Check whether driver already requested for MSI-X irqs */ 555 if (dev->msix_enabled) { 556 dev_info(&dev->dev, "can't enable MSI " 557 "(MSI-X already enabled)\n"); 558 return -EINVAL; 559 } 560 status = msi_capability_init(dev); 561 return status; 562} 563EXPORT_SYMBOL(pci_enable_msi); 564 565void pci_msi_shutdown(struct pci_dev* dev) 566{ 567 struct msi_desc *entry; 568 569 if (!pci_msi_enable || !dev || !dev->msi_enabled) 570 return; 571 572 msi_set_enable(dev, 0); 573 pci_intx_for_msi(dev, 1); 574 dev->msi_enabled = 0; 575 576 BUG_ON(list_empty(&dev->msi_list)); 577 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 578 /* Return the the pci reset with msi irqs unmasked */ 579 if (entry->msi_attrib.maskbit) { 580 u32 mask = entry->msi_attrib.maskbits_mask; 581 struct irq_desc *desc = irq_to_desc(dev->irq); 582 msi_set_mask_bits(desc, mask, ~mask); 583 } 584 if (!entry->dev || entry->msi_attrib.is_msix) 585 return; 586 587 /* Restore dev->irq to its default pin-assertion irq */ 588 dev->irq = entry->msi_attrib.default_irq; 589} 590 591void pci_disable_msi(struct pci_dev* dev) 592{ 593 struct msi_desc *entry; 594 595 if (!pci_msi_enable || !dev || !dev->msi_enabled) 596 return; 597 598 pci_msi_shutdown(dev); 599 600 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 601 if (!entry->dev || entry->msi_attrib.is_msix) 602 return; 603 604 msi_free_irqs(dev); 605} 606EXPORT_SYMBOL(pci_disable_msi); 607 608static int msi_free_irqs(struct pci_dev* dev) 609{ 610 struct msi_desc *entry, *tmp; 611 612 list_for_each_entry(entry, &dev->msi_list, list) { 613 if (entry->irq) 614 BUG_ON(irq_has_action(entry->irq)); 615 } 616 617 arch_teardown_msi_irqs(dev); 618 619 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { 620 if (entry->msi_attrib.is_msix) { 621 writel(1, entry->mask_base + entry->msi_attrib.entry_nr 622 * PCI_MSIX_ENTRY_SIZE 623 + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 624 625 if (list_is_last(&entry->list, &dev->msi_list)) 626 iounmap(entry->mask_base); 627 } 628 list_del(&entry->list); 629 kfree(entry); 630 } 631 632 return 0; 633} 634 635/** 636 * pci_msix_table_size - return the number of device's MSI-X table entries 637 * @dev: pointer to the pci_dev data structure of MSI-X device function 638 */ 639int pci_msix_table_size(struct pci_dev *dev) 640{ 641 int pos; 642 u16 control; 643 644 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 645 if (!pos) 646 return 0; 647 648 pci_read_config_word(dev, msi_control_reg(pos), &control); 649 return multi_msix_capable(control); 650} 651 652/** 653 * pci_enable_msix - configure device's MSI-X capability structure 654 * @dev: pointer to the pci_dev data structure of MSI-X device function 655 * @entries: pointer to an array of MSI-X entries 656 * @nvec: number of MSI-X irqs requested for allocation by device driver 657 * 658 * Setup the MSI-X capability structure of device function with the number 659 * of requested irqs upon its software driver call to request for 660 * MSI-X mode enabled on its hardware device function. A return of zero 661 * indicates the successful configuration of MSI-X capability structure 662 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 663 * Or a return of > 0 indicates that driver request is exceeding the number 664 * of irqs available. Driver should use the returned value to re-send 665 * its request. 666 **/ 667int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 668{ 669 int status, nr_entries; 670 int i, j; 671 672 if (!entries) 673 return -EINVAL; 674 675 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); 676 if (status) 677 return status; 678 679 nr_entries = pci_msix_table_size(dev); 680 if (nvec > nr_entries) 681 return -EINVAL; 682 683 /* Check for any invalid entries */ 684 for (i = 0; i < nvec; i++) { 685 if (entries[i].entry >= nr_entries) 686 return -EINVAL; /* invalid entry */ 687 for (j = i + 1; j < nvec; j++) { 688 if (entries[i].entry == entries[j].entry) 689 return -EINVAL; /* duplicate entry */ 690 } 691 } 692 WARN_ON(!!dev->msix_enabled); 693 694 /* Check whether driver already requested for MSI irq */ 695 if (dev->msi_enabled) { 696 dev_info(&dev->dev, "can't enable MSI-X " 697 "(MSI IRQ already assigned)\n"); 698 return -EINVAL; 699 } 700 status = msix_capability_init(dev, entries, nvec); 701 return status; 702} 703EXPORT_SYMBOL(pci_enable_msix); 704 705static void msix_free_all_irqs(struct pci_dev *dev) 706{ 707 msi_free_irqs(dev); 708} 709 710void pci_msix_shutdown(struct pci_dev* dev) 711{ 712 if (!pci_msi_enable || !dev || !dev->msix_enabled) 713 return; 714 715 msix_set_enable(dev, 0); 716 pci_intx_for_msi(dev, 1); 717 dev->msix_enabled = 0; 718} 719void pci_disable_msix(struct pci_dev* dev) 720{ 721 if (!pci_msi_enable || !dev || !dev->msix_enabled) 722 return; 723 724 pci_msix_shutdown(dev); 725 726 msix_free_all_irqs(dev); 727} 728EXPORT_SYMBOL(pci_disable_msix); 729 730/** 731 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 732 * @dev: pointer to the pci_dev data structure of MSI(X) device function 733 * 734 * Being called during hotplug remove, from which the device function 735 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 736 * allocated for this device function, are reclaimed to unused state, 737 * which may be used later on. 738 **/ 739void msi_remove_pci_irq_vectors(struct pci_dev* dev) 740{ 741 if (!pci_msi_enable || !dev) 742 return; 743 744 if (dev->msi_enabled) 745 msi_free_irqs(dev); 746 747 if (dev->msix_enabled) 748 msix_free_all_irqs(dev); 749} 750 751void pci_no_msi(void) 752{ 753 pci_msi_enable = 0; 754} 755 756/** 757 * pci_msi_enabled - is MSI enabled? 758 * 759 * Returns true if MSI has not been disabled by the command-line option 760 * pci=nomsi. 761 **/ 762int pci_msi_enabled(void) 763{ 764 return pci_msi_enable; 765} 766EXPORT_SYMBOL(pci_msi_enabled); 767 768void pci_msi_init_pci_dev(struct pci_dev *dev) 769{ 770 INIT_LIST_HEAD(&dev->msi_list); 771} 772