msi.c revision 264d9caaa1c574c0274b019a810abfe957391005
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17#include <linux/msi.h> 18#include <linux/smp.h> 19 20#include <asm/errno.h> 21#include <asm/io.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static int pci_msi_enable = 1; 27 28/* Arch hooks */ 29 30#ifndef arch_msi_check_device 31int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) 32{ 33 return 0; 34} 35#endif 36 37#ifndef arch_setup_msi_irqs 38int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 39{ 40 struct msi_desc *entry; 41 int ret; 42 43 list_for_each_entry(entry, &dev->msi_list, list) { 44 ret = arch_setup_msi_irq(dev, entry); 45 if (ret < 0) 46 return ret; 47 if (ret > 0) 48 return -ENOSPC; 49 } 50 51 return 0; 52} 53#endif 54 55#ifndef arch_teardown_msi_irqs 56void arch_teardown_msi_irqs(struct pci_dev *dev) 57{ 58 struct msi_desc *entry; 59 60 list_for_each_entry(entry, &dev->msi_list, list) { 61 if (entry->irq != 0) 62 arch_teardown_msi_irq(entry->irq); 63 } 64} 65#endif 66 67static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) 68{ 69 u16 control; 70 71 if (pos) { 72 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 73 control &= ~PCI_MSI_FLAGS_ENABLE; 74 if (enable) 75 control |= PCI_MSI_FLAGS_ENABLE; 76 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 77 } 78} 79 80static void msi_set_enable(struct pci_dev *dev, int enable) 81{ 82 __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); 83} 84 85static void msix_set_enable(struct pci_dev *dev, int enable) 86{ 87 int pos; 88 u16 control; 89 90 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 91 if (pos) { 92 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 93 control &= ~PCI_MSIX_FLAGS_ENABLE; 94 if (enable) 95 control |= PCI_MSIX_FLAGS_ENABLE; 96 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 97 } 98} 99 100static inline __attribute_const__ u32 msi_mask(unsigned x) 101{ 102 /* Don't shift by >= width of type */ 103 if (x >= 5) 104 return 0xffffffff; 105 return (1 << (1 << x)) - 1; 106} 107 108static void msix_flush_writes(struct irq_desc *desc) 109{ 110 struct msi_desc *entry; 111 112 entry = get_irq_desc_msi(desc); 113 BUG_ON(!entry); 114 if (entry->msi_attrib.is_msix) { 115 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 116 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 117 readl(entry->mask_base + offset); 118 } 119} 120 121/* 122 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to 123 * mask all MSI interrupts by clearing the MSI enable bit does not work 124 * reliably as devices without an INTx disable bit will then generate a 125 * level IRQ which will never be cleared. 126 * 127 * Returns 1 if it succeeded in masking the interrupt and 0 if the device 128 * doesn't support MSI masking. 129 */ 130static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag) 131{ 132 struct msi_desc *entry; 133 134 entry = get_irq_desc_msi(desc); 135 BUG_ON(!entry); 136 if (entry->msi_attrib.is_msix) { 137 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 138 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 139 writel(flag, entry->mask_base + offset); 140 readl(entry->mask_base + offset); 141 } else { 142 int pos; 143 u32 mask_bits; 144 145 if (!entry->msi_attrib.maskbit) 146 return 0; 147 148 pos = entry->mask_pos; 149 pci_read_config_dword(entry->dev, pos, &mask_bits); 150 mask_bits &= ~mask; 151 mask_bits |= flag & mask; 152 pci_write_config_dword(entry->dev, pos, mask_bits); 153 } 154 entry->msi_attrib.masked = !!flag; 155 return 1; 156} 157 158void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 159{ 160 struct msi_desc *entry = get_irq_desc_msi(desc); 161 if (entry->msi_attrib.is_msix) { 162 void __iomem *base = entry->mask_base + 163 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 164 165 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 166 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 167 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 168 } else { 169 struct pci_dev *dev = entry->dev; 170 int pos = entry->msi_attrib.pos; 171 u16 data; 172 173 pci_read_config_dword(dev, msi_lower_address_reg(pos), 174 &msg->address_lo); 175 if (entry->msi_attrib.is_64) { 176 pci_read_config_dword(dev, msi_upper_address_reg(pos), 177 &msg->address_hi); 178 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 179 } else { 180 msg->address_hi = 0; 181 pci_read_config_word(dev, msi_data_reg(pos, 0), &data); 182 } 183 msg->data = data; 184 } 185} 186 187void read_msi_msg(unsigned int irq, struct msi_msg *msg) 188{ 189 struct irq_desc *desc = irq_to_desc(irq); 190 191 read_msi_msg_desc(desc, msg); 192} 193 194void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 195{ 196 struct msi_desc *entry = get_irq_desc_msi(desc); 197 if (entry->msi_attrib.is_msix) { 198 void __iomem *base; 199 base = entry->mask_base + 200 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 201 202 writel(msg->address_lo, 203 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 204 writel(msg->address_hi, 205 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 206 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 207 } else { 208 struct pci_dev *dev = entry->dev; 209 int pos = entry->msi_attrib.pos; 210 211 pci_write_config_dword(dev, msi_lower_address_reg(pos), 212 msg->address_lo); 213 if (entry->msi_attrib.is_64) { 214 pci_write_config_dword(dev, msi_upper_address_reg(pos), 215 msg->address_hi); 216 pci_write_config_word(dev, msi_data_reg(pos, 1), 217 msg->data); 218 } else { 219 pci_write_config_word(dev, msi_data_reg(pos, 0), 220 msg->data); 221 } 222 } 223 entry->msg = *msg; 224} 225 226void write_msi_msg(unsigned int irq, struct msi_msg *msg) 227{ 228 struct irq_desc *desc = irq_to_desc(irq); 229 230 write_msi_msg_desc(desc, msg); 231} 232 233void mask_msi_irq(unsigned int irq) 234{ 235 struct irq_desc *desc = irq_to_desc(irq); 236 237 msi_set_mask_bits(desc, 1, 1); 238 msix_flush_writes(desc); 239} 240 241void unmask_msi_irq(unsigned int irq) 242{ 243 struct irq_desc *desc = irq_to_desc(irq); 244 245 msi_set_mask_bits(desc, 1, 0); 246 msix_flush_writes(desc); 247} 248 249static int msi_free_irqs(struct pci_dev* dev); 250 251static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) 252{ 253 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); 254 if (!desc) 255 return NULL; 256 257 INIT_LIST_HEAD(&desc->list); 258 desc->dev = dev; 259 260 return desc; 261} 262 263static void pci_intx_for_msi(struct pci_dev *dev, int enable) 264{ 265 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) 266 pci_intx(dev, enable); 267} 268 269static void __pci_restore_msi_state(struct pci_dev *dev) 270{ 271 int pos; 272 u16 control; 273 struct msi_desc *entry; 274 275 if (!dev->msi_enabled) 276 return; 277 278 entry = get_irq_msi(dev->irq); 279 pos = entry->msi_attrib.pos; 280 281 pci_intx_for_msi(dev, 0); 282 msi_set_enable(dev, 0); 283 write_msi_msg(dev->irq, &entry->msg); 284 if (entry->msi_attrib.maskbit) { 285 struct irq_desc *desc = irq_to_desc(dev->irq); 286 msi_set_mask_bits(desc, entry->msi_attrib.maskbits_mask, 287 entry->msi_attrib.masked); 288 } 289 290 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 291 control &= ~PCI_MSI_FLAGS_QSIZE; 292 control |= PCI_MSI_FLAGS_ENABLE; 293 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 294} 295 296static void __pci_restore_msix_state(struct pci_dev *dev) 297{ 298 int pos; 299 struct msi_desc *entry; 300 u16 control; 301 302 if (!dev->msix_enabled) 303 return; 304 305 /* route the table */ 306 pci_intx_for_msi(dev, 0); 307 msix_set_enable(dev, 0); 308 309 list_for_each_entry(entry, &dev->msi_list, list) { 310 struct irq_desc *desc = irq_to_desc(entry->irq); 311 write_msi_msg(entry->irq, &entry->msg); 312 msi_set_mask_bits(desc, 1, entry->msi_attrib.masked); 313 } 314 315 BUG_ON(list_empty(&dev->msi_list)); 316 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 317 pos = entry->msi_attrib.pos; 318 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 319 control &= ~PCI_MSIX_FLAGS_MASKALL; 320 control |= PCI_MSIX_FLAGS_ENABLE; 321 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 322} 323 324void pci_restore_msi_state(struct pci_dev *dev) 325{ 326 __pci_restore_msi_state(dev); 327 __pci_restore_msix_state(dev); 328} 329EXPORT_SYMBOL_GPL(pci_restore_msi_state); 330 331/** 332 * msi_capability_init - configure device's MSI capability structure 333 * @dev: pointer to the pci_dev data structure of MSI device function 334 * 335 * Setup the MSI capability structure of device function with a single 336 * MSI irq, regardless of device function is capable of handling 337 * multiple messages. A return of zero indicates the successful setup 338 * of an entry zero with the new MSI irq or non-zero for otherwise. 339 **/ 340static int msi_capability_init(struct pci_dev *dev) 341{ 342 struct msi_desc *entry; 343 int pos, ret; 344 u16 control; 345 346 msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ 347 348 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 349 pci_read_config_word(dev, msi_control_reg(pos), &control); 350 /* MSI Entry Initialization */ 351 entry = alloc_msi_entry(dev); 352 if (!entry) 353 return -ENOMEM; 354 355 entry->msi_attrib.is_msix = 0; 356 entry->msi_attrib.is_64 = is_64bit_address(control); 357 entry->msi_attrib.entry_nr = 0; 358 entry->msi_attrib.maskbit = is_mask_bit_support(control); 359 entry->msi_attrib.masked = 1; 360 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 361 entry->msi_attrib.pos = pos; 362 if (entry->msi_attrib.maskbit) { 363 unsigned int base, maskbits, temp; 364 365 base = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); 366 entry->mask_pos = base; 367 /* All MSIs are unmasked by default, Mask them all */ 368 pci_read_config_dword(dev, base, &maskbits); 369 temp = msi_mask((control & PCI_MSI_FLAGS_QMASK) >> 1); 370 maskbits |= temp; 371 pci_write_config_dword(dev, base, maskbits); 372 entry->msi_attrib.maskbits_mask = temp; 373 } 374 list_add_tail(&entry->list, &dev->msi_list); 375 376 /* Configure MSI capability structure */ 377 ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); 378 if (ret) { 379 msi_free_irqs(dev); 380 return ret; 381 } 382 383 /* Set MSI enabled bits */ 384 pci_intx_for_msi(dev, 0); 385 msi_set_enable(dev, 1); 386 dev->msi_enabled = 1; 387 388 dev->irq = entry->irq; 389 return 0; 390} 391 392/** 393 * msix_capability_init - configure device's MSI-X capability 394 * @dev: pointer to the pci_dev data structure of MSI-X device function 395 * @entries: pointer to an array of struct msix_entry entries 396 * @nvec: number of @entries 397 * 398 * Setup the MSI-X capability structure of device function with a 399 * single MSI-X irq. A return of zero indicates the successful setup of 400 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 401 **/ 402static int msix_capability_init(struct pci_dev *dev, 403 struct msix_entry *entries, int nvec) 404{ 405 struct msi_desc *entry; 406 int pos, i, j, nr_entries, ret; 407 unsigned long phys_addr; 408 u32 table_offset; 409 u16 control; 410 u8 bir; 411 void __iomem *base; 412 413 msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ 414 415 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 416 /* Request & Map MSI-X table region */ 417 pci_read_config_word(dev, msi_control_reg(pos), &control); 418 nr_entries = multi_msix_capable(control); 419 420 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 421 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 422 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 423 phys_addr = pci_resource_start (dev, bir) + table_offset; 424 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 425 if (base == NULL) 426 return -ENOMEM; 427 428 /* MSI-X Table Initialization */ 429 for (i = 0; i < nvec; i++) { 430 entry = alloc_msi_entry(dev); 431 if (!entry) 432 break; 433 434 j = entries[i].entry; 435 entry->msi_attrib.is_msix = 1; 436 entry->msi_attrib.is_64 = 1; 437 entry->msi_attrib.entry_nr = j; 438 entry->msi_attrib.maskbit = 1; 439 entry->msi_attrib.masked = 1; 440 entry->msi_attrib.default_irq = dev->irq; 441 entry->msi_attrib.pos = pos; 442 entry->mask_base = base; 443 444 list_add_tail(&entry->list, &dev->msi_list); 445 } 446 447 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); 448 if (ret < 0) { 449 /* If we had some success report the number of irqs 450 * we succeeded in setting up. */ 451 int avail = 0; 452 list_for_each_entry(entry, &dev->msi_list, list) { 453 if (entry->irq != 0) { 454 avail++; 455 } 456 } 457 458 if (avail != 0) 459 ret = avail; 460 } 461 462 if (ret) { 463 msi_free_irqs(dev); 464 return ret; 465 } 466 467 i = 0; 468 list_for_each_entry(entry, &dev->msi_list, list) { 469 entries[i].vector = entry->irq; 470 set_irq_msi(entry->irq, entry); 471 i++; 472 } 473 /* Set MSI-X enabled bits */ 474 pci_intx_for_msi(dev, 0); 475 msix_set_enable(dev, 1); 476 dev->msix_enabled = 1; 477 478 return 0; 479} 480 481/** 482 * pci_msi_check_device - check whether MSI may be enabled on a device 483 * @dev: pointer to the pci_dev data structure of MSI device function 484 * @nvec: how many MSIs have been requested ? 485 * @type: are we checking for MSI or MSI-X ? 486 * 487 * Look at global flags, the device itself, and its parent busses 488 * to determine if MSI/-X are supported for the device. If MSI/-X is 489 * supported return 0, else return an error code. 490 **/ 491static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) 492{ 493 struct pci_bus *bus; 494 int ret; 495 496 /* MSI must be globally enabled and supported by the device */ 497 if (!pci_msi_enable || !dev || dev->no_msi) 498 return -EINVAL; 499 500 /* 501 * You can't ask to have 0 or less MSIs configured. 502 * a) it's stupid .. 503 * b) the list manipulation code assumes nvec >= 1. 504 */ 505 if (nvec < 1) 506 return -ERANGE; 507 508 /* Any bridge which does NOT route MSI transactions from it's 509 * secondary bus to it's primary bus must set NO_MSI flag on 510 * the secondary pci_bus. 511 * We expect only arch-specific PCI host bus controller driver 512 * or quirks for specific PCI bridges to be setting NO_MSI. 513 */ 514 for (bus = dev->bus; bus; bus = bus->parent) 515 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 516 return -EINVAL; 517 518 ret = arch_msi_check_device(dev, nvec, type); 519 if (ret) 520 return ret; 521 522 if (!pci_find_capability(dev, type)) 523 return -EINVAL; 524 525 return 0; 526} 527 528/** 529 * pci_enable_msi - configure device's MSI capability structure 530 * @dev: pointer to the pci_dev data structure of MSI device function 531 * 532 * Setup the MSI capability structure of device function with 533 * a single MSI irq upon its software driver call to request for 534 * MSI mode enabled on its hardware device function. A return of zero 535 * indicates the successful setup of an entry zero with the new MSI 536 * irq or non-zero for otherwise. 537 **/ 538int pci_enable_msi(struct pci_dev* dev) 539{ 540 int status; 541 542 status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); 543 if (status) 544 return status; 545 546 WARN_ON(!!dev->msi_enabled); 547 548 /* Check whether driver already requested for MSI-X irqs */ 549 if (dev->msix_enabled) { 550 dev_info(&dev->dev, "can't enable MSI " 551 "(MSI-X already enabled)\n"); 552 return -EINVAL; 553 } 554 status = msi_capability_init(dev); 555 return status; 556} 557EXPORT_SYMBOL(pci_enable_msi); 558 559void pci_msi_shutdown(struct pci_dev* dev) 560{ 561 struct msi_desc *entry; 562 563 if (!pci_msi_enable || !dev || !dev->msi_enabled) 564 return; 565 566 msi_set_enable(dev, 0); 567 pci_intx_for_msi(dev, 1); 568 dev->msi_enabled = 0; 569 570 BUG_ON(list_empty(&dev->msi_list)); 571 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 572 /* Return the the pci reset with msi irqs unmasked */ 573 if (entry->msi_attrib.maskbit) { 574 u32 mask = entry->msi_attrib.maskbits_mask; 575 struct irq_desc *desc = irq_to_desc(dev->irq); 576 msi_set_mask_bits(desc, mask, ~mask); 577 } 578 if (entry->msi_attrib.is_msix) 579 return; 580 581 /* Restore dev->irq to its default pin-assertion irq */ 582 dev->irq = entry->msi_attrib.default_irq; 583} 584 585void pci_disable_msi(struct pci_dev* dev) 586{ 587 struct msi_desc *entry; 588 589 if (!pci_msi_enable || !dev || !dev->msi_enabled) 590 return; 591 592 pci_msi_shutdown(dev); 593 594 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 595 if (entry->msi_attrib.is_msix) 596 return; 597 598 msi_free_irqs(dev); 599} 600EXPORT_SYMBOL(pci_disable_msi); 601 602static int msi_free_irqs(struct pci_dev* dev) 603{ 604 struct msi_desc *entry, *tmp; 605 606 list_for_each_entry(entry, &dev->msi_list, list) { 607 if (entry->irq) 608 BUG_ON(irq_has_action(entry->irq)); 609 } 610 611 arch_teardown_msi_irqs(dev); 612 613 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { 614 if (entry->msi_attrib.is_msix) { 615 writel(1, entry->mask_base + entry->msi_attrib.entry_nr 616 * PCI_MSIX_ENTRY_SIZE 617 + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 618 619 if (list_is_last(&entry->list, &dev->msi_list)) 620 iounmap(entry->mask_base); 621 } 622 list_del(&entry->list); 623 kfree(entry); 624 } 625 626 return 0; 627} 628 629/** 630 * pci_msix_table_size - return the number of device's MSI-X table entries 631 * @dev: pointer to the pci_dev data structure of MSI-X device function 632 */ 633int pci_msix_table_size(struct pci_dev *dev) 634{ 635 int pos; 636 u16 control; 637 638 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 639 if (!pos) 640 return 0; 641 642 pci_read_config_word(dev, msi_control_reg(pos), &control); 643 return multi_msix_capable(control); 644} 645 646/** 647 * pci_enable_msix - configure device's MSI-X capability structure 648 * @dev: pointer to the pci_dev data structure of MSI-X device function 649 * @entries: pointer to an array of MSI-X entries 650 * @nvec: number of MSI-X irqs requested for allocation by device driver 651 * 652 * Setup the MSI-X capability structure of device function with the number 653 * of requested irqs upon its software driver call to request for 654 * MSI-X mode enabled on its hardware device function. A return of zero 655 * indicates the successful configuration of MSI-X capability structure 656 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 657 * Or a return of > 0 indicates that driver request is exceeding the number 658 * of irqs available. Driver should use the returned value to re-send 659 * its request. 660 **/ 661int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 662{ 663 int status, nr_entries; 664 int i, j; 665 666 if (!entries) 667 return -EINVAL; 668 669 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); 670 if (status) 671 return status; 672 673 nr_entries = pci_msix_table_size(dev); 674 if (nvec > nr_entries) 675 return -EINVAL; 676 677 /* Check for any invalid entries */ 678 for (i = 0; i < nvec; i++) { 679 if (entries[i].entry >= nr_entries) 680 return -EINVAL; /* invalid entry */ 681 for (j = i + 1; j < nvec; j++) { 682 if (entries[i].entry == entries[j].entry) 683 return -EINVAL; /* duplicate entry */ 684 } 685 } 686 WARN_ON(!!dev->msix_enabled); 687 688 /* Check whether driver already requested for MSI irq */ 689 if (dev->msi_enabled) { 690 dev_info(&dev->dev, "can't enable MSI-X " 691 "(MSI IRQ already assigned)\n"); 692 return -EINVAL; 693 } 694 status = msix_capability_init(dev, entries, nvec); 695 return status; 696} 697EXPORT_SYMBOL(pci_enable_msix); 698 699static void msix_free_all_irqs(struct pci_dev *dev) 700{ 701 msi_free_irqs(dev); 702} 703 704void pci_msix_shutdown(struct pci_dev* dev) 705{ 706 if (!pci_msi_enable || !dev || !dev->msix_enabled) 707 return; 708 709 msix_set_enable(dev, 0); 710 pci_intx_for_msi(dev, 1); 711 dev->msix_enabled = 0; 712} 713void pci_disable_msix(struct pci_dev* dev) 714{ 715 if (!pci_msi_enable || !dev || !dev->msix_enabled) 716 return; 717 718 pci_msix_shutdown(dev); 719 720 msix_free_all_irqs(dev); 721} 722EXPORT_SYMBOL(pci_disable_msix); 723 724/** 725 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 726 * @dev: pointer to the pci_dev data structure of MSI(X) device function 727 * 728 * Being called during hotplug remove, from which the device function 729 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 730 * allocated for this device function, are reclaimed to unused state, 731 * which may be used later on. 732 **/ 733void msi_remove_pci_irq_vectors(struct pci_dev* dev) 734{ 735 if (!pci_msi_enable || !dev) 736 return; 737 738 if (dev->msi_enabled) 739 msi_free_irqs(dev); 740 741 if (dev->msix_enabled) 742 msix_free_all_irqs(dev); 743} 744 745void pci_no_msi(void) 746{ 747 pci_msi_enable = 0; 748} 749 750/** 751 * pci_msi_enabled - is MSI enabled? 752 * 753 * Returns true if MSI has not been disabled by the command-line option 754 * pci=nomsi. 755 **/ 756int pci_msi_enabled(void) 757{ 758 return pci_msi_enable; 759} 760EXPORT_SYMBOL(pci_msi_enabled); 761 762void pci_msi_init_pci_dev(struct pci_dev *dev) 763{ 764 INIT_LIST_HEAD(&dev->msi_list); 765} 766