msi.c revision 277bc33bc2479707e88b0b2ae6fe56e8e4aabe81
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/smp_lock.h> 16#include <linux/pci.h> 17#include <linux/proc_fs.h> 18 19#include <asm/errno.h> 20#include <asm/io.h> 21#include <asm/smp.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static DEFINE_SPINLOCK(msi_lock); 27static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; 28static kmem_cache_t* msi_cachep; 29 30static int pci_msi_enable = 1; 31 32static struct msi_ops *msi_ops; 33 34int 35msi_register(struct msi_ops *ops) 36{ 37 msi_ops = ops; 38 return 0; 39} 40 41static int msi_cache_init(void) 42{ 43 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), 44 0, SLAB_HWCACHE_ALIGN, NULL, NULL); 45 if (!msi_cachep) 46 return -ENOMEM; 47 48 return 0; 49} 50 51static void msi_set_mask_bit(unsigned int irq, int flag) 52{ 53 struct msi_desc *entry; 54 55 entry = msi_desc[irq]; 56 BUG_ON(!entry || !entry->dev); 57 switch (entry->msi_attrib.type) { 58 case PCI_CAP_ID_MSI: 59 if (entry->msi_attrib.maskbit) { 60 int pos; 61 u32 mask_bits; 62 63 pos = (long)entry->mask_base; 64 pci_read_config_dword(entry->dev, pos, &mask_bits); 65 mask_bits &= ~(1); 66 mask_bits |= flag; 67 pci_write_config_dword(entry->dev, pos, mask_bits); 68 } 69 break; 70 case PCI_CAP_ID_MSIX: 71 { 72 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 73 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 74 writel(flag, entry->mask_base + offset); 75 break; 76 } 77 default: 78 BUG(); 79 break; 80 } 81} 82 83static void read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) 84{ 85 switch(entry->msi_attrib.type) { 86 case PCI_CAP_ID_MSI: 87 { 88 struct pci_dev *dev = entry->dev; 89 int pos = entry->msi_attrib.pos; 90 u16 data; 91 92 pci_read_config_dword(dev, msi_lower_address_reg(pos), 93 &msg->address_lo); 94 if (entry->msi_attrib.is_64) { 95 pci_read_config_dword(dev, msi_upper_address_reg(pos), 96 &msg->address_hi); 97 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 98 } else { 99 msg->address_hi = 0; 100 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 101 } 102 msg->data = data; 103 break; 104 } 105 case PCI_CAP_ID_MSIX: 106 { 107 void __iomem *base; 108 base = entry->mask_base + 109 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 110 111 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 112 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 113 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 114 break; 115 } 116 default: 117 BUG(); 118 } 119} 120 121static void write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) 122{ 123 switch (entry->msi_attrib.type) { 124 case PCI_CAP_ID_MSI: 125 { 126 struct pci_dev *dev = entry->dev; 127 int pos = entry->msi_attrib.pos; 128 129 pci_write_config_dword(dev, msi_lower_address_reg(pos), 130 msg->address_lo); 131 if (entry->msi_attrib.is_64) { 132 pci_write_config_dword(dev, msi_upper_address_reg(pos), 133 msg->address_hi); 134 pci_write_config_word(dev, msi_data_reg(pos, 1), 135 msg->data); 136 } else { 137 pci_write_config_word(dev, msi_data_reg(pos, 0), 138 msg->data); 139 } 140 break; 141 } 142 case PCI_CAP_ID_MSIX: 143 { 144 void __iomem *base; 145 base = entry->mask_base + 146 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 147 148 writel(msg->address_lo, 149 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 150 writel(msg->address_hi, 151 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 152 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 153 break; 154 } 155 default: 156 BUG(); 157 } 158} 159 160#ifdef CONFIG_SMP 161static void set_msi_affinity(unsigned int irq, cpumask_t cpu_mask) 162{ 163 struct msi_desc *entry; 164 struct msi_msg msg; 165 166 entry = msi_desc[irq]; 167 if (!entry || !entry->dev) 168 return; 169 170 read_msi_msg(entry, &msg); 171 msi_ops->target(irq, cpu_mask, &msg); 172 write_msi_msg(entry, &msg); 173 set_native_irq_info(irq, cpu_mask); 174} 175#else 176#define set_msi_affinity NULL 177#endif /* CONFIG_SMP */ 178 179static void mask_MSI_irq(unsigned int irq) 180{ 181 msi_set_mask_bit(irq, 1); 182} 183 184static void unmask_MSI_irq(unsigned int irq) 185{ 186 msi_set_mask_bit(irq, 0); 187} 188 189static void ack_msi_irq(unsigned int irq) 190{ 191 move_native_irq(irq); 192 ack_APIC_irq(); 193} 194 195/* 196 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, 197 * which implement the MSI or MSI-X Capability Structure. 198 */ 199static struct irq_chip msi_chip = { 200 .name = "PCI-MSI", 201 .unmask = unmask_MSI_irq, 202 .mask = mask_MSI_irq, 203 .ack = ack_msi_irq, 204 .set_affinity = set_msi_affinity 205}; 206 207static int msi_free_irq(struct pci_dev* dev, int irq); 208static int msi_init(void) 209{ 210 static int status = -ENOMEM; 211 212 if (!status) 213 return status; 214 215 if (pci_msi_quirk) { 216 pci_msi_enable = 0; 217 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n"); 218 status = -EINVAL; 219 return status; 220 } 221 222 status = msi_arch_init(); 223 if (status < 0) { 224 pci_msi_enable = 0; 225 printk(KERN_WARNING 226 "PCI: MSI arch init failed. MSI disabled.\n"); 227 return status; 228 } 229 230 if (! msi_ops) { 231 pci_msi_enable = 0; 232 printk(KERN_WARNING 233 "PCI: MSI ops not registered. MSI disabled.\n"); 234 status = -EINVAL; 235 return status; 236 } 237 238 status = msi_cache_init(); 239 if (status < 0) { 240 pci_msi_enable = 0; 241 printk(KERN_WARNING "PCI: MSI cache init failed\n"); 242 return status; 243 } 244 245 return status; 246} 247 248static struct msi_desc* alloc_msi_entry(void) 249{ 250 struct msi_desc *entry; 251 252 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); 253 if (!entry) 254 return NULL; 255 256 entry->link.tail = entry->link.head = 0; /* single message */ 257 entry->dev = NULL; 258 259 return entry; 260} 261 262static void attach_msi_entry(struct msi_desc *entry, int irq) 263{ 264 unsigned long flags; 265 266 spin_lock_irqsave(&msi_lock, flags); 267 msi_desc[irq] = entry; 268 spin_unlock_irqrestore(&msi_lock, flags); 269} 270 271static int create_msi_irq(struct irq_chip *chip) 272{ 273 struct msi_desc *entry; 274 int irq; 275 276 entry = alloc_msi_entry(); 277 if (!entry) 278 return -ENOMEM; 279 280 irq = create_irq(); 281 if (irq < 0) { 282 kmem_cache_free(msi_cachep, entry); 283 return -EBUSY; 284 } 285 286 set_irq_chip_and_handler(irq, chip, handle_edge_irq); 287 set_irq_data(irq, entry); 288 289 return irq; 290} 291 292static void destroy_msi_irq(unsigned int irq) 293{ 294 struct msi_desc *entry; 295 296 entry = get_irq_data(irq); 297 set_irq_chip(irq, NULL); 298 set_irq_data(irq, NULL); 299 destroy_irq(irq); 300 kmem_cache_free(msi_cachep, entry); 301} 302 303static void enable_msi_mode(struct pci_dev *dev, int pos, int type) 304{ 305 u16 control; 306 307 pci_read_config_word(dev, msi_control_reg(pos), &control); 308 if (type == PCI_CAP_ID_MSI) { 309 /* Set enabled bits to single MSI & enable MSI_enable bit */ 310 msi_enable(control, 1); 311 pci_write_config_word(dev, msi_control_reg(pos), control); 312 dev->msi_enabled = 1; 313 } else { 314 msix_enable(control); 315 pci_write_config_word(dev, msi_control_reg(pos), control); 316 dev->msix_enabled = 1; 317 } 318 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 319 /* PCI Express Endpoint device detected */ 320 pci_intx(dev, 0); /* disable intx */ 321 } 322} 323 324void disable_msi_mode(struct pci_dev *dev, int pos, int type) 325{ 326 u16 control; 327 328 pci_read_config_word(dev, msi_control_reg(pos), &control); 329 if (type == PCI_CAP_ID_MSI) { 330 /* Set enabled bits to single MSI & enable MSI_enable bit */ 331 msi_disable(control); 332 pci_write_config_word(dev, msi_control_reg(pos), control); 333 dev->msi_enabled = 0; 334 } else { 335 msix_disable(control); 336 pci_write_config_word(dev, msi_control_reg(pos), control); 337 dev->msix_enabled = 0; 338 } 339 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 340 /* PCI Express Endpoint device detected */ 341 pci_intx(dev, 1); /* enable intx */ 342 } 343} 344 345static int msi_lookup_irq(struct pci_dev *dev, int type) 346{ 347 int irq; 348 unsigned long flags; 349 350 spin_lock_irqsave(&msi_lock, flags); 351 for (irq = 0; irq < NR_IRQS; irq++) { 352 if (!msi_desc[irq] || msi_desc[irq]->dev != dev || 353 msi_desc[irq]->msi_attrib.type != type || 354 msi_desc[irq]->msi_attrib.default_irq != dev->irq) 355 continue; 356 spin_unlock_irqrestore(&msi_lock, flags); 357 /* This pre-assigned MSI irq for this device 358 already exits. Override dev->irq with this irq */ 359 dev->irq = irq; 360 return 0; 361 } 362 spin_unlock_irqrestore(&msi_lock, flags); 363 364 return -EACCES; 365} 366 367void pci_scan_msi_device(struct pci_dev *dev) 368{ 369 if (!dev) 370 return; 371} 372 373#ifdef CONFIG_PM 374int pci_save_msi_state(struct pci_dev *dev) 375{ 376 int pos, i = 0; 377 u16 control; 378 struct pci_cap_saved_state *save_state; 379 u32 *cap; 380 381 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 382 if (pos <= 0 || dev->no_msi) 383 return 0; 384 385 pci_read_config_word(dev, msi_control_reg(pos), &control); 386 if (!(control & PCI_MSI_FLAGS_ENABLE)) 387 return 0; 388 389 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, 390 GFP_KERNEL); 391 if (!save_state) { 392 printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); 393 return -ENOMEM; 394 } 395 cap = &save_state->data[0]; 396 397 pci_read_config_dword(dev, pos, &cap[i++]); 398 control = cap[0] >> 16; 399 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); 400 if (control & PCI_MSI_FLAGS_64BIT) { 401 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); 402 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); 403 } else 404 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); 405 if (control & PCI_MSI_FLAGS_MASKBIT) 406 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); 407 save_state->cap_nr = PCI_CAP_ID_MSI; 408 pci_add_saved_cap(dev, save_state); 409 return 0; 410} 411 412void pci_restore_msi_state(struct pci_dev *dev) 413{ 414 int i = 0, pos; 415 u16 control; 416 struct pci_cap_saved_state *save_state; 417 u32 *cap; 418 419 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); 420 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 421 if (!save_state || pos <= 0) 422 return; 423 cap = &save_state->data[0]; 424 425 control = cap[i++] >> 16; 426 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); 427 if (control & PCI_MSI_FLAGS_64BIT) { 428 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); 429 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); 430 } else 431 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); 432 if (control & PCI_MSI_FLAGS_MASKBIT) 433 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); 434 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 435 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 436 pci_remove_saved_cap(save_state); 437 kfree(save_state); 438} 439 440int pci_save_msix_state(struct pci_dev *dev) 441{ 442 int pos; 443 int temp; 444 int irq, head, tail = 0; 445 u16 control; 446 struct pci_cap_saved_state *save_state; 447 448 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 449 if (pos <= 0 || dev->no_msi) 450 return 0; 451 452 /* save the capability */ 453 pci_read_config_word(dev, msi_control_reg(pos), &control); 454 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 455 return 0; 456 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), 457 GFP_KERNEL); 458 if (!save_state) { 459 printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); 460 return -ENOMEM; 461 } 462 *((u16 *)&save_state->data[0]) = control; 463 464 /* save the table */ 465 temp = dev->irq; 466 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { 467 kfree(save_state); 468 return -EINVAL; 469 } 470 471 irq = head = dev->irq; 472 while (head != tail) { 473 struct msi_desc *entry; 474 475 entry = msi_desc[irq]; 476 read_msi_msg(entry, &entry->msg_save); 477 478 tail = msi_desc[irq]->link.tail; 479 irq = tail; 480 } 481 dev->irq = temp; 482 483 save_state->cap_nr = PCI_CAP_ID_MSIX; 484 pci_add_saved_cap(dev, save_state); 485 return 0; 486} 487 488void pci_restore_msix_state(struct pci_dev *dev) 489{ 490 u16 save; 491 int pos; 492 int irq, head, tail = 0; 493 struct msi_desc *entry; 494 int temp; 495 struct pci_cap_saved_state *save_state; 496 497 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); 498 if (!save_state) 499 return; 500 save = *((u16 *)&save_state->data[0]); 501 pci_remove_saved_cap(save_state); 502 kfree(save_state); 503 504 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 505 if (pos <= 0) 506 return; 507 508 /* route the table */ 509 temp = dev->irq; 510 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) 511 return; 512 irq = head = dev->irq; 513 while (head != tail) { 514 entry = msi_desc[irq]; 515 write_msi_msg(entry, &entry->msg_save); 516 517 tail = msi_desc[irq]->link.tail; 518 irq = tail; 519 } 520 dev->irq = temp; 521 522 pci_write_config_word(dev, msi_control_reg(pos), save); 523 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 524} 525#endif 526 527static int msi_register_init(struct pci_dev *dev, struct msi_desc *entry) 528{ 529 int status; 530 struct msi_msg msg; 531 int pos; 532 u16 control; 533 534 pos = entry->msi_attrib.pos; 535 pci_read_config_word(dev, msi_control_reg(pos), &control); 536 537 /* Configure MSI capability structure */ 538 status = msi_ops->setup(dev, dev->irq, &msg); 539 if (status < 0) 540 return status; 541 542 write_msi_msg(entry, &msg); 543 if (entry->msi_attrib.maskbit) { 544 unsigned int maskbits, temp; 545 /* All MSIs are unmasked by default, Mask them all */ 546 pci_read_config_dword(dev, 547 msi_mask_bits_reg(pos, is_64bit_address(control)), 548 &maskbits); 549 temp = (1 << multi_msi_capable(control)); 550 temp = ((temp - 1) & ~temp); 551 maskbits |= temp; 552 pci_write_config_dword(dev, 553 msi_mask_bits_reg(pos, is_64bit_address(control)), 554 maskbits); 555 } 556 557 return 0; 558} 559 560/** 561 * msi_capability_init - configure device's MSI capability structure 562 * @dev: pointer to the pci_dev data structure of MSI device function 563 * 564 * Setup the MSI capability structure of device function with a single 565 * MSI irq, regardless of device function is capable of handling 566 * multiple messages. A return of zero indicates the successful setup 567 * of an entry zero with the new MSI irq or non-zero for otherwise. 568 **/ 569static int msi_capability_init(struct pci_dev *dev) 570{ 571 int status; 572 struct msi_desc *entry; 573 int pos, irq; 574 u16 control; 575 576 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 577 pci_read_config_word(dev, msi_control_reg(pos), &control); 578 /* MSI Entry Initialization */ 579 irq = create_msi_irq(&msi_chip); 580 if (irq < 0) 581 return irq; 582 583 entry = get_irq_data(irq); 584 entry->link.head = irq; 585 entry->link.tail = irq; 586 entry->msi_attrib.type = PCI_CAP_ID_MSI; 587 entry->msi_attrib.is_64 = is_64bit_address(control); 588 entry->msi_attrib.entry_nr = 0; 589 entry->msi_attrib.maskbit = is_mask_bit_support(control); 590 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 591 entry->msi_attrib.pos = pos; 592 dev->irq = irq; 593 entry->dev = dev; 594 if (is_mask_bit_support(control)) { 595 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, 596 is_64bit_address(control)); 597 } 598 /* Configure MSI capability structure */ 599 status = msi_register_init(dev, entry); 600 if (status != 0) { 601 dev->irq = entry->msi_attrib.default_irq; 602 destroy_msi_irq(irq); 603 return status; 604 } 605 606 attach_msi_entry(entry, irq); 607 /* Set MSI enabled bits */ 608 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 609 610 return 0; 611} 612 613/** 614 * msix_capability_init - configure device's MSI-X capability 615 * @dev: pointer to the pci_dev data structure of MSI-X device function 616 * @entries: pointer to an array of struct msix_entry entries 617 * @nvec: number of @entries 618 * 619 * Setup the MSI-X capability structure of device function with a 620 * single MSI-X irq. A return of zero indicates the successful setup of 621 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 622 **/ 623static int msix_capability_init(struct pci_dev *dev, 624 struct msix_entry *entries, int nvec) 625{ 626 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; 627 struct msi_msg msg; 628 int status; 629 int irq, pos, i, j, nr_entries, temp = 0; 630 unsigned long phys_addr; 631 u32 table_offset; 632 u16 control; 633 u8 bir; 634 void __iomem *base; 635 636 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 637 /* Request & Map MSI-X table region */ 638 pci_read_config_word(dev, msi_control_reg(pos), &control); 639 nr_entries = multi_msix_capable(control); 640 641 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 642 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 643 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 644 phys_addr = pci_resource_start (dev, bir) + table_offset; 645 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 646 if (base == NULL) 647 return -ENOMEM; 648 649 /* MSI-X Table Initialization */ 650 for (i = 0; i < nvec; i++) { 651 irq = create_msi_irq(&msi_chip); 652 if (irq < 0) 653 break; 654 655 entry = get_irq_data(irq); 656 j = entries[i].entry; 657 entries[i].vector = irq; 658 entry->msi_attrib.type = PCI_CAP_ID_MSIX; 659 entry->msi_attrib.is_64 = 1; 660 entry->msi_attrib.entry_nr = j; 661 entry->msi_attrib.maskbit = 1; 662 entry->msi_attrib.default_irq = dev->irq; 663 entry->msi_attrib.pos = pos; 664 entry->dev = dev; 665 entry->mask_base = base; 666 if (!head) { 667 entry->link.head = irq; 668 entry->link.tail = irq; 669 head = entry; 670 } else { 671 entry->link.head = temp; 672 entry->link.tail = tail->link.tail; 673 tail->link.tail = irq; 674 head->link.head = irq; 675 } 676 temp = irq; 677 tail = entry; 678 /* Configure MSI-X capability structure */ 679 status = msi_ops->setup(dev, irq, &msg); 680 if (status < 0) { 681 destroy_msi_irq(irq); 682 break; 683 } 684 685 write_msi_msg(entry, &msg); 686 attach_msi_entry(entry, irq); 687 } 688 if (i != nvec) { 689 int avail = i - 1; 690 i--; 691 for (; i >= 0; i--) { 692 irq = (entries + i)->vector; 693 msi_free_irq(dev, irq); 694 (entries + i)->vector = 0; 695 } 696 /* If we had some success report the number of irqs 697 * we succeeded in setting up. 698 */ 699 if (avail <= 0) 700 avail = -EBUSY; 701 return avail; 702 } 703 /* Set MSI-X enabled bits */ 704 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 705 706 return 0; 707} 708 709/** 710 * pci_msi_supported - check whether MSI may be enabled on device 711 * @dev: pointer to the pci_dev data structure of MSI device function 712 * 713 * MSI must be globally enabled and supported by the device and its root 714 * bus. But, the root bus is not easy to find since some architectures 715 * have virtual busses on top of the PCI hierarchy (for instance the 716 * hypertransport bus), while the actual bus where MSI must be supported 717 * is below. So we test the MSI flag on all parent busses and assume 718 * that no quirk will ever set the NO_MSI flag on a non-root bus. 719 **/ 720static 721int pci_msi_supported(struct pci_dev * dev) 722{ 723 struct pci_bus *bus; 724 725 if (!pci_msi_enable || !dev || dev->no_msi) 726 return -EINVAL; 727 728 /* check MSI flags of all parent busses */ 729 for (bus = dev->bus; bus; bus = bus->parent) 730 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 731 return -EINVAL; 732 733 return 0; 734} 735 736/** 737 * pci_enable_msi - configure device's MSI capability structure 738 * @dev: pointer to the pci_dev data structure of MSI device function 739 * 740 * Setup the MSI capability structure of device function with 741 * a single MSI irq upon its software driver call to request for 742 * MSI mode enabled on its hardware device function. A return of zero 743 * indicates the successful setup of an entry zero with the new MSI 744 * irq or non-zero for otherwise. 745 **/ 746int pci_enable_msi(struct pci_dev* dev) 747{ 748 int pos, temp, status; 749 u16 control; 750 751 if (pci_msi_supported(dev) < 0) 752 return -EINVAL; 753 754 temp = dev->irq; 755 756 status = msi_init(); 757 if (status < 0) 758 return status; 759 760 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 761 if (!pos) 762 return -EINVAL; 763 764 pci_read_config_word(dev, msi_control_reg(pos), &control); 765 if (!is_64bit_address(control) && msi_ops->needs_64bit_address) 766 return -EINVAL; 767 768 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI)); 769 770 /* Check whether driver already requested for MSI-X irqs */ 771 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 772 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { 773 printk(KERN_INFO "PCI: %s: Can't enable MSI. " 774 "Device already has MSI-X irq assigned\n", 775 pci_name(dev)); 776 dev->irq = temp; 777 return -EINVAL; 778 } 779 status = msi_capability_init(dev); 780 return status; 781} 782 783void pci_disable_msi(struct pci_dev* dev) 784{ 785 struct msi_desc *entry; 786 int pos, default_irq; 787 u16 control; 788 unsigned long flags; 789 790 if (!pci_msi_enable) 791 return; 792 if (!dev) 793 return; 794 795 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 796 if (!pos) 797 return; 798 799 pci_read_config_word(dev, msi_control_reg(pos), &control); 800 if (!(control & PCI_MSI_FLAGS_ENABLE)) 801 return; 802 803 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 804 805 spin_lock_irqsave(&msi_lock, flags); 806 entry = msi_desc[dev->irq]; 807 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { 808 spin_unlock_irqrestore(&msi_lock, flags); 809 return; 810 } 811 if (irq_has_action(dev->irq)) { 812 spin_unlock_irqrestore(&msi_lock, flags); 813 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " 814 "free_irq() on MSI irq %d\n", 815 pci_name(dev), dev->irq); 816 BUG_ON(irq_has_action(dev->irq)); 817 } else { 818 default_irq = entry->msi_attrib.default_irq; 819 spin_unlock_irqrestore(&msi_lock, flags); 820 msi_free_irq(dev, dev->irq); 821 822 /* Restore dev->irq to its default pin-assertion irq */ 823 dev->irq = default_irq; 824 } 825} 826 827static int msi_free_irq(struct pci_dev* dev, int irq) 828{ 829 struct msi_desc *entry; 830 int head, entry_nr, type; 831 void __iomem *base; 832 unsigned long flags; 833 834 msi_ops->teardown(irq); 835 836 spin_lock_irqsave(&msi_lock, flags); 837 entry = msi_desc[irq]; 838 if (!entry || entry->dev != dev) { 839 spin_unlock_irqrestore(&msi_lock, flags); 840 return -EINVAL; 841 } 842 type = entry->msi_attrib.type; 843 entry_nr = entry->msi_attrib.entry_nr; 844 head = entry->link.head; 845 base = entry->mask_base; 846 msi_desc[entry->link.head]->link.tail = entry->link.tail; 847 msi_desc[entry->link.tail]->link.head = entry->link.head; 848 entry->dev = NULL; 849 msi_desc[irq] = NULL; 850 spin_unlock_irqrestore(&msi_lock, flags); 851 852 destroy_msi_irq(irq); 853 854 if (type == PCI_CAP_ID_MSIX) { 855 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + 856 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 857 858 if (head == irq) 859 iounmap(base); 860 } 861 862 return 0; 863} 864 865/** 866 * pci_enable_msix - configure device's MSI-X capability structure 867 * @dev: pointer to the pci_dev data structure of MSI-X device function 868 * @entries: pointer to an array of MSI-X entries 869 * @nvec: number of MSI-X irqs requested for allocation by device driver 870 * 871 * Setup the MSI-X capability structure of device function with the number 872 * of requested irqs upon its software driver call to request for 873 * MSI-X mode enabled on its hardware device function. A return of zero 874 * indicates the successful configuration of MSI-X capability structure 875 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 876 * Or a return of > 0 indicates that driver request is exceeding the number 877 * of irqs available. Driver should use the returned value to re-send 878 * its request. 879 **/ 880int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 881{ 882 int status, pos, nr_entries; 883 int i, j, temp; 884 u16 control; 885 886 if (!entries || pci_msi_supported(dev) < 0) 887 return -EINVAL; 888 889 status = msi_init(); 890 if (status < 0) 891 return status; 892 893 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 894 if (!pos) 895 return -EINVAL; 896 897 pci_read_config_word(dev, msi_control_reg(pos), &control); 898 nr_entries = multi_msix_capable(control); 899 if (nvec > nr_entries) 900 return -EINVAL; 901 902 /* Check for any invalid entries */ 903 for (i = 0; i < nvec; i++) { 904 if (entries[i].entry >= nr_entries) 905 return -EINVAL; /* invalid entry */ 906 for (j = i + 1; j < nvec; j++) { 907 if (entries[i].entry == entries[j].entry) 908 return -EINVAL; /* duplicate entry */ 909 } 910 } 911 temp = dev->irq; 912 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)); 913 914 /* Check whether driver already requested for MSI irq */ 915 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && 916 !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { 917 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " 918 "Device already has an MSI irq assigned\n", 919 pci_name(dev)); 920 dev->irq = temp; 921 return -EINVAL; 922 } 923 status = msix_capability_init(dev, entries, nvec); 924 return status; 925} 926 927void pci_disable_msix(struct pci_dev* dev) 928{ 929 int pos, temp; 930 u16 control; 931 932 if (!pci_msi_enable) 933 return; 934 if (!dev) 935 return; 936 937 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 938 if (!pos) 939 return; 940 941 pci_read_config_word(dev, msi_control_reg(pos), &control); 942 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 943 return; 944 945 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 946 947 temp = dev->irq; 948 if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { 949 int irq, head, tail = 0, warning = 0; 950 unsigned long flags; 951 952 irq = head = dev->irq; 953 dev->irq = temp; /* Restore pin IRQ */ 954 while (head != tail) { 955 spin_lock_irqsave(&msi_lock, flags); 956 tail = msi_desc[irq]->link.tail; 957 spin_unlock_irqrestore(&msi_lock, flags); 958 if (irq_has_action(irq)) 959 warning = 1; 960 else if (irq != head) /* Release MSI-X irq */ 961 msi_free_irq(dev, irq); 962 irq = tail; 963 } 964 msi_free_irq(dev, irq); 965 if (warning) { 966 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " 967 "free_irq() on all MSI-X irqs\n", 968 pci_name(dev)); 969 BUG_ON(warning > 0); 970 } 971 } 972} 973 974/** 975 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 976 * @dev: pointer to the pci_dev data structure of MSI(X) device function 977 * 978 * Being called during hotplug remove, from which the device function 979 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 980 * allocated for this device function, are reclaimed to unused state, 981 * which may be used later on. 982 **/ 983void msi_remove_pci_irq_vectors(struct pci_dev* dev) 984{ 985 int pos, temp; 986 unsigned long flags; 987 988 if (!pci_msi_enable || !dev) 989 return; 990 991 temp = dev->irq; /* Save IOAPIC IRQ */ 992 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 993 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { 994 if (irq_has_action(dev->irq)) { 995 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 996 "called without free_irq() on MSI irq %d\n", 997 pci_name(dev), dev->irq); 998 BUG_ON(irq_has_action(dev->irq)); 999 } else /* Release MSI irq assigned to this device */ 1000 msi_free_irq(dev, dev->irq); 1001 dev->irq = temp; /* Restore IOAPIC IRQ */ 1002 } 1003 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1004 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { 1005 int irq, head, tail = 0, warning = 0; 1006 void __iomem *base = NULL; 1007 1008 irq = head = dev->irq; 1009 while (head != tail) { 1010 spin_lock_irqsave(&msi_lock, flags); 1011 tail = msi_desc[irq]->link.tail; 1012 base = msi_desc[irq]->mask_base; 1013 spin_unlock_irqrestore(&msi_lock, flags); 1014 if (irq_has_action(irq)) 1015 warning = 1; 1016 else if (irq != head) /* Release MSI-X irq */ 1017 msi_free_irq(dev, irq); 1018 irq = tail; 1019 } 1020 msi_free_irq(dev, irq); 1021 if (warning) { 1022 iounmap(base); 1023 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 1024 "called without free_irq() on all MSI-X irqs\n", 1025 pci_name(dev)); 1026 BUG_ON(warning > 0); 1027 } 1028 dev->irq = temp; /* Restore IOAPIC IRQ */ 1029 } 1030} 1031 1032void pci_no_msi(void) 1033{ 1034 pci_msi_enable = 0; 1035} 1036 1037EXPORT_SYMBOL(pci_enable_msi); 1038EXPORT_SYMBOL(pci_disable_msi); 1039EXPORT_SYMBOL(pci_enable_msix); 1040EXPORT_SYMBOL(pci_disable_msix); 1041