msi.c revision 2c21fd4b333e4c780a46edcd6d1e85bfc6cdf371
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17#include <linux/msi.h> 18#include <linux/smp.h> 19 20#include <asm/errno.h> 21#include <asm/io.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static int pci_msi_enable = 1; 27 28/* Arch hooks */ 29 30#ifndef arch_msi_check_device 31int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) 32{ 33 return 0; 34} 35#endif 36 37#ifndef arch_setup_msi_irqs 38int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 39{ 40 struct msi_desc *entry; 41 int ret; 42 43 /* 44 * If an architecture wants to support multiple MSI, it needs to 45 * override arch_setup_msi_irqs() 46 */ 47 if (type == PCI_CAP_ID_MSI && nvec > 1) 48 return 1; 49 50 list_for_each_entry(entry, &dev->msi_list, list) { 51 ret = arch_setup_msi_irq(dev, entry); 52 if (ret < 0) 53 return ret; 54 if (ret > 0) 55 return -ENOSPC; 56 } 57 58 return 0; 59} 60#endif 61 62#ifndef arch_teardown_msi_irqs 63void arch_teardown_msi_irqs(struct pci_dev *dev) 64{ 65 struct msi_desc *entry; 66 67 list_for_each_entry(entry, &dev->msi_list, list) { 68 int i, nvec; 69 if (entry->irq == 0) 70 continue; 71 nvec = 1 << entry->msi_attrib.multiple; 72 for (i = 0; i < nvec; i++) 73 arch_teardown_msi_irq(entry->irq + i); 74 } 75} 76#endif 77 78static void msi_set_enable(struct pci_dev *dev, int pos, int enable) 79{ 80 u16 control; 81 82 BUG_ON(!pos); 83 84 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 85 control &= ~PCI_MSI_FLAGS_ENABLE; 86 if (enable) 87 control |= PCI_MSI_FLAGS_ENABLE; 88 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 89} 90 91static void msix_set_enable(struct pci_dev *dev, int enable) 92{ 93 int pos; 94 u16 control; 95 96 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 97 if (pos) { 98 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 99 control &= ~PCI_MSIX_FLAGS_ENABLE; 100 if (enable) 101 control |= PCI_MSIX_FLAGS_ENABLE; 102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 103 } 104} 105 106static inline __attribute_const__ u32 msi_mask(unsigned x) 107{ 108 /* Don't shift by >= width of type */ 109 if (x >= 5) 110 return 0xffffffff; 111 return (1 << (1 << x)) - 1; 112} 113 114static inline __attribute_const__ u32 msi_capable_mask(u16 control) 115{ 116 return msi_mask((control >> 1) & 7); 117} 118 119static inline __attribute_const__ u32 msi_enabled_mask(u16 control) 120{ 121 return msi_mask((control >> 4) & 7); 122} 123 124/* 125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to 126 * mask all MSI interrupts by clearing the MSI enable bit does not work 127 * reliably as devices without an INTx disable bit will then generate a 128 * level IRQ which will never be cleared. 129 */ 130static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) 131{ 132 u32 mask_bits = desc->masked; 133 134 if (!desc->msi_attrib.maskbit) 135 return; 136 137 mask_bits &= ~mask; 138 mask_bits |= flag; 139 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); 140 desc->masked = mask_bits; 141} 142 143/* 144 * This internal function does not flush PCI writes to the device. 145 * All users must ensure that they read from the device before either 146 * assuming that the device state is up to date, or returning out of this 147 * file. This saves a few milliseconds when initialising devices with lots 148 * of MSI-X interrupts. 149 */ 150static void msix_mask_irq(struct msi_desc *desc, u32 flag) 151{ 152 u32 mask_bits = desc->masked; 153 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 154 PCI_MSIX_ENTRY_VECTOR_CTRL; 155 mask_bits &= ~1; 156 mask_bits |= flag; 157 writel(mask_bits, desc->mask_base + offset); 158 desc->masked = mask_bits; 159} 160 161static void msi_set_mask_bit(unsigned irq, u32 flag) 162{ 163 struct msi_desc *desc = get_irq_msi(irq); 164 165 if (desc->msi_attrib.is_msix) { 166 msix_mask_irq(desc, flag); 167 readl(desc->mask_base); /* Flush write to device */ 168 } else { 169 unsigned offset = irq - desc->dev->irq; 170 msi_mask_irq(desc, 1 << offset, flag << offset); 171 } 172} 173 174void mask_msi_irq(unsigned int irq) 175{ 176 msi_set_mask_bit(irq, 1); 177} 178 179void unmask_msi_irq(unsigned int irq) 180{ 181 msi_set_mask_bit(irq, 0); 182} 183 184void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 185{ 186 struct msi_desc *entry = get_irq_desc_msi(desc); 187 if (entry->msi_attrib.is_msix) { 188 void __iomem *base = entry->mask_base + 189 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 190 191 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); 192 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); 193 msg->data = readl(base + PCI_MSIX_ENTRY_DATA); 194 } else { 195 struct pci_dev *dev = entry->dev; 196 int pos = entry->msi_attrib.pos; 197 u16 data; 198 199 pci_read_config_dword(dev, msi_lower_address_reg(pos), 200 &msg->address_lo); 201 if (entry->msi_attrib.is_64) { 202 pci_read_config_dword(dev, msi_upper_address_reg(pos), 203 &msg->address_hi); 204 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 205 } else { 206 msg->address_hi = 0; 207 pci_read_config_word(dev, msi_data_reg(pos, 0), &data); 208 } 209 msg->data = data; 210 } 211} 212 213void read_msi_msg(unsigned int irq, struct msi_msg *msg) 214{ 215 struct irq_desc *desc = irq_to_desc(irq); 216 217 read_msi_msg_desc(desc, msg); 218} 219 220void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 221{ 222 struct msi_desc *entry = get_irq_desc_msi(desc); 223 if (entry->msi_attrib.is_msix) { 224 void __iomem *base; 225 base = entry->mask_base + 226 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 227 228 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); 229 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); 230 writel(msg->data, base + PCI_MSIX_ENTRY_DATA); 231 } else { 232 struct pci_dev *dev = entry->dev; 233 int pos = entry->msi_attrib.pos; 234 u16 msgctl; 235 236 pci_read_config_word(dev, msi_control_reg(pos), &msgctl); 237 msgctl &= ~PCI_MSI_FLAGS_QSIZE; 238 msgctl |= entry->msi_attrib.multiple << 4; 239 pci_write_config_word(dev, msi_control_reg(pos), msgctl); 240 241 pci_write_config_dword(dev, msi_lower_address_reg(pos), 242 msg->address_lo); 243 if (entry->msi_attrib.is_64) { 244 pci_write_config_dword(dev, msi_upper_address_reg(pos), 245 msg->address_hi); 246 pci_write_config_word(dev, msi_data_reg(pos, 1), 247 msg->data); 248 } else { 249 pci_write_config_word(dev, msi_data_reg(pos, 0), 250 msg->data); 251 } 252 } 253 entry->msg = *msg; 254} 255 256void write_msi_msg(unsigned int irq, struct msi_msg *msg) 257{ 258 struct irq_desc *desc = irq_to_desc(irq); 259 260 write_msi_msg_desc(desc, msg); 261} 262 263static int msi_free_irqs(struct pci_dev* dev); 264 265static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) 266{ 267 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); 268 if (!desc) 269 return NULL; 270 271 INIT_LIST_HEAD(&desc->list); 272 desc->dev = dev; 273 274 return desc; 275} 276 277static void pci_intx_for_msi(struct pci_dev *dev, int enable) 278{ 279 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) 280 pci_intx(dev, enable); 281} 282 283static void __pci_restore_msi_state(struct pci_dev *dev) 284{ 285 int pos; 286 u16 control; 287 struct msi_desc *entry; 288 289 if (!dev->msi_enabled) 290 return; 291 292 entry = get_irq_msi(dev->irq); 293 pos = entry->msi_attrib.pos; 294 295 pci_intx_for_msi(dev, 0); 296 msi_set_enable(dev, pos, 0); 297 write_msi_msg(dev->irq, &entry->msg); 298 299 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 300 msi_mask_irq(entry, msi_capable_mask(control), entry->masked); 301 control &= ~PCI_MSI_FLAGS_QSIZE; 302 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; 303 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 304} 305 306static void __pci_restore_msix_state(struct pci_dev *dev) 307{ 308 int pos; 309 struct msi_desc *entry; 310 u16 control; 311 312 if (!dev->msix_enabled) 313 return; 314 BUG_ON(list_empty(&dev->msi_list)); 315 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 316 pos = entry->msi_attrib.pos; 317 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 318 319 /* route the table */ 320 pci_intx_for_msi(dev, 0); 321 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; 322 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 323 324 list_for_each_entry(entry, &dev->msi_list, list) { 325 write_msi_msg(entry->irq, &entry->msg); 326 msix_mask_irq(entry, entry->masked); 327 } 328 329 control &= ~PCI_MSIX_FLAGS_MASKALL; 330 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 331} 332 333void pci_restore_msi_state(struct pci_dev *dev) 334{ 335 __pci_restore_msi_state(dev); 336 __pci_restore_msix_state(dev); 337} 338EXPORT_SYMBOL_GPL(pci_restore_msi_state); 339 340/** 341 * msi_capability_init - configure device's MSI capability structure 342 * @dev: pointer to the pci_dev data structure of MSI device function 343 * @nvec: number of interrupts to allocate 344 * 345 * Setup the MSI capability structure of the device with the requested 346 * number of interrupts. A return value of zero indicates the successful 347 * setup of an entry with the new MSI irq. A negative return value indicates 348 * an error, and a positive return value indicates the number of interrupts 349 * which could have been allocated. 350 */ 351static int msi_capability_init(struct pci_dev *dev, int nvec) 352{ 353 struct msi_desc *entry; 354 int pos, ret; 355 u16 control; 356 unsigned mask; 357 358 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 359 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ 360 361 pci_read_config_word(dev, msi_control_reg(pos), &control); 362 /* MSI Entry Initialization */ 363 entry = alloc_msi_entry(dev); 364 if (!entry) 365 return -ENOMEM; 366 367 entry->msi_attrib.is_msix = 0; 368 entry->msi_attrib.is_64 = is_64bit_address(control); 369 entry->msi_attrib.entry_nr = 0; 370 entry->msi_attrib.maskbit = is_mask_bit_support(control); 371 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 372 entry->msi_attrib.pos = pos; 373 374 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); 375 /* All MSIs are unmasked by default, Mask them all */ 376 if (entry->msi_attrib.maskbit) 377 pci_read_config_dword(dev, entry->mask_pos, &entry->masked); 378 mask = msi_capable_mask(control); 379 msi_mask_irq(entry, mask, mask); 380 381 list_add_tail(&entry->list, &dev->msi_list); 382 383 /* Configure MSI capability structure */ 384 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); 385 if (ret) { 386 msi_free_irqs(dev); 387 return ret; 388 } 389 390 /* Set MSI enabled bits */ 391 pci_intx_for_msi(dev, 0); 392 msi_set_enable(dev, pos, 1); 393 dev->msi_enabled = 1; 394 395 dev->irq = entry->irq; 396 return 0; 397} 398 399/** 400 * msix_capability_init - configure device's MSI-X capability 401 * @dev: pointer to the pci_dev data structure of MSI-X device function 402 * @entries: pointer to an array of struct msix_entry entries 403 * @nvec: number of @entries 404 * 405 * Setup the MSI-X capability structure of device function with a 406 * single MSI-X irq. A return of zero indicates the successful setup of 407 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 408 **/ 409static int msix_capability_init(struct pci_dev *dev, 410 struct msix_entry *entries, int nvec) 411{ 412 struct msi_desc *entry; 413 int pos, i, j, nr_entries, ret; 414 unsigned long phys_addr; 415 u32 table_offset; 416 u16 control; 417 u8 bir; 418 void __iomem *base; 419 420 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 421 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 422 423 /* Ensure MSI-X is disabled while it is set up */ 424 control &= ~PCI_MSIX_FLAGS_ENABLE; 425 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 426 427 /* Request & Map MSI-X table region */ 428 nr_entries = multi_msix_capable(control); 429 430 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 431 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 432 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 433 phys_addr = pci_resource_start (dev, bir) + table_offset; 434 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 435 if (base == NULL) 436 return -ENOMEM; 437 438 for (i = 0; i < nvec; i++) { 439 entry = alloc_msi_entry(dev); 440 if (!entry) { 441 if (!i) 442 iounmap(base); 443 else 444 msi_free_irqs(dev); 445 /* No enough memory. Don't try again */ 446 return -ENOMEM; 447 } 448 449 j = entries[i].entry; 450 entry->msi_attrib.is_msix = 1; 451 entry->msi_attrib.is_64 = 1; 452 entry->msi_attrib.entry_nr = j; 453 entry->msi_attrib.default_irq = dev->irq; 454 entry->msi_attrib.pos = pos; 455 entry->mask_base = base; 456 457 list_add_tail(&entry->list, &dev->msi_list); 458 } 459 460 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); 461 if (ret < 0) { 462 /* If we had some success report the number of irqs 463 * we succeeded in setting up. */ 464 int avail = 0; 465 list_for_each_entry(entry, &dev->msi_list, list) { 466 if (entry->irq != 0) { 467 avail++; 468 } 469 } 470 471 if (avail != 0) 472 ret = avail; 473 } 474 475 if (ret) { 476 msi_free_irqs(dev); 477 return ret; 478 } 479 480 /* 481 * Some devices require MSI-X to be enabled before we can touch the 482 * MSI-X registers. We need to mask all the vectors to prevent 483 * interrupts coming in before they're fully set up. 484 */ 485 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; 486 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 487 488 i = 0; 489 list_for_each_entry(entry, &dev->msi_list, list) { 490 entries[i].vector = entry->irq; 491 set_irq_msi(entry->irq, entry); 492 j = entries[i].entry; 493 entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE + 494 PCI_MSIX_ENTRY_VECTOR_CTRL); 495 msix_mask_irq(entry, 1); 496 i++; 497 } 498 499 /* Set MSI-X enabled bits and unmask the function */ 500 pci_intx_for_msi(dev, 0); 501 dev->msix_enabled = 1; 502 503 control &= ~PCI_MSIX_FLAGS_MASKALL; 504 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 505 506 return 0; 507} 508 509/** 510 * pci_msi_check_device - check whether MSI may be enabled on a device 511 * @dev: pointer to the pci_dev data structure of MSI device function 512 * @nvec: how many MSIs have been requested ? 513 * @type: are we checking for MSI or MSI-X ? 514 * 515 * Look at global flags, the device itself, and its parent busses 516 * to determine if MSI/-X are supported for the device. If MSI/-X is 517 * supported return 0, else return an error code. 518 **/ 519static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) 520{ 521 struct pci_bus *bus; 522 int ret; 523 524 /* MSI must be globally enabled and supported by the device */ 525 if (!pci_msi_enable || !dev || dev->no_msi) 526 return -EINVAL; 527 528 /* 529 * You can't ask to have 0 or less MSIs configured. 530 * a) it's stupid .. 531 * b) the list manipulation code assumes nvec >= 1. 532 */ 533 if (nvec < 1) 534 return -ERANGE; 535 536 /* Any bridge which does NOT route MSI transactions from it's 537 * secondary bus to it's primary bus must set NO_MSI flag on 538 * the secondary pci_bus. 539 * We expect only arch-specific PCI host bus controller driver 540 * or quirks for specific PCI bridges to be setting NO_MSI. 541 */ 542 for (bus = dev->bus; bus; bus = bus->parent) 543 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 544 return -EINVAL; 545 546 ret = arch_msi_check_device(dev, nvec, type); 547 if (ret) 548 return ret; 549 550 if (!pci_find_capability(dev, type)) 551 return -EINVAL; 552 553 return 0; 554} 555 556/** 557 * pci_enable_msi_block - configure device's MSI capability structure 558 * @dev: device to configure 559 * @nvec: number of interrupts to configure 560 * 561 * Allocate IRQs for a device with the MSI capability. 562 * This function returns a negative errno if an error occurs. If it 563 * is unable to allocate the number of interrupts requested, it returns 564 * the number of interrupts it might be able to allocate. If it successfully 565 * allocates at least the number of interrupts requested, it returns 0 and 566 * updates the @dev's irq member to the lowest new interrupt number; the 567 * other interrupt numbers allocated to this device are consecutive. 568 */ 569int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 570{ 571 int status, pos, maxvec; 572 u16 msgctl; 573 574 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 575 if (!pos) 576 return -EINVAL; 577 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); 578 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); 579 if (nvec > maxvec) 580 return maxvec; 581 582 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); 583 if (status) 584 return status; 585 586 WARN_ON(!!dev->msi_enabled); 587 588 /* Check whether driver already requested MSI-X irqs */ 589 if (dev->msix_enabled) { 590 dev_info(&dev->dev, "can't enable MSI " 591 "(MSI-X already enabled)\n"); 592 return -EINVAL; 593 } 594 595 status = msi_capability_init(dev, nvec); 596 return status; 597} 598EXPORT_SYMBOL(pci_enable_msi_block); 599 600void pci_msi_shutdown(struct pci_dev *dev) 601{ 602 struct msi_desc *desc; 603 u32 mask; 604 u16 ctrl; 605 unsigned pos; 606 607 if (!pci_msi_enable || !dev || !dev->msi_enabled) 608 return; 609 610 BUG_ON(list_empty(&dev->msi_list)); 611 desc = list_first_entry(&dev->msi_list, struct msi_desc, list); 612 pos = desc->msi_attrib.pos; 613 614 msi_set_enable(dev, pos, 0); 615 pci_intx_for_msi(dev, 1); 616 dev->msi_enabled = 0; 617 618 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); 619 mask = msi_capable_mask(ctrl); 620 msi_mask_irq(desc, mask, ~mask); 621 622 /* Restore dev->irq to its default pin-assertion irq */ 623 dev->irq = desc->msi_attrib.default_irq; 624} 625 626void pci_disable_msi(struct pci_dev* dev) 627{ 628 struct msi_desc *entry; 629 630 if (!pci_msi_enable || !dev || !dev->msi_enabled) 631 return; 632 633 pci_msi_shutdown(dev); 634 635 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 636 if (entry->msi_attrib.is_msix) 637 return; 638 639 msi_free_irqs(dev); 640} 641EXPORT_SYMBOL(pci_disable_msi); 642 643static int msi_free_irqs(struct pci_dev* dev) 644{ 645 struct msi_desc *entry, *tmp; 646 647 list_for_each_entry(entry, &dev->msi_list, list) { 648 int i, nvec; 649 if (!entry->irq) 650 continue; 651 nvec = 1 << entry->msi_attrib.multiple; 652 for (i = 0; i < nvec; i++) 653 BUG_ON(irq_has_action(entry->irq + i)); 654 } 655 656 arch_teardown_msi_irqs(dev); 657 658 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { 659 if (entry->msi_attrib.is_msix) { 660 msix_mask_irq(entry, 1); 661 if (list_is_last(&entry->list, &dev->msi_list)) 662 iounmap(entry->mask_base); 663 } 664 list_del(&entry->list); 665 kfree(entry); 666 } 667 668 return 0; 669} 670 671/** 672 * pci_msix_table_size - return the number of device's MSI-X table entries 673 * @dev: pointer to the pci_dev data structure of MSI-X device function 674 */ 675int pci_msix_table_size(struct pci_dev *dev) 676{ 677 int pos; 678 u16 control; 679 680 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 681 if (!pos) 682 return 0; 683 684 pci_read_config_word(dev, msi_control_reg(pos), &control); 685 return multi_msix_capable(control); 686} 687 688/** 689 * pci_enable_msix - configure device's MSI-X capability structure 690 * @dev: pointer to the pci_dev data structure of MSI-X device function 691 * @entries: pointer to an array of MSI-X entries 692 * @nvec: number of MSI-X irqs requested for allocation by device driver 693 * 694 * Setup the MSI-X capability structure of device function with the number 695 * of requested irqs upon its software driver call to request for 696 * MSI-X mode enabled on its hardware device function. A return of zero 697 * indicates the successful configuration of MSI-X capability structure 698 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 699 * Or a return of > 0 indicates that driver request is exceeding the number 700 * of irqs or MSI-X vectors available. Driver should use the returned value to 701 * re-send its request. 702 **/ 703int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 704{ 705 int status, nr_entries; 706 int i, j; 707 708 if (!entries) 709 return -EINVAL; 710 711 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); 712 if (status) 713 return status; 714 715 nr_entries = pci_msix_table_size(dev); 716 if (nvec > nr_entries) 717 return nr_entries; 718 719 /* Check for any invalid entries */ 720 for (i = 0; i < nvec; i++) { 721 if (entries[i].entry >= nr_entries) 722 return -EINVAL; /* invalid entry */ 723 for (j = i + 1; j < nvec; j++) { 724 if (entries[i].entry == entries[j].entry) 725 return -EINVAL; /* duplicate entry */ 726 } 727 } 728 WARN_ON(!!dev->msix_enabled); 729 730 /* Check whether driver already requested for MSI irq */ 731 if (dev->msi_enabled) { 732 dev_info(&dev->dev, "can't enable MSI-X " 733 "(MSI IRQ already assigned)\n"); 734 return -EINVAL; 735 } 736 status = msix_capability_init(dev, entries, nvec); 737 return status; 738} 739EXPORT_SYMBOL(pci_enable_msix); 740 741static void msix_free_all_irqs(struct pci_dev *dev) 742{ 743 msi_free_irqs(dev); 744} 745 746void pci_msix_shutdown(struct pci_dev* dev) 747{ 748 if (!pci_msi_enable || !dev || !dev->msix_enabled) 749 return; 750 751 msix_set_enable(dev, 0); 752 pci_intx_for_msi(dev, 1); 753 dev->msix_enabled = 0; 754} 755void pci_disable_msix(struct pci_dev* dev) 756{ 757 if (!pci_msi_enable || !dev || !dev->msix_enabled) 758 return; 759 760 pci_msix_shutdown(dev); 761 762 msix_free_all_irqs(dev); 763} 764EXPORT_SYMBOL(pci_disable_msix); 765 766/** 767 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 768 * @dev: pointer to the pci_dev data structure of MSI(X) device function 769 * 770 * Being called during hotplug remove, from which the device function 771 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 772 * allocated for this device function, are reclaimed to unused state, 773 * which may be used later on. 774 **/ 775void msi_remove_pci_irq_vectors(struct pci_dev* dev) 776{ 777 if (!pci_msi_enable || !dev) 778 return; 779 780 if (dev->msi_enabled) 781 msi_free_irqs(dev); 782 783 if (dev->msix_enabled) 784 msix_free_all_irqs(dev); 785} 786 787void pci_no_msi(void) 788{ 789 pci_msi_enable = 0; 790} 791 792/** 793 * pci_msi_enabled - is MSI enabled? 794 * 795 * Returns true if MSI has not been disabled by the command-line option 796 * pci=nomsi. 797 **/ 798int pci_msi_enabled(void) 799{ 800 return pci_msi_enable; 801} 802EXPORT_SYMBOL(pci_msi_enabled); 803 804void pci_msi_init_pci_dev(struct pci_dev *dev) 805{ 806 INIT_LIST_HEAD(&dev->msi_list); 807} 808