msi.c revision 88187dfa4d8bb565df762f272511d2c91e427e0d
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/smp_lock.h> 16#include <linux/pci.h> 17#include <linux/proc_fs.h> 18#include <linux/msi.h> 19 20#include <asm/errno.h> 21#include <asm/io.h> 22#include <asm/smp.h> 23 24#include "pci.h" 25#include "msi.h" 26 27static DEFINE_SPINLOCK(msi_lock); 28static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; 29static struct kmem_cache* msi_cachep; 30 31static int pci_msi_enable = 1; 32 33static int msi_cache_init(void) 34{ 35 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), 36 0, SLAB_HWCACHE_ALIGN, NULL, NULL); 37 if (!msi_cachep) 38 return -ENOMEM; 39 40 return 0; 41} 42 43static void msi_set_mask_bit(unsigned int irq, int flag) 44{ 45 struct msi_desc *entry; 46 47 entry = msi_desc[irq]; 48 BUG_ON(!entry || !entry->dev); 49 switch (entry->msi_attrib.type) { 50 case PCI_CAP_ID_MSI: 51 if (entry->msi_attrib.maskbit) { 52 int pos; 53 u32 mask_bits; 54 55 pos = (long)entry->mask_base; 56 pci_read_config_dword(entry->dev, pos, &mask_bits); 57 mask_bits &= ~(1); 58 mask_bits |= flag; 59 pci_write_config_dword(entry->dev, pos, mask_bits); 60 } 61 break; 62 case PCI_CAP_ID_MSIX: 63 { 64 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 65 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 66 writel(flag, entry->mask_base + offset); 67 break; 68 } 69 default: 70 BUG(); 71 break; 72 } 73} 74 75void read_msi_msg(unsigned int irq, struct msi_msg *msg) 76{ 77 struct msi_desc *entry = get_irq_data(irq); 78 switch(entry->msi_attrib.type) { 79 case PCI_CAP_ID_MSI: 80 { 81 struct pci_dev *dev = entry->dev; 82 int pos = entry->msi_attrib.pos; 83 u16 data; 84 85 pci_read_config_dword(dev, msi_lower_address_reg(pos), 86 &msg->address_lo); 87 if (entry->msi_attrib.is_64) { 88 pci_read_config_dword(dev, msi_upper_address_reg(pos), 89 &msg->address_hi); 90 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 91 } else { 92 msg->address_hi = 0; 93 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 94 } 95 msg->data = data; 96 break; 97 } 98 case PCI_CAP_ID_MSIX: 99 { 100 void __iomem *base; 101 base = entry->mask_base + 102 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 103 104 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 105 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 106 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 107 break; 108 } 109 default: 110 BUG(); 111 } 112} 113 114void write_msi_msg(unsigned int irq, struct msi_msg *msg) 115{ 116 struct msi_desc *entry = get_irq_data(irq); 117 switch (entry->msi_attrib.type) { 118 case PCI_CAP_ID_MSI: 119 { 120 struct pci_dev *dev = entry->dev; 121 int pos = entry->msi_attrib.pos; 122 123 pci_write_config_dword(dev, msi_lower_address_reg(pos), 124 msg->address_lo); 125 if (entry->msi_attrib.is_64) { 126 pci_write_config_dword(dev, msi_upper_address_reg(pos), 127 msg->address_hi); 128 pci_write_config_word(dev, msi_data_reg(pos, 1), 129 msg->data); 130 } else { 131 pci_write_config_word(dev, msi_data_reg(pos, 0), 132 msg->data); 133 } 134 break; 135 } 136 case PCI_CAP_ID_MSIX: 137 { 138 void __iomem *base; 139 base = entry->mask_base + 140 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 141 142 writel(msg->address_lo, 143 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 144 writel(msg->address_hi, 145 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 146 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 147 break; 148 } 149 default: 150 BUG(); 151 } 152} 153 154void mask_msi_irq(unsigned int irq) 155{ 156 msi_set_mask_bit(irq, 1); 157} 158 159void unmask_msi_irq(unsigned int irq) 160{ 161 msi_set_mask_bit(irq, 0); 162} 163 164static int msi_free_irq(struct pci_dev* dev, int irq); 165 166static int msi_init(void) 167{ 168 static int status = -ENOMEM; 169 170 if (!status) 171 return status; 172 173 status = msi_cache_init(); 174 if (status < 0) { 175 pci_msi_enable = 0; 176 printk(KERN_WARNING "PCI: MSI cache init failed\n"); 177 return status; 178 } 179 180 return status; 181} 182 183static struct msi_desc* alloc_msi_entry(void) 184{ 185 struct msi_desc *entry; 186 187 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); 188 if (!entry) 189 return NULL; 190 191 entry->link.tail = entry->link.head = 0; /* single message */ 192 entry->dev = NULL; 193 194 return entry; 195} 196 197static void attach_msi_entry(struct msi_desc *entry, int irq) 198{ 199 unsigned long flags; 200 201 spin_lock_irqsave(&msi_lock, flags); 202 msi_desc[irq] = entry; 203 spin_unlock_irqrestore(&msi_lock, flags); 204} 205 206static int create_msi_irq(void) 207{ 208 struct msi_desc *entry; 209 int irq; 210 211 entry = alloc_msi_entry(); 212 if (!entry) 213 return -ENOMEM; 214 215 irq = create_irq(); 216 if (irq < 0) { 217 kmem_cache_free(msi_cachep, entry); 218 return -EBUSY; 219 } 220 221 set_irq_data(irq, entry); 222 223 return irq; 224} 225 226static void destroy_msi_irq(unsigned int irq) 227{ 228 struct msi_desc *entry; 229 230 entry = get_irq_data(irq); 231 set_irq_chip(irq, NULL); 232 set_irq_data(irq, NULL); 233 destroy_irq(irq); 234 kmem_cache_free(msi_cachep, entry); 235} 236 237static void enable_msi_mode(struct pci_dev *dev, int pos, int type) 238{ 239 u16 control; 240 241 pci_read_config_word(dev, msi_control_reg(pos), &control); 242 if (type == PCI_CAP_ID_MSI) { 243 /* Set enabled bits to single MSI & enable MSI_enable bit */ 244 msi_enable(control, 1); 245 pci_write_config_word(dev, msi_control_reg(pos), control); 246 dev->msi_enabled = 1; 247 } else { 248 msix_enable(control); 249 pci_write_config_word(dev, msi_control_reg(pos), control); 250 dev->msix_enabled = 1; 251 } 252 253 pci_intx(dev, 0); /* disable intx */ 254} 255 256void disable_msi_mode(struct pci_dev *dev, int pos, int type) 257{ 258 u16 control; 259 260 pci_read_config_word(dev, msi_control_reg(pos), &control); 261 if (type == PCI_CAP_ID_MSI) { 262 /* Set enabled bits to single MSI & enable MSI_enable bit */ 263 msi_disable(control); 264 pci_write_config_word(dev, msi_control_reg(pos), control); 265 dev->msi_enabled = 0; 266 } else { 267 msix_disable(control); 268 pci_write_config_word(dev, msi_control_reg(pos), control); 269 dev->msix_enabled = 0; 270 } 271 272 pci_intx(dev, 1); /* enable intx */ 273} 274 275static int msi_lookup_irq(struct pci_dev *dev, int type) 276{ 277 int irq; 278 unsigned long flags; 279 280 spin_lock_irqsave(&msi_lock, flags); 281 for (irq = 0; irq < NR_IRQS; irq++) { 282 if (!msi_desc[irq] || msi_desc[irq]->dev != dev || 283 msi_desc[irq]->msi_attrib.type != type || 284 msi_desc[irq]->msi_attrib.default_irq != dev->irq) 285 continue; 286 spin_unlock_irqrestore(&msi_lock, flags); 287 /* This pre-assigned MSI irq for this device 288 already exists. Override dev->irq with this irq */ 289 dev->irq = irq; 290 return 0; 291 } 292 spin_unlock_irqrestore(&msi_lock, flags); 293 294 return -EACCES; 295} 296 297void pci_scan_msi_device(struct pci_dev *dev) 298{ 299 if (!dev) 300 return; 301} 302 303#ifdef CONFIG_PM 304int pci_save_msi_state(struct pci_dev *dev) 305{ 306 int pos, i = 0; 307 u16 control; 308 struct pci_cap_saved_state *save_state; 309 u32 *cap; 310 311 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 312 if (pos <= 0 || dev->no_msi) 313 return 0; 314 315 pci_read_config_word(dev, msi_control_reg(pos), &control); 316 if (!(control & PCI_MSI_FLAGS_ENABLE)) 317 return 0; 318 319 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, 320 GFP_KERNEL); 321 if (!save_state) { 322 printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); 323 return -ENOMEM; 324 } 325 cap = &save_state->data[0]; 326 327 pci_read_config_dword(dev, pos, &cap[i++]); 328 control = cap[0] >> 16; 329 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); 330 if (control & PCI_MSI_FLAGS_64BIT) { 331 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); 332 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); 333 } else 334 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); 335 if (control & PCI_MSI_FLAGS_MASKBIT) 336 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); 337 save_state->cap_nr = PCI_CAP_ID_MSI; 338 pci_add_saved_cap(dev, save_state); 339 return 0; 340} 341 342void pci_restore_msi_state(struct pci_dev *dev) 343{ 344 int i = 0, pos; 345 u16 control; 346 struct pci_cap_saved_state *save_state; 347 u32 *cap; 348 349 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); 350 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 351 if (!save_state || pos <= 0) 352 return; 353 cap = &save_state->data[0]; 354 355 control = cap[i++] >> 16; 356 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); 357 if (control & PCI_MSI_FLAGS_64BIT) { 358 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); 359 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); 360 } else 361 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); 362 if (control & PCI_MSI_FLAGS_MASKBIT) 363 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); 364 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 365 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 366 pci_remove_saved_cap(save_state); 367 kfree(save_state); 368} 369 370int pci_save_msix_state(struct pci_dev *dev) 371{ 372 int pos; 373 int temp; 374 int irq, head, tail = 0; 375 u16 control; 376 struct pci_cap_saved_state *save_state; 377 378 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 379 if (pos <= 0 || dev->no_msi) 380 return 0; 381 382 /* save the capability */ 383 pci_read_config_word(dev, msi_control_reg(pos), &control); 384 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 385 return 0; 386 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), 387 GFP_KERNEL); 388 if (!save_state) { 389 printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); 390 return -ENOMEM; 391 } 392 *((u16 *)&save_state->data[0]) = control; 393 394 /* save the table */ 395 temp = dev->irq; 396 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { 397 kfree(save_state); 398 return -EINVAL; 399 } 400 401 irq = head = dev->irq; 402 while (head != tail) { 403 struct msi_desc *entry; 404 405 entry = msi_desc[irq]; 406 read_msi_msg(irq, &entry->msg_save); 407 408 tail = msi_desc[irq]->link.tail; 409 irq = tail; 410 } 411 dev->irq = temp; 412 413 save_state->cap_nr = PCI_CAP_ID_MSIX; 414 pci_add_saved_cap(dev, save_state); 415 return 0; 416} 417 418void pci_restore_msix_state(struct pci_dev *dev) 419{ 420 u16 save; 421 int pos; 422 int irq, head, tail = 0; 423 struct msi_desc *entry; 424 int temp; 425 struct pci_cap_saved_state *save_state; 426 427 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); 428 if (!save_state) 429 return; 430 save = *((u16 *)&save_state->data[0]); 431 pci_remove_saved_cap(save_state); 432 kfree(save_state); 433 434 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 435 if (pos <= 0) 436 return; 437 438 /* route the table */ 439 temp = dev->irq; 440 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) 441 return; 442 irq = head = dev->irq; 443 while (head != tail) { 444 entry = msi_desc[irq]; 445 write_msi_msg(irq, &entry->msg_save); 446 447 tail = msi_desc[irq]->link.tail; 448 irq = tail; 449 } 450 dev->irq = temp; 451 452 pci_write_config_word(dev, msi_control_reg(pos), save); 453 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 454} 455#endif /* CONFIG_PM */ 456 457/** 458 * msi_capability_init - configure device's MSI capability structure 459 * @dev: pointer to the pci_dev data structure of MSI device function 460 * 461 * Setup the MSI capability structure of device function with a single 462 * MSI irq, regardless of device function is capable of handling 463 * multiple messages. A return of zero indicates the successful setup 464 * of an entry zero with the new MSI irq or non-zero for otherwise. 465 **/ 466static int msi_capability_init(struct pci_dev *dev) 467{ 468 int status; 469 struct msi_desc *entry; 470 int pos, irq; 471 u16 control; 472 473 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 474 pci_read_config_word(dev, msi_control_reg(pos), &control); 475 /* MSI Entry Initialization */ 476 irq = create_msi_irq(); 477 if (irq < 0) 478 return irq; 479 480 entry = get_irq_data(irq); 481 entry->link.head = irq; 482 entry->link.tail = irq; 483 entry->msi_attrib.type = PCI_CAP_ID_MSI; 484 entry->msi_attrib.is_64 = is_64bit_address(control); 485 entry->msi_attrib.entry_nr = 0; 486 entry->msi_attrib.maskbit = is_mask_bit_support(control); 487 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 488 entry->msi_attrib.pos = pos; 489 if (is_mask_bit_support(control)) { 490 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, 491 is_64bit_address(control)); 492 } 493 entry->dev = dev; 494 if (entry->msi_attrib.maskbit) { 495 unsigned int maskbits, temp; 496 /* All MSIs are unmasked by default, Mask them all */ 497 pci_read_config_dword(dev, 498 msi_mask_bits_reg(pos, is_64bit_address(control)), 499 &maskbits); 500 temp = (1 << multi_msi_capable(control)); 501 temp = ((temp - 1) & ~temp); 502 maskbits |= temp; 503 pci_write_config_dword(dev, 504 msi_mask_bits_reg(pos, is_64bit_address(control)), 505 maskbits); 506 } 507 /* Configure MSI capability structure */ 508 status = arch_setup_msi_irq(irq, dev); 509 if (status < 0) { 510 destroy_msi_irq(irq); 511 return status; 512 } 513 514 attach_msi_entry(entry, irq); 515 /* Set MSI enabled bits */ 516 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 517 518 dev->irq = irq; 519 return 0; 520} 521 522/** 523 * msix_capability_init - configure device's MSI-X capability 524 * @dev: pointer to the pci_dev data structure of MSI-X device function 525 * @entries: pointer to an array of struct msix_entry entries 526 * @nvec: number of @entries 527 * 528 * Setup the MSI-X capability structure of device function with a 529 * single MSI-X irq. A return of zero indicates the successful setup of 530 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 531 **/ 532static int msix_capability_init(struct pci_dev *dev, 533 struct msix_entry *entries, int nvec) 534{ 535 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; 536 int status; 537 int irq, pos, i, j, nr_entries, temp = 0; 538 unsigned long phys_addr; 539 u32 table_offset; 540 u16 control; 541 u8 bir; 542 void __iomem *base; 543 544 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 545 /* Request & Map MSI-X table region */ 546 pci_read_config_word(dev, msi_control_reg(pos), &control); 547 nr_entries = multi_msix_capable(control); 548 549 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 550 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 551 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 552 phys_addr = pci_resource_start (dev, bir) + table_offset; 553 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 554 if (base == NULL) 555 return -ENOMEM; 556 557 /* MSI-X Table Initialization */ 558 for (i = 0; i < nvec; i++) { 559 irq = create_msi_irq(); 560 if (irq < 0) 561 break; 562 563 entry = get_irq_data(irq); 564 j = entries[i].entry; 565 entries[i].vector = irq; 566 entry->msi_attrib.type = PCI_CAP_ID_MSIX; 567 entry->msi_attrib.is_64 = 1; 568 entry->msi_attrib.entry_nr = j; 569 entry->msi_attrib.maskbit = 1; 570 entry->msi_attrib.default_irq = dev->irq; 571 entry->msi_attrib.pos = pos; 572 entry->dev = dev; 573 entry->mask_base = base; 574 if (!head) { 575 entry->link.head = irq; 576 entry->link.tail = irq; 577 head = entry; 578 } else { 579 entry->link.head = temp; 580 entry->link.tail = tail->link.tail; 581 tail->link.tail = irq; 582 head->link.head = irq; 583 } 584 temp = irq; 585 tail = entry; 586 /* Configure MSI-X capability structure */ 587 status = arch_setup_msi_irq(irq, dev); 588 if (status < 0) { 589 destroy_msi_irq(irq); 590 break; 591 } 592 593 attach_msi_entry(entry, irq); 594 } 595 if (i != nvec) { 596 int avail = i - 1; 597 i--; 598 for (; i >= 0; i--) { 599 irq = (entries + i)->vector; 600 msi_free_irq(dev, irq); 601 (entries + i)->vector = 0; 602 } 603 /* If we had some success report the number of irqs 604 * we succeeded in setting up. 605 */ 606 if (avail <= 0) 607 avail = -EBUSY; 608 return avail; 609 } 610 /* Set MSI-X enabled bits */ 611 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 612 613 return 0; 614} 615 616/** 617 * pci_msi_supported - check whether MSI may be enabled on device 618 * @dev: pointer to the pci_dev data structure of MSI device function 619 * 620 * Look at global flags, the device itself, and its parent busses 621 * to return 0 if MSI are supported for the device. 622 **/ 623static 624int pci_msi_supported(struct pci_dev * dev) 625{ 626 struct pci_bus *bus; 627 628 /* MSI must be globally enabled and supported by the device */ 629 if (!pci_msi_enable || !dev || dev->no_msi) 630 return -EINVAL; 631 632 /* Any bridge which does NOT route MSI transactions from it's 633 * secondary bus to it's primary bus must set NO_MSI flag on 634 * the secondary pci_bus. 635 * We expect only arch-specific PCI host bus controller driver 636 * or quirks for specific PCI bridges to be setting NO_MSI. 637 */ 638 for (bus = dev->bus; bus; bus = bus->parent) 639 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 640 return -EINVAL; 641 642 return 0; 643} 644 645/** 646 * pci_enable_msi - configure device's MSI capability structure 647 * @dev: pointer to the pci_dev data structure of MSI device function 648 * 649 * Setup the MSI capability structure of device function with 650 * a single MSI irq upon its software driver call to request for 651 * MSI mode enabled on its hardware device function. A return of zero 652 * indicates the successful setup of an entry zero with the new MSI 653 * irq or non-zero for otherwise. 654 **/ 655int pci_enable_msi(struct pci_dev* dev) 656{ 657 int pos, temp, status; 658 659 if (pci_msi_supported(dev) < 0) 660 return -EINVAL; 661 662 temp = dev->irq; 663 664 status = msi_init(); 665 if (status < 0) 666 return status; 667 668 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 669 if (!pos) 670 return -EINVAL; 671 672 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI)); 673 674 /* Check whether driver already requested for MSI-X irqs */ 675 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 676 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { 677 printk(KERN_INFO "PCI: %s: Can't enable MSI. " 678 "Device already has MSI-X irq assigned\n", 679 pci_name(dev)); 680 dev->irq = temp; 681 return -EINVAL; 682 } 683 status = msi_capability_init(dev); 684 return status; 685} 686 687void pci_disable_msi(struct pci_dev* dev) 688{ 689 struct msi_desc *entry; 690 int pos, default_irq; 691 u16 control; 692 unsigned long flags; 693 694 if (!pci_msi_enable) 695 return; 696 if (!dev) 697 return; 698 699 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 700 if (!pos) 701 return; 702 703 pci_read_config_word(dev, msi_control_reg(pos), &control); 704 if (!(control & PCI_MSI_FLAGS_ENABLE)) 705 return; 706 707 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 708 709 spin_lock_irqsave(&msi_lock, flags); 710 entry = msi_desc[dev->irq]; 711 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { 712 spin_unlock_irqrestore(&msi_lock, flags); 713 return; 714 } 715 if (irq_has_action(dev->irq)) { 716 spin_unlock_irqrestore(&msi_lock, flags); 717 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " 718 "free_irq() on MSI irq %d\n", 719 pci_name(dev), dev->irq); 720 BUG_ON(irq_has_action(dev->irq)); 721 } else { 722 default_irq = entry->msi_attrib.default_irq; 723 spin_unlock_irqrestore(&msi_lock, flags); 724 msi_free_irq(dev, dev->irq); 725 726 /* Restore dev->irq to its default pin-assertion irq */ 727 dev->irq = default_irq; 728 } 729} 730 731static int msi_free_irq(struct pci_dev* dev, int irq) 732{ 733 struct msi_desc *entry; 734 int head, entry_nr, type; 735 void __iomem *base; 736 unsigned long flags; 737 738 arch_teardown_msi_irq(irq); 739 740 spin_lock_irqsave(&msi_lock, flags); 741 entry = msi_desc[irq]; 742 if (!entry || entry->dev != dev) { 743 spin_unlock_irqrestore(&msi_lock, flags); 744 return -EINVAL; 745 } 746 type = entry->msi_attrib.type; 747 entry_nr = entry->msi_attrib.entry_nr; 748 head = entry->link.head; 749 base = entry->mask_base; 750 msi_desc[entry->link.head]->link.tail = entry->link.tail; 751 msi_desc[entry->link.tail]->link.head = entry->link.head; 752 entry->dev = NULL; 753 msi_desc[irq] = NULL; 754 spin_unlock_irqrestore(&msi_lock, flags); 755 756 destroy_msi_irq(irq); 757 758 if (type == PCI_CAP_ID_MSIX) { 759 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + 760 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 761 762 if (head == irq) 763 iounmap(base); 764 } 765 766 return 0; 767} 768 769/** 770 * pci_enable_msix - configure device's MSI-X capability structure 771 * @dev: pointer to the pci_dev data structure of MSI-X device function 772 * @entries: pointer to an array of MSI-X entries 773 * @nvec: number of MSI-X irqs requested for allocation by device driver 774 * 775 * Setup the MSI-X capability structure of device function with the number 776 * of requested irqs upon its software driver call to request for 777 * MSI-X mode enabled on its hardware device function. A return of zero 778 * indicates the successful configuration of MSI-X capability structure 779 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 780 * Or a return of > 0 indicates that driver request is exceeding the number 781 * of irqs available. Driver should use the returned value to re-send 782 * its request. 783 **/ 784int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 785{ 786 int status, pos, nr_entries; 787 int i, j, temp; 788 u16 control; 789 790 if (!entries || pci_msi_supported(dev) < 0) 791 return -EINVAL; 792 793 status = msi_init(); 794 if (status < 0) 795 return status; 796 797 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 798 if (!pos) 799 return -EINVAL; 800 801 pci_read_config_word(dev, msi_control_reg(pos), &control); 802 nr_entries = multi_msix_capable(control); 803 if (nvec > nr_entries) 804 return -EINVAL; 805 806 /* Check for any invalid entries */ 807 for (i = 0; i < nvec; i++) { 808 if (entries[i].entry >= nr_entries) 809 return -EINVAL; /* invalid entry */ 810 for (j = i + 1; j < nvec; j++) { 811 if (entries[i].entry == entries[j].entry) 812 return -EINVAL; /* duplicate entry */ 813 } 814 } 815 temp = dev->irq; 816 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)); 817 818 /* Check whether driver already requested for MSI irq */ 819 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && 820 !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { 821 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " 822 "Device already has an MSI irq assigned\n", 823 pci_name(dev)); 824 dev->irq = temp; 825 return -EINVAL; 826 } 827 status = msix_capability_init(dev, entries, nvec); 828 return status; 829} 830 831void pci_disable_msix(struct pci_dev* dev) 832{ 833 int pos, temp; 834 u16 control; 835 836 if (!pci_msi_enable) 837 return; 838 if (!dev) 839 return; 840 841 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 842 if (!pos) 843 return; 844 845 pci_read_config_word(dev, msi_control_reg(pos), &control); 846 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 847 return; 848 849 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 850 851 temp = dev->irq; 852 if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { 853 int irq, head, tail = 0, warning = 0; 854 unsigned long flags; 855 856 irq = head = dev->irq; 857 dev->irq = temp; /* Restore pin IRQ */ 858 while (head != tail) { 859 spin_lock_irqsave(&msi_lock, flags); 860 tail = msi_desc[irq]->link.tail; 861 spin_unlock_irqrestore(&msi_lock, flags); 862 if (irq_has_action(irq)) 863 warning = 1; 864 else if (irq != head) /* Release MSI-X irq */ 865 msi_free_irq(dev, irq); 866 irq = tail; 867 } 868 msi_free_irq(dev, irq); 869 if (warning) { 870 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " 871 "free_irq() on all MSI-X irqs\n", 872 pci_name(dev)); 873 BUG_ON(warning > 0); 874 } 875 } 876} 877 878/** 879 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 880 * @dev: pointer to the pci_dev data structure of MSI(X) device function 881 * 882 * Being called during hotplug remove, from which the device function 883 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 884 * allocated for this device function, are reclaimed to unused state, 885 * which may be used later on. 886 **/ 887void msi_remove_pci_irq_vectors(struct pci_dev* dev) 888{ 889 int pos, temp; 890 unsigned long flags; 891 892 if (!pci_msi_enable || !dev) 893 return; 894 895 temp = dev->irq; /* Save IOAPIC IRQ */ 896 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 897 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { 898 if (irq_has_action(dev->irq)) { 899 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 900 "called without free_irq() on MSI irq %d\n", 901 pci_name(dev), dev->irq); 902 BUG_ON(irq_has_action(dev->irq)); 903 } else /* Release MSI irq assigned to this device */ 904 msi_free_irq(dev, dev->irq); 905 dev->irq = temp; /* Restore IOAPIC IRQ */ 906 } 907 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 908 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { 909 int irq, head, tail = 0, warning = 0; 910 void __iomem *base = NULL; 911 912 irq = head = dev->irq; 913 while (head != tail) { 914 spin_lock_irqsave(&msi_lock, flags); 915 tail = msi_desc[irq]->link.tail; 916 base = msi_desc[irq]->mask_base; 917 spin_unlock_irqrestore(&msi_lock, flags); 918 if (irq_has_action(irq)) 919 warning = 1; 920 else if (irq != head) /* Release MSI-X irq */ 921 msi_free_irq(dev, irq); 922 irq = tail; 923 } 924 msi_free_irq(dev, irq); 925 if (warning) { 926 iounmap(base); 927 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 928 "called without free_irq() on all MSI-X irqs\n", 929 pci_name(dev)); 930 BUG_ON(warning > 0); 931 } 932 dev->irq = temp; /* Restore IOAPIC IRQ */ 933 } 934} 935 936void pci_no_msi(void) 937{ 938 pci_msi_enable = 0; 939} 940 941EXPORT_SYMBOL(pci_enable_msi); 942EXPORT_SYMBOL(pci_disable_msi); 943EXPORT_SYMBOL(pci_enable_msix); 944EXPORT_SYMBOL(pci_disable_msix); 945