msi.c revision 8d181018532dd709ec1f789e374cda92d7b01ce1
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17#include <linux/msi.h> 18#include <linux/smp.h> 19 20#include <asm/errno.h> 21#include <asm/io.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static int pci_msi_enable = 1; 27 28/* Arch hooks */ 29 30#ifndef arch_msi_check_device 31int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) 32{ 33 return 0; 34} 35#endif 36 37#ifndef arch_setup_msi_irqs 38int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 39{ 40 struct msi_desc *entry; 41 int ret; 42 43 /* 44 * If an architecture wants to support multiple MSI, it needs to 45 * override arch_setup_msi_irqs() 46 */ 47 if (type == PCI_CAP_ID_MSI && nvec > 1) 48 return 1; 49 50 list_for_each_entry(entry, &dev->msi_list, list) { 51 ret = arch_setup_msi_irq(dev, entry); 52 if (ret < 0) 53 return ret; 54 if (ret > 0) 55 return -ENOSPC; 56 } 57 58 return 0; 59} 60#endif 61 62#ifndef arch_teardown_msi_irqs 63void arch_teardown_msi_irqs(struct pci_dev *dev) 64{ 65 struct msi_desc *entry; 66 67 list_for_each_entry(entry, &dev->msi_list, list) { 68 int i, nvec; 69 if (entry->irq == 0) 70 continue; 71 nvec = 1 << entry->msi_attrib.multiple; 72 for (i = 0; i < nvec; i++) 73 arch_teardown_msi_irq(entry->irq + i); 74 } 75} 76#endif 77 78static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) 79{ 80 u16 control; 81 82 if (pos) { 83 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 84 control &= ~PCI_MSI_FLAGS_ENABLE; 85 if (enable) 86 control |= PCI_MSI_FLAGS_ENABLE; 87 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 88 } 89} 90 91static void msi_set_enable(struct pci_dev *dev, int enable) 92{ 93 __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); 94} 95 96static void msix_set_enable(struct pci_dev *dev, int enable) 97{ 98 int pos; 99 u16 control; 100 101 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 102 if (pos) { 103 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 104 control &= ~PCI_MSIX_FLAGS_ENABLE; 105 if (enable) 106 control |= PCI_MSIX_FLAGS_ENABLE; 107 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 108 } 109} 110 111static inline __attribute_const__ u32 msi_mask(unsigned x) 112{ 113 /* Don't shift by >= width of type */ 114 if (x >= 5) 115 return 0xffffffff; 116 return (1 << (1 << x)) - 1; 117} 118 119static inline __attribute_const__ u32 msi_capable_mask(u16 control) 120{ 121 return msi_mask((control >> 1) & 7); 122} 123 124static inline __attribute_const__ u32 msi_enabled_mask(u16 control) 125{ 126 return msi_mask((control >> 4) & 7); 127} 128 129/* 130 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to 131 * mask all MSI interrupts by clearing the MSI enable bit does not work 132 * reliably as devices without an INTx disable bit will then generate a 133 * level IRQ which will never be cleared. 134 * 135 * Returns 1 if it succeeded in masking the interrupt and 0 if the device 136 * doesn't support MSI masking. 137 */ 138static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) 139{ 140 u32 mask_bits = desc->masked; 141 142 if (!desc->msi_attrib.maskbit) 143 return; 144 145 mask_bits &= ~mask; 146 mask_bits |= flag; 147 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); 148 desc->masked = mask_bits; 149} 150 151/* 152 * This internal function does not flush PCI writes to the device. 153 * All users must ensure that they read from the device before either 154 * assuming that the device state is up to date, or returning out of this 155 * file. This saves a few milliseconds when initialising devices with lots 156 * of MSI-X interrupts. 157 */ 158static void msix_mask_irq(struct msi_desc *desc, u32 flag) 159{ 160 u32 mask_bits = desc->masked; 161 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 162 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 163 mask_bits &= ~1; 164 mask_bits |= flag; 165 writel(mask_bits, desc->mask_base + offset); 166 desc->masked = mask_bits; 167} 168 169static void msi_set_mask_bit(unsigned irq, u32 flag) 170{ 171 struct msi_desc *desc = get_irq_msi(irq); 172 173 if (desc->msi_attrib.is_msix) { 174 msix_mask_irq(desc, flag); 175 readl(desc->mask_base); /* Flush write to device */ 176 } else { 177 unsigned offset = irq - desc->dev->irq; 178 msi_mask_irq(desc, 1 << offset, flag << offset); 179 } 180} 181 182void mask_msi_irq(unsigned int irq) 183{ 184 msi_set_mask_bit(irq, 1); 185} 186 187void unmask_msi_irq(unsigned int irq) 188{ 189 msi_set_mask_bit(irq, 0); 190} 191 192void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 193{ 194 struct msi_desc *entry = get_irq_desc_msi(desc); 195 if (entry->msi_attrib.is_msix) { 196 void __iomem *base = entry->mask_base + 197 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 198 199 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 200 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 201 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 202 } else { 203 struct pci_dev *dev = entry->dev; 204 int pos = entry->msi_attrib.pos; 205 u16 data; 206 207 pci_read_config_dword(dev, msi_lower_address_reg(pos), 208 &msg->address_lo); 209 if (entry->msi_attrib.is_64) { 210 pci_read_config_dword(dev, msi_upper_address_reg(pos), 211 &msg->address_hi); 212 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 213 } else { 214 msg->address_hi = 0; 215 pci_read_config_word(dev, msi_data_reg(pos, 0), &data); 216 } 217 msg->data = data; 218 } 219} 220 221void read_msi_msg(unsigned int irq, struct msi_msg *msg) 222{ 223 struct irq_desc *desc = irq_to_desc(irq); 224 225 read_msi_msg_desc(desc, msg); 226} 227 228void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 229{ 230 struct msi_desc *entry = get_irq_desc_msi(desc); 231 if (entry->msi_attrib.is_msix) { 232 void __iomem *base; 233 base = entry->mask_base + 234 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 235 236 writel(msg->address_lo, 237 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 238 writel(msg->address_hi, 239 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 240 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 241 } else { 242 struct pci_dev *dev = entry->dev; 243 int pos = entry->msi_attrib.pos; 244 u16 msgctl; 245 246 pci_read_config_word(dev, msi_control_reg(pos), &msgctl); 247 msgctl &= ~PCI_MSI_FLAGS_QSIZE; 248 msgctl |= entry->msi_attrib.multiple << 4; 249 pci_write_config_word(dev, msi_control_reg(pos), msgctl); 250 251 pci_write_config_dword(dev, msi_lower_address_reg(pos), 252 msg->address_lo); 253 if (entry->msi_attrib.is_64) { 254 pci_write_config_dword(dev, msi_upper_address_reg(pos), 255 msg->address_hi); 256 pci_write_config_word(dev, msi_data_reg(pos, 1), 257 msg->data); 258 } else { 259 pci_write_config_word(dev, msi_data_reg(pos, 0), 260 msg->data); 261 } 262 } 263 entry->msg = *msg; 264} 265 266void write_msi_msg(unsigned int irq, struct msi_msg *msg) 267{ 268 struct irq_desc *desc = irq_to_desc(irq); 269 270 write_msi_msg_desc(desc, msg); 271} 272 273static int msi_free_irqs(struct pci_dev* dev); 274 275static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) 276{ 277 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); 278 if (!desc) 279 return NULL; 280 281 INIT_LIST_HEAD(&desc->list); 282 desc->dev = dev; 283 284 return desc; 285} 286 287static void pci_intx_for_msi(struct pci_dev *dev, int enable) 288{ 289 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) 290 pci_intx(dev, enable); 291} 292 293static void __pci_restore_msi_state(struct pci_dev *dev) 294{ 295 int pos; 296 u16 control; 297 struct msi_desc *entry; 298 299 if (!dev->msi_enabled) 300 return; 301 302 entry = get_irq_msi(dev->irq); 303 pos = entry->msi_attrib.pos; 304 305 pci_intx_for_msi(dev, 0); 306 msi_set_enable(dev, 0); 307 write_msi_msg(dev->irq, &entry->msg); 308 309 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 310 msi_mask_irq(entry, msi_capable_mask(control), entry->masked); 311 control &= ~PCI_MSI_FLAGS_QSIZE; 312 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; 313 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 314} 315 316static void __pci_restore_msix_state(struct pci_dev *dev) 317{ 318 int pos; 319 struct msi_desc *entry; 320 u16 control; 321 322 if (!dev->msix_enabled) 323 return; 324 325 /* route the table */ 326 pci_intx_for_msi(dev, 0); 327 msix_set_enable(dev, 0); 328 329 list_for_each_entry(entry, &dev->msi_list, list) { 330 write_msi_msg(entry->irq, &entry->msg); 331 msix_mask_irq(entry, entry->masked); 332 } 333 334 BUG_ON(list_empty(&dev->msi_list)); 335 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 336 pos = entry->msi_attrib.pos; 337 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 338 control &= ~PCI_MSIX_FLAGS_MASKALL; 339 control |= PCI_MSIX_FLAGS_ENABLE; 340 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 341} 342 343void pci_restore_msi_state(struct pci_dev *dev) 344{ 345 __pci_restore_msi_state(dev); 346 __pci_restore_msix_state(dev); 347} 348EXPORT_SYMBOL_GPL(pci_restore_msi_state); 349 350/** 351 * msi_capability_init - configure device's MSI capability structure 352 * @dev: pointer to the pci_dev data structure of MSI device function 353 * @nvec: number of interrupts to allocate 354 * 355 * Setup the MSI capability structure of the device with the requested 356 * number of interrupts. A return value of zero indicates the successful 357 * setup of an entry with the new MSI irq. A negative return value indicates 358 * an error, and a positive return value indicates the number of interrupts 359 * which could have been allocated. 360 */ 361static int msi_capability_init(struct pci_dev *dev, int nvec) 362{ 363 struct msi_desc *entry; 364 int pos, ret; 365 u16 control; 366 unsigned mask; 367 368 msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ 369 370 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 371 pci_read_config_word(dev, msi_control_reg(pos), &control); 372 /* MSI Entry Initialization */ 373 entry = alloc_msi_entry(dev); 374 if (!entry) 375 return -ENOMEM; 376 377 entry->msi_attrib.is_msix = 0; 378 entry->msi_attrib.is_64 = is_64bit_address(control); 379 entry->msi_attrib.entry_nr = 0; 380 entry->msi_attrib.maskbit = is_mask_bit_support(control); 381 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 382 entry->msi_attrib.pos = pos; 383 384 entry->mask_pos = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); 385 /* All MSIs are unmasked by default, Mask them all */ 386 if (entry->msi_attrib.maskbit) 387 pci_read_config_dword(dev, entry->mask_pos, &entry->masked); 388 mask = msi_capable_mask(control); 389 msi_mask_irq(entry, mask, mask); 390 391 list_add_tail(&entry->list, &dev->msi_list); 392 393 /* Configure MSI capability structure */ 394 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); 395 if (ret) { 396 msi_free_irqs(dev); 397 return ret; 398 } 399 400 /* Set MSI enabled bits */ 401 pci_intx_for_msi(dev, 0); 402 msi_set_enable(dev, 1); 403 dev->msi_enabled = 1; 404 405 dev->irq = entry->irq; 406 return 0; 407} 408 409/** 410 * msix_capability_init - configure device's MSI-X capability 411 * @dev: pointer to the pci_dev data structure of MSI-X device function 412 * @entries: pointer to an array of struct msix_entry entries 413 * @nvec: number of @entries 414 * 415 * Setup the MSI-X capability structure of device function with a 416 * single MSI-X irq. A return of zero indicates the successful setup of 417 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 418 **/ 419static int msix_capability_init(struct pci_dev *dev, 420 struct msix_entry *entries, int nvec) 421{ 422 struct msi_desc *entry; 423 int pos, i, j, nr_entries, ret; 424 unsigned long phys_addr; 425 u32 table_offset; 426 u16 control; 427 u8 bir; 428 void __iomem *base; 429 430 msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ 431 432 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 433 /* Request & Map MSI-X table region */ 434 pci_read_config_word(dev, msi_control_reg(pos), &control); 435 nr_entries = multi_msix_capable(control); 436 437 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 438 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 439 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 440 phys_addr = pci_resource_start (dev, bir) + table_offset; 441 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 442 if (base == NULL) 443 return -ENOMEM; 444 445 /* MSI-X Table Initialization */ 446 for (i = 0; i < nvec; i++) { 447 entry = alloc_msi_entry(dev); 448 if (!entry) 449 break; 450 451 j = entries[i].entry; 452 entry->msi_attrib.is_msix = 1; 453 entry->msi_attrib.is_64 = 1; 454 entry->msi_attrib.entry_nr = j; 455 entry->msi_attrib.default_irq = dev->irq; 456 entry->msi_attrib.pos = pos; 457 entry->mask_base = base; 458 msix_mask_irq(entry, 1); 459 460 list_add_tail(&entry->list, &dev->msi_list); 461 } 462 463 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); 464 if (ret < 0) { 465 /* If we had some success report the number of irqs 466 * we succeeded in setting up. */ 467 int avail = 0; 468 list_for_each_entry(entry, &dev->msi_list, list) { 469 if (entry->irq != 0) { 470 avail++; 471 } 472 } 473 474 if (avail != 0) 475 ret = avail; 476 } 477 478 if (ret) { 479 msi_free_irqs(dev); 480 return ret; 481 } 482 483 i = 0; 484 list_for_each_entry(entry, &dev->msi_list, list) { 485 entries[i].vector = entry->irq; 486 set_irq_msi(entry->irq, entry); 487 i++; 488 } 489 /* Set MSI-X enabled bits */ 490 pci_intx_for_msi(dev, 0); 491 msix_set_enable(dev, 1); 492 dev->msix_enabled = 1; 493 494 list_for_each_entry(entry, &dev->msi_list, list) { 495 int vector = entry->msi_attrib.entry_nr; 496 entry->masked = readl(base + vector * PCI_MSIX_ENTRY_SIZE + 497 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 498 } 499 500 return 0; 501} 502 503/** 504 * pci_msi_check_device - check whether MSI may be enabled on a device 505 * @dev: pointer to the pci_dev data structure of MSI device function 506 * @nvec: how many MSIs have been requested ? 507 * @type: are we checking for MSI or MSI-X ? 508 * 509 * Look at global flags, the device itself, and its parent busses 510 * to determine if MSI/-X are supported for the device. If MSI/-X is 511 * supported return 0, else return an error code. 512 **/ 513static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) 514{ 515 struct pci_bus *bus; 516 int ret; 517 518 /* MSI must be globally enabled and supported by the device */ 519 if (!pci_msi_enable || !dev || dev->no_msi) 520 return -EINVAL; 521 522 /* 523 * You can't ask to have 0 or less MSIs configured. 524 * a) it's stupid .. 525 * b) the list manipulation code assumes nvec >= 1. 526 */ 527 if (nvec < 1) 528 return -ERANGE; 529 530 /* Any bridge which does NOT route MSI transactions from it's 531 * secondary bus to it's primary bus must set NO_MSI flag on 532 * the secondary pci_bus. 533 * We expect only arch-specific PCI host bus controller driver 534 * or quirks for specific PCI bridges to be setting NO_MSI. 535 */ 536 for (bus = dev->bus; bus; bus = bus->parent) 537 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 538 return -EINVAL; 539 540 ret = arch_msi_check_device(dev, nvec, type); 541 if (ret) 542 return ret; 543 544 if (!pci_find_capability(dev, type)) 545 return -EINVAL; 546 547 return 0; 548} 549 550/** 551 * pci_enable_msi_block - configure device's MSI capability structure 552 * @dev: device to configure 553 * @nvec: number of interrupts to configure 554 * 555 * Allocate IRQs for a device with the MSI capability. 556 * This function returns a negative errno if an error occurs. If it 557 * is unable to allocate the number of interrupts requested, it returns 558 * the number of interrupts it might be able to allocate. If it successfully 559 * allocates at least the number of interrupts requested, it returns 0 and 560 * updates the @dev's irq member to the lowest new interrupt number; the 561 * other interrupt numbers allocated to this device are consecutive. 562 */ 563int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 564{ 565 int status, pos, maxvec; 566 u16 msgctl; 567 568 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 569 if (!pos) 570 return -EINVAL; 571 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); 572 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); 573 if (nvec > maxvec) 574 return maxvec; 575 576 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); 577 if (status) 578 return status; 579 580 WARN_ON(!!dev->msi_enabled); 581 582 /* Check whether driver already requested MSI-X irqs */ 583 if (dev->msix_enabled) { 584 dev_info(&dev->dev, "can't enable MSI " 585 "(MSI-X already enabled)\n"); 586 return -EINVAL; 587 } 588 589 status = msi_capability_init(dev, nvec); 590 return status; 591} 592EXPORT_SYMBOL(pci_enable_msi_block); 593 594void pci_msi_shutdown(struct pci_dev *dev) 595{ 596 struct msi_desc *desc; 597 u32 mask; 598 u16 ctrl; 599 600 if (!pci_msi_enable || !dev || !dev->msi_enabled) 601 return; 602 603 msi_set_enable(dev, 0); 604 pci_intx_for_msi(dev, 1); 605 dev->msi_enabled = 0; 606 607 BUG_ON(list_empty(&dev->msi_list)); 608 desc = list_first_entry(&dev->msi_list, struct msi_desc, list); 609 pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &ctrl); 610 mask = msi_capable_mask(ctrl); 611 msi_mask_irq(desc, mask, ~mask); 612 613 /* Restore dev->irq to its default pin-assertion irq */ 614 dev->irq = desc->msi_attrib.default_irq; 615} 616 617void pci_disable_msi(struct pci_dev* dev) 618{ 619 struct msi_desc *entry; 620 621 if (!pci_msi_enable || !dev || !dev->msi_enabled) 622 return; 623 624 pci_msi_shutdown(dev); 625 626 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 627 if (entry->msi_attrib.is_msix) 628 return; 629 630 msi_free_irqs(dev); 631} 632EXPORT_SYMBOL(pci_disable_msi); 633 634static int msi_free_irqs(struct pci_dev* dev) 635{ 636 struct msi_desc *entry, *tmp; 637 638 list_for_each_entry(entry, &dev->msi_list, list) { 639 int i, nvec; 640 if (!entry->irq) 641 continue; 642 nvec = 1 << entry->msi_attrib.multiple; 643 for (i = 0; i < nvec; i++) 644 BUG_ON(irq_has_action(entry->irq + i)); 645 } 646 647 arch_teardown_msi_irqs(dev); 648 649 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { 650 if (entry->msi_attrib.is_msix) { 651 writel(1, entry->mask_base + entry->msi_attrib.entry_nr 652 * PCI_MSIX_ENTRY_SIZE 653 + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 654 655 if (list_is_last(&entry->list, &dev->msi_list)) 656 iounmap(entry->mask_base); 657 } 658 list_del(&entry->list); 659 kfree(entry); 660 } 661 662 return 0; 663} 664 665/** 666 * pci_msix_table_size - return the number of device's MSI-X table entries 667 * @dev: pointer to the pci_dev data structure of MSI-X device function 668 */ 669int pci_msix_table_size(struct pci_dev *dev) 670{ 671 int pos; 672 u16 control; 673 674 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 675 if (!pos) 676 return 0; 677 678 pci_read_config_word(dev, msi_control_reg(pos), &control); 679 return multi_msix_capable(control); 680} 681 682/** 683 * pci_enable_msix - configure device's MSI-X capability structure 684 * @dev: pointer to the pci_dev data structure of MSI-X device function 685 * @entries: pointer to an array of MSI-X entries 686 * @nvec: number of MSI-X irqs requested for allocation by device driver 687 * 688 * Setup the MSI-X capability structure of device function with the number 689 * of requested irqs upon its software driver call to request for 690 * MSI-X mode enabled on its hardware device function. A return of zero 691 * indicates the successful configuration of MSI-X capability structure 692 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 693 * Or a return of > 0 indicates that driver request is exceeding the number 694 * of irqs available. Driver should use the returned value to re-send 695 * its request. 696 **/ 697int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 698{ 699 int status, nr_entries; 700 int i, j; 701 702 if (!entries) 703 return -EINVAL; 704 705 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); 706 if (status) 707 return status; 708 709 nr_entries = pci_msix_table_size(dev); 710 if (nvec > nr_entries) 711 return -EINVAL; 712 713 /* Check for any invalid entries */ 714 for (i = 0; i < nvec; i++) { 715 if (entries[i].entry >= nr_entries) 716 return -EINVAL; /* invalid entry */ 717 for (j = i + 1; j < nvec; j++) { 718 if (entries[i].entry == entries[j].entry) 719 return -EINVAL; /* duplicate entry */ 720 } 721 } 722 WARN_ON(!!dev->msix_enabled); 723 724 /* Check whether driver already requested for MSI irq */ 725 if (dev->msi_enabled) { 726 dev_info(&dev->dev, "can't enable MSI-X " 727 "(MSI IRQ already assigned)\n"); 728 return -EINVAL; 729 } 730 status = msix_capability_init(dev, entries, nvec); 731 return status; 732} 733EXPORT_SYMBOL(pci_enable_msix); 734 735static void msix_free_all_irqs(struct pci_dev *dev) 736{ 737 msi_free_irqs(dev); 738} 739 740void pci_msix_shutdown(struct pci_dev* dev) 741{ 742 if (!pci_msi_enable || !dev || !dev->msix_enabled) 743 return; 744 745 msix_set_enable(dev, 0); 746 pci_intx_for_msi(dev, 1); 747 dev->msix_enabled = 0; 748} 749void pci_disable_msix(struct pci_dev* dev) 750{ 751 if (!pci_msi_enable || !dev || !dev->msix_enabled) 752 return; 753 754 pci_msix_shutdown(dev); 755 756 msix_free_all_irqs(dev); 757} 758EXPORT_SYMBOL(pci_disable_msix); 759 760/** 761 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 762 * @dev: pointer to the pci_dev data structure of MSI(X) device function 763 * 764 * Being called during hotplug remove, from which the device function 765 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 766 * allocated for this device function, are reclaimed to unused state, 767 * which may be used later on. 768 **/ 769void msi_remove_pci_irq_vectors(struct pci_dev* dev) 770{ 771 if (!pci_msi_enable || !dev) 772 return; 773 774 if (dev->msi_enabled) 775 msi_free_irqs(dev); 776 777 if (dev->msix_enabled) 778 msix_free_all_irqs(dev); 779} 780 781void pci_no_msi(void) 782{ 783 pci_msi_enable = 0; 784} 785 786/** 787 * pci_msi_enabled - is MSI enabled? 788 * 789 * Returns true if MSI has not been disabled by the command-line option 790 * pci=nomsi. 791 **/ 792int pci_msi_enabled(void) 793{ 794 return pci_msi_enable; 795} 796EXPORT_SYMBOL(pci_msi_enabled); 797 798void pci_msi_init_pci_dev(struct pci_dev *dev) 799{ 800 INIT_LIST_HEAD(&dev->msi_list); 801} 802