msi.c revision 92db6d10bc1bc43330a4c540fa5b64c83d9d865f
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/mm.h> 10#include <linux/irq.h> 11#include <linux/interrupt.h> 12#include <linux/init.h> 13#include <linux/ioport.h> 14#include <linux/smp_lock.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17 18#include <asm/errno.h> 19#include <asm/io.h> 20#include <asm/smp.h> 21 22#include "pci.h" 23#include "msi.h" 24 25static DEFINE_SPINLOCK(msi_lock); 26static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; 27static kmem_cache_t* msi_cachep; 28 29static int pci_msi_enable = 1; 30static int last_alloc_vector; 31static int nr_released_vectors; 32 33#ifndef CONFIG_X86_IO_APIC 34int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1}; 35#endif 36 37static struct msi_ops *msi_ops; 38 39int 40msi_register(struct msi_ops *ops) 41{ 42 msi_ops = ops; 43 return 0; 44} 45 46static int msi_cache_init(void) 47{ 48 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), 49 0, SLAB_HWCACHE_ALIGN, NULL, NULL); 50 if (!msi_cachep) 51 return -ENOMEM; 52 53 return 0; 54} 55 56static void msi_set_mask_bit(unsigned int vector, int flag) 57{ 58 struct msi_desc *entry; 59 60 entry = (struct msi_desc *)msi_desc[vector]; 61 if (!entry || !entry->dev || !entry->mask_base) 62 return; 63 switch (entry->msi_attrib.type) { 64 case PCI_CAP_ID_MSI: 65 { 66 int pos; 67 u32 mask_bits; 68 69 pos = (long)entry->mask_base; 70 pci_read_config_dword(entry->dev, pos, &mask_bits); 71 mask_bits &= ~(1); 72 mask_bits |= flag; 73 pci_write_config_dword(entry->dev, pos, mask_bits); 74 break; 75 } 76 case PCI_CAP_ID_MSIX: 77 { 78 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 79 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 80 writel(flag, entry->mask_base + offset); 81 break; 82 } 83 default: 84 break; 85 } 86} 87 88static void read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) 89{ 90 switch(entry->msi_attrib.type) { 91 case PCI_CAP_ID_MSI: 92 { 93 struct pci_dev *dev = entry->dev; 94 int pos = entry->msi_attrib.pos; 95 u16 data; 96 97 pci_read_config_dword(dev, msi_lower_address_reg(pos), 98 &msg->address_lo); 99 if (entry->msi_attrib.is_64) { 100 pci_read_config_dword(dev, msi_upper_address_reg(pos), 101 &msg->address_hi); 102 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 103 } else { 104 msg->address_hi = 0; 105 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 106 } 107 msg->data = data; 108 break; 109 } 110 case PCI_CAP_ID_MSIX: 111 { 112 void __iomem *base; 113 base = entry->mask_base + 114 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 115 116 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 117 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 118 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 119 break; 120 } 121 default: 122 BUG(); 123 } 124} 125 126static void write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) 127{ 128 switch (entry->msi_attrib.type) { 129 case PCI_CAP_ID_MSI: 130 { 131 struct pci_dev *dev = entry->dev; 132 int pos = entry->msi_attrib.pos; 133 134 pci_write_config_dword(dev, msi_lower_address_reg(pos), 135 msg->address_lo); 136 if (entry->msi_attrib.is_64) { 137 pci_write_config_dword(dev, msi_upper_address_reg(pos), 138 msg->address_hi); 139 pci_write_config_word(dev, msi_data_reg(pos, 1), 140 msg->data); 141 } else { 142 pci_write_config_word(dev, msi_data_reg(pos, 0), 143 msg->data); 144 } 145 break; 146 } 147 case PCI_CAP_ID_MSIX: 148 { 149 void __iomem *base; 150 base = entry->mask_base + 151 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 152 153 writel(msg->address_lo, 154 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 155 writel(msg->address_hi, 156 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 157 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 158 break; 159 } 160 default: 161 BUG(); 162 } 163} 164 165#ifdef CONFIG_SMP 166static void set_msi_affinity(unsigned int irq, cpumask_t cpu_mask) 167{ 168 struct msi_desc *entry; 169 struct msi_msg msg; 170 171 entry = msi_desc[irq]; 172 if (!entry || !entry->dev) 173 return; 174 175 read_msi_msg(entry, &msg); 176 msi_ops->target(irq, cpu_mask, &msg); 177 write_msi_msg(entry, &msg); 178 set_native_irq_info(irq, cpu_mask); 179} 180#else 181#define set_msi_affinity NULL 182#endif /* CONFIG_SMP */ 183 184static void mask_MSI_irq(unsigned int vector) 185{ 186 msi_set_mask_bit(vector, 1); 187} 188 189static void unmask_MSI_irq(unsigned int vector) 190{ 191 msi_set_mask_bit(vector, 0); 192} 193 194static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector) 195{ 196 struct msi_desc *entry; 197 unsigned long flags; 198 199 spin_lock_irqsave(&msi_lock, flags); 200 entry = msi_desc[vector]; 201 if (!entry || !entry->dev) { 202 spin_unlock_irqrestore(&msi_lock, flags); 203 return 0; 204 } 205 entry->msi_attrib.state = 1; /* Mark it active */ 206 spin_unlock_irqrestore(&msi_lock, flags); 207 208 return 0; /* never anything pending */ 209} 210 211static unsigned int startup_msi_irq_w_maskbit(unsigned int vector) 212{ 213 startup_msi_irq_wo_maskbit(vector); 214 unmask_MSI_irq(vector); 215 return 0; /* never anything pending */ 216} 217 218static void shutdown_msi_irq(unsigned int vector) 219{ 220 struct msi_desc *entry; 221 unsigned long flags; 222 223 spin_lock_irqsave(&msi_lock, flags); 224 entry = msi_desc[vector]; 225 if (entry && entry->dev) 226 entry->msi_attrib.state = 0; /* Mark it not active */ 227 spin_unlock_irqrestore(&msi_lock, flags); 228} 229 230static void end_msi_irq_wo_maskbit(unsigned int vector) 231{ 232 move_native_irq(vector); 233 ack_APIC_irq(); 234} 235 236static void end_msi_irq_w_maskbit(unsigned int vector) 237{ 238 move_native_irq(vector); 239 unmask_MSI_irq(vector); 240 ack_APIC_irq(); 241} 242 243static void do_nothing(unsigned int vector) 244{ 245} 246 247/* 248 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices, 249 * which implement the MSI-X Capability Structure. 250 */ 251static struct hw_interrupt_type msix_irq_type = { 252 .typename = "PCI-MSI-X", 253 .startup = startup_msi_irq_w_maskbit, 254 .shutdown = shutdown_msi_irq, 255 .enable = unmask_MSI_irq, 256 .disable = mask_MSI_irq, 257 .ack = mask_MSI_irq, 258 .end = end_msi_irq_w_maskbit, 259 .set_affinity = set_msi_affinity 260}; 261 262/* 263 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, 264 * which implement the MSI Capability Structure with 265 * Mask-and-Pending Bits. 266 */ 267static struct hw_interrupt_type msi_irq_w_maskbit_type = { 268 .typename = "PCI-MSI", 269 .startup = startup_msi_irq_w_maskbit, 270 .shutdown = shutdown_msi_irq, 271 .enable = unmask_MSI_irq, 272 .disable = mask_MSI_irq, 273 .ack = mask_MSI_irq, 274 .end = end_msi_irq_w_maskbit, 275 .set_affinity = set_msi_affinity 276}; 277 278/* 279 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, 280 * which implement the MSI Capability Structure without 281 * Mask-and-Pending Bits. 282 */ 283static struct hw_interrupt_type msi_irq_wo_maskbit_type = { 284 .typename = "PCI-MSI", 285 .startup = startup_msi_irq_wo_maskbit, 286 .shutdown = shutdown_msi_irq, 287 .enable = do_nothing, 288 .disable = do_nothing, 289 .ack = do_nothing, 290 .end = end_msi_irq_wo_maskbit, 291 .set_affinity = set_msi_affinity 292}; 293 294static int msi_free_vector(struct pci_dev* dev, int vector, int reassign); 295static int assign_msi_vector(void) 296{ 297 static int new_vector_avail = 1; 298 int vector; 299 unsigned long flags; 300 301 /* 302 * msi_lock is provided to ensure that successful allocation of MSI 303 * vector is assigned unique among drivers. 304 */ 305 spin_lock_irqsave(&msi_lock, flags); 306 307 if (!new_vector_avail) { 308 int free_vector = 0; 309 310 /* 311 * vector_irq[] = -1 indicates that this specific vector is: 312 * - assigned for MSI (since MSI have no associated IRQ) or 313 * - assigned for legacy if less than 16, or 314 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping 315 * vector_irq[] = 0 indicates that this vector, previously 316 * assigned for MSI, is freed by hotplug removed operations. 317 * This vector will be reused for any subsequent hotplug added 318 * operations. 319 * vector_irq[] > 0 indicates that this vector is assigned for 320 * IOxAPIC IRQs. This vector and its value provides a 1-to-1 321 * vector-to-IOxAPIC IRQ mapping. 322 */ 323 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { 324 if (vector_irq[vector] != 0) 325 continue; 326 free_vector = vector; 327 if (!msi_desc[vector]) 328 break; 329 else 330 continue; 331 } 332 if (!free_vector) { 333 spin_unlock_irqrestore(&msi_lock, flags); 334 return -EBUSY; 335 } 336 vector_irq[free_vector] = -1; 337 nr_released_vectors--; 338 spin_unlock_irqrestore(&msi_lock, flags); 339 if (msi_desc[free_vector] != NULL) { 340 struct pci_dev *dev; 341 int tail; 342 343 /* free all linked vectors before re-assign */ 344 do { 345 spin_lock_irqsave(&msi_lock, flags); 346 dev = msi_desc[free_vector]->dev; 347 tail = msi_desc[free_vector]->link.tail; 348 spin_unlock_irqrestore(&msi_lock, flags); 349 msi_free_vector(dev, tail, 1); 350 } while (free_vector != tail); 351 } 352 353 return free_vector; 354 } 355 vector = assign_irq_vector(AUTO_ASSIGN); 356 last_alloc_vector = vector; 357 if (vector == LAST_DEVICE_VECTOR) 358 new_vector_avail = 0; 359 360 spin_unlock_irqrestore(&msi_lock, flags); 361 return vector; 362} 363 364static int get_new_vector(void) 365{ 366 int vector = assign_msi_vector(); 367 368 if (vector > 0) 369 set_intr_gate(vector, interrupt[vector]); 370 371 return vector; 372} 373 374static int msi_init(void) 375{ 376 static int status = -ENOMEM; 377 378 if (!status) 379 return status; 380 381 if (pci_msi_quirk) { 382 pci_msi_enable = 0; 383 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n"); 384 status = -EINVAL; 385 return status; 386 } 387 388 status = msi_arch_init(); 389 if (status < 0) { 390 pci_msi_enable = 0; 391 printk(KERN_WARNING 392 "PCI: MSI arch init failed. MSI disabled.\n"); 393 return status; 394 } 395 396 if (! msi_ops) { 397 printk(KERN_WARNING 398 "PCI: MSI ops not registered. MSI disabled.\n"); 399 status = -EINVAL; 400 return status; 401 } 402 403 last_alloc_vector = assign_irq_vector(AUTO_ASSIGN); 404 status = msi_cache_init(); 405 if (status < 0) { 406 pci_msi_enable = 0; 407 printk(KERN_WARNING "PCI: MSI cache init failed\n"); 408 return status; 409 } 410 411 if (last_alloc_vector < 0) { 412 pci_msi_enable = 0; 413 printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n"); 414 status = -EBUSY; 415 return status; 416 } 417 vector_irq[last_alloc_vector] = 0; 418 nr_released_vectors++; 419 420 return status; 421} 422 423static int get_msi_vector(struct pci_dev *dev) 424{ 425 return get_new_vector(); 426} 427 428static struct msi_desc* alloc_msi_entry(void) 429{ 430 struct msi_desc *entry; 431 432 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); 433 if (!entry) 434 return NULL; 435 436 entry->link.tail = entry->link.head = 0; /* single message */ 437 entry->dev = NULL; 438 439 return entry; 440} 441 442static void attach_msi_entry(struct msi_desc *entry, int vector) 443{ 444 unsigned long flags; 445 446 spin_lock_irqsave(&msi_lock, flags); 447 msi_desc[vector] = entry; 448 spin_unlock_irqrestore(&msi_lock, flags); 449} 450 451static void irq_handler_init(int cap_id, int pos, int mask) 452{ 453 unsigned long flags; 454 455 spin_lock_irqsave(&irq_desc[pos].lock, flags); 456 if (cap_id == PCI_CAP_ID_MSIX) 457 irq_desc[pos].chip = &msix_irq_type; 458 else { 459 if (!mask) 460 irq_desc[pos].chip = &msi_irq_wo_maskbit_type; 461 else 462 irq_desc[pos].chip = &msi_irq_w_maskbit_type; 463 } 464 spin_unlock_irqrestore(&irq_desc[pos].lock, flags); 465} 466 467static void enable_msi_mode(struct pci_dev *dev, int pos, int type) 468{ 469 u16 control; 470 471 pci_read_config_word(dev, msi_control_reg(pos), &control); 472 if (type == PCI_CAP_ID_MSI) { 473 /* Set enabled bits to single MSI & enable MSI_enable bit */ 474 msi_enable(control, 1); 475 pci_write_config_word(dev, msi_control_reg(pos), control); 476 dev->msi_enabled = 1; 477 } else { 478 msix_enable(control); 479 pci_write_config_word(dev, msi_control_reg(pos), control); 480 dev->msix_enabled = 1; 481 } 482 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 483 /* PCI Express Endpoint device detected */ 484 pci_intx(dev, 0); /* disable intx */ 485 } 486} 487 488void disable_msi_mode(struct pci_dev *dev, int pos, int type) 489{ 490 u16 control; 491 492 pci_read_config_word(dev, msi_control_reg(pos), &control); 493 if (type == PCI_CAP_ID_MSI) { 494 /* Set enabled bits to single MSI & enable MSI_enable bit */ 495 msi_disable(control); 496 pci_write_config_word(dev, msi_control_reg(pos), control); 497 dev->msi_enabled = 0; 498 } else { 499 msix_disable(control); 500 pci_write_config_word(dev, msi_control_reg(pos), control); 501 dev->msix_enabled = 0; 502 } 503 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 504 /* PCI Express Endpoint device detected */ 505 pci_intx(dev, 1); /* enable intx */ 506 } 507} 508 509static int msi_lookup_vector(struct pci_dev *dev, int type) 510{ 511 int vector; 512 unsigned long flags; 513 514 spin_lock_irqsave(&msi_lock, flags); 515 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { 516 if (!msi_desc[vector] || msi_desc[vector]->dev != dev || 517 msi_desc[vector]->msi_attrib.type != type || 518 msi_desc[vector]->msi_attrib.default_vector != dev->irq) 519 continue; 520 spin_unlock_irqrestore(&msi_lock, flags); 521 /* This pre-assigned MSI vector for this device 522 already exits. Override dev->irq with this vector */ 523 dev->irq = vector; 524 return 0; 525 } 526 spin_unlock_irqrestore(&msi_lock, flags); 527 528 return -EACCES; 529} 530 531void pci_scan_msi_device(struct pci_dev *dev) 532{ 533 if (!dev) 534 return; 535} 536 537#ifdef CONFIG_PM 538int pci_save_msi_state(struct pci_dev *dev) 539{ 540 int pos, i = 0; 541 u16 control; 542 struct pci_cap_saved_state *save_state; 543 u32 *cap; 544 545 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 546 if (pos <= 0 || dev->no_msi) 547 return 0; 548 549 pci_read_config_word(dev, msi_control_reg(pos), &control); 550 if (!(control & PCI_MSI_FLAGS_ENABLE)) 551 return 0; 552 553 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, 554 GFP_KERNEL); 555 if (!save_state) { 556 printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); 557 return -ENOMEM; 558 } 559 cap = &save_state->data[0]; 560 561 pci_read_config_dword(dev, pos, &cap[i++]); 562 control = cap[0] >> 16; 563 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); 564 if (control & PCI_MSI_FLAGS_64BIT) { 565 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); 566 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); 567 } else 568 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); 569 if (control & PCI_MSI_FLAGS_MASKBIT) 570 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); 571 save_state->cap_nr = PCI_CAP_ID_MSI; 572 pci_add_saved_cap(dev, save_state); 573 return 0; 574} 575 576void pci_restore_msi_state(struct pci_dev *dev) 577{ 578 int i = 0, pos; 579 u16 control; 580 struct pci_cap_saved_state *save_state; 581 u32 *cap; 582 583 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); 584 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 585 if (!save_state || pos <= 0) 586 return; 587 cap = &save_state->data[0]; 588 589 control = cap[i++] >> 16; 590 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); 591 if (control & PCI_MSI_FLAGS_64BIT) { 592 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); 593 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); 594 } else 595 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); 596 if (control & PCI_MSI_FLAGS_MASKBIT) 597 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); 598 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 599 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 600 pci_remove_saved_cap(save_state); 601 kfree(save_state); 602} 603 604int pci_save_msix_state(struct pci_dev *dev) 605{ 606 int pos; 607 int temp; 608 int vector, head, tail = 0; 609 u16 control; 610 struct pci_cap_saved_state *save_state; 611 612 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 613 if (pos <= 0 || dev->no_msi) 614 return 0; 615 616 /* save the capability */ 617 pci_read_config_word(dev, msi_control_reg(pos), &control); 618 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 619 return 0; 620 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), 621 GFP_KERNEL); 622 if (!save_state) { 623 printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); 624 return -ENOMEM; 625 } 626 *((u16 *)&save_state->data[0]) = control; 627 628 /* save the table */ 629 temp = dev->irq; 630 if (msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 631 kfree(save_state); 632 return -EINVAL; 633 } 634 635 vector = head = dev->irq; 636 while (head != tail) { 637 struct msi_desc *entry; 638 639 entry = msi_desc[vector]; 640 read_msi_msg(entry, &entry->msg_save); 641 642 tail = msi_desc[vector]->link.tail; 643 vector = tail; 644 } 645 dev->irq = temp; 646 647 save_state->cap_nr = PCI_CAP_ID_MSIX; 648 pci_add_saved_cap(dev, save_state); 649 return 0; 650} 651 652void pci_restore_msix_state(struct pci_dev *dev) 653{ 654 u16 save; 655 int pos; 656 int vector, head, tail = 0; 657 struct msi_desc *entry; 658 int temp; 659 struct pci_cap_saved_state *save_state; 660 661 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); 662 if (!save_state) 663 return; 664 save = *((u16 *)&save_state->data[0]); 665 pci_remove_saved_cap(save_state); 666 kfree(save_state); 667 668 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 669 if (pos <= 0) 670 return; 671 672 /* route the table */ 673 temp = dev->irq; 674 if (msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) 675 return; 676 vector = head = dev->irq; 677 while (head != tail) { 678 entry = msi_desc[vector]; 679 write_msi_msg(entry, &entry->msg_save); 680 681 tail = msi_desc[vector]->link.tail; 682 vector = tail; 683 } 684 dev->irq = temp; 685 686 pci_write_config_word(dev, msi_control_reg(pos), save); 687 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 688} 689#endif 690 691static int msi_register_init(struct pci_dev *dev, struct msi_desc *entry) 692{ 693 int status; 694 struct msi_msg msg; 695 int pos; 696 u16 control; 697 698 pos = entry->msi_attrib.pos; 699 pci_read_config_word(dev, msi_control_reg(pos), &control); 700 701 /* Configure MSI capability structure */ 702 status = msi_ops->setup(dev, dev->irq, &msg); 703 if (status < 0) 704 return status; 705 706 write_msi_msg(entry, &msg); 707 if (entry->msi_attrib.maskbit) { 708 unsigned int maskbits, temp; 709 /* All MSIs are unmasked by default, Mask them all */ 710 pci_read_config_dword(dev, 711 msi_mask_bits_reg(pos, is_64bit_address(control)), 712 &maskbits); 713 temp = (1 << multi_msi_capable(control)); 714 temp = ((temp - 1) & ~temp); 715 maskbits |= temp; 716 pci_write_config_dword(dev, 717 msi_mask_bits_reg(pos, is_64bit_address(control)), 718 maskbits); 719 } 720 721 return 0; 722} 723 724/** 725 * msi_capability_init - configure device's MSI capability structure 726 * @dev: pointer to the pci_dev data structure of MSI device function 727 * 728 * Setup the MSI capability structure of device function with a single 729 * MSI vector, regardless of device function is capable of handling 730 * multiple messages. A return of zero indicates the successful setup 731 * of an entry zero with the new MSI vector or non-zero for otherwise. 732 **/ 733static int msi_capability_init(struct pci_dev *dev) 734{ 735 int status; 736 struct msi_desc *entry; 737 int pos, vector; 738 u16 control; 739 740 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 741 pci_read_config_word(dev, msi_control_reg(pos), &control); 742 /* MSI Entry Initialization */ 743 entry = alloc_msi_entry(); 744 if (!entry) 745 return -ENOMEM; 746 747 vector = get_msi_vector(dev); 748 if (vector < 0) { 749 kmem_cache_free(msi_cachep, entry); 750 return -EBUSY; 751 } 752 entry->link.head = vector; 753 entry->link.tail = vector; 754 entry->msi_attrib.type = PCI_CAP_ID_MSI; 755 entry->msi_attrib.state = 0; /* Mark it not active */ 756 entry->msi_attrib.is_64 = is_64bit_address(control); 757 entry->msi_attrib.entry_nr = 0; 758 entry->msi_attrib.maskbit = is_mask_bit_support(control); 759 entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */ 760 entry->msi_attrib.pos = pos; 761 dev->irq = vector; 762 entry->dev = dev; 763 if (is_mask_bit_support(control)) { 764 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, 765 is_64bit_address(control)); 766 } 767 /* Replace with MSI handler */ 768 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit); 769 /* Configure MSI capability structure */ 770 status = msi_register_init(dev, entry); 771 if (status != 0) { 772 dev->irq = entry->msi_attrib.default_vector; 773 kmem_cache_free(msi_cachep, entry); 774 return status; 775 } 776 777 attach_msi_entry(entry, vector); 778 /* Set MSI enabled bits */ 779 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 780 781 return 0; 782} 783 784/** 785 * msix_capability_init - configure device's MSI-X capability 786 * @dev: pointer to the pci_dev data structure of MSI-X device function 787 * @entries: pointer to an array of struct msix_entry entries 788 * @nvec: number of @entries 789 * 790 * Setup the MSI-X capability structure of device function with a 791 * single MSI-X vector. A return of zero indicates the successful setup of 792 * requested MSI-X entries with allocated vectors or non-zero for otherwise. 793 **/ 794static int msix_capability_init(struct pci_dev *dev, 795 struct msix_entry *entries, int nvec) 796{ 797 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; 798 struct msi_msg msg; 799 int status; 800 int vector, pos, i, j, nr_entries, temp = 0; 801 unsigned long phys_addr; 802 u32 table_offset; 803 u16 control; 804 u8 bir; 805 void __iomem *base; 806 807 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 808 /* Request & Map MSI-X table region */ 809 pci_read_config_word(dev, msi_control_reg(pos), &control); 810 nr_entries = multi_msix_capable(control); 811 812 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 813 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 814 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 815 phys_addr = pci_resource_start (dev, bir) + table_offset; 816 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 817 if (base == NULL) 818 return -ENOMEM; 819 820 /* MSI-X Table Initialization */ 821 for (i = 0; i < nvec; i++) { 822 entry = alloc_msi_entry(); 823 if (!entry) 824 break; 825 vector = get_msi_vector(dev); 826 if (vector < 0) { 827 kmem_cache_free(msi_cachep, entry); 828 break; 829 } 830 831 j = entries[i].entry; 832 entries[i].vector = vector; 833 entry->msi_attrib.type = PCI_CAP_ID_MSIX; 834 entry->msi_attrib.state = 0; /* Mark it not active */ 835 entry->msi_attrib.is_64 = 1; 836 entry->msi_attrib.entry_nr = j; 837 entry->msi_attrib.maskbit = 1; 838 entry->msi_attrib.default_vector = dev->irq; 839 entry->msi_attrib.pos = pos; 840 entry->dev = dev; 841 entry->mask_base = base; 842 if (!head) { 843 entry->link.head = vector; 844 entry->link.tail = vector; 845 head = entry; 846 } else { 847 entry->link.head = temp; 848 entry->link.tail = tail->link.tail; 849 tail->link.tail = vector; 850 head->link.head = vector; 851 } 852 temp = vector; 853 tail = entry; 854 /* Replace with MSI-X handler */ 855 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1); 856 /* Configure MSI-X capability structure */ 857 status = msi_ops->setup(dev, vector, &msg); 858 if (status < 0) 859 break; 860 861 write_msi_msg(entry, &msg); 862 attach_msi_entry(entry, vector); 863 } 864 if (i != nvec) { 865 int avail = i - 1; 866 i--; 867 for (; i >= 0; i--) { 868 vector = (entries + i)->vector; 869 msi_free_vector(dev, vector, 0); 870 (entries + i)->vector = 0; 871 } 872 /* If we had some success report the number of irqs 873 * we succeeded in setting up. 874 */ 875 if (avail <= 0) 876 avail = -EBUSY; 877 return avail; 878 } 879 /* Set MSI-X enabled bits */ 880 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 881 882 return 0; 883} 884 885/** 886 * pci_msi_supported - check whether MSI may be enabled on device 887 * @dev: pointer to the pci_dev data structure of MSI device function 888 * 889 * MSI must be globally enabled and supported by the device and its root 890 * bus. But, the root bus is not easy to find since some architectures 891 * have virtual busses on top of the PCI hierarchy (for instance the 892 * hypertransport bus), while the actual bus where MSI must be supported 893 * is below. So we test the MSI flag on all parent busses and assume 894 * that no quirk will ever set the NO_MSI flag on a non-root bus. 895 **/ 896static 897int pci_msi_supported(struct pci_dev * dev) 898{ 899 struct pci_bus *bus; 900 901 if (!pci_msi_enable || !dev || dev->no_msi) 902 return -EINVAL; 903 904 /* check MSI flags of all parent busses */ 905 for (bus = dev->bus; bus; bus = bus->parent) 906 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 907 return -EINVAL; 908 909 return 0; 910} 911 912/** 913 * pci_enable_msi - configure device's MSI capability structure 914 * @dev: pointer to the pci_dev data structure of MSI device function 915 * 916 * Setup the MSI capability structure of device function with 917 * a single MSI vector upon its software driver call to request for 918 * MSI mode enabled on its hardware device function. A return of zero 919 * indicates the successful setup of an entry zero with the new MSI 920 * vector or non-zero for otherwise. 921 **/ 922int pci_enable_msi(struct pci_dev* dev) 923{ 924 int pos, temp, status; 925 u16 control; 926 927 if (pci_msi_supported(dev) < 0) 928 return -EINVAL; 929 930 temp = dev->irq; 931 932 status = msi_init(); 933 if (status < 0) 934 return status; 935 936 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 937 if (!pos) 938 return -EINVAL; 939 940 pci_read_config_word(dev, msi_control_reg(pos), &control); 941 if (!is_64bit_address(control) && msi_ops->needs_64bit_address) 942 return -EINVAL; 943 944 WARN_ON(!msi_lookup_vector(dev, PCI_CAP_ID_MSI)); 945 946 /* Check whether driver already requested for MSI-X vectors */ 947 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 948 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 949 printk(KERN_INFO "PCI: %s: Can't enable MSI. " 950 "Device already has MSI-X vectors assigned\n", 951 pci_name(dev)); 952 dev->irq = temp; 953 return -EINVAL; 954 } 955 status = msi_capability_init(dev); 956 return status; 957} 958 959void pci_disable_msi(struct pci_dev* dev) 960{ 961 struct msi_desc *entry; 962 int pos, default_vector; 963 u16 control; 964 unsigned long flags; 965 966 if (!pci_msi_enable) 967 return; 968 if (!dev) 969 return; 970 971 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 972 if (!pos) 973 return; 974 975 pci_read_config_word(dev, msi_control_reg(pos), &control); 976 if (!(control & PCI_MSI_FLAGS_ENABLE)) 977 return; 978 979 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 980 981 spin_lock_irqsave(&msi_lock, flags); 982 entry = msi_desc[dev->irq]; 983 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { 984 spin_unlock_irqrestore(&msi_lock, flags); 985 return; 986 } 987 if (entry->msi_attrib.state) { 988 spin_unlock_irqrestore(&msi_lock, flags); 989 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " 990 "free_irq() on MSI vector %d\n", 991 pci_name(dev), dev->irq); 992 BUG_ON(entry->msi_attrib.state > 0); 993 } else { 994 default_vector = entry->msi_attrib.default_vector; 995 spin_unlock_irqrestore(&msi_lock, flags); 996 msi_free_vector(dev, dev->irq, 0); 997 998 /* Restore dev->irq to its default pin-assertion vector */ 999 dev->irq = default_vector; 1000 } 1001} 1002 1003static int msi_free_vector(struct pci_dev* dev, int vector, int reassign) 1004{ 1005 struct msi_desc *entry; 1006 int head, entry_nr, type; 1007 void __iomem *base; 1008 unsigned long flags; 1009 1010 msi_ops->teardown(vector); 1011 1012 spin_lock_irqsave(&msi_lock, flags); 1013 entry = msi_desc[vector]; 1014 if (!entry || entry->dev != dev) { 1015 spin_unlock_irqrestore(&msi_lock, flags); 1016 return -EINVAL; 1017 } 1018 type = entry->msi_attrib.type; 1019 entry_nr = entry->msi_attrib.entry_nr; 1020 head = entry->link.head; 1021 base = entry->mask_base; 1022 msi_desc[entry->link.head]->link.tail = entry->link.tail; 1023 msi_desc[entry->link.tail]->link.head = entry->link.head; 1024 entry->dev = NULL; 1025 if (!reassign) { 1026 vector_irq[vector] = 0; 1027 nr_released_vectors++; 1028 } 1029 msi_desc[vector] = NULL; 1030 spin_unlock_irqrestore(&msi_lock, flags); 1031 1032 kmem_cache_free(msi_cachep, entry); 1033 1034 if (type == PCI_CAP_ID_MSIX) { 1035 if (!reassign) 1036 writel(1, base + 1037 entry_nr * PCI_MSIX_ENTRY_SIZE + 1038 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 1039 1040 if (head == vector) 1041 iounmap(base); 1042 } 1043 1044 return 0; 1045} 1046 1047/** 1048 * pci_enable_msix - configure device's MSI-X capability structure 1049 * @dev: pointer to the pci_dev data structure of MSI-X device function 1050 * @entries: pointer to an array of MSI-X entries 1051 * @nvec: number of MSI-X vectors requested for allocation by device driver 1052 * 1053 * Setup the MSI-X capability structure of device function with the number 1054 * of requested vectors upon its software driver call to request for 1055 * MSI-X mode enabled on its hardware device function. A return of zero 1056 * indicates the successful configuration of MSI-X capability structure 1057 * with new allocated MSI-X vectors. A return of < 0 indicates a failure. 1058 * Or a return of > 0 indicates that driver request is exceeding the number 1059 * of vectors available. Driver should use the returned value to re-send 1060 * its request. 1061 **/ 1062int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 1063{ 1064 int status, pos, nr_entries; 1065 int i, j, temp; 1066 u16 control; 1067 1068 if (!entries || pci_msi_supported(dev) < 0) 1069 return -EINVAL; 1070 1071 status = msi_init(); 1072 if (status < 0) 1073 return status; 1074 1075 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1076 if (!pos) 1077 return -EINVAL; 1078 1079 pci_read_config_word(dev, msi_control_reg(pos), &control); 1080 nr_entries = multi_msix_capable(control); 1081 if (nvec > nr_entries) 1082 return -EINVAL; 1083 1084 /* Check for any invalid entries */ 1085 for (i = 0; i < nvec; i++) { 1086 if (entries[i].entry >= nr_entries) 1087 return -EINVAL; /* invalid entry */ 1088 for (j = i + 1; j < nvec; j++) { 1089 if (entries[i].entry == entries[j].entry) 1090 return -EINVAL; /* duplicate entry */ 1091 } 1092 } 1093 temp = dev->irq; 1094 WARN_ON(!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)); 1095 1096 /* Check whether driver already requested for MSI vector */ 1097 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && 1098 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { 1099 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " 1100 "Device already has an MSI vector assigned\n", 1101 pci_name(dev)); 1102 dev->irq = temp; 1103 return -EINVAL; 1104 } 1105 status = msix_capability_init(dev, entries, nvec); 1106 return status; 1107} 1108 1109void pci_disable_msix(struct pci_dev* dev) 1110{ 1111 int pos, temp; 1112 u16 control; 1113 1114 if (!pci_msi_enable) 1115 return; 1116 if (!dev) 1117 return; 1118 1119 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1120 if (!pos) 1121 return; 1122 1123 pci_read_config_word(dev, msi_control_reg(pos), &control); 1124 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 1125 return; 1126 1127 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 1128 1129 temp = dev->irq; 1130 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 1131 int state, vector, head, tail = 0, warning = 0; 1132 unsigned long flags; 1133 1134 vector = head = dev->irq; 1135 dev->irq = temp; /* Restore pin IRQ */ 1136 while (head != tail) { 1137 spin_lock_irqsave(&msi_lock, flags); 1138 state = msi_desc[vector]->msi_attrib.state; 1139 tail = msi_desc[vector]->link.tail; 1140 spin_unlock_irqrestore(&msi_lock, flags); 1141 if (state) 1142 warning = 1; 1143 else if (vector != head) /* Release MSI-X vector */ 1144 msi_free_vector(dev, vector, 0); 1145 vector = tail; 1146 } 1147 msi_free_vector(dev, vector, 0); 1148 if (warning) { 1149 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " 1150 "free_irq() on all MSI-X vectors\n", 1151 pci_name(dev)); 1152 BUG_ON(warning > 0); 1153 } 1154 } 1155} 1156 1157/** 1158 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state 1159 * @dev: pointer to the pci_dev data structure of MSI(X) device function 1160 * 1161 * Being called during hotplug remove, from which the device function 1162 * is hot-removed. All previous assigned MSI/MSI-X vectors, if 1163 * allocated for this device function, are reclaimed to unused state, 1164 * which may be used later on. 1165 **/ 1166void msi_remove_pci_irq_vectors(struct pci_dev* dev) 1167{ 1168 int state, pos, temp; 1169 unsigned long flags; 1170 1171 if (!pci_msi_enable || !dev) 1172 return; 1173 1174 temp = dev->irq; /* Save IOAPIC IRQ */ 1175 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 1176 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { 1177 spin_lock_irqsave(&msi_lock, flags); 1178 state = msi_desc[dev->irq]->msi_attrib.state; 1179 spin_unlock_irqrestore(&msi_lock, flags); 1180 if (state) { 1181 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 1182 "called without free_irq() on MSI vector %d\n", 1183 pci_name(dev), dev->irq); 1184 BUG_ON(state > 0); 1185 } else /* Release MSI vector assigned to this device */ 1186 msi_free_vector(dev, dev->irq, 0); 1187 dev->irq = temp; /* Restore IOAPIC IRQ */ 1188 } 1189 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1190 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 1191 int vector, head, tail = 0, warning = 0; 1192 void __iomem *base = NULL; 1193 1194 vector = head = dev->irq; 1195 while (head != tail) { 1196 spin_lock_irqsave(&msi_lock, flags); 1197 state = msi_desc[vector]->msi_attrib.state; 1198 tail = msi_desc[vector]->link.tail; 1199 base = msi_desc[vector]->mask_base; 1200 spin_unlock_irqrestore(&msi_lock, flags); 1201 if (state) 1202 warning = 1; 1203 else if (vector != head) /* Release MSI-X vector */ 1204 msi_free_vector(dev, vector, 0); 1205 vector = tail; 1206 } 1207 msi_free_vector(dev, vector, 0); 1208 if (warning) { 1209 iounmap(base); 1210 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 1211 "called without free_irq() on all MSI-X vectors\n", 1212 pci_name(dev)); 1213 BUG_ON(warning > 0); 1214 } 1215 dev->irq = temp; /* Restore IOAPIC IRQ */ 1216 } 1217} 1218 1219void pci_no_msi(void) 1220{ 1221 pci_msi_enable = 0; 1222} 1223 1224EXPORT_SYMBOL(pci_enable_msi); 1225EXPORT_SYMBOL(pci_disable_msi); 1226EXPORT_SYMBOL(pci_enable_msix); 1227EXPORT_SYMBOL(pci_disable_msix); 1228