msi.c revision 99dc804d9bcc2c53f4c20c291bf4e185312a1a0c
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/mm.h> 10#include <linux/irq.h> 11#include <linux/interrupt.h> 12#include <linux/init.h> 13#include <linux/config.h> 14#include <linux/ioport.h> 15#include <linux/smp_lock.h> 16#include <linux/pci.h> 17#include <linux/proc_fs.h> 18 19#include <asm/errno.h> 20#include <asm/io.h> 21#include <asm/smp.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static DEFINE_SPINLOCK(msi_lock); 27static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; 28static kmem_cache_t* msi_cachep; 29 30static int pci_msi_enable = 1; 31static int last_alloc_vector; 32static int nr_released_vectors; 33static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS; 34static int nr_msix_devices; 35 36#ifndef CONFIG_X86_IO_APIC 37int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1}; 38u8 irq_vector[NR_IRQ_VECTORS]; 39#endif 40 41static struct msi_ops *msi_ops; 42 43int 44msi_register(struct msi_ops *ops) 45{ 46 msi_ops = ops; 47 return 0; 48} 49 50static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags) 51{ 52 memset(p, 0, NR_IRQS * sizeof(struct msi_desc)); 53} 54 55static int msi_cache_init(void) 56{ 57 msi_cachep = kmem_cache_create("msi_cache", 58 NR_IRQS * sizeof(struct msi_desc), 59 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL); 60 if (!msi_cachep) 61 return -ENOMEM; 62 63 return 0; 64} 65 66static void msi_set_mask_bit(unsigned int vector, int flag) 67{ 68 struct msi_desc *entry; 69 70 entry = (struct msi_desc *)msi_desc[vector]; 71 if (!entry || !entry->dev || !entry->mask_base) 72 return; 73 switch (entry->msi_attrib.type) { 74 case PCI_CAP_ID_MSI: 75 { 76 int pos; 77 u32 mask_bits; 78 79 pos = (long)entry->mask_base; 80 pci_read_config_dword(entry->dev, pos, &mask_bits); 81 mask_bits &= ~(1); 82 mask_bits |= flag; 83 pci_write_config_dword(entry->dev, pos, mask_bits); 84 break; 85 } 86 case PCI_CAP_ID_MSIX: 87 { 88 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 89 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 90 writel(flag, entry->mask_base + offset); 91 break; 92 } 93 default: 94 break; 95 } 96} 97 98#ifdef CONFIG_SMP 99static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask) 100{ 101 struct msi_desc *entry; 102 u32 address_hi, address_lo; 103 unsigned int irq = vector; 104 unsigned int dest_cpu = first_cpu(cpu_mask); 105 106 entry = (struct msi_desc *)msi_desc[vector]; 107 if (!entry || !entry->dev) 108 return; 109 110 switch (entry->msi_attrib.type) { 111 case PCI_CAP_ID_MSI: 112 { 113 int pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI); 114 115 if (!pos) 116 return; 117 118 pci_read_config_dword(entry->dev, msi_upper_address_reg(pos), 119 &address_hi); 120 pci_read_config_dword(entry->dev, msi_lower_address_reg(pos), 121 &address_lo); 122 123 msi_ops->target(vector, dest_cpu, &address_hi, &address_lo); 124 125 pci_write_config_dword(entry->dev, msi_upper_address_reg(pos), 126 address_hi); 127 pci_write_config_dword(entry->dev, msi_lower_address_reg(pos), 128 address_lo); 129 set_native_irq_info(irq, cpu_mask); 130 break; 131 } 132 case PCI_CAP_ID_MSIX: 133 { 134 int offset_hi = 135 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 136 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET; 137 int offset_lo = 138 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 139 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET; 140 141 address_hi = readl(entry->mask_base + offset_hi); 142 address_lo = readl(entry->mask_base + offset_lo); 143 144 msi_ops->target(vector, dest_cpu, &address_hi, &address_lo); 145 146 writel(address_hi, entry->mask_base + offset_hi); 147 writel(address_lo, entry->mask_base + offset_lo); 148 set_native_irq_info(irq, cpu_mask); 149 break; 150 } 151 default: 152 break; 153 } 154} 155#else 156#define set_msi_affinity NULL 157#endif /* CONFIG_SMP */ 158 159static void mask_MSI_irq(unsigned int vector) 160{ 161 msi_set_mask_bit(vector, 1); 162} 163 164static void unmask_MSI_irq(unsigned int vector) 165{ 166 msi_set_mask_bit(vector, 0); 167} 168 169static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector) 170{ 171 struct msi_desc *entry; 172 unsigned long flags; 173 174 spin_lock_irqsave(&msi_lock, flags); 175 entry = msi_desc[vector]; 176 if (!entry || !entry->dev) { 177 spin_unlock_irqrestore(&msi_lock, flags); 178 return 0; 179 } 180 entry->msi_attrib.state = 1; /* Mark it active */ 181 spin_unlock_irqrestore(&msi_lock, flags); 182 183 return 0; /* never anything pending */ 184} 185 186static unsigned int startup_msi_irq_w_maskbit(unsigned int vector) 187{ 188 startup_msi_irq_wo_maskbit(vector); 189 unmask_MSI_irq(vector); 190 return 0; /* never anything pending */ 191} 192 193static void shutdown_msi_irq(unsigned int vector) 194{ 195 struct msi_desc *entry; 196 unsigned long flags; 197 198 spin_lock_irqsave(&msi_lock, flags); 199 entry = msi_desc[vector]; 200 if (entry && entry->dev) 201 entry->msi_attrib.state = 0; /* Mark it not active */ 202 spin_unlock_irqrestore(&msi_lock, flags); 203} 204 205static void end_msi_irq_wo_maskbit(unsigned int vector) 206{ 207 move_native_irq(vector); 208 ack_APIC_irq(); 209} 210 211static void end_msi_irq_w_maskbit(unsigned int vector) 212{ 213 move_native_irq(vector); 214 unmask_MSI_irq(vector); 215 ack_APIC_irq(); 216} 217 218static void do_nothing(unsigned int vector) 219{ 220} 221 222/* 223 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices, 224 * which implement the MSI-X Capability Structure. 225 */ 226static struct hw_interrupt_type msix_irq_type = { 227 .typename = "PCI-MSI-X", 228 .startup = startup_msi_irq_w_maskbit, 229 .shutdown = shutdown_msi_irq, 230 .enable = unmask_MSI_irq, 231 .disable = mask_MSI_irq, 232 .ack = mask_MSI_irq, 233 .end = end_msi_irq_w_maskbit, 234 .set_affinity = set_msi_affinity 235}; 236 237/* 238 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, 239 * which implement the MSI Capability Structure with 240 * Mask-and-Pending Bits. 241 */ 242static struct hw_interrupt_type msi_irq_w_maskbit_type = { 243 .typename = "PCI-MSI", 244 .startup = startup_msi_irq_w_maskbit, 245 .shutdown = shutdown_msi_irq, 246 .enable = unmask_MSI_irq, 247 .disable = mask_MSI_irq, 248 .ack = mask_MSI_irq, 249 .end = end_msi_irq_w_maskbit, 250 .set_affinity = set_msi_affinity 251}; 252 253/* 254 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, 255 * which implement the MSI Capability Structure without 256 * Mask-and-Pending Bits. 257 */ 258static struct hw_interrupt_type msi_irq_wo_maskbit_type = { 259 .typename = "PCI-MSI", 260 .startup = startup_msi_irq_wo_maskbit, 261 .shutdown = shutdown_msi_irq, 262 .enable = do_nothing, 263 .disable = do_nothing, 264 .ack = do_nothing, 265 .end = end_msi_irq_wo_maskbit, 266 .set_affinity = set_msi_affinity 267}; 268 269static int msi_free_vector(struct pci_dev* dev, int vector, int reassign); 270static int assign_msi_vector(void) 271{ 272 static int new_vector_avail = 1; 273 int vector; 274 unsigned long flags; 275 276 /* 277 * msi_lock is provided to ensure that successful allocation of MSI 278 * vector is assigned unique among drivers. 279 */ 280 spin_lock_irqsave(&msi_lock, flags); 281 282 if (!new_vector_avail) { 283 int free_vector = 0; 284 285 /* 286 * vector_irq[] = -1 indicates that this specific vector is: 287 * - assigned for MSI (since MSI have no associated IRQ) or 288 * - assigned for legacy if less than 16, or 289 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping 290 * vector_irq[] = 0 indicates that this vector, previously 291 * assigned for MSI, is freed by hotplug removed operations. 292 * This vector will be reused for any subsequent hotplug added 293 * operations. 294 * vector_irq[] > 0 indicates that this vector is assigned for 295 * IOxAPIC IRQs. This vector and its value provides a 1-to-1 296 * vector-to-IOxAPIC IRQ mapping. 297 */ 298 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { 299 if (vector_irq[vector] != 0) 300 continue; 301 free_vector = vector; 302 if (!msi_desc[vector]) 303 break; 304 else 305 continue; 306 } 307 if (!free_vector) { 308 spin_unlock_irqrestore(&msi_lock, flags); 309 return -EBUSY; 310 } 311 vector_irq[free_vector] = -1; 312 nr_released_vectors--; 313 spin_unlock_irqrestore(&msi_lock, flags); 314 if (msi_desc[free_vector] != NULL) { 315 struct pci_dev *dev; 316 int tail; 317 318 /* free all linked vectors before re-assign */ 319 do { 320 spin_lock_irqsave(&msi_lock, flags); 321 dev = msi_desc[free_vector]->dev; 322 tail = msi_desc[free_vector]->link.tail; 323 spin_unlock_irqrestore(&msi_lock, flags); 324 msi_free_vector(dev, tail, 1); 325 } while (free_vector != tail); 326 } 327 328 return free_vector; 329 } 330 vector = assign_irq_vector(AUTO_ASSIGN); 331 last_alloc_vector = vector; 332 if (vector == LAST_DEVICE_VECTOR) 333 new_vector_avail = 0; 334 335 spin_unlock_irqrestore(&msi_lock, flags); 336 return vector; 337} 338 339static int get_new_vector(void) 340{ 341 int vector = assign_msi_vector(); 342 343 if (vector > 0) 344 set_intr_gate(vector, interrupt[vector]); 345 346 return vector; 347} 348 349static int msi_init(void) 350{ 351 static int status = -ENOMEM; 352 353 if (!status) 354 return status; 355 356 if (pci_msi_quirk) { 357 pci_msi_enable = 0; 358 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n"); 359 status = -EINVAL; 360 return status; 361 } 362 363 status = msi_arch_init(); 364 if (status < 0) { 365 pci_msi_enable = 0; 366 printk(KERN_WARNING 367 "PCI: MSI arch init failed. MSI disabled.\n"); 368 return status; 369 } 370 371 if (! msi_ops) { 372 printk(KERN_WARNING 373 "PCI: MSI ops not registered. MSI disabled.\n"); 374 status = -EINVAL; 375 return status; 376 } 377 378 last_alloc_vector = assign_irq_vector(AUTO_ASSIGN); 379 status = msi_cache_init(); 380 if (status < 0) { 381 pci_msi_enable = 0; 382 printk(KERN_WARNING "PCI: MSI cache init failed\n"); 383 return status; 384 } 385 386#ifndef CONFIG_X86_IO_APIC 387 irq_vector[0] = FIRST_DEVICE_VECTOR; 388#endif 389 390 if (last_alloc_vector < 0) { 391 pci_msi_enable = 0; 392 printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n"); 393 status = -EBUSY; 394 return status; 395 } 396 vector_irq[last_alloc_vector] = 0; 397 nr_released_vectors++; 398 399 return status; 400} 401 402static int get_msi_vector(struct pci_dev *dev) 403{ 404 return get_new_vector(); 405} 406 407static struct msi_desc* alloc_msi_entry(void) 408{ 409 struct msi_desc *entry; 410 411 entry = kmem_cache_alloc(msi_cachep, SLAB_KERNEL); 412 if (!entry) 413 return NULL; 414 415 memset(entry, 0, sizeof(struct msi_desc)); 416 entry->link.tail = entry->link.head = 0; /* single message */ 417 entry->dev = NULL; 418 419 return entry; 420} 421 422static void attach_msi_entry(struct msi_desc *entry, int vector) 423{ 424 unsigned long flags; 425 426 spin_lock_irqsave(&msi_lock, flags); 427 msi_desc[vector] = entry; 428 spin_unlock_irqrestore(&msi_lock, flags); 429} 430 431static void irq_handler_init(int cap_id, int pos, int mask) 432{ 433 unsigned long flags; 434 435 spin_lock_irqsave(&irq_desc[pos].lock, flags); 436 if (cap_id == PCI_CAP_ID_MSIX) 437 irq_desc[pos].handler = &msix_irq_type; 438 else { 439 if (!mask) 440 irq_desc[pos].handler = &msi_irq_wo_maskbit_type; 441 else 442 irq_desc[pos].handler = &msi_irq_w_maskbit_type; 443 } 444 spin_unlock_irqrestore(&irq_desc[pos].lock, flags); 445} 446 447static void enable_msi_mode(struct pci_dev *dev, int pos, int type) 448{ 449 u16 control; 450 451 pci_read_config_word(dev, msi_control_reg(pos), &control); 452 if (type == PCI_CAP_ID_MSI) { 453 /* Set enabled bits to single MSI & enable MSI_enable bit */ 454 msi_enable(control, 1); 455 pci_write_config_word(dev, msi_control_reg(pos), control); 456 dev->msi_enabled = 1; 457 } else { 458 msix_enable(control); 459 pci_write_config_word(dev, msi_control_reg(pos), control); 460 dev->msix_enabled = 1; 461 } 462 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 463 /* PCI Express Endpoint device detected */ 464 pci_intx(dev, 0); /* disable intx */ 465 } 466} 467 468void disable_msi_mode(struct pci_dev *dev, int pos, int type) 469{ 470 u16 control; 471 472 pci_read_config_word(dev, msi_control_reg(pos), &control); 473 if (type == PCI_CAP_ID_MSI) { 474 /* Set enabled bits to single MSI & enable MSI_enable bit */ 475 msi_disable(control); 476 pci_write_config_word(dev, msi_control_reg(pos), control); 477 dev->msi_enabled = 0; 478 } else { 479 msix_disable(control); 480 pci_write_config_word(dev, msi_control_reg(pos), control); 481 dev->msix_enabled = 0; 482 } 483 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 484 /* PCI Express Endpoint device detected */ 485 pci_intx(dev, 1); /* enable intx */ 486 } 487} 488 489static int msi_lookup_vector(struct pci_dev *dev, int type) 490{ 491 int vector; 492 unsigned long flags; 493 494 spin_lock_irqsave(&msi_lock, flags); 495 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { 496 if (!msi_desc[vector] || msi_desc[vector]->dev != dev || 497 msi_desc[vector]->msi_attrib.type != type || 498 msi_desc[vector]->msi_attrib.default_vector != dev->irq) 499 continue; 500 spin_unlock_irqrestore(&msi_lock, flags); 501 /* This pre-assigned MSI vector for this device 502 already exits. Override dev->irq with this vector */ 503 dev->irq = vector; 504 return 0; 505 } 506 spin_unlock_irqrestore(&msi_lock, flags); 507 508 return -EACCES; 509} 510 511void pci_scan_msi_device(struct pci_dev *dev) 512{ 513 if (!dev) 514 return; 515 516 if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0) 517 nr_msix_devices++; 518 else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0) 519 nr_reserved_vectors++; 520} 521 522#ifdef CONFIG_PM 523int pci_save_msi_state(struct pci_dev *dev) 524{ 525 int pos, i = 0; 526 u16 control; 527 struct pci_cap_saved_state *save_state; 528 u32 *cap; 529 530 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 531 if (pos <= 0 || dev->no_msi) 532 return 0; 533 534 pci_read_config_word(dev, msi_control_reg(pos), &control); 535 if (!(control & PCI_MSI_FLAGS_ENABLE)) 536 return 0; 537 538 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, 539 GFP_KERNEL); 540 if (!save_state) { 541 printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); 542 return -ENOMEM; 543 } 544 cap = &save_state->data[0]; 545 546 pci_read_config_dword(dev, pos, &cap[i++]); 547 control = cap[0] >> 16; 548 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); 549 if (control & PCI_MSI_FLAGS_64BIT) { 550 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); 551 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); 552 } else 553 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); 554 if (control & PCI_MSI_FLAGS_MASKBIT) 555 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); 556 save_state->cap_nr = PCI_CAP_ID_MSI; 557 pci_add_saved_cap(dev, save_state); 558 return 0; 559} 560 561void pci_restore_msi_state(struct pci_dev *dev) 562{ 563 int i = 0, pos; 564 u16 control; 565 struct pci_cap_saved_state *save_state; 566 u32 *cap; 567 568 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); 569 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 570 if (!save_state || pos <= 0) 571 return; 572 cap = &save_state->data[0]; 573 574 control = cap[i++] >> 16; 575 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); 576 if (control & PCI_MSI_FLAGS_64BIT) { 577 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); 578 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); 579 } else 580 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); 581 if (control & PCI_MSI_FLAGS_MASKBIT) 582 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); 583 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 584 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 585 pci_remove_saved_cap(save_state); 586 kfree(save_state); 587} 588 589int pci_save_msix_state(struct pci_dev *dev) 590{ 591 int pos; 592 int temp; 593 int vector, head, tail = 0; 594 u16 control; 595 struct pci_cap_saved_state *save_state; 596 597 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 598 if (pos <= 0 || dev->no_msi) 599 return 0; 600 601 /* save the capability */ 602 pci_read_config_word(dev, msi_control_reg(pos), &control); 603 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 604 return 0; 605 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), 606 GFP_KERNEL); 607 if (!save_state) { 608 printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); 609 return -ENOMEM; 610 } 611 *((u16 *)&save_state->data[0]) = control; 612 613 /* save the table */ 614 temp = dev->irq; 615 if (msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 616 kfree(save_state); 617 return -EINVAL; 618 } 619 620 vector = head = dev->irq; 621 while (head != tail) { 622 int j; 623 void __iomem *base; 624 struct msi_desc *entry; 625 626 entry = msi_desc[vector]; 627 base = entry->mask_base; 628 j = entry->msi_attrib.entry_nr; 629 630 entry->address_lo_save = 631 readl(base + j * PCI_MSIX_ENTRY_SIZE + 632 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 633 entry->address_hi_save = 634 readl(base + j * PCI_MSIX_ENTRY_SIZE + 635 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 636 entry->data_save = 637 readl(base + j * PCI_MSIX_ENTRY_SIZE + 638 PCI_MSIX_ENTRY_DATA_OFFSET); 639 640 tail = msi_desc[vector]->link.tail; 641 vector = tail; 642 } 643 dev->irq = temp; 644 645 save_state->cap_nr = PCI_CAP_ID_MSIX; 646 pci_add_saved_cap(dev, save_state); 647 return 0; 648} 649 650void pci_restore_msix_state(struct pci_dev *dev) 651{ 652 u16 save; 653 int pos; 654 int vector, head, tail = 0; 655 void __iomem *base; 656 int j; 657 struct msi_desc *entry; 658 int temp; 659 struct pci_cap_saved_state *save_state; 660 661 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); 662 if (!save_state) 663 return; 664 save = *((u16 *)&save_state->data[0]); 665 pci_remove_saved_cap(save_state); 666 kfree(save_state); 667 668 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 669 if (pos <= 0) 670 return; 671 672 /* route the table */ 673 temp = dev->irq; 674 if (msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) 675 return; 676 vector = head = dev->irq; 677 while (head != tail) { 678 entry = msi_desc[vector]; 679 base = entry->mask_base; 680 j = entry->msi_attrib.entry_nr; 681 682 writel(entry->address_lo_save, 683 base + j * PCI_MSIX_ENTRY_SIZE + 684 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 685 writel(entry->address_hi_save, 686 base + j * PCI_MSIX_ENTRY_SIZE + 687 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 688 writel(entry->data_save, 689 base + j * PCI_MSIX_ENTRY_SIZE + 690 PCI_MSIX_ENTRY_DATA_OFFSET); 691 692 tail = msi_desc[vector]->link.tail; 693 vector = tail; 694 } 695 dev->irq = temp; 696 697 pci_write_config_word(dev, msi_control_reg(pos), save); 698 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 699} 700#endif 701 702static int msi_register_init(struct pci_dev *dev, struct msi_desc *entry) 703{ 704 int status; 705 u32 address_hi; 706 u32 address_lo; 707 u32 data; 708 int pos, vector = dev->irq; 709 u16 control; 710 711 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 712 pci_read_config_word(dev, msi_control_reg(pos), &control); 713 714 /* Configure MSI capability structure */ 715 status = msi_ops->setup(dev, vector, &address_hi, &address_lo, &data); 716 if (status < 0) 717 return status; 718 719 pci_write_config_dword(dev, msi_lower_address_reg(pos), address_lo); 720 if (is_64bit_address(control)) { 721 pci_write_config_dword(dev, 722 msi_upper_address_reg(pos), address_hi); 723 pci_write_config_word(dev, 724 msi_data_reg(pos, 1), data); 725 } else 726 pci_write_config_word(dev, 727 msi_data_reg(pos, 0), data); 728 if (entry->msi_attrib.maskbit) { 729 unsigned int maskbits, temp; 730 /* All MSIs are unmasked by default, Mask them all */ 731 pci_read_config_dword(dev, 732 msi_mask_bits_reg(pos, is_64bit_address(control)), 733 &maskbits); 734 temp = (1 << multi_msi_capable(control)); 735 temp = ((temp - 1) & ~temp); 736 maskbits |= temp; 737 pci_write_config_dword(dev, 738 msi_mask_bits_reg(pos, is_64bit_address(control)), 739 maskbits); 740 } 741 742 return 0; 743} 744 745/** 746 * msi_capability_init - configure device's MSI capability structure 747 * @dev: pointer to the pci_dev data structure of MSI device function 748 * 749 * Setup the MSI capability structure of device function with a single 750 * MSI vector, regardless of device function is capable of handling 751 * multiple messages. A return of zero indicates the successful setup 752 * of an entry zero with the new MSI vector or non-zero for otherwise. 753 **/ 754static int msi_capability_init(struct pci_dev *dev) 755{ 756 int status; 757 struct msi_desc *entry; 758 int pos, vector; 759 u16 control; 760 761 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 762 pci_read_config_word(dev, msi_control_reg(pos), &control); 763 /* MSI Entry Initialization */ 764 entry = alloc_msi_entry(); 765 if (!entry) 766 return -ENOMEM; 767 768 vector = get_msi_vector(dev); 769 if (vector < 0) { 770 kmem_cache_free(msi_cachep, entry); 771 return -EBUSY; 772 } 773 entry->link.head = vector; 774 entry->link.tail = vector; 775 entry->msi_attrib.type = PCI_CAP_ID_MSI; 776 entry->msi_attrib.state = 0; /* Mark it not active */ 777 entry->msi_attrib.entry_nr = 0; 778 entry->msi_attrib.maskbit = is_mask_bit_support(control); 779 entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */ 780 dev->irq = vector; 781 entry->dev = dev; 782 if (is_mask_bit_support(control)) { 783 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, 784 is_64bit_address(control)); 785 } 786 /* Replace with MSI handler */ 787 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit); 788 /* Configure MSI capability structure */ 789 status = msi_register_init(dev, entry); 790 if (status != 0) { 791 dev->irq = entry->msi_attrib.default_vector; 792 kmem_cache_free(msi_cachep, entry); 793 return status; 794 } 795 796 attach_msi_entry(entry, vector); 797 /* Set MSI enabled bits */ 798 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 799 800 return 0; 801} 802 803/** 804 * msix_capability_init - configure device's MSI-X capability 805 * @dev: pointer to the pci_dev data structure of MSI-X device function 806 * @entries: pointer to an array of struct msix_entry entries 807 * @nvec: number of @entries 808 * 809 * Setup the MSI-X capability structure of device function with a 810 * single MSI-X vector. A return of zero indicates the successful setup of 811 * requested MSI-X entries with allocated vectors or non-zero for otherwise. 812 **/ 813static int msix_capability_init(struct pci_dev *dev, 814 struct msix_entry *entries, int nvec) 815{ 816 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; 817 u32 address_hi; 818 u32 address_lo; 819 u32 data; 820 int status; 821 int vector, pos, i, j, nr_entries, temp = 0; 822 unsigned long phys_addr; 823 u32 table_offset; 824 u16 control; 825 u8 bir; 826 void __iomem *base; 827 828 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 829 /* Request & Map MSI-X table region */ 830 pci_read_config_word(dev, msi_control_reg(pos), &control); 831 nr_entries = multi_msix_capable(control); 832 833 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 834 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 835 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 836 phys_addr = pci_resource_start (dev, bir) + table_offset; 837 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 838 if (base == NULL) 839 return -ENOMEM; 840 841 /* MSI-X Table Initialization */ 842 for (i = 0; i < nvec; i++) { 843 entry = alloc_msi_entry(); 844 if (!entry) 845 break; 846 vector = get_msi_vector(dev); 847 if (vector < 0) { 848 kmem_cache_free(msi_cachep, entry); 849 break; 850 } 851 852 j = entries[i].entry; 853 entries[i].vector = vector; 854 entry->msi_attrib.type = PCI_CAP_ID_MSIX; 855 entry->msi_attrib.state = 0; /* Mark it not active */ 856 entry->msi_attrib.entry_nr = j; 857 entry->msi_attrib.maskbit = 1; 858 entry->msi_attrib.default_vector = dev->irq; 859 entry->dev = dev; 860 entry->mask_base = base; 861 if (!head) { 862 entry->link.head = vector; 863 entry->link.tail = vector; 864 head = entry; 865 } else { 866 entry->link.head = temp; 867 entry->link.tail = tail->link.tail; 868 tail->link.tail = vector; 869 head->link.head = vector; 870 } 871 temp = vector; 872 tail = entry; 873 /* Replace with MSI-X handler */ 874 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1); 875 /* Configure MSI-X capability structure */ 876 status = msi_ops->setup(dev, vector, 877 &address_hi, 878 &address_lo, 879 &data); 880 if (status < 0) 881 break; 882 883 writel(address_lo, 884 base + j * PCI_MSIX_ENTRY_SIZE + 885 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 886 writel(address_hi, 887 base + j * PCI_MSIX_ENTRY_SIZE + 888 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 889 writel(data, 890 base + j * PCI_MSIX_ENTRY_SIZE + 891 PCI_MSIX_ENTRY_DATA_OFFSET); 892 attach_msi_entry(entry, vector); 893 } 894 if (i != nvec) { 895 i--; 896 for (; i >= 0; i--) { 897 vector = (entries + i)->vector; 898 msi_free_vector(dev, vector, 0); 899 (entries + i)->vector = 0; 900 } 901 return -EBUSY; 902 } 903 /* Set MSI-X enabled bits */ 904 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 905 906 return 0; 907} 908 909/** 910 * pci_enable_msi - configure device's MSI capability structure 911 * @dev: pointer to the pci_dev data structure of MSI device function 912 * 913 * Setup the MSI capability structure of device function with 914 * a single MSI vector upon its software driver call to request for 915 * MSI mode enabled on its hardware device function. A return of zero 916 * indicates the successful setup of an entry zero with the new MSI 917 * vector or non-zero for otherwise. 918 **/ 919int pci_enable_msi(struct pci_dev* dev) 920{ 921 struct pci_bus *bus; 922 int pos, temp, status = -EINVAL; 923 u16 control; 924 925 if (!pci_msi_enable || !dev) 926 return status; 927 928 if (dev->no_msi) 929 return status; 930 931 for (bus = dev->bus; bus; bus = bus->parent) 932 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 933 return -EINVAL; 934 935 temp = dev->irq; 936 937 status = msi_init(); 938 if (status < 0) 939 return status; 940 941 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 942 if (!pos) 943 return -EINVAL; 944 945 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { 946 /* Lookup Sucess */ 947 unsigned long flags; 948 949 pci_read_config_word(dev, msi_control_reg(pos), &control); 950 if (control & PCI_MSI_FLAGS_ENABLE) 951 return 0; /* Already in MSI mode */ 952 spin_lock_irqsave(&msi_lock, flags); 953 if (!vector_irq[dev->irq]) { 954 msi_desc[dev->irq]->msi_attrib.state = 0; 955 vector_irq[dev->irq] = -1; 956 nr_released_vectors--; 957 spin_unlock_irqrestore(&msi_lock, flags); 958 status = msi_register_init(dev, msi_desc[dev->irq]); 959 if (status == 0) 960 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 961 return status; 962 } 963 spin_unlock_irqrestore(&msi_lock, flags); 964 dev->irq = temp; 965 } 966 /* Check whether driver already requested for MSI-X vectors */ 967 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 968 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 969 printk(KERN_INFO "PCI: %s: Can't enable MSI. " 970 "Device already has MSI-X vectors assigned\n", 971 pci_name(dev)); 972 dev->irq = temp; 973 return -EINVAL; 974 } 975 status = msi_capability_init(dev); 976 if (!status) { 977 if (!pos) 978 nr_reserved_vectors--; /* Only MSI capable */ 979 else if (nr_msix_devices > 0) 980 nr_msix_devices--; /* Both MSI and MSI-X capable, 981 but choose enabling MSI */ 982 } 983 984 return status; 985} 986 987void pci_disable_msi(struct pci_dev* dev) 988{ 989 struct msi_desc *entry; 990 int pos, default_vector; 991 u16 control; 992 unsigned long flags; 993 994 if (!pci_msi_enable) 995 return; 996 if (!dev) 997 return; 998 999 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 1000 if (!pos) 1001 return; 1002 1003 pci_read_config_word(dev, msi_control_reg(pos), &control); 1004 if (!(control & PCI_MSI_FLAGS_ENABLE)) 1005 return; 1006 1007 spin_lock_irqsave(&msi_lock, flags); 1008 entry = msi_desc[dev->irq]; 1009 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { 1010 spin_unlock_irqrestore(&msi_lock, flags); 1011 return; 1012 } 1013 if (entry->msi_attrib.state) { 1014 spin_unlock_irqrestore(&msi_lock, flags); 1015 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " 1016 "free_irq() on MSI vector %d\n", 1017 pci_name(dev), dev->irq); 1018 BUG_ON(entry->msi_attrib.state > 0); 1019 } else { 1020 vector_irq[dev->irq] = 0; /* free it */ 1021 nr_released_vectors++; 1022 default_vector = entry->msi_attrib.default_vector; 1023 spin_unlock_irqrestore(&msi_lock, flags); 1024 /* Restore dev->irq to its default pin-assertion vector */ 1025 dev->irq = default_vector; 1026 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), 1027 PCI_CAP_ID_MSI); 1028 } 1029} 1030 1031static int msi_free_vector(struct pci_dev* dev, int vector, int reassign) 1032{ 1033 struct msi_desc *entry; 1034 int head, entry_nr, type; 1035 void __iomem *base; 1036 unsigned long flags; 1037 1038 msi_ops->teardown(vector); 1039 1040 spin_lock_irqsave(&msi_lock, flags); 1041 entry = msi_desc[vector]; 1042 if (!entry || entry->dev != dev) { 1043 spin_unlock_irqrestore(&msi_lock, flags); 1044 return -EINVAL; 1045 } 1046 type = entry->msi_attrib.type; 1047 entry_nr = entry->msi_attrib.entry_nr; 1048 head = entry->link.head; 1049 base = entry->mask_base; 1050 msi_desc[entry->link.head]->link.tail = entry->link.tail; 1051 msi_desc[entry->link.tail]->link.head = entry->link.head; 1052 entry->dev = NULL; 1053 if (!reassign) { 1054 vector_irq[vector] = 0; 1055 nr_released_vectors++; 1056 } 1057 msi_desc[vector] = NULL; 1058 spin_unlock_irqrestore(&msi_lock, flags); 1059 1060 kmem_cache_free(msi_cachep, entry); 1061 1062 if (type == PCI_CAP_ID_MSIX) { 1063 if (!reassign) 1064 writel(1, base + 1065 entry_nr * PCI_MSIX_ENTRY_SIZE + 1066 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 1067 1068 if (head == vector) { 1069 /* 1070 * Detect last MSI-X vector to be released. 1071 * Release the MSI-X memory-mapped table. 1072 */ 1073#if 0 1074 int pos, nr_entries; 1075 unsigned long phys_addr; 1076 u32 table_offset; 1077 u16 control; 1078 u8 bir; 1079 1080 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1081 pci_read_config_word(dev, msi_control_reg(pos), 1082 &control); 1083 nr_entries = multi_msix_capable(control); 1084 pci_read_config_dword(dev, msix_table_offset_reg(pos), 1085 &table_offset); 1086 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 1087 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 1088 phys_addr = pci_resource_start(dev, bir) + table_offset; 1089/* 1090 * FIXME! and what did you want to do with phys_addr? 1091 */ 1092#endif 1093 iounmap(base); 1094 } 1095 } 1096 1097 return 0; 1098} 1099 1100static int reroute_msix_table(int head, struct msix_entry *entries, int *nvec) 1101{ 1102 int vector = head, tail = 0; 1103 int i, j = 0, nr_entries = 0; 1104 void __iomem *base; 1105 unsigned long flags; 1106 1107 spin_lock_irqsave(&msi_lock, flags); 1108 while (head != tail) { 1109 nr_entries++; 1110 tail = msi_desc[vector]->link.tail; 1111 if (entries[0].entry == msi_desc[vector]->msi_attrib.entry_nr) 1112 j = vector; 1113 vector = tail; 1114 } 1115 if (*nvec > nr_entries) { 1116 spin_unlock_irqrestore(&msi_lock, flags); 1117 *nvec = nr_entries; 1118 return -EINVAL; 1119 } 1120 vector = ((j > 0) ? j : head); 1121 for (i = 0; i < *nvec; i++) { 1122 j = msi_desc[vector]->msi_attrib.entry_nr; 1123 msi_desc[vector]->msi_attrib.state = 0; /* Mark it not active */ 1124 vector_irq[vector] = -1; /* Mark it busy */ 1125 nr_released_vectors--; 1126 entries[i].vector = vector; 1127 if (j != (entries + i)->entry) { 1128 base = msi_desc[vector]->mask_base; 1129 msi_desc[vector]->msi_attrib.entry_nr = 1130 (entries + i)->entry; 1131 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE + 1132 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET), base + 1133 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE + 1134 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 1135 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE + 1136 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET), base + 1137 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE + 1138 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 1139 writel( (readl(base + j * PCI_MSIX_ENTRY_SIZE + 1140 PCI_MSIX_ENTRY_DATA_OFFSET) & 0xff00) | vector, 1141 base + (entries+i)->entry*PCI_MSIX_ENTRY_SIZE + 1142 PCI_MSIX_ENTRY_DATA_OFFSET); 1143 } 1144 vector = msi_desc[vector]->link.tail; 1145 } 1146 spin_unlock_irqrestore(&msi_lock, flags); 1147 1148 return 0; 1149} 1150 1151/** 1152 * pci_enable_msix - configure device's MSI-X capability structure 1153 * @dev: pointer to the pci_dev data structure of MSI-X device function 1154 * @entries: pointer to an array of MSI-X entries 1155 * @nvec: number of MSI-X vectors requested for allocation by device driver 1156 * 1157 * Setup the MSI-X capability structure of device function with the number 1158 * of requested vectors upon its software driver call to request for 1159 * MSI-X mode enabled on its hardware device function. A return of zero 1160 * indicates the successful configuration of MSI-X capability structure 1161 * with new allocated MSI-X vectors. A return of < 0 indicates a failure. 1162 * Or a return of > 0 indicates that driver request is exceeding the number 1163 * of vectors available. Driver should use the returned value to re-send 1164 * its request. 1165 **/ 1166int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 1167{ 1168 struct pci_bus *bus; 1169 int status, pos, nr_entries, free_vectors; 1170 int i, j, temp; 1171 u16 control; 1172 unsigned long flags; 1173 1174 if (!pci_msi_enable || !dev || !entries) 1175 return -EINVAL; 1176 1177 if (dev->no_msi) 1178 return -EINVAL; 1179 1180 for (bus = dev->bus; bus; bus = bus->parent) 1181 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 1182 return -EINVAL; 1183 1184 status = msi_init(); 1185 if (status < 0) 1186 return status; 1187 1188 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1189 if (!pos) 1190 return -EINVAL; 1191 1192 pci_read_config_word(dev, msi_control_reg(pos), &control); 1193 if (control & PCI_MSIX_FLAGS_ENABLE) 1194 return -EINVAL; /* Already in MSI-X mode */ 1195 1196 nr_entries = multi_msix_capable(control); 1197 if (nvec > nr_entries) 1198 return -EINVAL; 1199 1200 /* Check for any invalid entries */ 1201 for (i = 0; i < nvec; i++) { 1202 if (entries[i].entry >= nr_entries) 1203 return -EINVAL; /* invalid entry */ 1204 for (j = i + 1; j < nvec; j++) { 1205 if (entries[i].entry == entries[j].entry) 1206 return -EINVAL; /* duplicate entry */ 1207 } 1208 } 1209 temp = dev->irq; 1210 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 1211 /* Lookup Sucess */ 1212 nr_entries = nvec; 1213 /* Reroute MSI-X table */ 1214 if (reroute_msix_table(dev->irq, entries, &nr_entries)) { 1215 /* #requested > #previous-assigned */ 1216 dev->irq = temp; 1217 return nr_entries; 1218 } 1219 dev->irq = temp; 1220 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 1221 return 0; 1222 } 1223 /* Check whether driver already requested for MSI vector */ 1224 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && 1225 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { 1226 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " 1227 "Device already has an MSI vector assigned\n", 1228 pci_name(dev)); 1229 dev->irq = temp; 1230 return -EINVAL; 1231 } 1232 1233 spin_lock_irqsave(&msi_lock, flags); 1234 /* 1235 * msi_lock is provided to ensure that enough vectors resources are 1236 * available before granting. 1237 */ 1238 free_vectors = pci_vector_resources(last_alloc_vector, 1239 nr_released_vectors); 1240 /* Ensure that each MSI/MSI-X device has one vector reserved by 1241 default to avoid any MSI-X driver to take all available 1242 resources */ 1243 free_vectors -= nr_reserved_vectors; 1244 /* Find the average of free vectors among MSI-X devices */ 1245 if (nr_msix_devices > 0) 1246 free_vectors /= nr_msix_devices; 1247 spin_unlock_irqrestore(&msi_lock, flags); 1248 1249 if (nvec > free_vectors) { 1250 if (free_vectors > 0) 1251 return free_vectors; 1252 else 1253 return -EBUSY; 1254 } 1255 1256 status = msix_capability_init(dev, entries, nvec); 1257 if (!status && nr_msix_devices > 0) 1258 nr_msix_devices--; 1259 1260 return status; 1261} 1262 1263void pci_disable_msix(struct pci_dev* dev) 1264{ 1265 int pos, temp; 1266 u16 control; 1267 1268 if (!pci_msi_enable) 1269 return; 1270 if (!dev) 1271 return; 1272 1273 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1274 if (!pos) 1275 return; 1276 1277 pci_read_config_word(dev, msi_control_reg(pos), &control); 1278 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 1279 return; 1280 1281 temp = dev->irq; 1282 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 1283 int state, vector, head, tail = 0, warning = 0; 1284 unsigned long flags; 1285 1286 vector = head = dev->irq; 1287 spin_lock_irqsave(&msi_lock, flags); 1288 while (head != tail) { 1289 state = msi_desc[vector]->msi_attrib.state; 1290 if (state) 1291 warning = 1; 1292 else { 1293 vector_irq[vector] = 0; /* free it */ 1294 nr_released_vectors++; 1295 } 1296 tail = msi_desc[vector]->link.tail; 1297 vector = tail; 1298 } 1299 spin_unlock_irqrestore(&msi_lock, flags); 1300 if (warning) { 1301 dev->irq = temp; 1302 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " 1303 "free_irq() on all MSI-X vectors\n", 1304 pci_name(dev)); 1305 BUG_ON(warning > 0); 1306 } else { 1307 dev->irq = temp; 1308 disable_msi_mode(dev, 1309 pci_find_capability(dev, PCI_CAP_ID_MSIX), 1310 PCI_CAP_ID_MSIX); 1311 1312 } 1313 } 1314} 1315 1316/** 1317 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state 1318 * @dev: pointer to the pci_dev data structure of MSI(X) device function 1319 * 1320 * Being called during hotplug remove, from which the device function 1321 * is hot-removed. All previous assigned MSI/MSI-X vectors, if 1322 * allocated for this device function, are reclaimed to unused state, 1323 * which may be used later on. 1324 **/ 1325void msi_remove_pci_irq_vectors(struct pci_dev* dev) 1326{ 1327 int state, pos, temp; 1328 unsigned long flags; 1329 1330 if (!pci_msi_enable || !dev) 1331 return; 1332 1333 temp = dev->irq; /* Save IOAPIC IRQ */ 1334 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 1335 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { 1336 spin_lock_irqsave(&msi_lock, flags); 1337 state = msi_desc[dev->irq]->msi_attrib.state; 1338 spin_unlock_irqrestore(&msi_lock, flags); 1339 if (state) { 1340 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 1341 "called without free_irq() on MSI vector %d\n", 1342 pci_name(dev), dev->irq); 1343 BUG_ON(state > 0); 1344 } else /* Release MSI vector assigned to this device */ 1345 msi_free_vector(dev, dev->irq, 0); 1346 dev->irq = temp; /* Restore IOAPIC IRQ */ 1347 } 1348 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 1349 if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { 1350 int vector, head, tail = 0, warning = 0; 1351 void __iomem *base = NULL; 1352 1353 vector = head = dev->irq; 1354 while (head != tail) { 1355 spin_lock_irqsave(&msi_lock, flags); 1356 state = msi_desc[vector]->msi_attrib.state; 1357 tail = msi_desc[vector]->link.tail; 1358 base = msi_desc[vector]->mask_base; 1359 spin_unlock_irqrestore(&msi_lock, flags); 1360 if (state) 1361 warning = 1; 1362 else if (vector != head) /* Release MSI-X vector */ 1363 msi_free_vector(dev, vector, 0); 1364 vector = tail; 1365 } 1366 msi_free_vector(dev, vector, 0); 1367 if (warning) { 1368 /* Force to release the MSI-X memory-mapped table */ 1369#if 0 1370 unsigned long phys_addr; 1371 u32 table_offset; 1372 u16 control; 1373 u8 bir; 1374 1375 pci_read_config_word(dev, msi_control_reg(pos), 1376 &control); 1377 pci_read_config_dword(dev, msix_table_offset_reg(pos), 1378 &table_offset); 1379 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 1380 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 1381 phys_addr = pci_resource_start(dev, bir) + table_offset; 1382/* 1383 * FIXME! and what did you want to do with phys_addr? 1384 */ 1385#endif 1386 iounmap(base); 1387 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 1388 "called without free_irq() on all MSI-X vectors\n", 1389 pci_name(dev)); 1390 BUG_ON(warning > 0); 1391 } 1392 dev->irq = temp; /* Restore IOAPIC IRQ */ 1393 } 1394} 1395 1396void pci_no_msi(void) 1397{ 1398 pci_msi_enable = 0; 1399} 1400 1401EXPORT_SYMBOL(pci_enable_msi); 1402EXPORT_SYMBOL(pci_disable_msi); 1403EXPORT_SYMBOL(pci_enable_msix); 1404EXPORT_SYMBOL(pci_disable_msix); 1405