msi.c revision ab7de999a2c771482698efa6fe7c7b7fcb1d482a
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17#include <linux/msi.h> 18#include <linux/smp.h> 19 20#include <asm/errno.h> 21#include <asm/io.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static int pci_msi_enable = 1; 27 28/* Arch hooks */ 29 30#ifndef arch_msi_check_device 31int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) 32{ 33 return 0; 34} 35#endif 36 37#ifndef arch_setup_msi_irqs 38int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 39{ 40 struct msi_desc *entry; 41 int ret; 42 43 /* 44 * If an architecture wants to support multiple MSI, it needs to 45 * override arch_setup_msi_irqs() 46 */ 47 if (type == PCI_CAP_ID_MSI && nvec > 1) 48 return 1; 49 50 list_for_each_entry(entry, &dev->msi_list, list) { 51 ret = arch_setup_msi_irq(dev, entry); 52 if (ret < 0) 53 return ret; 54 if (ret > 0) 55 return -ENOSPC; 56 } 57 58 return 0; 59} 60#endif 61 62#ifndef arch_teardown_msi_irqs 63void arch_teardown_msi_irqs(struct pci_dev *dev) 64{ 65 struct msi_desc *entry; 66 67 list_for_each_entry(entry, &dev->msi_list, list) { 68 int i, nvec; 69 if (entry->irq == 0) 70 continue; 71 nvec = 1 << entry->msi_attrib.multiple; 72 for (i = 0; i < nvec; i++) 73 arch_teardown_msi_irq(entry->irq + i); 74 } 75} 76#endif 77 78static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) 79{ 80 u16 control; 81 82 if (pos) { 83 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 84 control &= ~PCI_MSI_FLAGS_ENABLE; 85 if (enable) 86 control |= PCI_MSI_FLAGS_ENABLE; 87 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 88 } 89} 90 91static void msi_set_enable(struct pci_dev *dev, int enable) 92{ 93 __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); 94} 95 96static void msix_set_enable(struct pci_dev *dev, int enable) 97{ 98 int pos; 99 u16 control; 100 101 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 102 if (pos) { 103 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 104 control &= ~PCI_MSIX_FLAGS_ENABLE; 105 if (enable) 106 control |= PCI_MSIX_FLAGS_ENABLE; 107 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 108 } 109} 110 111static inline __attribute_const__ u32 msi_mask(unsigned x) 112{ 113 /* Don't shift by >= width of type */ 114 if (x >= 5) 115 return 0xffffffff; 116 return (1 << (1 << x)) - 1; 117} 118 119static inline __attribute_const__ u32 msi_capable_mask(u16 control) 120{ 121 return msi_mask((control >> 1) & 7); 122} 123 124static inline __attribute_const__ u32 msi_enabled_mask(u16 control) 125{ 126 return msi_mask((control >> 4) & 7); 127} 128 129/* 130 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to 131 * mask all MSI interrupts by clearing the MSI enable bit does not work 132 * reliably as devices without an INTx disable bit will then generate a 133 * level IRQ which will never be cleared. 134 */ 135static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) 136{ 137 u32 mask_bits = desc->masked; 138 139 if (!desc->msi_attrib.maskbit) 140 return; 141 142 mask_bits &= ~mask; 143 mask_bits |= flag; 144 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); 145 desc->masked = mask_bits; 146} 147 148/* 149 * This internal function does not flush PCI writes to the device. 150 * All users must ensure that they read from the device before either 151 * assuming that the device state is up to date, or returning out of this 152 * file. This saves a few milliseconds when initialising devices with lots 153 * of MSI-X interrupts. 154 */ 155static void msix_mask_irq(struct msi_desc *desc, u32 flag) 156{ 157 u32 mask_bits = desc->masked; 158 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 159 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 160 mask_bits &= ~1; 161 mask_bits |= flag; 162 writel(mask_bits, desc->mask_base + offset); 163 desc->masked = mask_bits; 164} 165 166static void msi_set_mask_bit(unsigned irq, u32 flag) 167{ 168 struct msi_desc *desc = get_irq_msi(irq); 169 170 if (desc->msi_attrib.is_msix) { 171 msix_mask_irq(desc, flag); 172 readl(desc->mask_base); /* Flush write to device */ 173 } else { 174 unsigned offset = irq - desc->dev->irq; 175 msi_mask_irq(desc, 1 << offset, flag << offset); 176 } 177} 178 179void mask_msi_irq(unsigned int irq) 180{ 181 msi_set_mask_bit(irq, 1); 182} 183 184void unmask_msi_irq(unsigned int irq) 185{ 186 msi_set_mask_bit(irq, 0); 187} 188 189void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 190{ 191 struct msi_desc *entry = get_irq_desc_msi(desc); 192 if (entry->msi_attrib.is_msix) { 193 void __iomem *base = entry->mask_base + 194 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 195 196 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 197 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 198 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 199 } else { 200 struct pci_dev *dev = entry->dev; 201 int pos = entry->msi_attrib.pos; 202 u16 data; 203 204 pci_read_config_dword(dev, msi_lower_address_reg(pos), 205 &msg->address_lo); 206 if (entry->msi_attrib.is_64) { 207 pci_read_config_dword(dev, msi_upper_address_reg(pos), 208 &msg->address_hi); 209 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 210 } else { 211 msg->address_hi = 0; 212 pci_read_config_word(dev, msi_data_reg(pos, 0), &data); 213 } 214 msg->data = data; 215 } 216} 217 218void read_msi_msg(unsigned int irq, struct msi_msg *msg) 219{ 220 struct irq_desc *desc = irq_to_desc(irq); 221 222 read_msi_msg_desc(desc, msg); 223} 224 225void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 226{ 227 struct msi_desc *entry = get_irq_desc_msi(desc); 228 if (entry->msi_attrib.is_msix) { 229 void __iomem *base; 230 base = entry->mask_base + 231 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 232 233 writel(msg->address_lo, 234 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 235 writel(msg->address_hi, 236 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 237 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 238 } else { 239 struct pci_dev *dev = entry->dev; 240 int pos = entry->msi_attrib.pos; 241 u16 msgctl; 242 243 pci_read_config_word(dev, msi_control_reg(pos), &msgctl); 244 msgctl &= ~PCI_MSI_FLAGS_QSIZE; 245 msgctl |= entry->msi_attrib.multiple << 4; 246 pci_write_config_word(dev, msi_control_reg(pos), msgctl); 247 248 pci_write_config_dword(dev, msi_lower_address_reg(pos), 249 msg->address_lo); 250 if (entry->msi_attrib.is_64) { 251 pci_write_config_dword(dev, msi_upper_address_reg(pos), 252 msg->address_hi); 253 pci_write_config_word(dev, msi_data_reg(pos, 1), 254 msg->data); 255 } else { 256 pci_write_config_word(dev, msi_data_reg(pos, 0), 257 msg->data); 258 } 259 } 260 entry->msg = *msg; 261} 262 263void write_msi_msg(unsigned int irq, struct msi_msg *msg) 264{ 265 struct irq_desc *desc = irq_to_desc(irq); 266 267 write_msi_msg_desc(desc, msg); 268} 269 270static int msi_free_irqs(struct pci_dev* dev); 271 272static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) 273{ 274 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); 275 if (!desc) 276 return NULL; 277 278 INIT_LIST_HEAD(&desc->list); 279 desc->dev = dev; 280 281 return desc; 282} 283 284static void pci_intx_for_msi(struct pci_dev *dev, int enable) 285{ 286 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) 287 pci_intx(dev, enable); 288} 289 290static void __pci_restore_msi_state(struct pci_dev *dev) 291{ 292 int pos; 293 u16 control; 294 struct msi_desc *entry; 295 296 if (!dev->msi_enabled) 297 return; 298 299 entry = get_irq_msi(dev->irq); 300 pos = entry->msi_attrib.pos; 301 302 pci_intx_for_msi(dev, 0); 303 msi_set_enable(dev, 0); 304 write_msi_msg(dev->irq, &entry->msg); 305 306 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 307 msi_mask_irq(entry, msi_capable_mask(control), entry->masked); 308 control &= ~PCI_MSI_FLAGS_QSIZE; 309 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; 310 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 311} 312 313static void __pci_restore_msix_state(struct pci_dev *dev) 314{ 315 int pos; 316 struct msi_desc *entry; 317 u16 control; 318 319 if (!dev->msix_enabled) 320 return; 321 322 /* route the table */ 323 pci_intx_for_msi(dev, 0); 324 msix_set_enable(dev, 0); 325 326 list_for_each_entry(entry, &dev->msi_list, list) { 327 write_msi_msg(entry->irq, &entry->msg); 328 msix_mask_irq(entry, entry->masked); 329 } 330 331 BUG_ON(list_empty(&dev->msi_list)); 332 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 333 pos = entry->msi_attrib.pos; 334 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 335 control &= ~PCI_MSIX_FLAGS_MASKALL; 336 control |= PCI_MSIX_FLAGS_ENABLE; 337 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 338} 339 340void pci_restore_msi_state(struct pci_dev *dev) 341{ 342 __pci_restore_msi_state(dev); 343 __pci_restore_msix_state(dev); 344} 345EXPORT_SYMBOL_GPL(pci_restore_msi_state); 346 347/** 348 * msi_capability_init - configure device's MSI capability structure 349 * @dev: pointer to the pci_dev data structure of MSI device function 350 * @nvec: number of interrupts to allocate 351 * 352 * Setup the MSI capability structure of the device with the requested 353 * number of interrupts. A return value of zero indicates the successful 354 * setup of an entry with the new MSI irq. A negative return value indicates 355 * an error, and a positive return value indicates the number of interrupts 356 * which could have been allocated. 357 */ 358static int msi_capability_init(struct pci_dev *dev, int nvec) 359{ 360 struct msi_desc *entry; 361 int pos, ret; 362 u16 control; 363 unsigned mask; 364 365 msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ 366 367 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 368 pci_read_config_word(dev, msi_control_reg(pos), &control); 369 /* MSI Entry Initialization */ 370 entry = alloc_msi_entry(dev); 371 if (!entry) 372 return -ENOMEM; 373 374 entry->msi_attrib.is_msix = 0; 375 entry->msi_attrib.is_64 = is_64bit_address(control); 376 entry->msi_attrib.entry_nr = 0; 377 entry->msi_attrib.maskbit = is_mask_bit_support(control); 378 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 379 entry->msi_attrib.pos = pos; 380 381 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); 382 /* All MSIs are unmasked by default, Mask them all */ 383 if (entry->msi_attrib.maskbit) 384 pci_read_config_dword(dev, entry->mask_pos, &entry->masked); 385 mask = msi_capable_mask(control); 386 msi_mask_irq(entry, mask, mask); 387 388 list_add_tail(&entry->list, &dev->msi_list); 389 390 /* Configure MSI capability structure */ 391 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); 392 if (ret) { 393 msi_free_irqs(dev); 394 return ret; 395 } 396 397 /* Set MSI enabled bits */ 398 pci_intx_for_msi(dev, 0); 399 msi_set_enable(dev, 1); 400 dev->msi_enabled = 1; 401 402 dev->irq = entry->irq; 403 return 0; 404} 405 406/** 407 * msix_capability_init - configure device's MSI-X capability 408 * @dev: pointer to the pci_dev data structure of MSI-X device function 409 * @entries: pointer to an array of struct msix_entry entries 410 * @nvec: number of @entries 411 * 412 * Setup the MSI-X capability structure of device function with a 413 * single MSI-X irq. A return of zero indicates the successful setup of 414 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 415 **/ 416static int msix_capability_init(struct pci_dev *dev, 417 struct msix_entry *entries, int nvec) 418{ 419 struct msi_desc *entry; 420 int pos, i, j, nr_entries, ret; 421 unsigned long phys_addr; 422 u32 table_offset; 423 u16 control; 424 u8 bir; 425 void __iomem *base; 426 427 msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ 428 429 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 430 /* Request & Map MSI-X table region */ 431 pci_read_config_word(dev, msi_control_reg(pos), &control); 432 nr_entries = multi_msix_capable(control); 433 434 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 435 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 436 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 437 phys_addr = pci_resource_start (dev, bir) + table_offset; 438 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 439 if (base == NULL) 440 return -ENOMEM; 441 442 /* MSI-X Table Initialization */ 443 for (i = 0; i < nvec; i++) { 444 entry = alloc_msi_entry(dev); 445 if (!entry) 446 break; 447 448 j = entries[i].entry; 449 entry->msi_attrib.is_msix = 1; 450 entry->msi_attrib.is_64 = 1; 451 entry->msi_attrib.entry_nr = j; 452 entry->msi_attrib.default_irq = dev->irq; 453 entry->msi_attrib.pos = pos; 454 entry->mask_base = base; 455 msix_mask_irq(entry, 1); 456 457 list_add_tail(&entry->list, &dev->msi_list); 458 } 459 460 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); 461 if (ret < 0) { 462 /* If we had some success report the number of irqs 463 * we succeeded in setting up. */ 464 int avail = 0; 465 list_for_each_entry(entry, &dev->msi_list, list) { 466 if (entry->irq != 0) { 467 avail++; 468 } 469 } 470 471 if (avail != 0) 472 ret = avail; 473 } 474 475 if (ret) { 476 msi_free_irqs(dev); 477 return ret; 478 } 479 480 i = 0; 481 list_for_each_entry(entry, &dev->msi_list, list) { 482 entries[i].vector = entry->irq; 483 set_irq_msi(entry->irq, entry); 484 i++; 485 } 486 /* Set MSI-X enabled bits */ 487 pci_intx_for_msi(dev, 0); 488 msix_set_enable(dev, 1); 489 dev->msix_enabled = 1; 490 491 list_for_each_entry(entry, &dev->msi_list, list) { 492 int vector = entry->msi_attrib.entry_nr; 493 entry->masked = readl(base + vector * PCI_MSIX_ENTRY_SIZE + 494 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 495 } 496 497 return 0; 498} 499 500/** 501 * pci_msi_check_device - check whether MSI may be enabled on a device 502 * @dev: pointer to the pci_dev data structure of MSI device function 503 * @nvec: how many MSIs have been requested ? 504 * @type: are we checking for MSI or MSI-X ? 505 * 506 * Look at global flags, the device itself, and its parent busses 507 * to determine if MSI/-X are supported for the device. If MSI/-X is 508 * supported return 0, else return an error code. 509 **/ 510static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) 511{ 512 struct pci_bus *bus; 513 int ret; 514 515 /* MSI must be globally enabled and supported by the device */ 516 if (!pci_msi_enable || !dev || dev->no_msi) 517 return -EINVAL; 518 519 /* 520 * You can't ask to have 0 or less MSIs configured. 521 * a) it's stupid .. 522 * b) the list manipulation code assumes nvec >= 1. 523 */ 524 if (nvec < 1) 525 return -ERANGE; 526 527 /* Any bridge which does NOT route MSI transactions from it's 528 * secondary bus to it's primary bus must set NO_MSI flag on 529 * the secondary pci_bus. 530 * We expect only arch-specific PCI host bus controller driver 531 * or quirks for specific PCI bridges to be setting NO_MSI. 532 */ 533 for (bus = dev->bus; bus; bus = bus->parent) 534 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 535 return -EINVAL; 536 537 ret = arch_msi_check_device(dev, nvec, type); 538 if (ret) 539 return ret; 540 541 if (!pci_find_capability(dev, type)) 542 return -EINVAL; 543 544 return 0; 545} 546 547/** 548 * pci_enable_msi_block - configure device's MSI capability structure 549 * @dev: device to configure 550 * @nvec: number of interrupts to configure 551 * 552 * Allocate IRQs for a device with the MSI capability. 553 * This function returns a negative errno if an error occurs. If it 554 * is unable to allocate the number of interrupts requested, it returns 555 * the number of interrupts it might be able to allocate. If it successfully 556 * allocates at least the number of interrupts requested, it returns 0 and 557 * updates the @dev's irq member to the lowest new interrupt number; the 558 * other interrupt numbers allocated to this device are consecutive. 559 */ 560int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 561{ 562 int status, pos, maxvec; 563 u16 msgctl; 564 565 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 566 if (!pos) 567 return -EINVAL; 568 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); 569 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); 570 if (nvec > maxvec) 571 return maxvec; 572 573 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); 574 if (status) 575 return status; 576 577 WARN_ON(!!dev->msi_enabled); 578 579 /* Check whether driver already requested MSI-X irqs */ 580 if (dev->msix_enabled) { 581 dev_info(&dev->dev, "can't enable MSI " 582 "(MSI-X already enabled)\n"); 583 return -EINVAL; 584 } 585 586 status = msi_capability_init(dev, nvec); 587 return status; 588} 589EXPORT_SYMBOL(pci_enable_msi_block); 590 591void pci_msi_shutdown(struct pci_dev *dev) 592{ 593 struct msi_desc *desc; 594 u32 mask; 595 u16 ctrl; 596 597 if (!pci_msi_enable || !dev || !dev->msi_enabled) 598 return; 599 600 msi_set_enable(dev, 0); 601 pci_intx_for_msi(dev, 1); 602 dev->msi_enabled = 0; 603 604 BUG_ON(list_empty(&dev->msi_list)); 605 desc = list_first_entry(&dev->msi_list, struct msi_desc, list); 606 pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &ctrl); 607 mask = msi_capable_mask(ctrl); 608 msi_mask_irq(desc, mask, ~mask); 609 610 /* Restore dev->irq to its default pin-assertion irq */ 611 dev->irq = desc->msi_attrib.default_irq; 612} 613 614void pci_disable_msi(struct pci_dev* dev) 615{ 616 struct msi_desc *entry; 617 618 if (!pci_msi_enable || !dev || !dev->msi_enabled) 619 return; 620 621 pci_msi_shutdown(dev); 622 623 entry = list_entry(dev->msi_list.next, struct msi_desc, list); 624 if (entry->msi_attrib.is_msix) 625 return; 626 627 msi_free_irqs(dev); 628} 629EXPORT_SYMBOL(pci_disable_msi); 630 631static int msi_free_irqs(struct pci_dev* dev) 632{ 633 struct msi_desc *entry, *tmp; 634 635 list_for_each_entry(entry, &dev->msi_list, list) { 636 int i, nvec; 637 if (!entry->irq) 638 continue; 639 nvec = 1 << entry->msi_attrib.multiple; 640 for (i = 0; i < nvec; i++) 641 BUG_ON(irq_has_action(entry->irq + i)); 642 } 643 644 arch_teardown_msi_irqs(dev); 645 646 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { 647 if (entry->msi_attrib.is_msix) { 648 writel(1, entry->mask_base + entry->msi_attrib.entry_nr 649 * PCI_MSIX_ENTRY_SIZE 650 + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 651 652 if (list_is_last(&entry->list, &dev->msi_list)) 653 iounmap(entry->mask_base); 654 } 655 list_del(&entry->list); 656 kfree(entry); 657 } 658 659 return 0; 660} 661 662/** 663 * pci_msix_table_size - return the number of device's MSI-X table entries 664 * @dev: pointer to the pci_dev data structure of MSI-X device function 665 */ 666int pci_msix_table_size(struct pci_dev *dev) 667{ 668 int pos; 669 u16 control; 670 671 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 672 if (!pos) 673 return 0; 674 675 pci_read_config_word(dev, msi_control_reg(pos), &control); 676 return multi_msix_capable(control); 677} 678 679/** 680 * pci_enable_msix - configure device's MSI-X capability structure 681 * @dev: pointer to the pci_dev data structure of MSI-X device function 682 * @entries: pointer to an array of MSI-X entries 683 * @nvec: number of MSI-X irqs requested for allocation by device driver 684 * 685 * Setup the MSI-X capability structure of device function with the number 686 * of requested irqs upon its software driver call to request for 687 * MSI-X mode enabled on its hardware device function. A return of zero 688 * indicates the successful configuration of MSI-X capability structure 689 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 690 * Or a return of > 0 indicates that driver request is exceeding the number 691 * of irqs or MSI-X vectors available. Driver should use the returned value to 692 * re-send its request. 693 **/ 694int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 695{ 696 int status, nr_entries; 697 int i, j; 698 699 if (!entries) 700 return -EINVAL; 701 702 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); 703 if (status) 704 return status; 705 706 nr_entries = pci_msix_table_size(dev); 707 if (nvec > nr_entries) 708 return nr_entries; 709 710 /* Check for any invalid entries */ 711 for (i = 0; i < nvec; i++) { 712 if (entries[i].entry >= nr_entries) 713 return -EINVAL; /* invalid entry */ 714 for (j = i + 1; j < nvec; j++) { 715 if (entries[i].entry == entries[j].entry) 716 return -EINVAL; /* duplicate entry */ 717 } 718 } 719 WARN_ON(!!dev->msix_enabled); 720 721 /* Check whether driver already requested for MSI irq */ 722 if (dev->msi_enabled) { 723 dev_info(&dev->dev, "can't enable MSI-X " 724 "(MSI IRQ already assigned)\n"); 725 return -EINVAL; 726 } 727 status = msix_capability_init(dev, entries, nvec); 728 return status; 729} 730EXPORT_SYMBOL(pci_enable_msix); 731 732static void msix_free_all_irqs(struct pci_dev *dev) 733{ 734 msi_free_irqs(dev); 735} 736 737void pci_msix_shutdown(struct pci_dev* dev) 738{ 739 if (!pci_msi_enable || !dev || !dev->msix_enabled) 740 return; 741 742 msix_set_enable(dev, 0); 743 pci_intx_for_msi(dev, 1); 744 dev->msix_enabled = 0; 745} 746void pci_disable_msix(struct pci_dev* dev) 747{ 748 if (!pci_msi_enable || !dev || !dev->msix_enabled) 749 return; 750 751 pci_msix_shutdown(dev); 752 753 msix_free_all_irqs(dev); 754} 755EXPORT_SYMBOL(pci_disable_msix); 756 757/** 758 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 759 * @dev: pointer to the pci_dev data structure of MSI(X) device function 760 * 761 * Being called during hotplug remove, from which the device function 762 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 763 * allocated for this device function, are reclaimed to unused state, 764 * which may be used later on. 765 **/ 766void msi_remove_pci_irq_vectors(struct pci_dev* dev) 767{ 768 if (!pci_msi_enable || !dev) 769 return; 770 771 if (dev->msi_enabled) 772 msi_free_irqs(dev); 773 774 if (dev->msix_enabled) 775 msix_free_all_irqs(dev); 776} 777 778void pci_no_msi(void) 779{ 780 pci_msi_enable = 0; 781} 782 783/** 784 * pci_msi_enabled - is MSI enabled? 785 * 786 * Returns true if MSI has not been disabled by the command-line option 787 * pci=nomsi. 788 **/ 789int pci_msi_enabled(void) 790{ 791 return pci_msi_enable; 792} 793EXPORT_SYMBOL(pci_msi_enabled); 794 795void pci_msi_init_pci_dev(struct pci_dev *dev) 796{ 797 INIT_LIST_HEAD(&dev->msi_list); 798} 799