msi.c revision d40f540ce6d992d4123827dbd62f68c4a39c53d0
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/smp_lock.h> 16#include <linux/pci.h> 17#include <linux/proc_fs.h> 18#include <linux/msi.h> 19 20#include <asm/errno.h> 21#include <asm/io.h> 22#include <asm/smp.h> 23 24#include "pci.h" 25#include "msi.h" 26 27static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; 28static struct kmem_cache* msi_cachep; 29 30static int pci_msi_enable = 1; 31 32static int msi_cache_init(void) 33{ 34 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), 35 0, SLAB_HWCACHE_ALIGN, NULL, NULL); 36 if (!msi_cachep) 37 return -ENOMEM; 38 39 return 0; 40} 41 42static void msi_set_mask_bit(unsigned int irq, int flag) 43{ 44 struct msi_desc *entry; 45 46 entry = msi_desc[irq]; 47 BUG_ON(!entry || !entry->dev); 48 switch (entry->msi_attrib.type) { 49 case PCI_CAP_ID_MSI: 50 if (entry->msi_attrib.maskbit) { 51 int pos; 52 u32 mask_bits; 53 54 pos = (long)entry->mask_base; 55 pci_read_config_dword(entry->dev, pos, &mask_bits); 56 mask_bits &= ~(1); 57 mask_bits |= flag; 58 pci_write_config_dword(entry->dev, pos, mask_bits); 59 } 60 break; 61 case PCI_CAP_ID_MSIX: 62 { 63 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 64 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; 65 writel(flag, entry->mask_base + offset); 66 break; 67 } 68 default: 69 BUG(); 70 break; 71 } 72} 73 74void read_msi_msg(unsigned int irq, struct msi_msg *msg) 75{ 76 struct msi_desc *entry = get_irq_data(irq); 77 switch(entry->msi_attrib.type) { 78 case PCI_CAP_ID_MSI: 79 { 80 struct pci_dev *dev = entry->dev; 81 int pos = entry->msi_attrib.pos; 82 u16 data; 83 84 pci_read_config_dword(dev, msi_lower_address_reg(pos), 85 &msg->address_lo); 86 if (entry->msi_attrib.is_64) { 87 pci_read_config_dword(dev, msi_upper_address_reg(pos), 88 &msg->address_hi); 89 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 90 } else { 91 msg->address_hi = 0; 92 pci_read_config_word(dev, msi_data_reg(pos, 1), &data); 93 } 94 msg->data = data; 95 break; 96 } 97 case PCI_CAP_ID_MSIX: 98 { 99 void __iomem *base; 100 base = entry->mask_base + 101 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 102 103 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 104 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 105 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); 106 break; 107 } 108 default: 109 BUG(); 110 } 111} 112 113void write_msi_msg(unsigned int irq, struct msi_msg *msg) 114{ 115 struct msi_desc *entry = get_irq_data(irq); 116 switch (entry->msi_attrib.type) { 117 case PCI_CAP_ID_MSI: 118 { 119 struct pci_dev *dev = entry->dev; 120 int pos = entry->msi_attrib.pos; 121 122 pci_write_config_dword(dev, msi_lower_address_reg(pos), 123 msg->address_lo); 124 if (entry->msi_attrib.is_64) { 125 pci_write_config_dword(dev, msi_upper_address_reg(pos), 126 msg->address_hi); 127 pci_write_config_word(dev, msi_data_reg(pos, 1), 128 msg->data); 129 } else { 130 pci_write_config_word(dev, msi_data_reg(pos, 0), 131 msg->data); 132 } 133 break; 134 } 135 case PCI_CAP_ID_MSIX: 136 { 137 void __iomem *base; 138 base = entry->mask_base + 139 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 140 141 writel(msg->address_lo, 142 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); 143 writel(msg->address_hi, 144 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); 145 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); 146 break; 147 } 148 default: 149 BUG(); 150 } 151} 152 153void mask_msi_irq(unsigned int irq) 154{ 155 msi_set_mask_bit(irq, 1); 156} 157 158void unmask_msi_irq(unsigned int irq) 159{ 160 msi_set_mask_bit(irq, 0); 161} 162 163static int msi_free_irq(struct pci_dev* dev, int irq); 164 165static int msi_init(void) 166{ 167 static int status = -ENOMEM; 168 169 if (!status) 170 return status; 171 172 status = msi_cache_init(); 173 if (status < 0) { 174 pci_msi_enable = 0; 175 printk(KERN_WARNING "PCI: MSI cache init failed\n"); 176 return status; 177 } 178 179 return status; 180} 181 182static struct msi_desc* alloc_msi_entry(void) 183{ 184 struct msi_desc *entry; 185 186 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); 187 if (!entry) 188 return NULL; 189 190 entry->link.tail = entry->link.head = 0; /* single message */ 191 entry->dev = NULL; 192 193 return entry; 194} 195 196static void attach_msi_entry(struct msi_desc *entry, int irq) 197{ 198 msi_desc[irq] = entry; 199} 200 201static int create_msi_irq(void) 202{ 203 struct msi_desc *entry; 204 int irq; 205 206 entry = alloc_msi_entry(); 207 if (!entry) 208 return -ENOMEM; 209 210 irq = create_irq(); 211 if (irq < 0) { 212 kmem_cache_free(msi_cachep, entry); 213 return -EBUSY; 214 } 215 216 set_irq_data(irq, entry); 217 218 return irq; 219} 220 221static void destroy_msi_irq(unsigned int irq) 222{ 223 struct msi_desc *entry; 224 225 entry = get_irq_data(irq); 226 set_irq_chip(irq, NULL); 227 set_irq_data(irq, NULL); 228 destroy_irq(irq); 229 kmem_cache_free(msi_cachep, entry); 230} 231 232static void enable_msi_mode(struct pci_dev *dev, int pos, int type) 233{ 234 u16 control; 235 236 pci_read_config_word(dev, msi_control_reg(pos), &control); 237 if (type == PCI_CAP_ID_MSI) { 238 /* Set enabled bits to single MSI & enable MSI_enable bit */ 239 msi_enable(control, 1); 240 pci_write_config_word(dev, msi_control_reg(pos), control); 241 dev->msi_enabled = 1; 242 } else { 243 msix_enable(control); 244 pci_write_config_word(dev, msi_control_reg(pos), control); 245 dev->msix_enabled = 1; 246 } 247 248 pci_intx(dev, 0); /* disable intx */ 249} 250 251void disable_msi_mode(struct pci_dev *dev, int pos, int type) 252{ 253 u16 control; 254 255 pci_read_config_word(dev, msi_control_reg(pos), &control); 256 if (type == PCI_CAP_ID_MSI) { 257 /* Set enabled bits to single MSI & enable MSI_enable bit */ 258 msi_disable(control); 259 pci_write_config_word(dev, msi_control_reg(pos), control); 260 dev->msi_enabled = 0; 261 } else { 262 msix_disable(control); 263 pci_write_config_word(dev, msi_control_reg(pos), control); 264 dev->msix_enabled = 0; 265 } 266 267 pci_intx(dev, 1); /* enable intx */ 268} 269 270#ifdef CONFIG_PM 271static int __pci_save_msi_state(struct pci_dev *dev) 272{ 273 int pos, i = 0; 274 u16 control; 275 struct pci_cap_saved_state *save_state; 276 u32 *cap; 277 278 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 279 if (pos <= 0 || dev->no_msi) 280 return 0; 281 282 pci_read_config_word(dev, msi_control_reg(pos), &control); 283 if (!(control & PCI_MSI_FLAGS_ENABLE)) 284 return 0; 285 286 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, 287 GFP_KERNEL); 288 if (!save_state) { 289 printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); 290 return -ENOMEM; 291 } 292 cap = &save_state->data[0]; 293 294 pci_read_config_dword(dev, pos, &cap[i++]); 295 control = cap[0] >> 16; 296 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); 297 if (control & PCI_MSI_FLAGS_64BIT) { 298 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); 299 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); 300 } else 301 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); 302 if (control & PCI_MSI_FLAGS_MASKBIT) 303 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); 304 save_state->cap_nr = PCI_CAP_ID_MSI; 305 pci_add_saved_cap(dev, save_state); 306 return 0; 307} 308 309static void __pci_restore_msi_state(struct pci_dev *dev) 310{ 311 int i = 0, pos; 312 u16 control; 313 struct pci_cap_saved_state *save_state; 314 u32 *cap; 315 316 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); 317 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 318 if (!save_state || pos <= 0) 319 return; 320 cap = &save_state->data[0]; 321 322 control = cap[i++] >> 16; 323 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); 324 if (control & PCI_MSI_FLAGS_64BIT) { 325 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); 326 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); 327 } else 328 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); 329 if (control & PCI_MSI_FLAGS_MASKBIT) 330 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); 331 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 332 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 333 pci_remove_saved_cap(save_state); 334 kfree(save_state); 335} 336 337static int __pci_save_msix_state(struct pci_dev *dev) 338{ 339 int pos; 340 int irq, head, tail = 0; 341 u16 control; 342 struct pci_cap_saved_state *save_state; 343 344 if (!dev->msix_enabled) 345 return 0; 346 347 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 348 if (pos <= 0 || dev->no_msi) 349 return 0; 350 351 /* save the capability */ 352 pci_read_config_word(dev, msi_control_reg(pos), &control); 353 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 354 return 0; 355 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), 356 GFP_KERNEL); 357 if (!save_state) { 358 printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); 359 return -ENOMEM; 360 } 361 *((u16 *)&save_state->data[0]) = control; 362 363 /* save the table */ 364 irq = head = dev->first_msi_irq; 365 while (head != tail) { 366 struct msi_desc *entry; 367 368 entry = msi_desc[irq]; 369 read_msi_msg(irq, &entry->msg_save); 370 371 tail = msi_desc[irq]->link.tail; 372 irq = tail; 373 } 374 375 save_state->cap_nr = PCI_CAP_ID_MSIX; 376 pci_add_saved_cap(dev, save_state); 377 return 0; 378} 379 380int pci_save_msi_state(struct pci_dev *dev) 381{ 382 int rc; 383 384 rc = __pci_save_msi_state(dev); 385 if (rc) 386 return rc; 387 388 rc = __pci_save_msix_state(dev); 389 390 return rc; 391} 392 393static void __pci_restore_msix_state(struct pci_dev *dev) 394{ 395 u16 save; 396 int pos; 397 int irq, head, tail = 0; 398 struct msi_desc *entry; 399 struct pci_cap_saved_state *save_state; 400 401 if (!dev->msix_enabled) 402 return; 403 404 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); 405 if (!save_state) 406 return; 407 save = *((u16 *)&save_state->data[0]); 408 pci_remove_saved_cap(save_state); 409 kfree(save_state); 410 411 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 412 if (pos <= 0) 413 return; 414 415 /* route the table */ 416 irq = head = dev->first_msi_irq; 417 while (head != tail) { 418 entry = msi_desc[irq]; 419 write_msi_msg(irq, &entry->msg_save); 420 421 tail = msi_desc[irq]->link.tail; 422 irq = tail; 423 } 424 425 pci_write_config_word(dev, msi_control_reg(pos), save); 426 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 427} 428 429void pci_restore_msi_state(struct pci_dev *dev) 430{ 431 __pci_restore_msi_state(dev); 432 __pci_restore_msix_state(dev); 433} 434#endif /* CONFIG_PM */ 435 436/** 437 * msi_capability_init - configure device's MSI capability structure 438 * @dev: pointer to the pci_dev data structure of MSI device function 439 * 440 * Setup the MSI capability structure of device function with a single 441 * MSI irq, regardless of device function is capable of handling 442 * multiple messages. A return of zero indicates the successful setup 443 * of an entry zero with the new MSI irq or non-zero for otherwise. 444 **/ 445static int msi_capability_init(struct pci_dev *dev) 446{ 447 int status; 448 struct msi_desc *entry; 449 int pos, irq; 450 u16 control; 451 452 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 453 pci_read_config_word(dev, msi_control_reg(pos), &control); 454 /* MSI Entry Initialization */ 455 irq = create_msi_irq(); 456 if (irq < 0) 457 return irq; 458 459 entry = get_irq_data(irq); 460 entry->link.head = irq; 461 entry->link.tail = irq; 462 entry->msi_attrib.type = PCI_CAP_ID_MSI; 463 entry->msi_attrib.is_64 = is_64bit_address(control); 464 entry->msi_attrib.entry_nr = 0; 465 entry->msi_attrib.maskbit = is_mask_bit_support(control); 466 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 467 entry->msi_attrib.pos = pos; 468 if (is_mask_bit_support(control)) { 469 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, 470 is_64bit_address(control)); 471 } 472 entry->dev = dev; 473 if (entry->msi_attrib.maskbit) { 474 unsigned int maskbits, temp; 475 /* All MSIs are unmasked by default, Mask them all */ 476 pci_read_config_dword(dev, 477 msi_mask_bits_reg(pos, is_64bit_address(control)), 478 &maskbits); 479 temp = (1 << multi_msi_capable(control)); 480 temp = ((temp - 1) & ~temp); 481 maskbits |= temp; 482 pci_write_config_dword(dev, 483 msi_mask_bits_reg(pos, is_64bit_address(control)), 484 maskbits); 485 } 486 /* Configure MSI capability structure */ 487 status = arch_setup_msi_irq(irq, dev); 488 if (status < 0) { 489 destroy_msi_irq(irq); 490 return status; 491 } 492 493 dev->first_msi_irq = irq; 494 attach_msi_entry(entry, irq); 495 /* Set MSI enabled bits */ 496 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 497 498 dev->irq = irq; 499 return 0; 500} 501 502/** 503 * msix_capability_init - configure device's MSI-X capability 504 * @dev: pointer to the pci_dev data structure of MSI-X device function 505 * @entries: pointer to an array of struct msix_entry entries 506 * @nvec: number of @entries 507 * 508 * Setup the MSI-X capability structure of device function with a 509 * single MSI-X irq. A return of zero indicates the successful setup of 510 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 511 **/ 512static int msix_capability_init(struct pci_dev *dev, 513 struct msix_entry *entries, int nvec) 514{ 515 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; 516 int status; 517 int irq, pos, i, j, nr_entries, temp = 0; 518 unsigned long phys_addr; 519 u32 table_offset; 520 u16 control; 521 u8 bir; 522 void __iomem *base; 523 524 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 525 /* Request & Map MSI-X table region */ 526 pci_read_config_word(dev, msi_control_reg(pos), &control); 527 nr_entries = multi_msix_capable(control); 528 529 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 530 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 531 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 532 phys_addr = pci_resource_start (dev, bir) + table_offset; 533 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 534 if (base == NULL) 535 return -ENOMEM; 536 537 /* MSI-X Table Initialization */ 538 for (i = 0; i < nvec; i++) { 539 irq = create_msi_irq(); 540 if (irq < 0) 541 break; 542 543 entry = get_irq_data(irq); 544 j = entries[i].entry; 545 entries[i].vector = irq; 546 entry->msi_attrib.type = PCI_CAP_ID_MSIX; 547 entry->msi_attrib.is_64 = 1; 548 entry->msi_attrib.entry_nr = j; 549 entry->msi_attrib.maskbit = 1; 550 entry->msi_attrib.default_irq = dev->irq; 551 entry->msi_attrib.pos = pos; 552 entry->dev = dev; 553 entry->mask_base = base; 554 if (!head) { 555 entry->link.head = irq; 556 entry->link.tail = irq; 557 head = entry; 558 } else { 559 entry->link.head = temp; 560 entry->link.tail = tail->link.tail; 561 tail->link.tail = irq; 562 head->link.head = irq; 563 } 564 temp = irq; 565 tail = entry; 566 /* Configure MSI-X capability structure */ 567 status = arch_setup_msi_irq(irq, dev); 568 if (status < 0) { 569 destroy_msi_irq(irq); 570 break; 571 } 572 573 attach_msi_entry(entry, irq); 574 } 575 if (i != nvec) { 576 int avail = i - 1; 577 i--; 578 for (; i >= 0; i--) { 579 irq = (entries + i)->vector; 580 msi_free_irq(dev, irq); 581 (entries + i)->vector = 0; 582 } 583 /* If we had some success report the number of irqs 584 * we succeeded in setting up. 585 */ 586 if (avail <= 0) 587 avail = -EBUSY; 588 return avail; 589 } 590 dev->first_msi_irq = entries[0].vector; 591 /* Set MSI-X enabled bits */ 592 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 593 594 return 0; 595} 596 597/** 598 * pci_msi_supported - check whether MSI may be enabled on device 599 * @dev: pointer to the pci_dev data structure of MSI device function 600 * 601 * Look at global flags, the device itself, and its parent busses 602 * to return 0 if MSI are supported for the device. 603 **/ 604static 605int pci_msi_supported(struct pci_dev * dev) 606{ 607 struct pci_bus *bus; 608 609 /* MSI must be globally enabled and supported by the device */ 610 if (!pci_msi_enable || !dev || dev->no_msi) 611 return -EINVAL; 612 613 /* Any bridge which does NOT route MSI transactions from it's 614 * secondary bus to it's primary bus must set NO_MSI flag on 615 * the secondary pci_bus. 616 * We expect only arch-specific PCI host bus controller driver 617 * or quirks for specific PCI bridges to be setting NO_MSI. 618 */ 619 for (bus = dev->bus; bus; bus = bus->parent) 620 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 621 return -EINVAL; 622 623 return 0; 624} 625 626/** 627 * pci_enable_msi - configure device's MSI capability structure 628 * @dev: pointer to the pci_dev data structure of MSI device function 629 * 630 * Setup the MSI capability structure of device function with 631 * a single MSI irq upon its software driver call to request for 632 * MSI mode enabled on its hardware device function. A return of zero 633 * indicates the successful setup of an entry zero with the new MSI 634 * irq or non-zero for otherwise. 635 **/ 636int pci_enable_msi(struct pci_dev* dev) 637{ 638 int pos, status; 639 640 if (pci_msi_supported(dev) < 0) 641 return -EINVAL; 642 643 status = msi_init(); 644 if (status < 0) 645 return status; 646 647 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 648 if (!pos) 649 return -EINVAL; 650 651 WARN_ON(!!dev->msi_enabled); 652 653 /* Check whether driver already requested for MSI-X irqs */ 654 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 655 if (pos > 0 && dev->msix_enabled) { 656 printk(KERN_INFO "PCI: %s: Can't enable MSI. " 657 "Device already has MSI-X enabled\n", 658 pci_name(dev)); 659 return -EINVAL; 660 } 661 status = msi_capability_init(dev); 662 return status; 663} 664 665void pci_disable_msi(struct pci_dev* dev) 666{ 667 struct msi_desc *entry; 668 int pos, default_irq; 669 u16 control; 670 671 if (!pci_msi_enable) 672 return; 673 if (!dev) 674 return; 675 676 if (!dev->msi_enabled) 677 return; 678 679 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 680 if (!pos) 681 return; 682 683 pci_read_config_word(dev, msi_control_reg(pos), &control); 684 if (!(control & PCI_MSI_FLAGS_ENABLE)) 685 return; 686 687 688 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); 689 690 entry = msi_desc[dev->first_msi_irq]; 691 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { 692 return; 693 } 694 if (irq_has_action(dev->first_msi_irq)) { 695 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " 696 "free_irq() on MSI irq %d\n", 697 pci_name(dev), dev->first_msi_irq); 698 BUG_ON(irq_has_action(dev->first_msi_irq)); 699 } else { 700 default_irq = entry->msi_attrib.default_irq; 701 msi_free_irq(dev, dev->first_msi_irq); 702 703 /* Restore dev->irq to its default pin-assertion irq */ 704 dev->irq = default_irq; 705 } 706 dev->first_msi_irq = 0; 707} 708 709static int msi_free_irq(struct pci_dev* dev, int irq) 710{ 711 struct msi_desc *entry; 712 int head, entry_nr, type; 713 void __iomem *base; 714 715 arch_teardown_msi_irq(irq); 716 717 entry = msi_desc[irq]; 718 if (!entry || entry->dev != dev) { 719 return -EINVAL; 720 } 721 type = entry->msi_attrib.type; 722 entry_nr = entry->msi_attrib.entry_nr; 723 head = entry->link.head; 724 base = entry->mask_base; 725 msi_desc[entry->link.head]->link.tail = entry->link.tail; 726 msi_desc[entry->link.tail]->link.head = entry->link.head; 727 entry->dev = NULL; 728 msi_desc[irq] = NULL; 729 730 destroy_msi_irq(irq); 731 732 if (type == PCI_CAP_ID_MSIX) { 733 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + 734 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); 735 736 if (head == irq) 737 iounmap(base); 738 } 739 740 return 0; 741} 742 743/** 744 * pci_enable_msix - configure device's MSI-X capability structure 745 * @dev: pointer to the pci_dev data structure of MSI-X device function 746 * @entries: pointer to an array of MSI-X entries 747 * @nvec: number of MSI-X irqs requested for allocation by device driver 748 * 749 * Setup the MSI-X capability structure of device function with the number 750 * of requested irqs upon its software driver call to request for 751 * MSI-X mode enabled on its hardware device function. A return of zero 752 * indicates the successful configuration of MSI-X capability structure 753 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 754 * Or a return of > 0 indicates that driver request is exceeding the number 755 * of irqs available. Driver should use the returned value to re-send 756 * its request. 757 **/ 758int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) 759{ 760 int status, pos, nr_entries; 761 int i, j; 762 u16 control; 763 764 if (!entries || pci_msi_supported(dev) < 0) 765 return -EINVAL; 766 767 status = msi_init(); 768 if (status < 0) 769 return status; 770 771 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 772 if (!pos) 773 return -EINVAL; 774 775 pci_read_config_word(dev, msi_control_reg(pos), &control); 776 nr_entries = multi_msix_capable(control); 777 if (nvec > nr_entries) 778 return -EINVAL; 779 780 /* Check for any invalid entries */ 781 for (i = 0; i < nvec; i++) { 782 if (entries[i].entry >= nr_entries) 783 return -EINVAL; /* invalid entry */ 784 for (j = i + 1; j < nvec; j++) { 785 if (entries[i].entry == entries[j].entry) 786 return -EINVAL; /* duplicate entry */ 787 } 788 } 789 WARN_ON(!!dev->msix_enabled); 790 791 /* Check whether driver already requested for MSI irq */ 792 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && 793 dev->msi_enabled) { 794 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " 795 "Device already has an MSI irq assigned\n", 796 pci_name(dev)); 797 return -EINVAL; 798 } 799 status = msix_capability_init(dev, entries, nvec); 800 return status; 801} 802 803void pci_disable_msix(struct pci_dev* dev) 804{ 805 int irq, head, tail = 0, warning = 0; 806 int pos; 807 u16 control; 808 809 if (!pci_msi_enable) 810 return; 811 if (!dev) 812 return; 813 814 if (!dev->msix_enabled) 815 return; 816 817 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 818 if (!pos) 819 return; 820 821 pci_read_config_word(dev, msi_control_reg(pos), &control); 822 if (!(control & PCI_MSIX_FLAGS_ENABLE)) 823 return; 824 825 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); 826 827 irq = head = dev->first_msi_irq; 828 while (head != tail) { 829 tail = msi_desc[irq]->link.tail; 830 if (irq_has_action(irq)) 831 warning = 1; 832 else if (irq != head) /* Release MSI-X irq */ 833 msi_free_irq(dev, irq); 834 irq = tail; 835 } 836 msi_free_irq(dev, irq); 837 if (warning) { 838 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " 839 "free_irq() on all MSI-X irqs\n", 840 pci_name(dev)); 841 BUG_ON(warning > 0); 842 } 843 dev->first_msi_irq = 0; 844} 845 846/** 847 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 848 * @dev: pointer to the pci_dev data structure of MSI(X) device function 849 * 850 * Being called during hotplug remove, from which the device function 851 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 852 * allocated for this device function, are reclaimed to unused state, 853 * which may be used later on. 854 **/ 855void msi_remove_pci_irq_vectors(struct pci_dev* dev) 856{ 857 int pos; 858 859 if (!pci_msi_enable || !dev) 860 return; 861 862 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 863 if (pos > 0 && dev->msi_enabled) { 864 if (irq_has_action(dev->first_msi_irq)) { 865 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 866 "called without free_irq() on MSI irq %d\n", 867 pci_name(dev), dev->first_msi_irq); 868 BUG_ON(irq_has_action(dev->first_msi_irq)); 869 } else /* Release MSI irq assigned to this device */ 870 msi_free_irq(dev, dev->first_msi_irq); 871 } 872 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 873 if (pos > 0 && dev->msix_enabled) { 874 int irq, head, tail = 0, warning = 0; 875 void __iomem *base = NULL; 876 877 irq = head = dev->first_msi_irq; 878 while (head != tail) { 879 tail = msi_desc[irq]->link.tail; 880 base = msi_desc[irq]->mask_base; 881 if (irq_has_action(irq)) 882 warning = 1; 883 else if (irq != head) /* Release MSI-X irq */ 884 msi_free_irq(dev, irq); 885 irq = tail; 886 } 887 msi_free_irq(dev, irq); 888 if (warning) { 889 iounmap(base); 890 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " 891 "called without free_irq() on all MSI-X irqs\n", 892 pci_name(dev)); 893 BUG_ON(warning > 0); 894 } 895 } 896} 897 898void pci_no_msi(void) 899{ 900 pci_msi_enable = 0; 901} 902 903EXPORT_SYMBOL(pci_enable_msi); 904EXPORT_SYMBOL(pci_disable_msi); 905EXPORT_SYMBOL(pci_enable_msix); 906EXPORT_SYMBOL(pci_disable_msix); 907