msi.c revision fcd097f31a6ee207cc0c3da9cccd2a86d4334785
1/* 2 * File: msi.c 3 * Purpose: PCI Message Signaled Interrupt (MSI) 4 * 5 * Copyright (C) 2003-2004 Intel 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 */ 8 9#include <linux/err.h> 10#include <linux/mm.h> 11#include <linux/irq.h> 12#include <linux/interrupt.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/proc_fs.h> 17#include <linux/msi.h> 18#include <linux/smp.h> 19#include <linux/errno.h> 20#include <linux/io.h> 21#include <linux/slab.h> 22 23#include "pci.h" 24#include "msi.h" 25 26static int pci_msi_enable = 1; 27 28/* Arch hooks */ 29 30#ifndef arch_msi_check_device 31int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) 32{ 33 return 0; 34} 35#endif 36 37#ifndef arch_setup_msi_irqs 38int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 39{ 40 struct msi_desc *entry; 41 int ret; 42 43 /* 44 * If an architecture wants to support multiple MSI, it needs to 45 * override arch_setup_msi_irqs() 46 */ 47 if (type == PCI_CAP_ID_MSI && nvec > 1) 48 return 1; 49 50 list_for_each_entry(entry, &dev->msi_list, list) { 51 ret = arch_setup_msi_irq(dev, entry); 52 if (ret < 0) 53 return ret; 54 if (ret > 0) 55 return -ENOSPC; 56 } 57 58 return 0; 59} 60#endif 61 62#ifndef arch_teardown_msi_irqs 63void arch_teardown_msi_irqs(struct pci_dev *dev) 64{ 65 struct msi_desc *entry; 66 67 list_for_each_entry(entry, &dev->msi_list, list) { 68 int i, nvec; 69 if (entry->irq == 0) 70 continue; 71 nvec = 1 << entry->msi_attrib.multiple; 72 for (i = 0; i < nvec; i++) 73 arch_teardown_msi_irq(entry->irq + i); 74 } 75} 76#endif 77 78static void msi_set_enable(struct pci_dev *dev, int pos, int enable) 79{ 80 u16 control; 81 82 BUG_ON(!pos); 83 84 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 85 control &= ~PCI_MSI_FLAGS_ENABLE; 86 if (enable) 87 control |= PCI_MSI_FLAGS_ENABLE; 88 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 89} 90 91static void msix_set_enable(struct pci_dev *dev, int enable) 92{ 93 int pos; 94 u16 control; 95 96 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 97 if (pos) { 98 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 99 control &= ~PCI_MSIX_FLAGS_ENABLE; 100 if (enable) 101 control |= PCI_MSIX_FLAGS_ENABLE; 102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 103 } 104} 105 106static inline __attribute_const__ u32 msi_mask(unsigned x) 107{ 108 /* Don't shift by >= width of type */ 109 if (x >= 5) 110 return 0xffffffff; 111 return (1 << (1 << x)) - 1; 112} 113 114static inline __attribute_const__ u32 msi_capable_mask(u16 control) 115{ 116 return msi_mask((control >> 1) & 7); 117} 118 119static inline __attribute_const__ u32 msi_enabled_mask(u16 control) 120{ 121 return msi_mask((control >> 4) & 7); 122} 123 124/* 125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to 126 * mask all MSI interrupts by clearing the MSI enable bit does not work 127 * reliably as devices without an INTx disable bit will then generate a 128 * level IRQ which will never be cleared. 129 */ 130static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) 131{ 132 u32 mask_bits = desc->masked; 133 134 if (!desc->msi_attrib.maskbit) 135 return 0; 136 137 mask_bits &= ~mask; 138 mask_bits |= flag; 139 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); 140 141 return mask_bits; 142} 143 144static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) 145{ 146 desc->masked = __msi_mask_irq(desc, mask, flag); 147} 148 149/* 150 * This internal function does not flush PCI writes to the device. 151 * All users must ensure that they read from the device before either 152 * assuming that the device state is up to date, or returning out of this 153 * file. This saves a few milliseconds when initialising devices with lots 154 * of MSI-X interrupts. 155 */ 156static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) 157{ 158 u32 mask_bits = desc->masked; 159 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + 160 PCI_MSIX_ENTRY_VECTOR_CTRL; 161 mask_bits &= ~1; 162 mask_bits |= flag; 163 writel(mask_bits, desc->mask_base + offset); 164 165 return mask_bits; 166} 167 168static void msix_mask_irq(struct msi_desc *desc, u32 flag) 169{ 170 desc->masked = __msix_mask_irq(desc, flag); 171} 172 173static void msi_set_mask_bit(unsigned irq, u32 flag) 174{ 175 struct msi_desc *desc = get_irq_msi(irq); 176 177 if (desc->msi_attrib.is_msix) { 178 msix_mask_irq(desc, flag); 179 readl(desc->mask_base); /* Flush write to device */ 180 } else { 181 unsigned offset = irq - desc->dev->irq; 182 msi_mask_irq(desc, 1 << offset, flag << offset); 183 } 184} 185 186void mask_msi_irq(unsigned int irq) 187{ 188 msi_set_mask_bit(irq, 1); 189} 190 191void unmask_msi_irq(unsigned int irq) 192{ 193 msi_set_mask_bit(irq, 0); 194} 195 196void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 197{ 198 struct msi_desc *entry = get_irq_desc_msi(desc); 199 200 /* We do not touch the hardware (which may not even be 201 * accessible at the moment) but return the last message 202 * written. Assert that this is valid, assuming that 203 * valid messages are not all-zeroes. */ 204 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | 205 entry->msg.data)); 206 207 *msg = entry->msg; 208} 209 210void read_msi_msg(unsigned int irq, struct msi_msg *msg) 211{ 212 struct irq_desc *desc = irq_to_desc(irq); 213 214 read_msi_msg_desc(desc, msg); 215} 216 217void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) 218{ 219 struct msi_desc *entry = get_irq_desc_msi(desc); 220 221 if (entry->dev->current_state != PCI_D0) { 222 /* Don't touch the hardware now */ 223 } else if (entry->msi_attrib.is_msix) { 224 void __iomem *base; 225 base = entry->mask_base + 226 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; 227 228 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); 229 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); 230 writel(msg->data, base + PCI_MSIX_ENTRY_DATA); 231 } else { 232 struct pci_dev *dev = entry->dev; 233 int pos = entry->msi_attrib.pos; 234 u16 msgctl; 235 236 pci_read_config_word(dev, msi_control_reg(pos), &msgctl); 237 msgctl &= ~PCI_MSI_FLAGS_QSIZE; 238 msgctl |= entry->msi_attrib.multiple << 4; 239 pci_write_config_word(dev, msi_control_reg(pos), msgctl); 240 241 pci_write_config_dword(dev, msi_lower_address_reg(pos), 242 msg->address_lo); 243 if (entry->msi_attrib.is_64) { 244 pci_write_config_dword(dev, msi_upper_address_reg(pos), 245 msg->address_hi); 246 pci_write_config_word(dev, msi_data_reg(pos, 1), 247 msg->data); 248 } else { 249 pci_write_config_word(dev, msi_data_reg(pos, 0), 250 msg->data); 251 } 252 } 253 entry->msg = *msg; 254} 255 256void write_msi_msg(unsigned int irq, struct msi_msg *msg) 257{ 258 struct irq_desc *desc = irq_to_desc(irq); 259 260 write_msi_msg_desc(desc, msg); 261} 262 263static void free_msi_irqs(struct pci_dev *dev) 264{ 265 struct msi_desc *entry, *tmp; 266 267 list_for_each_entry(entry, &dev->msi_list, list) { 268 int i, nvec; 269 if (!entry->irq) 270 continue; 271 nvec = 1 << entry->msi_attrib.multiple; 272 for (i = 0; i < nvec; i++) 273 BUG_ON(irq_has_action(entry->irq + i)); 274 } 275 276 arch_teardown_msi_irqs(dev); 277 278 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { 279 if (entry->msi_attrib.is_msix) { 280 if (list_is_last(&entry->list, &dev->msi_list)) 281 iounmap(entry->mask_base); 282 } 283 list_del(&entry->list); 284 kfree(entry); 285 } 286} 287 288static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) 289{ 290 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); 291 if (!desc) 292 return NULL; 293 294 INIT_LIST_HEAD(&desc->list); 295 desc->dev = dev; 296 297 return desc; 298} 299 300static void pci_intx_for_msi(struct pci_dev *dev, int enable) 301{ 302 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) 303 pci_intx(dev, enable); 304} 305 306static void __pci_restore_msi_state(struct pci_dev *dev) 307{ 308 int pos; 309 u16 control; 310 struct msi_desc *entry; 311 312 if (!dev->msi_enabled) 313 return; 314 315 entry = get_irq_msi(dev->irq); 316 pos = entry->msi_attrib.pos; 317 318 pci_intx_for_msi(dev, 0); 319 msi_set_enable(dev, pos, 0); 320 write_msi_msg(dev->irq, &entry->msg); 321 322 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 323 msi_mask_irq(entry, msi_capable_mask(control), entry->masked); 324 control &= ~PCI_MSI_FLAGS_QSIZE; 325 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; 326 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 327} 328 329static void __pci_restore_msix_state(struct pci_dev *dev) 330{ 331 int pos; 332 struct msi_desc *entry; 333 u16 control; 334 335 if (!dev->msix_enabled) 336 return; 337 BUG_ON(list_empty(&dev->msi_list)); 338 entry = list_first_entry(&dev->msi_list, struct msi_desc, list); 339 pos = entry->msi_attrib.pos; 340 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 341 342 /* route the table */ 343 pci_intx_for_msi(dev, 0); 344 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; 345 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 346 347 list_for_each_entry(entry, &dev->msi_list, list) { 348 write_msi_msg(entry->irq, &entry->msg); 349 msix_mask_irq(entry, entry->masked); 350 } 351 352 control &= ~PCI_MSIX_FLAGS_MASKALL; 353 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 354} 355 356void pci_restore_msi_state(struct pci_dev *dev) 357{ 358 __pci_restore_msi_state(dev); 359 __pci_restore_msix_state(dev); 360} 361EXPORT_SYMBOL_GPL(pci_restore_msi_state); 362 363/** 364 * msi_capability_init - configure device's MSI capability structure 365 * @dev: pointer to the pci_dev data structure of MSI device function 366 * @nvec: number of interrupts to allocate 367 * 368 * Setup the MSI capability structure of the device with the requested 369 * number of interrupts. A return value of zero indicates the successful 370 * setup of an entry with the new MSI irq. A negative return value indicates 371 * an error, and a positive return value indicates the number of interrupts 372 * which could have been allocated. 373 */ 374static int msi_capability_init(struct pci_dev *dev, int nvec) 375{ 376 struct msi_desc *entry; 377 int pos, ret; 378 u16 control; 379 unsigned mask; 380 381 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 382 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ 383 384 pci_read_config_word(dev, msi_control_reg(pos), &control); 385 /* MSI Entry Initialization */ 386 entry = alloc_msi_entry(dev); 387 if (!entry) 388 return -ENOMEM; 389 390 entry->msi_attrib.is_msix = 0; 391 entry->msi_attrib.is_64 = is_64bit_address(control); 392 entry->msi_attrib.entry_nr = 0; 393 entry->msi_attrib.maskbit = is_mask_bit_support(control); 394 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ 395 entry->msi_attrib.pos = pos; 396 397 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); 398 /* All MSIs are unmasked by default, Mask them all */ 399 if (entry->msi_attrib.maskbit) 400 pci_read_config_dword(dev, entry->mask_pos, &entry->masked); 401 mask = msi_capable_mask(control); 402 msi_mask_irq(entry, mask, mask); 403 404 list_add_tail(&entry->list, &dev->msi_list); 405 406 /* Configure MSI capability structure */ 407 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); 408 if (ret) { 409 msi_mask_irq(entry, mask, ~mask); 410 free_msi_irqs(dev); 411 return ret; 412 } 413 414 /* Set MSI enabled bits */ 415 pci_intx_for_msi(dev, 0); 416 msi_set_enable(dev, pos, 1); 417 dev->msi_enabled = 1; 418 419 dev->irq = entry->irq; 420 return 0; 421} 422 423static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, 424 unsigned nr_entries) 425{ 426 resource_size_t phys_addr; 427 u32 table_offset; 428 u8 bir; 429 430 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); 431 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); 432 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; 433 phys_addr = pci_resource_start(dev, bir) + table_offset; 434 435 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); 436} 437 438static int msix_setup_entries(struct pci_dev *dev, unsigned pos, 439 void __iomem *base, struct msix_entry *entries, 440 int nvec) 441{ 442 struct msi_desc *entry; 443 int i; 444 445 for (i = 0; i < nvec; i++) { 446 entry = alloc_msi_entry(dev); 447 if (!entry) { 448 if (!i) 449 iounmap(base); 450 else 451 free_msi_irqs(dev); 452 /* No enough memory. Don't try again */ 453 return -ENOMEM; 454 } 455 456 entry->msi_attrib.is_msix = 1; 457 entry->msi_attrib.is_64 = 1; 458 entry->msi_attrib.entry_nr = entries[i].entry; 459 entry->msi_attrib.default_irq = dev->irq; 460 entry->msi_attrib.pos = pos; 461 entry->mask_base = base; 462 463 list_add_tail(&entry->list, &dev->msi_list); 464 } 465 466 return 0; 467} 468 469static void msix_program_entries(struct pci_dev *dev, 470 struct msix_entry *entries) 471{ 472 struct msi_desc *entry; 473 int i = 0; 474 475 list_for_each_entry(entry, &dev->msi_list, list) { 476 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + 477 PCI_MSIX_ENTRY_VECTOR_CTRL; 478 479 entries[i].vector = entry->irq; 480 set_irq_msi(entry->irq, entry); 481 entry->masked = readl(entry->mask_base + offset); 482 msix_mask_irq(entry, 1); 483 i++; 484 } 485} 486 487/** 488 * msix_capability_init - configure device's MSI-X capability 489 * @dev: pointer to the pci_dev data structure of MSI-X device function 490 * @entries: pointer to an array of struct msix_entry entries 491 * @nvec: number of @entries 492 * 493 * Setup the MSI-X capability structure of device function with a 494 * single MSI-X irq. A return of zero indicates the successful setup of 495 * requested MSI-X entries with allocated irqs or non-zero for otherwise. 496 **/ 497static int msix_capability_init(struct pci_dev *dev, 498 struct msix_entry *entries, int nvec) 499{ 500 int pos, ret; 501 u16 control; 502 void __iomem *base; 503 504 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 505 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 506 507 /* Ensure MSI-X is disabled while it is set up */ 508 control &= ~PCI_MSIX_FLAGS_ENABLE; 509 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 510 511 /* Request & Map MSI-X table region */ 512 base = msix_map_region(dev, pos, multi_msix_capable(control)); 513 if (!base) 514 return -ENOMEM; 515 516 ret = msix_setup_entries(dev, pos, base, entries, nvec); 517 if (ret) 518 return ret; 519 520 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); 521 if (ret) 522 goto error; 523 524 /* 525 * Some devices require MSI-X to be enabled before we can touch the 526 * MSI-X registers. We need to mask all the vectors to prevent 527 * interrupts coming in before they're fully set up. 528 */ 529 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; 530 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 531 532 msix_program_entries(dev, entries); 533 534 /* Set MSI-X enabled bits and unmask the function */ 535 pci_intx_for_msi(dev, 0); 536 dev->msix_enabled = 1; 537 538 control &= ~PCI_MSIX_FLAGS_MASKALL; 539 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 540 541 return 0; 542 543error: 544 if (ret < 0) { 545 /* 546 * If we had some success, report the number of irqs 547 * we succeeded in setting up. 548 */ 549 struct msi_desc *entry; 550 int avail = 0; 551 552 list_for_each_entry(entry, &dev->msi_list, list) { 553 if (entry->irq != 0) 554 avail++; 555 } 556 if (avail != 0) 557 ret = avail; 558 } 559 560 free_msi_irqs(dev); 561 562 return ret; 563} 564 565/** 566 * pci_msi_check_device - check whether MSI may be enabled on a device 567 * @dev: pointer to the pci_dev data structure of MSI device function 568 * @nvec: how many MSIs have been requested ? 569 * @type: are we checking for MSI or MSI-X ? 570 * 571 * Look at global flags, the device itself, and its parent busses 572 * to determine if MSI/-X are supported for the device. If MSI/-X is 573 * supported return 0, else return an error code. 574 **/ 575static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) 576{ 577 struct pci_bus *bus; 578 int ret; 579 580 /* MSI must be globally enabled and supported by the device */ 581 if (!pci_msi_enable || !dev || dev->no_msi) 582 return -EINVAL; 583 584 /* 585 * You can't ask to have 0 or less MSIs configured. 586 * a) it's stupid .. 587 * b) the list manipulation code assumes nvec >= 1. 588 */ 589 if (nvec < 1) 590 return -ERANGE; 591 592 /* 593 * Any bridge which does NOT route MSI transactions from its 594 * secondary bus to its primary bus must set NO_MSI flag on 595 * the secondary pci_bus. 596 * We expect only arch-specific PCI host bus controller driver 597 * or quirks for specific PCI bridges to be setting NO_MSI. 598 */ 599 for (bus = dev->bus; bus; bus = bus->parent) 600 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) 601 return -EINVAL; 602 603 ret = arch_msi_check_device(dev, nvec, type); 604 if (ret) 605 return ret; 606 607 if (!pci_find_capability(dev, type)) 608 return -EINVAL; 609 610 return 0; 611} 612 613/** 614 * pci_enable_msi_block - configure device's MSI capability structure 615 * @dev: device to configure 616 * @nvec: number of interrupts to configure 617 * 618 * Allocate IRQs for a device with the MSI capability. 619 * This function returns a negative errno if an error occurs. If it 620 * is unable to allocate the number of interrupts requested, it returns 621 * the number of interrupts it might be able to allocate. If it successfully 622 * allocates at least the number of interrupts requested, it returns 0 and 623 * updates the @dev's irq member to the lowest new interrupt number; the 624 * other interrupt numbers allocated to this device are consecutive. 625 */ 626int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 627{ 628 int status, pos, maxvec; 629 u16 msgctl; 630 631 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 632 if (!pos) 633 return -EINVAL; 634 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); 635 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); 636 if (nvec > maxvec) 637 return maxvec; 638 639 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); 640 if (status) 641 return status; 642 643 WARN_ON(!!dev->msi_enabled); 644 645 /* Check whether driver already requested MSI-X irqs */ 646 if (dev->msix_enabled) { 647 dev_info(&dev->dev, "can't enable MSI " 648 "(MSI-X already enabled)\n"); 649 return -EINVAL; 650 } 651 652 status = msi_capability_init(dev, nvec); 653 return status; 654} 655EXPORT_SYMBOL(pci_enable_msi_block); 656 657void pci_msi_shutdown(struct pci_dev *dev) 658{ 659 struct msi_desc *desc; 660 u32 mask; 661 u16 ctrl; 662 unsigned pos; 663 664 if (!pci_msi_enable || !dev || !dev->msi_enabled) 665 return; 666 667 BUG_ON(list_empty(&dev->msi_list)); 668 desc = list_first_entry(&dev->msi_list, struct msi_desc, list); 669 pos = desc->msi_attrib.pos; 670 671 msi_set_enable(dev, pos, 0); 672 pci_intx_for_msi(dev, 1); 673 dev->msi_enabled = 0; 674 675 /* Return the device with MSI unmasked as initial states */ 676 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); 677 mask = msi_capable_mask(ctrl); 678 /* Keep cached state to be restored */ 679 __msi_mask_irq(desc, mask, ~mask); 680 681 /* Restore dev->irq to its default pin-assertion irq */ 682 dev->irq = desc->msi_attrib.default_irq; 683} 684 685void pci_disable_msi(struct pci_dev *dev) 686{ 687 if (!pci_msi_enable || !dev || !dev->msi_enabled) 688 return; 689 690 pci_msi_shutdown(dev); 691 free_msi_irqs(dev); 692} 693EXPORT_SYMBOL(pci_disable_msi); 694 695/** 696 * pci_msix_table_size - return the number of device's MSI-X table entries 697 * @dev: pointer to the pci_dev data structure of MSI-X device function 698 */ 699int pci_msix_table_size(struct pci_dev *dev) 700{ 701 int pos; 702 u16 control; 703 704 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 705 if (!pos) 706 return 0; 707 708 pci_read_config_word(dev, msi_control_reg(pos), &control); 709 return multi_msix_capable(control); 710} 711 712/** 713 * pci_enable_msix - configure device's MSI-X capability structure 714 * @dev: pointer to the pci_dev data structure of MSI-X device function 715 * @entries: pointer to an array of MSI-X entries 716 * @nvec: number of MSI-X irqs requested for allocation by device driver 717 * 718 * Setup the MSI-X capability structure of device function with the number 719 * of requested irqs upon its software driver call to request for 720 * MSI-X mode enabled on its hardware device function. A return of zero 721 * indicates the successful configuration of MSI-X capability structure 722 * with new allocated MSI-X irqs. A return of < 0 indicates a failure. 723 * Or a return of > 0 indicates that driver request is exceeding the number 724 * of irqs or MSI-X vectors available. Driver should use the returned value to 725 * re-send its request. 726 **/ 727int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) 728{ 729 int status, nr_entries; 730 int i, j; 731 732 if (!entries) 733 return -EINVAL; 734 735 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); 736 if (status) 737 return status; 738 739 nr_entries = pci_msix_table_size(dev); 740 if (nvec > nr_entries) 741 return nr_entries; 742 743 /* Check for any invalid entries */ 744 for (i = 0; i < nvec; i++) { 745 if (entries[i].entry >= nr_entries) 746 return -EINVAL; /* invalid entry */ 747 for (j = i + 1; j < nvec; j++) { 748 if (entries[i].entry == entries[j].entry) 749 return -EINVAL; /* duplicate entry */ 750 } 751 } 752 WARN_ON(!!dev->msix_enabled); 753 754 /* Check whether driver already requested for MSI irq */ 755 if (dev->msi_enabled) { 756 dev_info(&dev->dev, "can't enable MSI-X " 757 "(MSI IRQ already assigned)\n"); 758 return -EINVAL; 759 } 760 status = msix_capability_init(dev, entries, nvec); 761 return status; 762} 763EXPORT_SYMBOL(pci_enable_msix); 764 765void pci_msix_shutdown(struct pci_dev *dev) 766{ 767 struct msi_desc *entry; 768 769 if (!pci_msi_enable || !dev || !dev->msix_enabled) 770 return; 771 772 /* Return the device with MSI-X masked as initial states */ 773 list_for_each_entry(entry, &dev->msi_list, list) { 774 /* Keep cached states to be restored */ 775 __msix_mask_irq(entry, 1); 776 } 777 778 msix_set_enable(dev, 0); 779 pci_intx_for_msi(dev, 1); 780 dev->msix_enabled = 0; 781} 782 783void pci_disable_msix(struct pci_dev *dev) 784{ 785 if (!pci_msi_enable || !dev || !dev->msix_enabled) 786 return; 787 788 pci_msix_shutdown(dev); 789 free_msi_irqs(dev); 790} 791EXPORT_SYMBOL(pci_disable_msix); 792 793/** 794 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state 795 * @dev: pointer to the pci_dev data structure of MSI(X) device function 796 * 797 * Being called during hotplug remove, from which the device function 798 * is hot-removed. All previous assigned MSI/MSI-X irqs, if 799 * allocated for this device function, are reclaimed to unused state, 800 * which may be used later on. 801 **/ 802void msi_remove_pci_irq_vectors(struct pci_dev *dev) 803{ 804 if (!pci_msi_enable || !dev) 805 return; 806 807 if (dev->msi_enabled || dev->msix_enabled) 808 free_msi_irqs(dev); 809} 810 811void pci_no_msi(void) 812{ 813 pci_msi_enable = 0; 814} 815 816/** 817 * pci_msi_enabled - is MSI enabled? 818 * 819 * Returns true if MSI has not been disabled by the command-line option 820 * pci=nomsi. 821 **/ 822int pci_msi_enabled(void) 823{ 824 return pci_msi_enable; 825} 826EXPORT_SYMBOL(pci_msi_enabled); 827 828void pci_msi_init_pci_dev(struct pci_dev *dev) 829{ 830 INIT_LIST_HEAD(&dev->msi_list); 831} 832